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PI3PCIE2612-A
High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout
Features
* 6 Differential Channel, 1 to 2 demux that will support 5.0Gbps PCIexpress Gen2 signals on one path, and DP 1.1 signals on the second path * Insertion Loss for high speed channels @ 5.0 Gbps: -5.0dB * Low Bit-to-Bit Skew , 7ps max (between '+' and '-' bits) * Latched Mux Select * Matched paths for all PCIe signals * Low Crosstalk for high speed channels: -35dB@2.5 GHz * Low Off Isolation for high speed channels: -35dB@2.5 GHz * VDD Operating Range: 3.3V 10% * ESD Tolerance: 8kV contact on Display Port Path output 4kV HBM on PCI-Express path output * Low channel-to-channel skew, 35ps max * Packaging (Pb-free & Green): - 56 TQFN (ZFE)
Description
Pericom Semiconductor's PI3PCIE2612-A one to two Mux/ Demux is targeted for next generation systems that combine PCIExpress gen-II signals with Display Port Signals.
Application
Routing DP and PCIExpress Gen1 or Gen2 signals with low signal attenuation.
Pin Diagram (top-side view)
Tx0+ Tx1+ GND
49
GND
VDD
Block Diagram
56 55 54 53 52 51 50
VDD
Tx0-
Tx1-
GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
GND Tx2+ Tx2Tx3+ Tx3D0+ D0D1+ D1D2+ D2D3+ D3GND VDD Rx0+ Rx0Rx1+ Rx1GND
IN_0+ IN_0IN_1+ IN_1IN_2+ IN_2IN_3+ IN_3-
D0+ D0D1+ D1D2+ D2D3+ D3Tx0+ Tx0 Tx1+ Tx1 Tx2+ Tx2 Tx3+ Tx3 -
IN_0+ IN_0IN_1+ IN_1VDD IN_2+ IN_2IN_3+ IN_3GND OUT+ OUTX+ XGND VDD SEL LE# GND
OUT+ OUTX+ X-
AUX+ AUXHPD NC Rx0+ Rx0Rx1+ Rx1-
SEL LE#
AUX+
VDD
Truth Table (SEL control)
Function PCI-Express Gen2 path is active (Tx) Digital Video Port is active (Dx)
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Truth Table (Latch control)
SEL L H
1
LE# 0 1
Internal mux select Respond to changes on SEL Latched
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AUX-
GND
GND
VDD
NC
HPD
Logic Control
PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout Application Example
GMCH
DP/TMDS/ PCIe genII x4 IN
PI3PCIE2612-A DP/PCIe2.0 (1:2) Mux
Dx
PEG
HPD HPD / PEG RX x2 PEG RX
DP Path will support 2.7 Gbps
Aux / PEG RX x12 Tx x14 Rx
x2 PEG RX Rx Rx Tx
AUX
PCIe Path will support 5 Gbps
x16 PEG Connector
Pin Description Pin Number Pin Name 26 AUX+
Type O
25
AUX-
O
43, 42 41, 40 39, 38 37, 36
D0+, D0D1+, D1D2+, D2D3+, D3-
O O O O
Description Differential input from HDMI/DP connector. AUX+ makes a differential pair with AUX-. AUX+ is passed through to the OUT+ pin when SEL = 1. Differential input from HDMI/DP connector. AUX- makes a differential pair with AUX+. AUX- is passed through to the OUTpin when SEL = 1. Analog "pass through" output#1 corresponding to IN_0+ and IN_0-, when SEL = 1. Analog "pass through" output#1 corresponding to IN_1+ and IN_1-, when SEL = 1. Analog "pass through" output#1 corresponding to IN_2+ and IN_2-, when SEL = 1. Analog "pass through" output#1 corresponding to IN_3+ and IN_3-, when SEL = 1.
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PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout Pin Number Pin Name 1, 11, 20, 21, GND 28, 29, 35, 48, 49, 56 24 HPD Type Description Power Ground. I The HPD signal comes from the HDMI or DP connector. This is a low frequency, 0V to 5V (HDMI) or 3.6V (DP) input signal at the connector. The HPD input at the mux is 3.6V max, so HDMI HPD must be shifted down from 5V before it is passed to the mux. Differential input from GMCH PCIE outputs. IN_0+ makes a differential pair with IN_0-. Differential input from GMCH PCIE outputs. IN_0- makes a differential pair with IN_0+. Differential input from GMCH PCIE outputs. IN_1+ makes a differential pair with IN_1-. Differential input from GMCH PCIE outputs. IN_1- makes a differential pair with IN_1+. Differential input from GMCH PCIE outputs. IN_2+ makes a differential pair with IN_2-. Differential input from GMCH PCIE outputs. IN_2- makes a differential pair with IN_2+. Differential input from GMCH PCIE outputs. IN_3+ makes a differential pair with IN_3-. Differential input from GMCH PCIE outputs. IN_3- makes a differential pair with IN_3+. The latch gate is controlled by LE. 3.6V tolerant, low-voltage, single-ended input.
2 3 4 5 7 8 9 10 19 23 12 13 33
IN_0+ IN_0IN_1+ IN_1IN_2+ IN_2IN_3+ IN_3LE# NC OUT+ OUTRx0+
I I I I I I I I I
32
Rx0-
31
Rx1+
Do Not Connect O Pass-through output from AUX+ input when SEL = 1. Passthrough output from Rx0+ input when SEL = 0. O Pass-through output from AUX- input when SEL = 1. Passthrough output from Rx0- input when SEL = 0. I/O Differential input from PCIE connector or device. Rx0+ makes a differential pair with Rx0-. Rx0+ is passed through to the OUT+ pin when SEL = 0. I/O Differential input from PCIE connector or device. Rx0- makes a differential pair with Rx0+. Rx0- is passed through to the OUTpin when SEL = 0. I Differential input from PCIE connector or device. Rx1+ makes a differential pair with Rx1-. Rx1+ is passed through to the X+ pin when SEL = 0. (Continued)
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PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout Pin Number 30 Pin Name Rx1Type I Description Differential input from PCIE connector or device. Rx1- makes a differential pair with Rx1+. Rx1- is passed through to the X- pin on a path that matches the Rx1+ to X+ path. SEL controls the mux through a flow-through latch. 3.6V tollerant low-voltage single-ended output SEL = 0 for PCIE Mode SEL = 1 for DP Mode Analog "pass through" output#2 corresponding to IN_0+ and IN_0-, when SEL = 0. Analog "pass through" output#2 corresponding to IN_1+ and IN_1-, when SEL = 0. Analog "pass through" output#2 corresponding to IN_2+ and IN_2-, when SEL = 0. Analog "pass through" output#2 corresponding to IN_3+ and IN_3-, when SEL = 0. 3.3V DC Supply, 3.3V +/- 10% HPD: Low frequency, 0V to 5V/3.3V (nominal) input signal at the connector. This signal comes from the HDMI/DP connector. X+: Analog "pass through" output corresponding to Rx1+. X- is an analog "pass-through" output corresponding to the Rx1input. The path from Rx1- to X- must be matched with the path from Rx1+ to X+. X+ and X- form a differential pair when the pass-through mux mode is selected.
18
SEL
I
54, 53 52, 51 47, 46 45, 44 6, 17, 22, 27, 34, 50, 55 14
Tx0+,Tx0Tx1+, Tx1Tx2+, Tx2Tx3+, Tx3VDD X+
O O O O Power I/O
15
X-
I
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PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature ....................................................-65C to +150C Supply Voltage to Ground Potential ................................-0.5V to +4.6V DC Input Voltage .............................................................. -0.5V to VDD DC Output Current ....................................................................... 120mA Power Dissipation ........................................................................... 0.5W
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Electrical Characteristics Recommended Operating Conditions
Symbol Parameter Conditions Min Typ Max Units
VDD IDD TCASE
3.3V Power Supply Total current from VDD 3.3V supply Case temperature range for operation within spec.
3.0 0 -40
3.3
3.6 2.5 85
V mA Celcius
DC Electrical Characteristics (TA = -40C to +85C, VDD = 3.3V 10%)
Parameter Description Test Conditions Min Typ(1) Max Units
VIH-EN(2) VIL-EN(2) IIN_EN(2)
RON CON
Input high level Input Low Level Input Leakage Current Measured with input at VIH-EN max and VIL-EN min
On Resistance On Channel Capacitance VDD = Min., VIN = 1.3V, IIN = 40mA VIN = 0, VDD = 3.3V
2.0 0 -10
3.6 0.8 10
10 3.0
V V uA
Ohm pF
Note: 1. Typical values are at VDD = 3.3V, TA = 25C ambient and maximum loading. 2. For SEL and LE# inputs
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PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout Dynamic Electrical Characteristics for IN_x+/-, Rxy+/-, and Txy+/Parameter DDIL Description Differential Insertion Loss Test Conditions f=1.2GHz f=2.5GHz f=5.0GHz f=7.5GHz f= 0 to 3.0GHz f= 5.0GHz f= 0 to 2.8GHz f= 2.8 to 5.0GHz f= 5.0 to 7.5GHz f= 0 to 2.5GHz f= 2.5 to 5.0GHz f= 5.0 to 7.5GHz Min. Typ.(1) -1.5 -2.0 -5.0 -9.0 -23.0 -20.0 -14.0 -8.0 -4.0 -32.0 -26.0 -20.0 dB Max. Units
DDILOFF DDRL
Differential Off Isolation Differential Return Loss
DDNEXT
Near End Crosstalk
Dynamic Electrical Characteristics for Dx+/Parameter DDILDP DDRLDP DDNEXTDP
Description Display Port Differential Insertion Loss Display Port Differential Return Loss Display Port Near End Crosstalk
Test Conditions f= 0 to 1.35GHz f= 1.35 to 2.7GHz f= 0 to 2.7GHz f= 0 to 2.7GHz
Min.
Typ.(1) -1.5 -4.5 -14 -32.0
Max.
Units
dB
Switching Characteristics (TA= -40 to +85C, VDD = 3.3V10%)
Parameter tPZH, tPZL tPHZ, tPLZ tb-b tch-ch Description Line Enable Time - SEL to DX, TXY, RXY, AUX, HPD Line Disable Time - SEL to DX, TXY, RXY, AUX, HPD Test Conditions See "Test Circuit for Electrical Chatacteristics" See "Test Circuit for Electrical Chatacteristics" Min. 0.5 0.5 Typ. Max. 12.0 12.0 7 35 Units ns ns ps ps
Bit-to-bit skew within the same differential See "Test Circuit for pair Electrical Chatacteristics" Channel-to-channel skew See "Test Circuit for Electrical Chatacteristics"
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PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout
Differential Insertion Loss
Differential Return Loss
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PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout
Off Isolation
Crosstalk
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PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout
Tx Eye Diagram, 5.0 Gbps
Dx Eye Diagram, 2.7 Gbps
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PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout
Test Circuit
Test Circuit
Test Circuit
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PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout Test Circuit for Electrical Characteristics(1-5)
2 x VDD VDD
Switch Positions
Test tPLZ, tPZL tPHZ, tPZH Prop Delay Switch 2 x VDD GND Open
200-ohm Pulse Generator VIN D.U.T RT VOUT 4pF CL 200-ohm
Notes: 1. CL = Load capacitance: includes jig and probe capacitance. 2. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator 3. Output 1 is for an output with internal conditions such that the output is low except when disabled by the output control. output 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 4. All input impulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50, tR 2.5ns, tF 2.5ns. 5. The outputs are measured one at a time with one transition per measurement.
Switching Waveforms
SEL VDD/2 tPZL VDD/2 0V Output 1 tPLZ VOH VDD
VDD/2
tPZH tPHZ
VOL + 0.15V VOH - 0.15V
VOL VOH VOL
VDD/2
Output 2
Voltage Waveforms Enable and Disable Times
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PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout Applications Information Differential Input Characteristics for IN_x+/- and Rxx+/- signals. Symbol Parameter Min Nom Max Tbit Unit Interval 199.94 200.00 200.06 1.200 VRX-Diffp-p Differential Input Peak 0.175 to Peak Voltage TRX-EYE VCM-AC-pp Minimum Eye Width at TBD IN_D input pair. AC Peak CommonMode Input Voltage
Units Ps V
Comments Defined by Gen2 spec. VRX-DIFFp-p = 2*|VRXD+ - VRX-D-|. Applies to IN_D and RX_IN signals.
Tbit 100 mV VCM-AC-pp = |VRX-D+ + VRX-D-| / 2 - VRX-CM-DC. VRX-CM-DC = DC(avg) of |VRX-D++ VRX-D-| / 2 VCM-AC-pp includes all frequencies above 30kHz. Rx DC Differential Mode impedance. Required IN_D+ as well as IN_D- DC impedance (50 +/- 20% tolerance). Includes mux resistance. Intended to limit powerup stress on PCIE output buffers.
ZRX-DIFF-DC DC Differential Input Impedance ZRX-DC DC Input Impedance
80 40
100 50
120 60

VRX-Bias
Rx input termination voltage Differential Insertion Loss
0
2.0
V
DDIL
DDRL
Differential Return Loss Near End Crosstalk
DDNEXT
DDIL when Differential Insertion switch is off Loss when switch is off
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-[0.6*(f)+0.5] dB up to 2.5 GHz (for example, -2 dB at f = 2.5 GHz); -[1.2*(f-2.5)+2] dB for 2.5 GHz < f 5 GHz (for example, -5 dB at f = 5 GHz); -[1.6*(f-5)+5] dB for 5 GHz < f 7.5 GHz (for example, -9 dB at f = 7.5 GHz); -14 dB up to 2.8 GHz; -8 dB up to 5 GHz; -4 dB up to 7.5 GHz. -32 dB max up to 2.5 GHz; 26 dB max up to 5.0 GHz; -20 dB max up to 7.5 GHz; -20 dB up to 3 GHz;
dB
dB
dB
dB
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PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout PCIe Gen2 Output Characteristics Symbol Parameter ZRX-DIFF-DC DC Differential Input Impedance ZRX-DC DC Input Impedance Min 80 40 Nom 100 50 Max 120 60 Units Comments Rx DC Differential Mode impedance. Required IN_D+ as well as IN_D- DC impedance (50 +/- 20% tolerance). Includes mux resistance. Intended to limit power-up stress on PCIE output buffers.
VRX-Bias
Rx input termination volt- 0 age Differential Insertion Loss
2.0
V
DDIL
DDRL
Differential Return Loss
DDNEXT
Near End Crosstalk
DDIL when switch is off
Differential Insertion Loss when switch is off
-[0.6*(f)+0.5] dB up to 2.5 GHz (for example, -2 dB at f = 2.5 GHz); -[1.2*(f-2.5)+2] dB for 2.5 GHz < f 5 GHz (for example, -5 dB at f = 5 GHz); -[1.6*(f-5)+5] dB for 5 GHz < f 7.5 GHz (for example, -9 dB at f = 7.5 GHz); -14 dB up to 2.8 GHz; -8 dB up to 5 GHz; -4 dB up to 7.5 GHz. -32 dB max up to 2.5 GHz; -26 dB max up to 5.0 GHz; -20 dB max up to 7.5 GHz; -20 dB up to 3 GHz;
dB
dB
dB
dB
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PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout Display Port Output Characteristics Symbol Parameter Tbit Unit Interval Min 333 Nom Max Units ps Comments Normal Tbit at 2.7Gb/ s=370ps. 333ps=370ps10% VRX-DIFFp-p = 2*|VRX-D+ - VRX-D|. Applies to IN_D and RX_IN signals. Jitter budget for highspeed signals as they pass through the display mux. 7.4ps = 0.02 Tbit at 2.7Gb/s For example, -1.5 dB at f = 1.35 GHz For example, -4.5 dB at f = 2.7 GHz
VRX-Diffp-p
Differential Input Peak to 0.340 Peak Voltage
1.38
V
TJIT
Jitter added to high-speed signals
7.4
ps
DDIL
Differential Insertion Loss
DDRL DDNEXT
Differential Return Loss Near End Crosstalk
-[0.75*(f)+0.5] dB up to 1.35 GHz; -[2.2*(f-1.35)+1.5] dB for 1.35 GHz < f 2.7 GHz -14 dB up to 2.7 GHz -32 dB max up to 2.7 GHz Min Nom Max 3.6
dB
dB dB Units V Comments Low-speed input changes state on cable plug/ unplug. V Measured with HPD at VIH-HPD max and VIL-HPD min Time from HPD_IN changing state to HPD changing state. Includes HPD rise/fall time. Time required to transition from VOH-HPD to VOL-HPD or from VOL-HPD to VOHHPD. Comments Applies to both 3.3V and 5V pull up resistors.
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HPD Input Characteristics Symbol Parameter Input high level VIH-HPD
VIL-HPD IIN_HPD
HPD Input Low Level HPD input leakage current HPD_IN to HPD propagation delay.
0 |10| uA
THPD
200
ns
TRF-HPD
HPD rise/fall time.
1
20
ns
Termination Resistors Symbol Parameter DDC Termination ResisRDDC tors
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Min 1.3K
Nom 1.5k
14
Max 2.2k
Units W
PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout
Switch Signal Integrity Requirements and Test Procedures for 5.0 Gb/s Signal integrity requirements for 5.0 Gb/s applications of the switch are specified. Also included are the requirements of the test fixture for switch S-parameter measurements. Signal Integrity Requirements The procedures outlined in ANSI Electronics Industry Alliance (EIA) standards documents shall be followed: * EIA 364-101 - Attenuation Test Procedure for Electrical Connectors, Sockets, Cable Assemblies or Interconnection Systems * EIA 364-90 - Crosstalk Ratio Test Procedure for Electrical Connectors, Sockets, Cable Assemblies or Interconnection Systems * EIA 364-108- Impedance, Reflection Coefficient, Return Loss, and VSWR Measured in the Time and Frequency Domain Test Procedure for Electrical Connectors, Sockets, Cable Assemblies or Interconnection Systems
Signal Integrity Requirements and Test Procedures for 5.0 Gb/s
Procedure EIA 364-101 The EIA standard shall be used with the following considerations: 1. The measured differential S parameter shall be referenced to a 100 ohms differential impedance. 2. The test fixture shall meet the test fixture requirement defined in Section 1.12. 3. The test fixture effect shall be removed from the measured S parameters. Refer to Note 1. EIA 364-108 Differential The EIA standard shall be used with the following considerations: Return Loss 1. The measured differential S parameter shall be referenced to a (DDRL) 100 ohms differential impedance. 2. The test fixture shall meet the test fixture requirement in Section 1.12. 3. The test fixture effect shall be removed. Refer to Note 1. Intra-pair Skew Intra-pair skew must be achieved by design; measurement not required. Differential Near EIA 364-90 End Crosstalk The EIA standard must be used with the following considerations: (DDNEXT) 1. The crosstalk requirement is with respect to all the adjacent differential pairs Differential EIA 364-101 Insertion Loss (DDIL) when switch is turned off Parameter Differential Insertion Loss (DDIL) Requirements -[0.6*(f)+0.5] dB up to 2.5 GHz (for example, -2 dB at f = 2.5 GHz); -[1.2*(f-2.5)+2] dB for 2.5 GHz < f 5 GHz (for example, -5 dB at f = 5 GHz); -[1.6*(f-5)+5] dB for 5 GHz < f 7.5 GHz (for example, -9 dB at f = 7.5 GHz); Refer to Figure 1. -14 dB up to 2.8 GHz; -8 dB up to 5 GHz; -4 dB up to 7.5 GHz. Refer to Figure 2.
5 ps max -32 dB max up to 2.5 GHz; -26 dB max up to 5.0 GHz; -20 dB max up to 7.5 GHz; See Figure 3. -20 dB up to 3 GHz;
Notes: 1. The specified S parameters requirements are for switch component only, not including the test fixture effect. While the TRL calibration method is recommended, other calibration methods are allowed.
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PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout
0 SDD21 Zref=100 Ohms -1 -2
Differential Insertion Loss [dB]
-3 -4 -5 -6 -7 -8 -9 -10 0
1
2
3
4
5
Frequency, GHz
6
7
8
9
10
Figure 1: Illustration of differential insertion loss requirement.
0 SDD11 Zref=100 Ohms -5
Differential Return Loss [dB]
-10
-15
-20
-25
-30 0
1
2
3
4
5
Frequency, GHz
6
7
8
9
10
Figure 2: Illustration of differential return loss requirement.
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-10 SDD21 Zref=85 Ohms -15 Differential Near End Crosstalk, dB
-20
-25
-30
-35
-40
-45
0
1
2
3
4 5 Frequency, GHz
6
7
8
Figure 3: Illustration of different ial near end crosstalk requirement. Switch Test Fixture Requirements The test fixture for switch S-parameter measurement shall be designed and built to specific requirements, as described below, to ensure good measurement quality and consistency: * The test fixture shall be a FR4-based PCB of the microstrip structure; the dielectric thickness or stackup shall be about 4 mils. * The total thickness of the test fixture PCB shall be 1.57 mm (0.62"). * The measurement signals shall be launched into the switch from the top of the test fixture, capturing the through-hole stub effect. * Traces between the DUT and measurement ports (SMA or microprobe) should be uncoupled from each other, as much as possible. Therefore, the traces should be routed in such a way that traces will diverge from each other exiting from the switch pin field. * The trace lengths between the DUT and measurement port shall be minimized. The maximum trace length shall not exceed 1000 mils. The trace lengths between the DUT and measurement port shall be equal. * All of the traces on the test board and add-in card must be held to a characteristic impedance of 50 Ohms with a tolerance of +/- 7%. * SMA connector is recommended for ease of use. The SMA launch structure shall be designed to minimize the connection discontinuity from SMA to the trace. The impedance range of the SMA seen from a TDR with a 60 ps rise time should be within 50+/-7 ohms.
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PI3PCIE2612-A High Bandwidth, 6-Differential Channel 1:2 DP/PCIe Gen2 Display Mux, ATX Pinout Packaging Mechanical: 56-Contact TQFN (ZFE)
DATE: 03/03/06
DESCRIPTION: 56-contact, Thin Fine Pitch Quad Flat No-lead (TQFN) PACKAGE CODE: ZF56 DOCUMENT CONTROL #: PD-2024 REVISION: B
Ordering Information
Ordering Code PI3PCIE2612-AZFE Package Code ZF Package Description Pb-free & Green, 56-contact TQFN
Notes: * Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ * "E" denotes Pb-free and Green * Adding an "X" at the end of the ordering code denotes tape and reel packaging
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
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