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Si5323
P R E L I M I N A R Y D A TA S H E E T
PI N -P R O G R A M M A B L E P R E C I S I O N C L O C K M U L T I P L I E R /JI T T E R A T T E N U A T O R
Description
The Si5323 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5323 accepts dual clock inputs ranging from 8 kHz to 707 MHz and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. The Si5323 is based on Silicon Laboratories' 3rdgeneration DSPLL(R) technology, which provides anyrate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5323 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications.
Features
Selectable output frequencies ranging from 8 kHz to 1050 MHz Ultra-low jitter clock outputs with jitter generation as low as 0.3 ps rms (50 kHz-80 MHz) Integrated loop filter with selectable loop bandwidth (60 Hz to 8.4 kHz) Meets OC-192 GR-253-CORE jitter specifications Dual clock inputs w/manual or automatically controlled hitless switching Dual clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS) Support for ITU G.709 FEC ratios (255/238, 255/237, 255/236) LOL, LOS alarm outputs Pin-controlled output phase adjust Pin-programmable settings On-chip voltage regulator for 1.8, 2.5, or 3.3 V 10% operation Small size: 6 x 6 mm 36-lead QFN Pb-free, ROHS compliant
Applications
SONET/SDH OC-48/OC-192 line cards GbE/10GbE, 1/2/4/8/10GFC line cards ITU G.709 line cards Optical modules Test and measurement
Xtal or Refclock
CKIN1
CKOUT1
DSPLL
CKIN2
(R)
Signal Format CKOUT2 Disable/BYPASS
Loss of Signal Loss of Lock
Signal Detect
Control VDD (1.8, 2.5, or 3.3 V) GND Frequency Select Bandwidth Select Rate Select Manual/Auto Switch / Clock Select Latency Control
Preliminary Rev. 0.2 3/07
Copyright (c) 2007 by Silicon Laboratories
Si5323
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5323
Table 1. Performance Specifications
(VDD = 1.8, 2.5, or 3.3 V 10%, TA = -40 to 85 C)
Parameter Temperature Range Supply Voltage
Symbol TA VDD
Test Condition
Min -40 2.97 2.25 1.62
Typ 25 3.3 2.5 1.8 251
Max 85 3.63 2.75 1.98 279
Unit C V V V mA
Supply Current
IDD
fOUT = 622.08 MHz Both CKOUTs enabled LVPECL format output CKOUT2 disabled fOUT = 19.44 MHz Both CKOUTs enabled CMOS format output CKOUT2 disabled Tristate/Sleep Mode -- --
217 204
243 234
mA mA
-- 0.008 0.008
194 TBD -- --
220 TBD 707.35 1049.76
mA mA MHz MHz
Input Clock Frequency (CKIN1, CKIN2) Output Clock Frequency (CKOUT1, CKOUT2)
CKF CKOF
Input frequency and clock multiplication ratio pin-selectable from table of values using FRQSEL and FRQTBL settings. Consult Silicon Laboratories configuration software DSPLLsim or Any-Rate Precision Clock Family Reference Manual at www.silabs.com/timing for table selections.
Input Clocks (CKIN1, CKIN2) Differential Voltage Swing Common Mode Voltage CKNDPP CKNVCM 1.8V 10% 2.5V 10% 3.3V 10% Rise/Fall Time Duty Cycle CKNTRF CKNDC 20-80% Whichever is less 0.25 0.9 1.0 1.1 -- 40 50 Output Clocks (CKOUT1, CKOUT2) Common Mode Differential Output Swing Single Ended Output Swing VOCM VOD VSE LVPECL 100 load line-to-line VDD - 1.42 1.1 0.5 -- -- -- VDD - 1.25 1.9 0.93 V V V -- -- -- -- -- -- -- 1.9 1.4 1.7 1.95 11 60 -- VPP V V V ns % ns
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
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Preliminary Rev. 0.2
Si5323
Table 1. Performance Specifications (Continued)
(VDD = 1.8, 2.5, or 3.3 V 10%, TA = -40 to 85 C)
Parameter Rise/Fall Time Duty Cycle PLL Performance Jitter Generation
Symbol CKOTRF CKODC JGEN
Test Condition 20-80%
Min -- 45
Typ 230 -- 0.3
Max 350 55 TBD
Unit ps % ps rms
fOUT = 622.08 MHz, LVPECL output format 50 kHz-80 MHz 12 kHz-20 MHz
--
-- -- --
0.3 0.05 TBD TBD TBD TBD TBD TBD TBD TBD
TBD 0.1 TBD TBD TBD TBD TBD TBD TBD TBD
ps rms dB dB dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc
Jitter Transfer External Reference Jitter Transfer Phase Noise
JPK JPKEXTN CKOPN fOUT = 622.08 MHz 100 Hz offset 1 kHz offset 10 kHz offset 100 kHz offset 1 MHz offset
-- -- -- -- -- -- --
Subharmonic Noise Spurious Noise Package Thermal Resistance Junction to Ambient
SPSUBH SPSPUR
Phase Noise @ 100 kHz Offset Max spur @ n x F3 (n > 1, n x F3 < 100 MHz) Still Air
JA
--
38
--
C/W
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
Table 2. Absolute Maximum Ratings
Parameter DC Supply Voltage LVCMOS Input Voltage Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 k) ESD MM Tolerance Latch-Up Tolerance Symbol VDD VDIG TJCT TSTG Value -0.5 to 3.6 -0.3 to (VDD + 0.3) -55 to 150 -55 to 150 2 200 JESD78 Compliant Unit V V C C kV V
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
Preliminary Rev. 0.2
3
Si5323
155.52 MHz in, 622.08 MHz out
0 -20 Phase Noise (dBc/Hz) -40 -60 -80 -100 -120 -140 -160 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency (Hz)
Figure 1. Typical Phase Noise Plot
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Preliminary Rev. 0.2
Si5323
Figure 2. Si5323 Typical Application Circuit
Preliminary Rev. 0.2
5
Si5323
1. Functional Description
The Si5323 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5323 accepts dual clock inputs ranging from 8 kHz to 707 MHz and generates two frequencymultiplied clock outputs ranging from 8 kHz to 1050 MHz. The two input clocks are at the same frequency and the two output clocks are at the same frequency. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. In addition to providing clock multiplication in SONET and datacom applications, the Si5323 supports SONET-to-datacom frequency translations. Silicon Laboratories offers a PCbased software utility, DSPLLsim, that can be used to look up valid Si5323 frequency translations. This utility can be downloaded from www.silabs.com/timing. This information is also available in the Any-Rate Precision Clock Family Reference Manual, also available from www.silabs.com/timing. The Si5323 is based on Silicon Laboratories' 3rdgeneration DSPLL(R) technology, which provides anyrate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5323 PLL loop bandwidth is selectable via the BWSEL[1:0] pins and supports a range from 60 Hz to 8.4 kHz. The DSPLLsim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio. The Si5323 supports hitless switching between the two input clocks in compliance with GR-253-CORE and GR1244-CORE that greatly minimizes the propagation of phase transients to the clock outputs during an input clock transition (<200 ps typ). Manual and automatic revertive and non-revertive input clock switching options are available via the AUTOSEL input pin. The Si5323 monitors both input clocks for loss-of-signal and provides a LOS alarm when it detects missing pulses on either input clock. The device monitors the lock status of the PLL. The lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. The Si5323 provides a digital hold capability that allows the device to continue generation of a stable output clock when the selected input reference is lost. During digital hold, the DSPLL generates an output frequency based on a historical average that existed a fixed amount of time before the error event occurred, eliminating the effects of phase and frequency transients that may occur immediately preceding digital hold. The Si5323 has two differential clock outputs. The electrical format of the clock outputs is programmable to support LVPECL, LVDS, CML, or CMOS loads. If not required, the second clock output can be powered down to minimize power consumption. The phase difference between the selected input clock and the output clocks is adjustable in 200 ps increments for system skew control. For system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8, 2.5, or 3.3 V supply.
1.1. External Reference
An external, 38.88 MHz clock or a low-cost 114.285 MHz 3rd overtone crystal is used as part of a fixed-frequency oscillator within the DSPLL. This external reference is required for the device to perform jitter attenuation. Silicon Laboratories recommends using a high-quality crystal from TXC (www.txc.com.tw), part number 7MA1400014. An external 38.88 MHz clock from a high quality OCXO or TCXO can also be used as a reference for the device. In digital hold, the DSPLL remains locked to this external reference. Any changes in the frequency of this reference when the DSPLL is in digital hold will be tracked by the output of the device. Note that crystals can have temperature sensitivities.
1.2. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual (FRM) for more detailed information about the Si5323. The FRM can be downloaded from www.silabs.com/timing. Silicon Laboratories has developed a PC-based software utility called DSPLLsim to simplify device configuration, including frequency planning and loop bandwidth selection. This utility can be downloaded from www.silabs.com/timing.
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Preliminary Rev. 0.2
Si5323
2. Pin Descriptions: Si5323
CKOUT1- CKIN1- CKOUT2+ CKOUT2- CKOUT1+ 27 FRQSEL3 26 FRQSEL2 25 FRQSEL1 24 FRQSEL0 23 BWSEL1 22 BWSEL0 21 CS_CA 20 INC 19 DEC 10 11 12 13 14 15 16 17 18 VDD RATE0 DBL2_BY RATE1 CKIN2+ CKIN1+ CKIN2- LOL SFOUT0 SFOUT1
VDD
36 35 34 33 32 31 30 29 28 RST 1 FRQTBL 2 C1B 3 C2B 4 VDD 5 XA 6 XB 7
NC
GND Pad
GND 8 AUTOSEL 9
Pin assignments are preliminary and subject to change. Pin # 1 Pin Name RST I/O I Signal Level LVCMOS
Table 3. Si5323 Pin Descriptions
Description External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state. Clock outputs are tristated during reset. After rising edge of RST signal, the Si5323 will perform an internal self-calibration. This pin has a weak pull-up. Frequency Table Select. Selects SONET/SDH, datacom, or SONET/SDH to datacom frequency table. L = SONET/SDH M = Datacom H = SONET/SDH to Datacom This pin has a weak pull-down. CKIN1 Loss of Signal. Active high loss-of-signal indicator for CKIN1. Once triggered, the alarm will remain active until CKIN1 is validated. 0 = CKIN1 present 1 = LOS on CKIN1 CKIN2 Loss of Signal. Active high loss-of-signal indicator for CKIN2. Once triggered, the alarm will remain active until CKIN2 is validated. 0 = CKIN2 present 1 = LOS on CKIN2
2
FRQTBL
I
3-Level
3
C1B
O
LVCMOS
4
C2B
O
LVCMOS
Preliminary Rev. 0.2
GND
7
Si5323
Table 3. Si5323 Pin Descriptions (Continued)
Pin # 5, 10, 32 Pin Name VDD I/O VDD Signal Level Supply Description Supply. The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capacitors should be associated with the following VDD pins: 5 0.1 F 10 0.1 F 32 0.1 F A 1.0 F should be placed as close to device as is practical. External Crystal or Reference Clock. External crystal should be connected to these pins to use internal oscillator based reference. If external reference is used, apply reference clock to XA input and leave XB pin floating. External reference must be from a high-quality clock source (TCXO, OCXO). Frequency of crystal or external clock is set by the RATE pin. Ground. Must be connected to system ground. Minimize the ground path impedance for optimal performance of this device. Manual/Automatic Clock Selection. Three level input that selects the method of input clock selection to be used. L = Manual M = Automatic non-revertive H = Automatic revertive External Crystal or Reference Clock Rate. Three level input that selects the type and rate of external crystal or reference clock to be applied to the XA/XB port. RATE[1:0] LM = 38.88 MHz external clock MM = 114.285 MHz 3rd OT Crystal HH = Converts part to Si5322 All Others = Reserved Clock Input 2. Differential input clock. This input can also be driven with a single-ended signal. Input frequency selected from a table of values. The same frequency must be applied to CKIN1 and CKIN2. 3-Level Output 2 Disable/Bypass Mode Control. Controls enable of CKOUT2 divider/output buffer path and PLL bypass mode. L = CKOUT2 enabled M = CKOUT2 disabled H = Bypass mode with CKOUT2 enabled
7 6
XB XA
I
Analog
8, 31
GND
GND
Supply
9
AUTOSEL
I
3-Level
11 15
RATE0 RATE1
I
3-Level
12 13
CKIN2+ CKIN2-
I
14
DBL2_BY
I
8
Preliminary Rev. 0.2
Si5323
Table 3. Si5323 Pin Descriptions (Continued)
Pin # 16 17 Pin Name CKIN1+ CKIN1- I/O I Signal Level Multi Description Clock Input 1. Differential input clock. This input can also be driven with a single-ended signal. Input frequency selected from a table of values. The same frequency must be applied to CKIN1 and CKIN2. PLL Loss of Lock Indicator. This pin functions as the active high PLL loss of lock indicator. 0 = PLL locked 1 = PLL unlocked Latency Decrement. A pulse on this pin decreases the input to output device latency by 1/fOSC (approximately 200 ps). There is no limit on the range of latency adjustment by this method. If both INC and DEC are tied high, phase buildout is disabled and the device maintains a fixed-phase relationship between the selected input clock and the output clock during an input clock transition. Detailed operations and timing characteristics for this pin may be found in the Any-Rate Precision Clock Family Reference Manual. This pin has a weak pull-down. Latency Increment. A pulse on this pin increases the input to output device latency by 1/fOSC (approximately 200 ps). There is no limit on the range of latency adjustment by this method. If both INC and DEC are tied high, phase buildout is disabled and the device maintains a fixed-phase relationship between the selected input clock and the output clock during an input clock transition. Detailed operations and timing characteristics for this pin may be found in the Any-Rate Precision Clock Family Reference Manual. This pin has a weak pull-down. Input Clock Select/Active Clock Indicator. If manual clock selection mode is chosen (AUTOSEL = L), this pin functions as the manual input clock selector. This input is internally deglitched to prevent inadvertent clock switching during changes in the CS input state. 0 = Select CKIN1 1 = Select CKIN2 If automatic clock selection mode is chosen (AUTOSEL = M or H), this pin indicates which of the two input clocks is currently the active clock. If alarms exist on both CKIN1 and CKIN2, indicating that the digital hold state has been entered, CA will indicate the last active clock that was used before entering the hold state. 0 = CKIN1 active input clock 1 = CKIN2 active input clock
18
LOL
O
LVCMOS
19
DEC
I
LVCMOS
20
INC
I
LVCMOS
21
CS_CA
I/O
LVCMOS
Preliminary Rev. 0.2
9
Si5323
Table 3. Si5323 Pin Descriptions (Continued)
Pin # 23 22 Pin Name BWSEL1 BWSEL0 I/O I Signal Level 3-Level Description Bandwidth Select. Three level inputs that select the DSPLL closed loop bandwidth. Detailed operations and timing characteristics for these pins may be found in the Any-Rate Precision Clock Family Reference Manual. Multiplier Select. Three level inputs that select the input clock and clock multiplication ratio, depending on the FRQTBL setting. Consult the Any-Rate Precision Clock Family Reference Manual or DSPLLsim configuration software for settings, both available for download at www.silabs.com/timing. Clock Output 1. Differential output clock with a frequency selected from a table of values. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. Signal Format Select. Three level inputs that select the output signal format (common mode voltage and differential swing) for both CKOUT1 and CKOUT2. SFOUT[1:0] HH HM HL MH MM ML LH LM LL 34 35 CKOUT2- CKOUT2+ O Multi Signal Format Reserved Reserved CML LVPECL Reserved LVDS CMOS Tristate/Sleep Reserved
27 26 25 24
FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0
I
3-Level
29 28
CKOUT1- CKOUT1+
O
Multi
33 30
SFOUT0 SFOUT1
I
3-Level
Clock Output 2. Differential output clock with a frequency selected from a table of values. Output signal format is selected by SFOUT pins. Output is differential for LVPECL, LVDS, and CML compatible modes. For CMOS format, both output pins drive identical single-ended clock outputs. No Connect. These pins must be left unconnected for normal operation. Ground Pad. The ground pad must provide a low thermal and electrical impedance to a ground plane.
36 GND PAD
NC GND
-- GND
-- Supply
10
Preliminary Rev. 0.2
Si5323
3. Ordering Guide
Ordering Part Number SI5323-B-GM Package 36-Lead 6 x 6 mm QFN Temperature Range -40 to 85 C
Preliminary Rev. 0.2
11
Si5323
4. Package Outline: 36-Lead QFN
Figure 3 illustrates the package details for the Si5323. Table 4 lists the values for the dimensions shown in the illustration.
Figure 3. 36-Pin Quad Flat No-lead (QFN)
Table 4. Package Dimensions
Symbol Min A A1 b D D2 e E E2 3.95 3.95 0.80 0.00 0.18 Millimeters Nom 0.85 0.01 0.23 6.00 BSC 4.10 0.50 BSC 6.00 BSC 4.10 4.25 4.25 Max 0.90 0.05 0.30 L aaa bbb ccc ddd eee Symbol Min 0.50 -- -- -- -- -- -- Millimeters Nom 0.60 -- -- -- -- -- -- Max 0.75 12 0.10 0.10 0.05 0.10 0.05
Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VJJD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
12
Preliminary Rev. 0.2
Si5323
5. Recommended PCB Layout
Figure 4. PCB Land Pattern Diagram
Preliminary Rev. 0.2
13
Si5323
Table 5. PCB Land Pattern Dimensions
Dimension e E D E2 D2 GE GD X Y ZE ZD -- -- 4.00 4.00 4.53 4.53 -- 0.89 REF. 6.31 6.31 MIN 0.50 BSC. 5.42 REF. 5.42 REF. 4.20 4.20 -- -- 0.28 MAX
Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Notes (Solder Mask Design): 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Notes (Stencil Design): 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. Notes (Card Assembly): 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
14
Preliminary Rev. 0.2
Si5323
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Changed LVTTL to LVCMOS in Table 2, "Absolute Maximum Ratings," on page 3. Added Figure 1, "Typical Phase Noise Plot," on page 4. Updated Figure 2, "Si5323 Typical Application Circuit," on page 5 to show external reference interface. Added RATE0 and expanded the RATE[1:0] description in 2. `Pin Descriptions: Si5323". Updated 3."Ordering Guide" on page 11. Added 5. `Recommended PCB Layout".
Preliminary Rev. 0.2
15
Si5323
CONTACT INFORMATION
Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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Preliminary Rev. 0.2

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