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MDT10P10
MDT10P10
1. General Description
This EPROM-Based 8-bit micro-controller uses a fully static CMOS design technology combines higher speeds and smaller size with the low power and high noise immunity. On chip memory system includes 1.0 K words of ROM, and 32 bytes of static RAM. u Power edge-detector Reset u Sleep Mode for power saving u 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler u 4 types of oscillator can be selected by programming option (Internal Capacitor about 10p ): RCLow cost RC oscillator LFXTLow frequency crystal oscillator XTALStandard crystal oscillator HFXTHigh frequency crystal oscillator u 4 oscillator start-up time can be selected by programming option: 150 s, 20 ms, 40 ms, 80 ms u On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely u 12 I/O pins with their own independent direction control
2. Features
The followings are some of the features on the hardware and software : u u u u Fully CMOS static design 8-bit data bus On chip ROM size :1 K words Internal RAM size : 32 bytes (25 general purpose registers, 7 special registers) u 36 single word instructions u 14-bit instructions u 2-level stacks u Operating voltage : 2.3V ~ 5.5 V u Operating frequency : 0 ~ 20 MHz u The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instructions u Addressing modes include direct, indirect and relative addressing modes u Power-on Reset
3. Applications
The application areas of this MDT10P10 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral ... etc.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 1
2004/1 VER 1.2
MDT10P10
4. Pin Assignment
PA2 PA3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 PA1 PA0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4
5. Pin Function Description
Pin Name PA0~PA3 PB0~PB7 RTCC /MCLR OSC1 OSC2 Vdd Vss I/O I/O I/O I I I O Function Description Port A, TTL input level Port B, TTL input level Real Time Clock/Counter, Schmitt Trigger input levels Master Clear, Schmitt Trigger input levels Oscillator Input Oscillator Output Power supply Ground
6. Memory Map
(A) Register Map Address 00 01 02 03 04 05 06 07~1F Description Indirect Addressing Register RTCC PC STATUS MSR Port A Port B Internal RAM, General Purpose Register
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P. 2
2004/1 VER 1.2
MDT10P10
(1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 (3) PC (Program Counter) : R2
Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTIW, RET --- from STACK
A9
A8
A7~A0
Write PC, JUMP, CALL --- from STATUS b5 (ROM 1K) LJUMP, LCALL --- from instruction word RTIW, RET --- from STACK
Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTIW, RET --- from STACK
(4) STATUS (Status register) : R3 Bit 0 1 2 3 4 5 Symbol C HC Z PF TF page 0 Carry bit Half Carry bit Zero bit Power loss Flag bit Time overflow Flag bit Page select bit : 0 : 000H --- 1FFH 1 : 200H --- 3FFH 6X7 XX General purpose bit Function
(5) MSR (Memory Select Register) : R4 (6) PORT A : R5 PA3~PA0, I/O Register (7) PORT B : R6 PB7~PB0, I/O Register
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P. 3
2004/1 VER 1.2
MDT10P10
(8) TMR (Time Mode Register) Bit Symbol Prescaler Value Function RTCC rate WDT rate 1:1 1:2 000 1:2 1:4 001 1:4 1:8 010 1:8 1 : 16 011 1 : 16 1 : 32 100 1 : 32 1 : 64 101 1 : 64 1 : 128 110 1 : 128 1 : 256 111 Prescaler assignment bit : 0 X RTCC 1 X Watchdog Timer RTCC signal Edge : 0 X Increment on low-to-high transition on RTCC pin 1 X Increment on high-to-low transition on RTCC pin RTCC signal set : 0 X Internal instruction cycle clock 1 X Transition on RTCC pin
2X0
PS2X0
3
PSC
4
TCE
5
TCS
(9) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is "write-only" x"0", I/O pin in output mode; x"1", I/O pin in input mode. (10) EPROM Option by writer programming : Oscillator Type RC Oscillator Oscillator Start-up Time 150 s,20ms,40ms,80ms 20 ms,40ms,80ms 20ms,40 ms,80ms 40 ms,80 ms
HFXT Oscillator XTAL Oscillator LFXT Oscillator
Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time
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P. 4
2004/1 VER 1.2
MDT10P10
Power Edge Detect PED Disable PED Enable Security bit Security Disable Security Enable
The default EPROM security is disable. Once the IC was set to enable, it can not to set to enable again. (B) Program Memory Address 000-3FF 3FF Description Program memory for MDT10P10 The starting address of the power on, external reset or WDT time-out reset for MDT10P10
7. Reset Condition for all Registers
Register CPIO A CPIO B TMR IAR RTCC PC STATUS MSR PORT A PORT B Address 00h 01h 02h 03h 04h 05h 06h Power-On Reset 1111 1111 1111 1111 - - 11 1111 xxxx xxxx xxxx xxxx 1111 1111 0001 1xxx 111x xxxx - - - - xxxx xxxx xxxx /MCLR or WDT Reset 1111 1111 1111 1111 - - 11 1111 uuuu uuuu uuuu uuuu 1111 1111 000# #uuu 111u uuuu - - - - uuuu uuuu uuuu
Note : uxunchanged, xxunknown, - xunimplemented, read as "0" #xvalue depends on the condition of the following table Condition /MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP Status: bit 4 u 1 0 0 Status: bit 3 u 0 1 0
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P. 5
2004/1 VER 1.2
MDT10P10
8. Instruction Set
Instruction Code Mnemonic Operands Function No operation Clear Watchdog timer Sleep mode Load W to TMODE register Return R Control I/O port register Store W to register Load register Load immediate to W Operating None 0/WT 0/WT, stop OSC W/TMODE Stack/PC W/CPIO W/R R/t I/W [R(0~3) R(4~7)]/t R + 1/t R + 1/t W + R/t R W/t (R+/W+1/t) R 1/t R 1/t R a W/t i a W/W R a W/t i a W/W R o W/t i o W/W /R/t R(n) /R(n-1), C/R(7), R(0)/C R(n)/r(n+1), C/R(0), R(7)/C 0/W r TF, PF TF, PF None None None None Z None None Z None C, HC, Z C, HC, Z Z None Z Z Z Z Z Z Z C Status
010000 00000000 NOP 010000 00000001 CLRWT 010000 00000010 SLEEP 010000 00000011 TMODE 010000 00000100 RET 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr CPIO STWR R LDR R, t LDWI I
SWAPR R, t Swap halves register INCR R, t Increment register
INCRSZ R, t Increment register, skip if zero ADDWR R, t Add W and register SUBWR R, t Subtract W from register DECR R, t Decrement register DECRSZ R, t Decrement register, skip if zero ANDWR R, t AND W and register ANDWI i IORWR R, t IORWI XORWI RRR i i R, t AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Exclu. OR W and immediate Rotate right register
XORWR R, t Exclu. OR W and register COMR R, t Complement register
010101 trrrrrrr
RLR
R, t
Rotate left register
C
010000 1xxxxxxx
CLRW
Clear working register
Z
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P. 6
2004/1 VER 1.2
MDT10P10
Instruction Code 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr 1000nn nnnnnnnn 1010nn nnnnnnnn 110000 nnnnnnnn 110001 iiiiiiii 11001n nnnnnnnn Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ` a' Exclusive ` o' Logic AND ` a' b t : : Bit position Target 0: Working register 1 : General register General register address Carry flag Half carry Zero flag Complement Don' care t Immediate data ( 8 bits ) Immediate address Mnemonic Operands CLRR BCR BSR R R, b R, b Bit clear Bit set Function Clear register Operating 0/R 0/R(b) 1/R(b) Skip if R(b)=0 Skip if R(b)=1 n/PC, PC+1/Stack n/PC n/PC, PC+1/Stack Stack/PC, i/W n/PC Status Z None None None None None None None None None
BTSC R, b Bit Test, skip if clear BTSS R, b Bit Test, skip if set LCALL n LJUMP n CALL RTIW JUMP n i n Long CALL subroutine Long JUMP to address Call subroutine Return, place immediate to W JUMP to address
R C HC Z / x i n
: : : : : : : :
9. Electrical Characteristics
(A) Operating Voltage & Frequency Vdd R 2.3V ~ 5.5 V FrequencyR Hz ~ 20 MHz 0
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P. 7
2004/1 VER 1.2
MDT10P10
(B) Input Voltage @ Vddx 5.0 V, Temperaturex25 J Port Vil Vih PA, PB RTCC, /MCLR PA, PB Min. Vss Vss 2.0 V Max. 1.0 V 1.0V Vdd
RTCC, /MCLR 3.2 V Vdd Threshold Voltage : Port A, Port B Vthx 1.45V RTCC Vilx 1.2 V, Vihx 3.0 V (Schmitt Trigger) /MCLR Vilx 1.6 V, Vihx 3.0 V (Schmitt Trigger) (C) Output VoltageR @ Vddx 5.0 V, Temperaturex25 J, the typical value as followings : PA, PB Port Iohx 20.0 mA Iolx 20.0 mA Iohx 5.0 mA Iolx 5.0 mA (D) Leakage Current @ Vddx 5.0 V, Temperaturex25 J, the typical value as followings : Iil Iih (E) Sleep Current @WDTDisable, Temperaturex25 J, the typical value as followings : Vddx 2.3 V Vddx 3.0 V Vddx 4.0 V Vddx 5.0 V Vddx 5.5V IddO 1.0 A IddO 1.0 A IddO 1.0 A IddO 1.0 A IddO 45A 0.1A (Max.) I 0.1A (Max.) Vohx 3.3 V Volx 0.44 V Vohx 4.2 V Volx 0.12 V
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P. 8
2004/1 VER 1.2
MDT10P10
@WDTEnable, Temperaturex25 J, the typical value as followings : Vddx 2.3 V Vddx 3.0 V Vddx 4.0 V Vddx 5.0 V Vddx 6.3 V (F) Operating Current Temperaturex25 J, the typical value as followings : (i) OSC TypexRC ( Internal capacitor 10p ) ; WDTEnable; @ Vddx 5.0 V Cext. (F) Rext. (Ohm) 4.7 K 10.0 K 0P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 3P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 20P 47.0 K 100.0 K 300.0 K 470.0 K Frequency (Hz) 10.0 M 5.6 M 1.3 M 630 K 210 K 130 K 9.0 M 4.8 M 1.1 M 530 K 180 K 110 K 5.4 M 2.7 M 620 K 290 K 100 K 63 K Current (A) 940 A 540 A 200 A 150 A 120 A 115 A 820 A 470 A 190 A 150 A 120 A 115 A 530 A 320 A 160 A 135 A 120 A 115 A IddO 1.5 A Iddx 3.3 A Iddx 8.0 A Iddx 16.0 A Iddx 29.0 A
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P. 9
2004/1 VER 1.2
MDT10P10
Cext. (F) Rext. (Ohm) 4.7 K 10.0 K 100P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 300P 47.0 K 100.0 K 300.0 K 470.0 K (ii) Frequency (Hz) 2.0 M 1.0 M 220 K 105 K 36 K 22 K 915 K 450 K 99 K 46 K 15 K 9.5 K Current (A) 265 A 180 A 120 A 110 A 105 A 104 A 170 A 135 A 106 A 102 A 99 A 98 A
OSC TypexLF (Internal C=10 p); WDTDisable Voltage/Frequency 2.3 V 3.0 V 4.0 V 5.0 V 5.5 V 6.3 V 32 K 3.3 A 11 A 44 A 84 A 110 A 125 A
@2.4V
455 K 19 A 33 A 70 A 130 A 155 A 165 A
@2.4V
1M 27 A 44 A 80 A 121 A 140 A 200 A
Sleep O1.0 A O1.0 A O1.0 A O1.0 A O45 A O120 A
(iii) OSC TypexXT (Internal C=10 p); WDTEnable Voltage/Frequency 2.3 V 3.0 V 4.0 V 5.0 V 6.3 V 1M 35 A 65 A 130 A 220 A 400 A 4M 100 A 160 A 290 A 440 A 640 A 10 M 220 A 370 A 590 A 860 A 1.2 mA Sleep 1.5 A 3.3 A 8.0 A 16 A 29 A
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 10
2004/1 VER 1.2
MDT10P10
(iv) OSC TypexHF (Internal C=10 p); WDTEnable Voltage/Frequency 2.3 V 3.0 V 4.0 V 5.0 V 6.3 V 4M 110 A 175 A 340 A 520 A 770 A 10 M 265 A 400 A 630 A 950 A 1.3 mA 20 M X 750 A 1.2 mA 1.7 mA 2.4 mA Sleep 1.5 A 3.3 A 8.0 A 16 A 29 A
(G) The basic WDT time-out cycle time @ Vdd=5.0v ,Temperaturex25 J, the typical value as followings : Voltage (V) 2.3 3.0 4.0 5.0 6.3 Basic WDT time-out cycle time (ms) 28.0 24.0 21.0 19.0 17.0
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P. 11
2004/1 VER 1.2
MDT10P10
(H) Reset & Watchdog Timer Timing
/MCLR, WATCHDOG timer and internal POR timing Vdd
/MCLR Internal POR Tost OST Time-out
Internal Reset
WDT reset Tmclr I/O pin Tost Tio Twdt Tio
Symbol Tost Tio Tmclr Twdt
Description Oscillator start up time I/O floating from /MCLR low /MCLR pulse width Watchdog timer time-out period (No postscaler)
Min 15
Typ 20
Max 24 100
Unit ms ns ns
500 15 20 24
ms
(I) Power Edge-detector Reset Voltage (Not in Sleep Mode), @ Vddx 5.0 V VprO 1.8~2.0 V Vpr R Vdd (Power Supply)
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P. 12
2004/1 VER 1.2
MDT10P10
(J) MCLRB FilterG Vdd=5.0v @ Wm O1.0us Wm : Filter pulse width (low) in /MCLR pin.
10. Port A and Port B Equivalent Circuit
Working Register
D QB
Data I/P
I/O Control
CK
I/O Control Latch
Q
Port I/O Pin
D
Write
CK
Data O/P Latch
Q
Data Bus
QB D
Read
Data I/P Latch
CK
Input Resistor TTL Input Level
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 13
2004/1 VER 1.2
MDT10P10
11. MCLRB and RTCC Input Equivalent Circuit
R U 1 K
MCLRB Schmitt Trigger
R U 1 K
RTCC Schmitt Trigger
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 14
2004/1 VER 1.2
MDT10P10
12. Block Diagram
Stack Two Levels
EPROM 1024 4 (MDT10P10) N 1
RAM 25 N 8 Port A
Port PA0~PA3 4 bits
9 or10 bits 9 or 10 bits 14 bits
Program Counters
Instruction Register
Special Register
OSC1 OSC2 MCLR Instruction Decoder
D0~D7
Port B Control Circuit
Port PB0 ~PB7 8 bits
Oscillator Circuit
Data 8-bit
Power on Reset Power Down Reset Working Register ALU Status Register
8-bit Timer/Counter
Prescale
WDT/OST Timer
RTCC
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P. 15
2004/1 VER 1.2
MDT10P10
13. Internal Capacitor Selection For Crystal Oscillator
@ Vddx 2.3 V~5.5 V , C1=C2=10P
To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor range can be recommended for reference, but the higher capacitance also increases the start-up time.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 16
2004/1 VER 1.2

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