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| M58LT128HST M58LT128HSB 128 Mbit (8 Mb x16, multiple bank, multilevel interface, burst) 1.8 V supply, secure Flash memories Features Supply voltage - VDD = 1.7 V to 2.0 V for Program, Erase and Read - VDDQ = 2.7 V to 3.6 V for I/O buffers - VPP = 9 V for fast program Synchronous/Asynchronous Read - Synchronous Burst Read mode: 52 MHz - Asynchronous Page Read mode - Random access: 85 ns Synchronous Burst Read Suspend Programming time - 2.5 s typical word program time using Buffer Enhanced Factory Program command Memory organization - Multiple bank memory array: 8-Mbit banks - Parameter blocks (top or bottom location) Dual operations - program/erase in one bank while read in others - No delay between Read and Write operations Block protection - All blocks protected at power-up - Any combination of blocks can be protected with zero latency - Absolute write protection with VPP = VSS Security - Software security features - 64-bit unique device number - 2112-bit user programmable OTP Cells Common flash interface (CFI) 100 000 program/erase cycles per block BGA TBGA64 (ZA) 10 x 13 mm Electronic signature - Manufacturer code: 20h - Top device codes: M58LT128HST: 88D6h - Bottom device codes M58LT128HSB: 88D7h TBGA64 package - ECOPACK(R) available December 2007 Rev 3 1/110 www.numonyx.com 1 Contents M58LT128HST, M58LT128HSB Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 Address inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data inputs/outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VPP program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VSSQ ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 3.2 3.3 3.4 3.5 3.6 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 4.2 4.3 4.4 4.5 Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/110 M58LT128HST, M58LT128HSB Contents 4.6 4.7 4.8 4.9 4.10 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Blank Check command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Buffer Enhanced Factory Program command . . . . . . . . . . . . . . . . . . . . . 24 4.10.1 4.10.2 4.10.3 Setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Program and verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.11 4.12 4.13 4.14 4.15 4.16 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Block Protect command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Block Unprotect command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Program/Erase Controller status bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . 33 Erase Suspend status bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Erase/Blank Check status bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Program status bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 VPP status bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Program Suspend status bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Block Protection status bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Bank Write/Multiple Word Program status bit (SR0) . . . . . . . . . . . . . . . . 35 6 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Read Select bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 X-Latency bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Wait Polarity bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data Output Configuration bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Wait Configuration bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Burst Type bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Valid Clock Edge bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Wrap Burst bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3/110 Contents M58LT128HST, M58LT128HSB 6.9 Burst length bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7 Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.1 7.2 7.3 Asynchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Synchronous Burst Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.2.1 Synchronous Burst Read Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Single Synchronous Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8 9 Dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 47 Block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.1 9.2 9.3 9.4 Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Protected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Unprotected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Protection operations during Erase Suspend . . . . . . . . . . . . . . . . . . . . . . 50 10 11 12 13 14 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 51 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Appendix B Common Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Appendix C Flowcharts and pseudo codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Appendix D Command Interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4/110 M58LT128HST, M58LT128HSB List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Factory commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Protection Register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 X-Latency Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Program/erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 DC characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 DC characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Asynchronous Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Synchronous Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Reset and power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Top boot block addresses, M58LT128HST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Bottom boot block addresses, M58LT128HSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Protection Register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Burst Read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Bank and Erase Block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Bank and Erase Block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Bank and Erase Block region 2 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Command Interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Command Interface states - modify table, next output state . . . . . . . . . . . . . . . . . . . . . . 103 Command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Command interface states - lock table, next output state . . . . . . . . . . . . . . . . . . . . . . . . 107 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5/110 List of figures M58LT128HST, M58LT128HSB List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TBGA64 package connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . 10 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 X-latency and data output configuration example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Asynchronous random access Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Asynchronous Page Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Synchronous Burst Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Single Synchronous Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Synchronous Burst Read Suspend AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Clock input AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Reset and power-up AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, bottom view package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Blank Check flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Buffer Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Program Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 94 Block Erase flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Erase Suspend & Resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Protect/Unprotect operation flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Protection Register Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 98 Buffer Enhanced Factory Program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . 99 6/110 M58LT128HST, M58LT128HSB Description 1 Description The M58LT128HST/B are 128 Mbit (8 Mbit x 16) non-volatile secure Flash memories. They may be erased electrically at block level and programmed in system on a word-by-word basis using a 1.7 V to 2.0 V VDD supply for the circuitry and a 2.7 V to 3.6 V VDDQ supply for the Input/Output pins. An optional 9 V VPP power supply is provided to accelerate factory programming. The devices feature an asymmetrical block architecture, with an array of 131 blocks, divided into 8 Mbit banks. There are 15 banks each containing 8 main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16 Kwords and 7 main blocks of 64 Kwords. The multiple bank architecture allows dual operations, while programming or erasing in one bank, Read operations are possible in other banks. Only one bank at a time is allowed to be in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory map is shown in Figure 3. The parameter blocks are located at the top of the memory address space for the M58LT128HST, and at the bottom for the M58LT128HSB. Each block can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage VDD. There is a buffer-enhanced factory programming command available to accelerate programming. Program And Erase Commands Are Written To The command interface of the memory. An internal Program/Erase Controller manages the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports Synchronous Burst Read and Asynchronous Read from all blocks of the memory array; at power-up the device is configured for Asynchronous Read. In Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to 52 MHz. The Synchronous Burst Read operation can be suspended and resumed. The device features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. The M58LT128HST/B features an instant, individual block protection scheme that allows any block to be protected or unprotected with no latency, enabling instant code and data protection. They can be protected individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP VPPLK all blocks are protected against program or erase. All blocks are protected at powerup. 7/110 Description M58LT128HST, M58LT128HSB The device includes 17 Protection Registers and 2 Protection Register locks, one for the first Protection Register and the other for the 16 one-time-programmable (OTP) Protection Registers of 128 bits each. The first Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by Numonyx, and a 64 bit segment OTP by the user. The user programmable segment can be permanently protected. Figure 4, shows the Protection Register memory map. The M58LT128HST/B also has a full set of software security features that are not described in this datasheet, but are documented in a dedicated application note. For further information, please contact Numonyx. The M58LT128HST/B are offered in a TBGA64, 10 x 13 mm, 1 mm pitch package. They are supplied with all the bits erased (set to '1'). 8/110 M58LT128HST, M58LT128HSB Figure 1. Logic diagram VDD VDDQ VPP 16 A0-A22 W E G RP L K M58LT128HST M58LT128HSB WAIT DQ0-DQ15 Description VSS VSSQ AI12887 Table 1. Signal names Function Address inputs Data input/outputs, command inputs Chip Enable Output Enable Write Enable Reset Clock Latch Enable Wait Supply voltage Supply voltage for input/output buffers Optional supply voltage for fast program & erase Ground Ground input/output supply Not Connected Internally Do Not Use Input Direction Inputs I/O Input Input Input Input Input Input Output Input Input Input Signal name A0-A22 DQ0-DQ15 E G W RP K L WAIT VDD VDDQ VPP VSS VSSQ NC DU 9/110 Description Figure 2. M58LT128HST, M58LT128HSB TBGA64 package connections (top view through package) 1 2 3 4 5 6 7 8 A A0 A5 A7 VPP A12 VDD A17 A21 B A1 VSS A8 E A13 NC A18 WAIT C A2 A6 A9 A11 A14 NC A19 A20 D A3 A4 A10 RP NC NC A15 A16 E DQ8 DQ1 DQ9 DQ3 DQ4 NC DQ15 NC F K DQ0 DQ10 DQ11 DQ12 NC NC G G A22 NC DQ2 VDDQ DQ5 DQ6 DQ14 W H L NC VDD VSSQ DQ13 VSS DQ7 NC AI10270b 10/110 M58LT128HST, M58LT128HSB Table 2. Bank architecture Bank size 8 Mbits 8 Mbits 8 Mbits 8 Mbits ---Parameter blocks 4 blocks of 16 Kwords ---- Description Number Parameter bank Bank 1 Bank 2 Bank 3 ---- Main blocks 7 blocks of 64 Kwords 8 blocks of 64 Kwords 8 blocks of 64 Kwords 8 blocks of 64 Kwords ---8 blocks of 64 Kwords 8 blocks of 64 Kwords Bank 14 Bank 15 8 Mbits 8 Mbits - Figure 3. Memory map M58LT128HST - Top Boot Block Address lines A0-A16 000000h 00FFFFh 64 KWord 8 Main Blocks 64 KWord Parameter Bank M58LT128HSB - Bottom Boot Block Address lines A0-A16 000000h 003FFFh 00C000h 00FFFFh 010000h 01FFFFh 070000h 07FFFFh 080000h 08FFFFh Bank 1 0F0000h 0FFFFFh 100000h 10FFFFh Bank 2 170000h 17FFFFh 180000h 18FFFFh Bank 3 1F0000h 1FFFFFh 7 Main Blocks 64 KWord 16 KWord 4 Parameter Blocks Bank 15 16 KWord 780000h 78FFFFh 7F0000h 7FFFFFh 64 KWord 8 Main Blocks 64 KWord 64 KWord 64 KWord 64 KWord 8 Main Blocks 64 KWord 64 KWord 8 Main Blocks 16 KWord 4 Parameter Blocks 16 KWord 64 KWord 7 Main Blocks 64 KWord 64 KWord 8 Main Blocks Bank 15 070000h 07FFFFh 600000h 60FFFFh Bank 3 670000h 67FFFFh 680000h 68FFFFh Bank 2 6F0000h 6FFFFFh 700000h 70FFFFh Bank 1 770000h 77FFFFh 780000h 78FFFFh 7E0000h Parameter 7EFFFFh Bank 7F0000h 7F3FFFh 7FC000h 7FFFFFh 64 KWord 8 Main Blocks 64 KWord 64 KWord 8 Main Blocks 64 KWord 64 KWord 8 Main Blocks 64 KWord 64 KWord AI12888 11/110 Signal descriptions M58LT128HST, M58LT128HSB 2 Signal descriptions See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device. 2.1 Address inputs (A0-A22) The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the command interface of the Program/Erase Controller. 2.2 Data inputs/outputs (DQ0-DQ15) The Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation. 2.3 Chip Enable (E) The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. 2.4 Output Enable (G) The Output Enable input controls data outputs during the Bus Read operation of the memory. 2.5 Write Enable (W) The Write Enable input controls the Bus Write operation of the memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. 2.6 Reset (RP) The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 20: DC characteristics - currents, for the value of IDD2. After Reset, all blocks are in the protected state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. When exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. 12/110 M58LT128HST, M58LT128HSB Signal descriptions 2.7 Latch Enable (L) Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. 2.8 Clock (K) The Clock input synchronizes the memory to the microcontroller during Synchronous Read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is ignored during Asynchronous Read and in Write operations. 2.9 Wait (WAIT) Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at VIH, Output Enable is at VIH or Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. 2.10 VDD supply voltage VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program, and Erase). 2.11 VDDQ supply voltage VDDQ provides the power supply to the I/O pins and enables all outputs to be powered independently from VDD. 2.12 VPP program supply voltage VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives absolute protection against program or erase, while VPP in the VPP1 range enables these functions (see Tables 20 and 21, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed. 13/110 Signal descriptions M58LT128HST, M58LT128HSB 2.13 VSS ground VSS ground is the reference for the core supply. It must be connected to the system ground. 2.14 VSSQ ground VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS Note: Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1F ceramic capacitor close to the pin (high-frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 8: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents. 14/110 M58LT128HST, M58LT128HSB Bus operations 3 Bus operations There are six standard bus operations that control the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset. See Table 3: Bus operations, for a summary. Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations. 3.1 Bus Read Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at VIL to perform a Read operation. The Chip Enable input is used to enable the device. Output Enable is used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figures 9, 10 and 11 Read AC Waveforms, and Tables 22 and 23 Read AC Characteristics, for details of when the output becomes valid. 3.2 Bus Write Bus Write operations write commands to the memory or latch input data to be programmed. A Bus Write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, input data and addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses must be latched prior to the write operation by toggling Latch Enable (when Chip Enable is at VIL). The Latch Enable must be tied to VIH during the Bus Write operation. See Figures 15 and 16, Write AC waveforms, and Tables 24 and 25, Write AC characteristics, for details of the timing requirements. 3.3 Address Latch Address Latch operations input valid addresses. Both Chip Enable and Latch Enable must be at VIL during Address Latch operations. The addresses are latched on the rising edge of Latch Enable. 3.4 Output Disable The outputs are high impedance when the Output Enable is at VIH. 15/110 Bus operations M58LT128HST, M58LT128HSB 3.5 Standby Standby disables most of the internal circuitry, allowing a substantial reduction of the current consumption. The memory is in Standby when Chip Enable and Reset are at VIH. The power consumption is reduced to the standby level IDD3 and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a Program or Erase operation, the device enters Standby mode when finished. 3.6 Reset During Reset mode the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the Reset level, independently from the Chip Enable, Output Enable, or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid. Table 3. Bus operations(1) E VIL VIL VIL VIL VIH X G VIL VIH X VIH X X W VIH VIL VIH VIH X X L VIL(3) VIL (3) Operation Bus Read Bus Write Address Latch Output Disable Standby Reset 1. X = `Don't care'. RP VIH VIH VIH VIH VIH VIL WAIT(2) DQ15-DQ0 Data Output Data Input Data Output or Hi-Z(4) VIL X X X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 2. WAIT signal polarity is configured using the Set Configuration Register command. 3. L can be tied to VIH if the valid address has been previously latched. 4. Depends on G. 16/110 M58LT128HST, M58LT128HSB Command interface 4 Command interface All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the program and erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation. When exiting from Reset or whenever VDD is lower than VLKO, the Command Interface is reset to Read mode when power is first applied. Command sequences must be followed exactly. Any invalid combination of commands is ignored. Refer to Table 4: Command codes, Table 5: Standard commands, Table 6: Factory commands, and Appendix D: Command Interface state tables for a summary of the Command Interface. Table 4. Command codes Command Block Protect Confirm Set Configuration Register Confirm Alternative Program Setup Block Erase Setup Program Setup Clear Status Register Block Protect Setup, Block Unprotect Setup and Set Configuration Register Setup Read Status Register Buffer Enhanced Factory Program Setup Read Electronic Signature Read CFI Query Program/Erase Suspend Blank Check Setup Protection Register Program Blank Check Confirm Program/Erase Resume, Block Erase Confirm, Block Unprotect Confirm, Buffer Program or Buffer Enhanced Factory Program Confirm Buffer Program Read Array Hex Code 01h 03h 10h 20h 40h 50h 60h 70h 80h 90h 98h B0h BCh C0h CBh D0h E8h FFh 17/110 Command interface M58LT128HST, M58LT128HSB 4.1 Read Array command The Read Array command returns the addressed bank to Read Array mode. One Bus Write cycle is required to issue the Read Array command. Once a bank is in Read Array mode, subsequent read operations outputs the data from the memory array. A Read Array command can be issued to any banks while programming or erasing in another bank. If the Read Array command is issued to a bank currently executing a program or erase operation, the bank returns to Read Array mode, but the Program or Erase operation continues. However, the data output from the bank is not guaranteed until the Program or Erase operation is finished. The Read modes of other banks are not affected. 4.2 Read Status Register command The device contains a Status Register that is used to monitor program or erase operations. The Read Status Register command is used to read the contents of the Status Register for the addressed bank. One Bus Write cycle is required to issue the Read Status Register command. Once a bank is in Read Status Register mode, subsequent Read operations output the contents of the Status Register. The Status Register data is latched on the falling edge of the Chip Enable or Output Enable signals. Either Chip Enable or Output Enable must be toggled to update the Status Register data The Read Status Register command can be issued at any time, even during Program or Erase operations. The Read Status Register command only changes the Read mode of the addressed bank. The Read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read the Status Register. A Read Array command is required to return the bank to Read Array mode. See Table 9 for the description of the Status Register Bits. 18/110 M58LT128HST, M58LT128HSB Command interface 4.3 Read Electronic Signature command The Read Electronic Signature command is used to read the manufacturer and device codes, the protection status of the addressed bank, the Protection Register, and the Configuration Register. One Bus Write cycle is required to issue the Read Electronic Signature command. Once a bank is in Read Electronic Signature mode, subsequent Read operations in the same bank output the manufacturer code, the device code, the protection status of the addressed bank, the Protection Register, or the Configuration Register (see Table 8). The Read Electronic Signature command can be issued at any time, even during Program or Erase operations, except during Protection Register Program operations. Dual operations between the parameter bank and the electronic signature location are not allowed (see Table 15: Dual operation limitations for details). If a Read Electronic Signature command is issued to a bank that is executing a Program or Erase operation the bank go into Read Electronic Signature mode. Subsequent Bus Read cycles output the Electronic Signature data and the Program/Erase Controller continues to program or erase in the background. The Read Electronic Signature command only changes the Read mode of the addressed bank. The Read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read the Electronic Signature. A Read Array command is required to return the bank to Read Array mode. 4.4 Read CFI Query command The Read CFI Query command is used to read data from the Common Flash Interface (CFI). One Bus Write cycle is required to issue the Read CFI Query command. Once a bank is in Read CFI Query mode, subsequent Bus Read operations in the same bank read from the Common Flash Interface. The Read CFI Query command can be issued at any time, even during Program or Erase operations. If a Read CFI Query command is issued to a bank that is executing a Program or Erase operation the bank goes into Read CFI Query mode. Subsequent Bus Read cycles output the CFI data and the Program/Erase controller continues to Program or Erase in the background. The Read CFI Query command only changes the Read mode of the addressed bank. The Read modes of other banks are not affected. Only Asynchronous Read and Single Synchronous Read operations should be used to read from the CFI. A Read Array command is required to return the bank to Read Array mode. Dual operations between the Parameter Bank and the CFI memory space are not allowed (see Table 15: Dual operation limitations for details). See Appendix B: Common Flash Interface, Tables 31, 32, 33, 34, 35, 36, 37, 38, 39 and 40 for details on the information contained in the Common Flash Interface memory area. 19/110 Command interface M58LT128HST, M58LT128HSB 4.5 Clear Status Register command The Clear Status Register command can be used to reset (set to `0') all error bits (SR1, 3, 4 and 5) in the Status Register. One Bus Write cycle is required to issue the Clear Status Register command. The Clear Status Register command does not affect the Read mode of the bank. The error bits in the Status Register do not automatically return to `0' when a new command is issued. The error bits in the Status Register should be cleared before attempting a new Program or Erase command. 4.6 Block Erase command The Block Erase command is used to erase a block. It sets all the bits within the selected block to '1'. All previous data in the block is lost. If the block is protected then the erase operation aborts, the data in the block is not changed, and the Status Register outputs the error. The following two Bus Write cycles are required to issue the command: The first bus cycle sets up the Block Erase command. The second latches the block address and starts the Program/Erase Controller. If the second bus cycle is not the Block Erase Confirm code, Status Register bits SR4 and SR5 are set and the command is aborted. Once the command is issued, the bank enters Read Status Register mode and any Read operation within the addressed bank outputs the contents of the Status Register. A Read Array command is required to return the bank to Read Array mode. During Block Erase operations the bank containing the block being erased only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query, and the Program/Erase Suspend command; all other commands are ignored. The Block Erase operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed when the Block Erase operation is aborted, the block must be erased again. Refer to Chapter 8: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed in banks not being erased. Typical erase times are given in Table 16: Program/erase times and endurance cycles. See Appendix C, Figure 23: Block Erase flowchart and pseudo code for a suggested flowchart for using the Block Erase command. 20/110 M58LT128HST, M58LT128HSB Command interface 4.7 Blank Check command The Blank Check command is used to check whether a block has been completely erased. Only one block at a time can be checked. To use the Blank Check command, VPP must be equal to VPPH. If VPP is not equal to VPPH, the device ignores the command and no error is shown in the Status Register. The following two bus cycles are required to issue the Blank Check command: The first bus cycle writes the Blank Check command (BCh) to any address in the block to be checked. The second bus cycle writes the Blank Check Confirm command (CBh) to any address in the block to be checked and starts the Blank Check operation. If the second bus cycle is not Blank Check Confirm, Status Register bits SR4 and SR5 are set to '1' and the command aborts. Once the command is issued the addressed bank automatically enters the Status Register mode and further reads the Status Register contents within the bank output. The only operation permitted during Blank Check is Read Status Register. Dual operations are not supported while a Blank Check operation is in progress. Blank Check operations cannot be suspended and are not allowed while the device is in Program/Erase Suspend. The SR7 Status Register bit indicates the status of the Blank Check operation in progress: SR7 = '0' means that the Blank Check operation is still ongoing, and SR7 = '1' means that the operation is complete. The SR5 Status Register bit goes High (SR5 = '1') to indicate if the Blank Check operation has failed. At the end of the operation the bank remains in the Read Status Register mode until another command is written to the Command Interface. See Appendix C, Figure 20: Blank Check flowchart and pseudo code for a suggested flowchart for using the Blank Check command. Typical Blank Check times are given in Table 16: Program/erase times and endurance cycles. 21/110 Command interface M58LT128HST, M58LT128HSB 4.8 Program command The Program command is used to program a single word to the memory array. If the block being programmed is protected, then the Program operation aborts, the data in the block is not changed, and the Status Register outputs the error. The following two Bus Write cycles are required to issue the Program Command: The first bus cycle sets up the Program command. The second latches the address and data to be programmed and starts the Program/Erase Controller. Once the programming has started, Read operations in the bank being programmed output the Status Register content. During a Program operation, the bank containing the word being programmed only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend commands; all other commands are ignored. A Read Array command is required to return the bank to Read Array mode. Refer to Chapter 8: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 16: Program/erase times and endurance cycles. The Program operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed when the Program operation is aborted, the word must be reprogrammed. See Appendix C, Figure 19: Program flowchart and pseudo code for the flowchart for using the Program command. 22/110 M58LT128HST, M58LT128HSB Command interface 4.9 Buffer Program command The Buffer Program Command makes use of the device's 32-word Write Buffer to accelerate programming. Up to 32 words can be loaded into the Write Buffer, which can dramatically reduce in-system programming time compared to the standard non-buffered Program command. Four successive steps are required to issue the Buffer Program command: 1. The first Bus Write cycle sets up the Buffer Program command. The setup code can be addressed to any location within the targeted block. After the first Bus Write cycle, Read operations in the bank output the contents of the Status Register. Status Register bit SR7 should be read to check that the buffer is available (SR7 = `1'). If the buffer is not available (SR7 = `0'), re-issue the Buffer Program command to update the Status Register contents. 2. The second Bus Write cycle sets up the number of words to be programmed. Value "n" is written to the same block address, where n+1 is the number of words to be programmed. Use n+1 Bus Write cycles to load the address and data for each word into the Write Buffer. Addresses must lie within the range from the start address to the start address + n, where the start address is the location of the first data to be programmed. Optimum performance is obtained when the start address corresponds to a 32-word boundary. The final Bus Write cycle confirms the Buffer Program command and starts the program operation. 3. 4. All the addresses used in the Buffer Program operation must lie within the same block. Invalid address combinations or an incorrect sequence of Bus Write cycles sets an error in the Status Register and aborts the operation without affecting the data in the memory array. If the block being programmed is protected an error is set in the Status Register, and the operation aborts without affecting the data in the memory array. During Buffer Program operations the bank being programmed only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query, and the Program/Erase Suspend command; all other commands are ignored. Refer to Chapter 8: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed in banks not being programmed. See Appendix C, Figure 21: Buffer Program flowchart and pseudo code for a suggested flowchart on using the Buffer Program command. 23/110 Command interface M58LT128HST, M58LT128HSB 4.10 Buffer Enhanced Factory Program command The Buffer Enhanced Factory Program command has been specially developed to accelerate programming in manufacturing environments where the programming time is critical. It is used to program one or more Write Buffer(s) of 32 words to a block. Once the device enters Buffer Enhanced Factory Program mode, the Write Buffer can be reloaded any number of times as long as the address remains within the same block. Only one block can be programmed at a time. If the block being programmed is protected, then the Program operation aborts, the data in the block is not changed and the Status Register outputs the error. The use of the Buffer Enhanced Factory Program command requires the following operating conditions: VPP must be set to VPPH VDD must be within operating range Ambient temperature TA must be 30C 10C The targeted block must be unprotected The start address must be aligned with the start of a 32-word buffer boundary The address must remain the Start Address throughout programming. Dual operations are not supported during the Buffer Enhanced Factory Program operation and the command cannot be suspended. The Buffer Enhanced Factory Program Command consists of three phases: the Setup Phase, the Program and Verify Phase, and the Exit Phase. Refer to Table 6: Factory commands for detailed information. 4.10.1 Setup phase The Buffer Enhanced Factory Program command requires the following two Bus Write cycles to initiate the command. The first Bus Write cycle sets up the Buffer Enhanced Factory Program command. The second Bus Write cycle confirms the command. After the Confirm command is issued, Read operations output the contents of the Status Register. The read Status Register command must not be issued, othewise it is interpreted as data to program. The Status Register Program/Erase Controller bit SR7 should be read to check that the Program/Erase Controller is ready to proceed to the next phase. If an error is detected, SR4 goes high (set to `1') and the Buffer Enhanced Factory Program operation is terminated. See Chapter 5: Status Register for details on the error. 24/110 M58LT128HST, M58LT128HSB Command interface 4.10.2 Program and verify phase The program and verify phase requires 32 cycles to program the 32 words to the Write Buffer. The data is stored sequentially, starting at the first address of the Write Buffer, until the Write Buffer is full (32 words). To program less than 32 words, the remaining words should be programmed with FFFFh. The following three successive steps are required to issue and execute the program and verify phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first word to be programmed. The Status Register Bank Write status bit SR0 should be read to check that the Program/Erase Controller is ready for the next word. Each subsequent word to be programmed is latched with a new Bus Write operation. The address must remain the start address as the Program/Erase Controller increments the address location. If any address is given that is not in the same block as the start address, the program and verify phase terminates. Status Register bit SR0 should be read between each Bus Write cycle to check that the Program/Erase Controller is ready for the next word. Once the Write Buffer is full, the data is programmed sequentially to the memory array. After the Program operation, the device automatically verifies the data and reprograms, if necessary. 2. 3. The program and verify phase can be repeated, without re-issuing the command, to program additional 32 word locations as long as the address remains in the same block. 4. Finally, after all words, or the entire block has been programmed, write one Bus Write operation to any address outside the block containing the start address, to terminate program and verify phase. Status Register bit SR0 must be checked to determine whether the Program operation is finished. The Status Register may be checked for errors at any time but it must be checked after the entire block has been programmed. 4.10.3 Exit phase Status Register Program/Erase Controller bit SR7 set to `1' indicates that the device has exited the Buffer Enhanced Factory Program operation and returned to Read Status Register mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See Section Table 5: Status Register for more details. For optimum performance the Buffer Enhanced Factory Program command should be limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded, the internal algorithm continues to work properly but some degradation in performance is possible. Typical program times are given in Table 16. See Appendix C, Figure 27: Buffer Enhanced Factory Program flowchart and pseudo code for a suggested flowchart on using the Buffer Enhanced Factory Program command. 25/110 Command interface M58LT128HST, M58LT128HSB 4.11 Program/Erase Suspend command The Program/Erase Suspend command is used to pause a Program or Block Erase operation. The command can be addressed to any bank. The Program/Erase Resume command is required to restart the suspended operation. One Bus Write cycle is required to issue the Program/Erase Suspend command. Once the Program/Erase Controller has paused, bits SR7, SR6, and/or SR2 of the Status Register are set to `1'. The following commands are accepted during Program/Erase Suspend: - - - - - Program/Erase Resume Read Array (data from erase-suspended blocks or program-suspended words is not valid) Read Status Register Read Electronic Signature Read CFI Query In addition, if the suspended operation is a Block Erase, then the following commands are also accepted: - - - - - - Clear Status Register Program (except in erase-suspended blocks) Buffer Program (except in erase suspended blocks) Block Protect Block Unprotect Set Configuration Register During an Erase Suspend, the block being erased can be protected by issuing the Block Protect command. When the Program/Erase Resume command is issued, the operation completes. It is possible to accumulate multiple suspend operations. For example, suspend an Erase operation, start a Program operation, suspend the Program operation, and then read the array. If a Program command is issued during a Block Erase Suspend, the Erase operation cannot be resumed until the program operation has completed. The Program/Erase Suspend command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature, or Read CFI Query mode, the bank remains in that mode and outputs the corresponding data. Refer to Section Table 8: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in Standby mode by driving Chip Enable to VIH. Program/Erase is aborted if Reset, RP, goes to VIL. See Appendix C, Figure 22: Program Suspend & Resume flowchart and pseudo code and Figure 24: Erase Suspend & Resume flowchart and pseudo code for flowcharts for using the Program/Erase Suspend command. 26/110 M58LT128HST, M58LT128HSB Command interface 4.12 Program/Erase Resume command The Program/Erase Resume command is used to restart the Program or Erase operation suspended by the Program/Erase Suspend command. One Bus Write cycle is required to issue the command. The command can be issued to any address. The Program/Erase Resume command does not change the Read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature, or Read CFI Query mode, the bank remains in that mode and outputs the corresponding data. If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the program operation has completed. See Appendix C, Figure 22: Program Suspend & Resume flowchart and pseudo code and Figure 24: Erase Suspend & Resume flowchart and pseudo code for flowcharts for using the Program/Erase Resume command. 4.13 Protection Register Program command The Protection Register Program command is used to program the user segments of the Protection Register and the two Protection Register Locks. The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as shown in Figure 4: Protection Register memory map. The segments are programmed one word at a time. When shipped, all bits in the segment are set to `1'. The user can only program the bits to `0'. The following two Bus Write cycles are required to issue the Protection Register Program command: The first bus cycle sets up the Protection Register Program command. The second latches the address and data to be programmed to the Protection Register and starts the Program/Erase Controller. Read operations to the bank being programmed output the Status Register content after the Program operation has started. Attempting to program a previously protected Protection Register results in a Status Register error. The Protection Register Program cannot be suspended. Dual operations between the Parameter Bank and the Protection Register memory space are not allowed (see Table 15: Dual operation limitations for details). The two Protection Register Locks are used to protect the OTP segments from further modification. The protection of the OTP segments is not reversible. Refer to Figure 4: Protection Register memory map and Table 8: Protection Register locks for details on the Lock bits. See Appendix C, Figure 26: Protection Register Program flowchart and pseudo code for a flowchart for using the Protection Register Program command. 27/110 Command interface M58LT128HST, M58LT128HSB 4.14 Set Configuration Register command The Set Configuration Register command is used to write a new value to the Configuration Register. The following two Bus Write cycles are required to issue the Set Configuration Register command. The first cycle sets up the Set Configuration Register command and the address corresponding to the Configuration Register content. The second cycle writes the Configuration Register data and the Confirm command. The Configuration Register data must be written as an address during the bus write cycles, such as A0 = CR0, A1 = CR1, ..., A15 = CR15. Addresses A16-A22 are ignored. Read operations output the array content after the Set Configuration Register command is issued. The Read Electronic Signature command is required to read the updated contents of the Configuration Register. 4.15 Block Protect command The Block Protect command is used to protect a block and prevent Program or Erase operations from changing the data in it. All blocks are protected after power-up or reset. The following two Bus Write cycles are required to issue the Block Protect command: The first bus cycle sets up the Block Protect command. The second Bus Write cycle latches the block address and protects the block. Once the command has been issued, subsequent Bus Read operations read the Status Register. The protection status can be monitored for each block using the Read Electronic Signature command. Refer to Section 9: Block protection for a detailed explanation. See Appendix C, Figure 25: Protect/Unprotect operation flowchart and pseudo code for a flowchart for using the Block Protect command. 4.16 Block Unprotect command The Block Unprotect command is used to unprotect a block, allowing the block to be programmed or erased. The following two Bus Write cycles are required to issue the Block Unprotect command: The first bus cycle sets up the Block Unprotect command. The second Bus Write cycle latches the block address and unprotects the block. Once the command has been issued, subsequent Bus Read operations read the Status Register. The protection status can be monitored for each block using the Read Electronic Signature command. Refer to Section 9: Block protection for a detailed explanation and Appendix C, Figure 25: Protect/Unprotect operation flowchart and pseudo code for a flowchart for using the Block Unprotect command. 28/110 M58LT128HST, M58LT128HSB Table 5. Standard commands(1) Bus operations Cycles Commands 1st cycle Op. Read Array Read Status Register Read Electronic Signature Read CFI Query Clear Status Register Block Erase Program 1+ 1+ 1+ 1+ 1 2 2 Write Write Write Write Write Write Write Write Buffer Program(4) n+4 Write Write Program/Erase Suspend Program/Erase Resume Protection Register Program Set Configuration Register Block Protect Block Unprotect 1 1 2 2 2 2 Write Write Write Write Write Write Add BKA BKA BKA BKA X BKA or BA(3) BKA or WA(3) BA PA1 PAn+1 X X PRA CRD BKA or BA(3) BKA or BA(3) Data FFh 70h 90h 98h 50h 20h 40h or 10h E8h PD1 PDn+1 B0h D0h C0h 60h 60h 60h Op. Command interface 2nd cycle Add WA BKA(2) BKA (2) Data RD SRD ESD QD Read Read Read Read BKA(2) Write Write Write Write Write BA WA BA PA2 X D0h PD n PD2 D0h Write Write Write Write PRA CRD BA BA PRD 03h 01h D0h 1. X = `Don't Care', WA = word Address in targeted bank, RD = Read Data, SRD = Status Register Data, ESD = Electronic Signature Data, QD = Query Data, BA = Block Address, BKA = Bank Address, PD = Program Data, PRA = Protection Register Address, PRD = Protection Register Data, CRD = Configuration Register Data. 2. Must be same bank as in the first cycle. The signature addresses are listed in Table 7. 3. Any address within the bank can be used. 4. n+1 is the number of words to be programmed. 29/110 Command interface Table 6. Factory commands M58LT128HST, M58LT128HSB Bus Write operations(1) Cycles Command Phase 1st Add Blank Check Setup 2 2 BA BKA or WA(2) WA1 NOT BA1(4) 2nd 3rd Final -1 Add Data Final Add Data Data Add Data Add Data BCh 80h PD1 X BA WA1 WA1 CBh D0h PD2 WA1 PD3 Buffer Enhanced Program/ 32 Factory Verify(3) Program Exit 1 WA1 PD31 WA1 PD32 1. WA = word Address in targeted bank, BKA = Bank Address, PD = Program Data, BA = Block Address, X = `Don't Care'. 2. Any address within the bank can be used. 3. The Program/Verify phase can be executed any number of times as long as the data is to be programmed to the same block. 4. WA1 is the Start Address, NOT BA1 = Not Block Address of WA1. Table 7. Electronic signature codes Code Address (h) Bank Address + 000 Top Bank Address + 001 Bank Address + 001 Block Address + 002 Bank Address + 005 Numonyx Factory Default Data (h) 0020 88D6 (M58LT128HST) 88D7 (M58LT128HSB) 0001 0000 CR(1) 0002 Bank Address + 080 0000 Bank Address + 081 Bank Address + 084 Unique Device Number OTP Area PRLD(1) OTP Area Manufacturer code Device code Bottom Protected Block protection Unprotected Configuration Register Protection Register PR0 Lock OTP Area Permanently Protected Protection Register PR0 Bank Address + 085 Bank Address + 088 Protection Register PR1 through PR16 Lock Protection Registers PR1-PR16 Bank Address + 089 Bank Address + 08A Bank Address + 109 1. CR = Configuration Register, PRLD = Protection Register Lock Data. 30/110 M58LT128HST, M58LT128HSB Figure 4. Protection Register memory map PROTECTION REGISTERS Command interface 109h PR16 User Programmable OTP 102h 91h PR1 User Programmable OTP 8Ah Protection Register Lock 89h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 88h 85h 84h PR0 User Programmable OTP Unique device number 81h 80h Protection Register Lock 10 AI07563 31/110 Command interface Table 8. Protection Register locks Lock M58LT128HST, M58LT128HSB Description Number Address Bits Bit 0 Lock 1 80h Bit 1 Preprogrammed to protect unique device number, address 81h to 84h in PR0 Protects 64 bits of OTP segment, address 85h to 88h in PR0 Bits 2 to 15 reserved Bit 0 Bit 1 Bit 2 ---Lock 2 89h Protects 128 bits of OTP segment PR1 Protects 128 bits of OTP segment PR2 Protects 128 bits of OTP segment PR3 ---Protects 128 bits of OTP segment PR14 Protects 128 bits of OTP segment PR15 Protects 128 bits of OTP segment PR16 Bit 13 Bit 14 Bit 15 32/110 M58LT128HST, M58LT128HSB Status Register 5 Status Register The Status Register provides information on the current or previous Program or Erase operations. The Read Status Register command reads the contents of the Status Register (refer to Section 4.2: Read Status Register command for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals, and can be read until Chip Enable or Output Enable returns to VIH. The Status Register can only be read using single Asynchronous or Single Synchronous reads. If no Read Array command has been issued, Bus Read operations from any address within the bank always read the Status Register during Program and Erase operations. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2, and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3, and SR1 give information about any errors; they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to `1' the Status Register should be reset before issuing another command. The bits in the Status Register are summarized in Table 9: Status Register bits. Refer to Table 9 in conjunction with the following text descriptions. 5.1 Program/Erase Controller status bit (SR7) The Program/Erase Controller status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller status bit is Low (set to `0'), the Program/Erase Controller is active. When the bit is High (set to `1'), the Program/Erase Controller is inactive and the device is ready to process a new command. The Program/Erase Controller status bit is Low immediately after a Program/Erase Suspend command is issued, until the Program/Erase Controller pauses. After the Program/Erase Controller pauses, the bit is High. 5.2 Erase Suspend status bit (SR6) The Erase Suspend status bit indicates that an erase operation has been suspended. When the Erase Suspend status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend status bit should only be considered valid when the Program/Erase Controller status bit is High (Program/Erase Controller inactive). SR6 is set within the Erase Suspend latency time of the Program/Erase Suspend command being issued; therefore, the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued, the Erase Suspend status bit returns Low. 33/110 Status Register M58LT128HST, M58LT128HSB 5.3 Erase/Blank Check status bit (SR5) The Erase/Blank Check status bit is used to identify if there was an error during a Block Erase operation. When the Erase/Blank Check status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that it has erased correctly. The Erase/Blank Check status bit should be read once the Program/Erase Controller status bit is High (Program/Erase Controller inactive). The Erase/Blank Check status bit is also used to indicate whether an error occurred during the Blank Check operation. If the data at one or more locations in the block where the Blank Check command has been issued is different from FFFFh, SR5 is set to '1'. Once set High, the Erase/Blank Check status bit must be set Low by a Clear Status Register command or a hardware reset before a new erase command is issued, otherwise the new command appears to fail. 5.4 Program status bit (SR4) The Program status bit is used to identify if there was an error during a Program operation. The Program status bit should be read once the Program/Erase Controller status bit is High (Program/Erase Controller inactive). When the Program status bit is High (set to `1'), the Program/Erase Controller has applied the maximum number of pulses to the word and still failed to verify that it has programmed correctly. Attempting to program a '1' to an already programmed bit while VPP = VPPH also sets the Program status bit High. If VPP is different from VPPH, SR4 remains Low (set to '0') and the attempt is not shown. Once set High, the Program status bit must be set Low by a Clear Status Register command or a hardware reset before a new Program command is issued, otherwise the new command appears to fail. 5.5 VPP status bit (SR3) The VPP status bit is used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Program and Erase operations are not guaranteed if VPP becomes invalid during an operation. When the VPP status bit is Low (set to `0'), the voltage on the VPP pin was sampled at a valid voltage. When the VPP status bit is High (set to `1'), the VPP pin has a voltage that is below the VPP Lockout Voltage, VPPLK. This means the memory is protected and Program and Erase operations cannot be performed. Once set High, the VPP status bit must be set Low by a Clear Status Register command or a hardware reset before a new Program or Erase command is issued, otherwise the new command appears to fail. 34/110 M58LT128HST, M58LT128HSB Status Register 5.6 Program Suspend status bit (SR2) The Program Suspend status bit indicates that a Program operation has been suspended. The Program Suspend status bit should only be considered valid when the Program/Erase Controller status bit is High (Program/Erase Controller inactive). When the Program Suspend status bit is High (set to `1'), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. SR2 is set within the Program Suspend latency time of the Program/Erase Suspend command being issued; therefore,the memory may still complete the operation rather than entering Suspend mode. When a Program/Erase Resume command is issued, the Program Suspend status bit returns Low. 5.7 Block Protection status bit (SR1) The Block Protection status bit is used to identify if a Program or Block Erase operation has tried to modify the contents of a protected block. When the Block Protection status bit is High (set to `1'), a Program or Erase operation has been attempted on a protected block. Once set High, the Block Protection status bit must be set Low by a Clear Status Register command or a hardware reset before a new Program or Erase command is issued, otherwise the new command appears to fail. 5.8 Bank Write/Multiple Word Program status bit (SR0) The Bank Write status bit indicates whether the addressed bank is programming or erasing. In Buffer Enhanced Factory Program mode the Multiple Word Program bit shows if the device is ready to accept a new word to be programmed to the memory array. The Bank Write status bit should only be considered valid when the Program/Erase Controller Status SR7 is Low (set to `0'). When both the Program/Erase Controller status bit and the Bank Write status bit are Low (set to `0'), the addressed bank is executing a Program or Erase operation. When the Program/Erase Controller status bit is Low (set to `0') and the Bank Write status bit is High (set to `1'), a program or erase operation is being executed in a bank other than the one being addressed. In Buffer Enhanced Factory Program mode, if Multiple Word Program status bit is Low (set to `0'), the device is ready for the next word. If the Multiple Word Program status bit is High (set to `1'), the device is not ready for the next word. For further details on how to use the Status Register, see the Flowcharts and Pseudocodes provided in Appendix C. 35/110 Status Register Table 9. Bit M58LT128HST, M58LT128HSB Status Register bits Name Type Logic Level(1) '1' Ready Busy Erase suspended Erase In progress or completed Erase/Blank Check error Erase/Blank Check success Program error Program success VPP invalid, abort VPP OK Program suspended Program in progress or completed Program/Erase on protected block, abort No operation to protected blocks SR7 = `1' Not allowed '1' SR7 = `0' Bank Write Status Status SR7 = `1' '0' SR7 = `0' Program or Erase operation in addressed bank Program or Erase operation in a bank other than the addressed bank No Program or Erase operation in the device Definition SR7 P/E.C. Status Erase Suspend Status Erase/Blank Check Status Status '0' '1' Status '0' '1' Error '0' '1' Error '0' '1' SR6 SR5 SR4 Program Status SR3 VPP Status Program Suspend Status Block Protection Status Error '0' '1' Status '0' '1' Error '0' SR2 SR1 SR0 Multiple Word Program Status (Buffer Enhanced Factory Program mode) '1' Status SR7 = `1' Not allowed The device is NOT ready for the next SR7 = `0' buffer loading or is going to exit the BEFP mode SR7 = `1' '0' SR7 = `0' The device is ready for the next Buffer loading The device has exited the BEFP mode 1. Logic level '1' is High, '0' is Low. 36/110 M58LT128HST, M58LT128HSB Configuration Register 6 Configuration Register The Configuration Register is used to configure the type of bus access that the memory performs. Refer to Chapter 7: Read modes for details on Read operations. The Configuration Register is set through the Command Interface using the Set Configuration Register command. After a reset or power-up, the device is configured for Asynchronous Read (CR15 = 1). The Configuration Register bits are described in Table 11 and specify the selection of the burst length, burst type, burst X latency, and the Read operation. Refer to Figures 5 and 6 for examples of synchronous burst configurations. 6.1 Read Select bit (CR15) The Read Select bit, CR15, is used to switch between Asynchronous and Synchronous Read operations. When the Read Select bit is set to '1', Read operations are asynchronous; when the Read Select bit is set to '0', Read operations are synchronous. Synchronous Burst Read is supported in both parameter and main blocks, and can be performed across banks. On reset or power-up the Read Select bit is set to '1' for asynchronous access. 6.2 X-Latency bits (CR13-CR11) The X-Latency bits are used during Synchronous Read operations to set the number of clock cycles between the address being latched and the first data becoming available. Refer to Figure 5: X-latency and data output configuration example. For correct operation the X-Latency bits can only assume the values in Table 11: Configuration Register. Table 10 shows how to set the X-Latency parameter, taking into account the speed class of the device and the frequency used to read the Flash memory in Synchronous mode. Table 10. X-Latency Settings fmax 30 MHz 40 MHz 52 MHz tKmin 33 ns 25 ns 19 ns X-Latency min 3 4 5 37/110 Configuration Register M58LT128HST, M58LT128HSB 6.3 Wait Polarity bit (CR10) The Wait Polarity bit is used to set the polarity of the Wait signal used in Synchronous Burst Read mode. During Synchronous Burst Read mode the Wait signal indicates whether the data output is valid or a WAIT state must be inserted. When the Wait Polarity bit is set to `0' the Wait signal is active Low. When the Wait Polarity bit is set to `1' the Wait signal is active High. 6.4 Data Output Configuration bit (CR9) The Data Output Configuration bit is used to configure the output to remain valid for either one or two clock cycles during Synchronous mode. When the Data Output Configuration bit is '0' the output data is valid for one clock cycle; when the Data Output Configuration bit is '1' the output data is valid for two clock cycles. The Data Output Configuration bit must be configured using the following condition: tK > tKQV + tQVK_CPU tK is the clock period tQVK_CPU is the data setup time required by the system CPU tKQV is the clock to data valid time. where: If this condition is not satisfied, the Data Output Configuration bit should be set to `1' (two clock cycles). Refer to Figure 5: X-latency and data output configuration example. 6.5 Wait Configuration bit (CR8) The Wait Configuration bit is used to control the timing of the Wait output pin, WAIT, in Synchronous Burst Read mode. When WAIT is asserted, Data is Not Valid and when WAIT is de-asserted, Data is Valid. When the Wait Configuration bit is Low (set to '0'), the Wait output pin is asserted during the WAIT state. When the Wait Configuration bit is High (set to '1'), the Wait output pin is asserted one data cycle before the WAIT state. 6.6 Burst Type bit (CR7) The Burst Type bit determines the sequence of addresses read during Synchronous Burst Reads. The Burst Type bit is High (set to '1') because the memory only outputs from sequential addresses. See Table 12: Burst type definition for the sequence of addresses output from a given starting address in Sequential mode. 38/110 M58LT128HST, M58LT128HSB Configuration Register 6.7 Valid Clock Edge bit (CR6) The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during Synchronous Read operations. When the Valid Clock Edge bit is Low (set to '0') the falling edge of the Clock is the active edge. When the Valid Clock Edge bit is High (set to '1') the rising edge of the Clock is the active edge. 6.8 Wrap Burst bit (CR3) The Wrap Burst bit, CR3, is used to select between wrap and no wrap. Synchronous Burst reads can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary (no wrap). When the Wrap Burst bit is Low (set to `0') the Burst Read wraps. When it is High (set to `1') the Burst Read does not wrap. 6.9 Burst length bits (CR2-CR0) The Burst Length bits are used to set the number of words to be output during a Synchronous Burst Read operation as result of a single address latch cycle. They can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. In Continuous Burst mode the burst sequence can cross bank boundaries. In continuous burst mode, in 4, 8 or 16 words no-wrap, depending on the starting address, the device asserts the WAIT signal to indicate that a delay is necessary before the data is output. If the starting address is shifted by 1, 2 or 3 positions from the four-word boundary, WAIT is asserted for 1, 2 or 3 clock cycles, respectively, when the burst sequence crosses the first 16-word boundary. This indicates that the device needs an internal delay to read the successive words in the array. WAIT is only asserted once during a continuous burst access. See also Table 12: Burst type definition. CR14, CR5 and CR4 are reserved for future use. 39/110 Configuration Register Table 11. Bit CR15 CR14 M58LT128HST, M58LT128HSB Configuration Register Description Read Select 1 Reserved 010 011 100 2 clock latency(1) 3 clock latency 4 clock latency 5 clock latency 6 clock latency 7 clock latency (default) Asynchronous Read (Default at power-on) Value 0 Description Synchronous Read CR13-CR11 X-Latency 101 110 111 Other configurations reserved 0 CR10 Wait Polarity 1 CR9 Data Output Configuration 0 1 0 CR8 Wait Configuration 1 0 CR7 Burst Type 1 0 CR6 CR5-CR4 CR3 Valid Clock Edge 1 Reserved 0 Wrap Burst 1 001 010 CR2-CR0 Burst Length 011 111 16 words Continuous (default) No Wrap (default) 4 words 8 words Wrap Rising Clock edge (default) Sequential (default) Falling Clock edge WAIT is active High (default) Data held for one clock cycle Data held for two clock cycles (default)(1) WAIT is active during WAIT state WAIT is active one data cycle before WAIT state(1) (default) Reserved WAIT is active Low 1. The combination X-Latency = 2, Data held for two clock cycles and Wait active one data cycle before the WAIT state is not supported. 40/110 M58LT128HST, M58LT128HSB Table 12. Mode Start Add 0 1 2 3 Wrap ... 7 ... 12 13 14 15 7-4-5-6 7-0-1-2-3-4-56 7-8-9-10-11-12-13-1415-0-1-2-3-4-5-6 Configuration Register Burst type definition Sequential Continuous Burst 4 words 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8 words 0-1-2-3-4-5-67 1-2-3-4-5-6-70 2-3-4-5-6-7-01 16 words 0-1-2-3-4-5-6-7-8-9-1011-12-13-14-15 1-2-3-4-5-6-7-8-9-1011-12-13-14-15-0 2-3-4-5-6-7-8-9-10-1112-13-14-15-0-1 0-1-2-3-4-5-6... 1-2-3-4-5-6-7-...15-WAIT-16-1718... 2-3-4-5-6-7...15-WAIT-WAIT-1617-18... 3-4-5-6-7...15-WAIT-WAITWAIT-16-17-18... 3-4-5-6-7-0-1- 3-4-5-6-7-8-9-10-11-122 13-14-15-0-1-2 7-8-9-10-11-12-13-14-15-WAITWAIT-WAIT-16-17... 12-13-14-15-16-17-18... 13-14-15-WAIT-16-17-18... 14-15-WAIT-WAIT-16-17-18.... 15-WAIT-WAIT-WAIT-16-17-18... 41/110 Configuration Register Table 12. Mode Start Add 0 M58LT128HST, M58LT128HSB Burst type definition (continued) Sequential Continuous Burst 4 words 0-1-2-3 8 words 0-1-2-3-4-5-67 1-2-3-4-5-6-78 2-3-4-5-6-7-89... 3-4-5-6-7-8-910 16 words 0-1-2-3-4-5-6-7-8-9-1011-12-13-14-15 1-2-3-4-5-6-7-8-9-1011-12-13-14-15-WAIT16 2-3-4-5-6-7-8-9-10-1112-13-14-15-WAITWAIT-16-17 3-4-5-6-7-8-9-10-11-1213-14-15-WAIT-WAITWAIT-16-17-18 1 1-2-3-4 2 2-3-4-5 3 ... 7 ... 12 3-4-5-6 No-wrap 7-8-9-10 7-8-9-10-1112-13-14 7-8-9-10-11-12-13-1415-WAIT-WAIT-WAIT16-17-18-19-20-21-22 Same as for wrap (wrap /no wrap has no effect on continuous burst) 12-13-1415 13-14-15WAIT-16 14-15WAITWAIT-1617 15-WAITWAITWAIT-1617-18 12-13-14-1516-17-18-19 13-14-15WAIT-16-1718-19-20 14-15-WAITWAIT-16-1718-19-20-21 15-WAITWAIT-WAIT16-17-18-1920-21-22 12-13-14-15-16-17-1819-20-21-22-23-24-2526-27 13-14-15-WAIT-16-1718-19-20-21-22-23-2425-26-27-28 14-15-WAIT-WAIT-1617-18-19-20-21-22-2324-25-26-27-28-29 15-WAIT-WAIT-WAIT16-17-18-19-20-21-2223-24-25-26-27-28-2930 13 14 15 42/110 M58LT128HST, M58LT128HSB Figure 5. X-latency and data output configuration example X-latency 1st cycle K 2nd cycle 3rd cycle 4th cycle Configuration Register E L A22-A0 tDELAY DQ15-DQ0 VALID ADDRESS tAVK_CPU tACC tQVK_CPU tKQV tK tQVK_CPU VALID DATA VALID DATA AI10542 1. The settings shown are X-latency = 4, Data Output held for one clock cycle. Figure 6. Wait configuration example E K L A22-A0 VALID ADDRESS DQ15-DQ0 VALID DATA VALID DATA NOT VALID VALID DATA WAIT CR8 = '0' CR10 = '0' WAIT CR8 = '1' CR10 = '0' WAIT CR8 = '0' CR10 = '1' WAIT CR8 = '1' CR10 = '1' AI06972 43/110 Read modes M58LT128HST, M58LT128HSB 7 Read modes Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is `don't care' for the data output, the Read operation is asynchronous. If the data output is synchronized with clock, the Read operation is synchronous. The Read mode and format of the data output are determined by the Configuration Register. (See Section 6: Configuration Register for details). All banks support both asynchronous and Synchronous Read operations. 7.1 Asynchronous Read mode In Asynchronous Read operations the clock signal is `don't care'. The device outputs the data corresponding to the address latched; that is the memory array, Status Register, Common Flash Interface, or Electronic Signature depending on the command issued. CR15 in the Configuration Register must be set to `1' for synchronous operations. Asynchronous Read operations can be performed in two different ways, Asynchronous Random Access Read and Asynchronous Page Read. Only Asynchronous Page Read takes full advantage of the internal page storage so different timings are applied. In Asynchronous Read mode a page of data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by address inputs A0 and A1. The first Read operation within the page has a longer access time (tAVQV, random access time). Subsequent reads within the same page have much shorter access times (tAVQV1, page access time). If the page changes, then the normal, longer timings apply again. The device features an Automatic Standby mode. During Asynchronous Read operations, after a bus inactivity of 150 ns, the device automatically switches to the Automatic Standby mode. In this situation, the power consumption is reduced to the standby value and the outputs are still driven. In Asynchronous Read mode, the WAIT signal is always de-asserted. See Table 22: Asynchronous Read AC characteristics, Figure 9: Asynchronous random access Read AC waveforms, and Figure 10: Asynchronous Page Read AC waveforms for details. 44/110 M58LT128HST, M58LT128HSB Read modes 7.2 Synchronous Burst Read mode In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is possible to perform Burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other Read operations, such as Read Status Register, Read CFI and Read Electronic Signature, then Single Synchronous Read or Asynchronous Random Access Read must be used. In Synchronous Burst Read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A burst sequence starts at the first clock edge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and data is output on each data cycle after a delay, which depends on the X-latency bits CR13-CR11 of the Configuration Register. The number of words to be output during a Synchronous Burst Read operation can be configured as 4 words, 8 words, 16 words or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Configuration bit CR9). The order of the data output can be modified through the Wrap Burst bit in the Configuration Register. The burst sequence is sequential and can be confined inside the 4-, 8- or 16-word boundary (wrap) or overcome the boundary (no wrap). The WAIT signal may be asserted to indicate to the system that an output delay occurs. This delay depends on the starting address of the burst sequence and on the burst configuration. WAIT is asserted during the X-latency, the WAIT state, and at the end of a 4-, 8- and 16word burst. It is only de-asserted when output data is valid. In Continuous Burst Read mode a WAIT state occurs when crossing the first 16-word boundary. If the starting address is aligned to the burst length (4-, 8- or 16-words), the wrapped configuration has no impact on the output sequence. The WAIT signal can be configured to be active Low or active High by setting CR10 in the Configuration Register. See Table 23: Synchronous Read AC characteristics and Figure 11: Synchronous Burst Read AC waveforms for details. 45/110 Read modes M58LT128HST, M58LT128HSB 7.2.1 Synchronous Burst Read Suspend A Synchronous Burst Read operation can be suspended, freeing the data bus for other higher priority devices. It can be suspended during the initial access latency time (before data is output) or after the device has output data. When the Synchronous Burst Read operation is suspended, internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met. A Synchronous Burst Read operation is suspended when Chip Enable, E, is Low and the current address has been latched (on a Latch Enable rising edge or on a valid clock edge). The Clock signal is then halted at VIH or at VIL, and Output Enable, G, goes High. When Output Enable, G, becomes Low again and the Clock signal restarts, the Synchronous Burst Read operation resumes exactly where it stopped. WAIT reverts to high-impedance whenever Chip Enable, E, or Output Enable, G, goes High. See Table 23: Synchronous Read AC characteristics and Figure 13: Synchronous Burst Read Suspend AC waveforms for details. 7.3 Single Synchronous Read mode Single Synchronous Read operations are similar to Synchronous Burst Read operations except that the memory outputs the same data to the end of the operation. Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI, Block Protection Status, Configuration Register Status or Protection Register. When the addressed bank is in Read CFI, Read Status Register, or Read Electronic Signature mode, the WAIT signal is asserted during the X-latency, the WAIT state, and at the end of a 4-, 8and 16-word burst. It is only de-asserted when output data are valid. See Table 23: Synchronous Read AC characteristics and Figure 12: Single Synchronous Read AC waveforms for details. 46/110 M58LT128HST, M58LT128HSB Dual operations and multiple bank architecture 8 Dual operations and multiple bank architecture The multiple bank architecture of the M58LT128HST/B gives greater flexibility for software developers to split the code and data spaces within the memory array. The dual operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. The dual operations feature means that while programming or erasing in one bank, read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in Program or Erase mode). If a read operation is required in a bank, which is programming or erasing, the program or erase operation can be suspended. Also if the suspended operation was Erase then a Program command can be issued to another block. This means the device can have one block in Erase Suspend mode, one programming, and other banks in Read mode. Bus Read operations are allowed in another bank between setup and confirm cycles of Program or Erase operations. By using a combination of these features, Read operations are possible at any moment in the M58LT128HST/B device. Dual operations between the parameter bank and either of the CFI, the OTP or the electronic signature memory space are not allowed. Table 15 shows which dual operations are allowed or not between the CFI, the OTP, the electronic signature locations, and the memory array. Table 13 and Table 14 show the dual operations possible in other banks and in the same bank. Table 13. Dual operations allowed in other banks Commands allowed in another bank Status of bank Read Array Yes Yes Yes Yes Yes Read Read Read Status CFI Electronic Register Query Signature Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Program, Buffer Program Yes - - - Yes Block Erase Yes - - - - Program Program /Erase /Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes Idle Programming Erasing Program suspended Erase suspended 47/110 Dual operations and multiple bank architecture Table 14. Dual operations allowed in same bank M58LT128HST, M58LT128HSB Commands allowed in same bank Status of bank Read Array Yes - - (1) (1) Read Read Read Status CFI Electronic Register Query Signature Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Program, Buffer Program Yes - - - Yes(3) Block Erase Yes - - - - Program Program /Erase /Erase Suspend Resume Yes Yes Yes - - Yes - - Yes Yes Idle Programming Erasing Program suspended Erase suspended Yes(2) Yes(2) 1. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed. 2. The Read Array command is accepted but the data output is not guaranteed in the block that is being erased, or in the word that is being programmed. 3. Not allowed in the block that is being erased or in the word that is being programmed. Table 15. Dual operation limitations Commands allowed Read main blocks Current status Read CFI/OTP/ electronic signature Read parameter blocks Located in parameter bank No Not located in parameter bank Yes Programming/erasing parameter blocks Located in parameter bank No No Yes No No Yes Programming/ erasing main Not located in blocks parameter bank Programming OTP Yes No Yes No Yes No In different bank only No 48/110 M58LT128HST, M58LT128HSB Block protection 9 Block protection The M58LT128HST/B features an instant, individual block protection scheme that allows any block to be protected or unprotected with no latency. This protection scheme has two levels of protection. Protect/unprotect: this first level allows software only control of block protection. VPP VPPLK : the second level offers a complete hardware protection against Program and Erase operations on all blocks. The protection status of each block can be set to protected and unprotected. Appendix C, Figure 25 shows a flowchart for the protection operations. 9.1 Protection status The protection status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode, issue the Read Electronic Signature command. Subsequent reads at the address specified in Table 7 output the protection status of that block. The protection status is represented by DQ0. DQ0 indicates the block protect/unprotect status. It is set by the Protect command and cleared by the Unprotect command. The following sections explain the operation of the protection system. 9.2 Protected state The default state of all blocks on power-up or after a hardware reset is protected (state = 1). Protected blocks are fully protected from Program or Erase operations. Any Program or Erase operations attempted on a protected block return an error in the Status Register. The state of a protected block can be changed to unprotected using the appropriate software commands. An unprotected block can be protected by issuing the Protect command. 9.3 Unprotected state Unprotected blocks (state = 0) can be programmed or erased. All unprotected blocks return to the protected state after a hardware reset or when the device is powered-down. The state of an unprotected block can be changed to protected using the appropriate software commands. A protected block can be unprotected by issuing the Unprotect command. 49/110 Block protection M58LT128HST, M58LT128HSB 9.4 Protection operations during Erase Suspend Changes to the block protection state can be made during an Erase Suspend by using the standard protection command sequences to unprotect or protect a block. This is useful in the case where another block needs to be updated while an Erase operation is in progress. To change block protection during an Erase operation, first write the Erase Suspend command, then check the Status Register until it indicates that the Erase operation has been suspended. Next, write the desired Protect command sequence to a block and the protection status changes. After completing any desired Protect, Read, or Program operations, resume the Erase operation with the Erase Resume command. If a block is protected during an Erase Suspend of the same block, the Erase operation completes when the erase is resumed. Protection operations cannot be performed during a Program Suspend operation. 50/110 M58LT128HST, M58LT128HSB Program and erase times and endurance cycles 10 Program and erase times and endurance cycles The program and erase times and the number of program/erase cycles per block are shown in Table 16. Exact erase times may change depending on the memory array condition. The best case is when all the bits in the block are at `0' (preprogrammed). The worst case is when all the bits in the block are at `1' (not preprogrammed). Usually, the system overhead is negligible with respect to the erase time. In the M58LT128HST/B the maximum number of program/erase cycles depends on the VPP voltage supply used. Table 16. Program/erase times and endurance cycles(1) (2) Condition Parameter block (16 Kword) Min Typ 0.4 1.2 1.5 12 12 384 768 5 5 100,000 100,000 10 20 Typical after 100kW/E Cycles 1 3 Max 2.5 4 4 180 180 Unit s s s s s s ms s s cycles cycles Parameter Erase Main block (64 Kword) Single word Preprogrammed Not preprogrammed Word program VPP = VDD Program(3) Buffer program Buffer (32 words) (Buffer Program) Main block (64 Kword) Program Suspend latency Erase Program/erase cycles (per block) Main blocks Parameter blocks 51/110 Program and erase times and endurance cycles Table 16. M58LT128HST, M58LT128HSB Program/erase times and endurance cycles(1) (2) (continued) Condition Parameter block (16 Kword) Min Typ 0.4 1 10 2.5 80 80 160 160 1.28 1.28 Typical after 100kW/E Cycles Max 2.5 4 170 Unit s s s s s s ms ms s s 1000 cycles 2500 cycles 16 4 ms ms Parameter Erase Main block (64 Kword) Word program Single word Buffer enhanced factory program(4) Buffer program Buffer (32 words) Buffer enhanced factory program Buffer program Main Block (64 Kwords) Buffer enhanced factory program Buffer program Bank (8 Mbits) Buffer enhanced factory program VPP = VPPH Program (3) Program/erase cycles (per block) Blank check Main blocks Parameter blocks Main blocks Parameter blocks 1. TA = -40 to 85C; VDD = 1.7 V to 2 V; VDDQ = 2.7 V to 3.6 V. 2. Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution). 3. Excludes the time needed to execute the command sequence. 4. This is an average value on the entire device. 52/110 M58LT128HST, M58LT128HSB Maximum rating 11 Maximum rating Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer to the Numonyx SURE Program and other relevant quality documents. Table 17. Symbol TA TBIAS TSTG VIO VDD VDDQ VPP IO tVPPH Absolute maximum ratings Value Parameter Min Ambient operating temperature Temperature under bias Storage temperature Input or output voltage Supply voltage Input/output supply voltage Program voltage Output short circuit current Time for VPP at VPPH -40 -40 -65 -0.5 -0.2 -0.2 -0.2 Max 85 85 125 3.8 2.5 4.2 10 100 100 C C C V V V V mA hours Unit 53/110 DC and AC parameters M58LT128HST, M58LT128HSB 12 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from tests performed under the measurement conditions summarized in Table 18: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 18. Operating and AC measurement conditions M58LT128HST/B Parameter Min VDD supply voltage VDDQ supply voltage VPP supply voltage (factory environment) VPP supply voltage (application environment) Ambient operating temperature Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages 0 to VDDQ VDDQ/2 1.7 2.7 8.5 -0.4 -40 30 5 85 Max 2.0 3.6 9.5 VDDQ+0.4 85 V V V V C pF ns V V Units Figure 7. AC measurement I/O waveform VDDQ VDDQ/2 0V AI06161 54/110 M58LT128HST, M58LT128HSB Figure 8. AC measurement load circuit VDDQ DC and AC parameters VDDQ VDD 22k DEVICE UNDER TEST 0.1F 0.1F CL 22k CL includes JIG capacitance AI12842 Table 19. Symbol CIN COUT Capacitance(1) Parameter Input capacitance Output capacitance Test Condition VIN = 0V VOUT = 0V Min 6 8 Max 8 12 Unit pF pF 1. Sampled only, not 100% tested. 55/110 DC and AC parameters Table 20. Symbol ILI ILO M58LT128HST, M58LT128HSB DC characteristics - currents Parameter Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VIL, G = VIH 4 word 14 13 15 17 21 16 19 22 23 25 25 25 8 10 8 10 24 Typ Max 1 1 16 17 19 21 26 19 23 26 28 75 75 75 20 25 20 25 41 Unit A A mA mA mA mA mA mA mA mA mA A A A mA mA mA mA mA Input leakage current Output leakage current Supply current Asynchronous Read (f=5 MHz) Supply current Synchronous Read (f = 40 MHz) IDD1 8 word 16 word Continuous 4 word Supply current Synchronous Read (f = 52 MHz) 8 word 16 word Continuous IDD2 IDD3 IDD4 Supply current (Reset) Supply current (Standby) Supply current (Automatic Standby) Supply current (Program) RP = VSS 0.2V E = VDDQ 0.2V K=VSS E = VIL, G = VIH VPP = VPPH VPP = VDD IDD5(1) Supply current (Erase) VPP = VPPH VPP = VDD Program/erase in one bank, Asynchronous Read in another bank Program/erase in one bank, Synchronous Read (continuous f=52 MHz) in another bank E = VDDQ 0.2V K=VSS VPP = VPPH VPP = VDD VPP = VPPH VPP = VDD VPP VDD VPP VDD Supply current IDD6(1),(2) (Dual operations) 33 53 mA IDD7(1) Supply current Program/Erase Suspended (standby) VPP supply current (Program) 25 2 0.2 2 0.2 0.2 0.2 75 5 5 5 5 5 5 A mA A mA A A A IPP1(1) VPP supply current (Erase) IPP2 IPP3(1) VPP supply current (Read) VPP supply current (Standby) 1. Sampled only, not 100% tested. 2. VDD Dual Operation current is the sum of Read and Program or Erase currents. 56/110 M58LT128HST, M58LT128HSB Table 21. Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO DC and AC parameters DC characteristics - voltages Parameter Input low voltage Input high voltage Output low voltage Output high voltage VPP program voltage-logic VPP program voltage factory Program or Erase lockout VDD lock voltage IOL = 100A IOH = -100A Program, Erase Program, Erase VDDQ -0.1 1.3 8.5 3 9.0 3.6 9.5 0.4 1 Test Condition Min 0 VDDQ -0.4 Typ Max 0.4 VDDQ + 0.4 0.1 Unit V V V V V V V V 57/110 58/110 DC and AC parameters Figure 9. tAVAV VALID VALID tLHAX tAVQV tAXQX tAVLH A0-A22 L(2) tLLLH tLLQV tELLH E tELQV tELQX tEHQZ tEHQX G tGLQV tGLQX Hi-Z tGLTV tELTV Hi-Z tGHTZ VALID tEHTZ tGHQX tGHQZ Asynchronous random access Read AC waveforms DQ0-DQ15 WAIT(1) M58LT128HST, M58LT128HSB Notes: 1. Write Enable, W, is High, WAIT is active Low. 2. Latch Enable, L, can be kept Low (also at board level) when the Latch Enable function is not required or supported. AI09817 M58LT128HST, M58LT128HSB Figure 10. Asynchronous Page Read AC waveforms A2-A22 tAVAV A0-A1 VALID ADDRESS tAVLH L tLLLH tLLQV tELLH E tELQV tELQX G tGLTV tELTV (1) WAIT Hi-Z tGLQV tGLQX DQ0-DQ15 VALID DATA Outputs Valid Address Latch Enabled tAVQV1 VALID DATA tLHAX VALID ADDRESS DC and AC parameters VALID ADD. VALID ADD. VALID ADD. VALID DATA VALID DATA Valid Data Standby AI13570b 1. WAIT is active Low. 59/110 DC and AC parameters Table 22. Symbol tAVAV tAVQV tAVQV1 tAXQX(1) tELTV tELQV(2) Read Timings tELQX(1) tEHTZ tEHQX(1) tEHQZ (1) M58LT128HST, M58LT128HSB Asynchronous Read AC characteristics M58LT128HST/B Alt tRC tACC tPAGE tOH Parameter 85 Address Valid to Next Address Valid Address Valid to Output Valid (Random) Address Valid to Output Valid (Page) Address Transition to Output Transition Chip Enable Low to Wait Valid tCE tLZ Chip Enable Low to Output Valid Chip Enable Low to Output Transition Chip Enable High to Wait Hi-Z tOH tHZ tOE tOLZ Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Wait Valid tOH tDF Output Enable High to Output Transition Output Enable High to Output Hi-Z Output Enable High to Wait Hi-Z tAVADVH tELADVH tADVHAX Address Valid to Latch Enable High Chip Enable Low to Latch Enable High Latch Enable High to Address Transition Min Max Max Min Max Max Min Max Min Max Max Min Max Min Max Max Min Min Min Min Max 85 85 25 0 17 85 0 17 0 17 25 0 17 0 17 17 10 10 9 10 85 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tGLQV(2) tGLQX(1) tGLTV tGHQX (1) tGHQZ(1) tGHTZ tAVLH Latch Timings tELLH tLHAX tLLLH tLLQV tADVLADVH Latch Enable Pulse Width tADVLQV Latch Enable Low to Output Valid (Random) 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. 60/110 DQ0-DQ15 VALID VALID VALID NOT VALID VALID Hi-Z M58LT128HST, M58LT128HSB A0-A22 VALID ADDRESS tAVLH tLLLH L tEHQX tKHQV Note 1 tKHAX tEHEL tKHQX tEHQZ tLLKH tAVKH K(4) tELKH E tGHQX tGLQX tGHQZ Figure 11. Synchronous Burst Read AC waveforms G tGLTV Note 2 tKHTV tKHTX Note 2 Note 2 Valid Valid Data Flow Boundary Crossing Data tEHTZ Hi-Z WAIT X Latency Address Latch Standby DC and AC parameters Note 1. The number of clock cycles to be inserted depends on the X-latency set in the Burst Configuration Register. 2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low. 3. Address latched and data output on the rising clock edge. 4. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge of K is the rising one. 61/110 AI09819c DC and AC parameters Figure 12. Single Synchronous Read AC waveforms A0-A22 VALID ADDRESS tAVKH L tLLKH K(2) tELKH tELQV E tGLQV tGLQX G tELQX DQ0-DQ15 Hi-Z tKHQV M58LT128HST, M58LT128HSB tGHTZ VALID tKHTV tGLTV WAIT(1,2) Hi-Z Ai12359 1. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 2. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge is the rising one. 62/110 Hi-Z VALID VALID VALID VALID DQ0-DQ15 M58LT128HST, M58LT128HSB A0-A22 VALID ADDRESS tAVLH tLLLH L tEHQX tKHQV Note 1 Note 3 tEHEL tEHQZ tLLKH tAVKH K(4) tELKH tKHAX E tGLQX tGLQV tGHQZ tGHQX G tGLTV tGHTZ tEHTZ Figure 13. Synchronous Burst Read Suspend AC waveforms Hi-Z WAIT(2) Notes 1. The number of clock cycles to be inserted depends on the X-latency set in the Configuration Register. 2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 3. The CLOCK signal can be held high or low. 4. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge is the rising one. AI12366c DC and AC parameters 63/110 DC and AC parameters Figure 14. Clock input AC waveform tKHKL M58LT128HST, M58LT128HSB tKHKH tf tr tKLKH AI06981 Table 23. Symbol tAVKH Synchronous Read Timings tELKH tEHEL tEHTZ tKHAX tKHQV tKHTV tKHQX tKHTX tLLKH Clock Specifications tKHKH tKHKL tKLKH tf tr Synchronous Read AC characteristics(1) (2) M58LT128HST/B Alt tAVCLKH tELCLKH Parameter 85 Address Valid to Clock High Chip Enable Low to Clock High Chip Enable Pulse Width (subsequent synchronous reads) Chip Enable High to Wait Hi-Z tCLKHAX tCLKHQV tCLKHQX tADVLCLKH tCLK Clock High to Address Transition Clock High to Output Valid Clock High to WAIT Valid Clock High to Output Transition Clock High to WAIT Transition Latch Enable Low to Clock High Clock Period (f=52 MHz) Clock High to Clock Low Clock Low to Clock High Clock Fall or Rise Time Min Min Min Max Min Max Min Min Min Min 9 9 20 17 10 17 3 9 19 6 ns ns ns ns ns ns ns ns ns ns Unit Max 2 ns 1. Sampled only, not 100% tested. 2. For other timings please refer to Table 22: Asynchronous Read AC characteristics. 64/110 PROGRAM OR ERASE tAVAV BANK ADDRESS VALID ADDRESS tAVWH tWHAV tWHAX VALID ADDRESS tLHAX tLLLH A0-A22 M58LT128HST, M58LT128HSB tAVLH L tWHLL tELLH E tWHEH tELWL G tWHWL tWHGL tGHWL W tWLWH tWHDX COMMAND CMD or DATA tWHVPL tVPHWH tQVVPL STATUS REGISTER tWHEL tELQV tDVWH Figure 15. Write AC waveforms, Write Enable controlled DQ0-DQ15 VPP tELKV K CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING Ai12889 DC and AC parameters SET-UP COMMAND 65/110 DC and AC parameters Table 24. Symbol tAVAV tAVLH tAVWH(2) tDVWH tELLH tELWL Write Enable Controlled Timings tELQV tELKV tGHWL tLHAX tLLLH tWHAV(2) tWHAX(2) tWHDX tWHEH tWHEL (3) M58LT128HST, M58LT128HSB Write AC characteristics, Write Enable controlled(1) M58LT128HST/B Alt tWC Parameter 85 Address Valid to Next Address Valid Address Valid to Latch Enable High Address Valid to Write Enable High tDS Data Valid to Write Enable High Chip Enable Low to Latch Enable High tCS Chip Enable Low to Write Enable Low Chip Enable Low to Output Valid Chip Enable Low to Clock Valid Output Enable High to Write Enable Low Latch Enable High to Address Transition Latch Enable Pulse Width Write Enable High to Address Valid tAH tDH tCH Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Chip Enable Low Write Enable High to Output Enable Low Write Enable High to Latch Enable Low tWPH Write Enable High to Write Enable Low tWP Write Enable Low to Write Enable High Output (Status Register) Valid to VPP Low tVPS VPP High to Write Enable High Write Enable High to VPP Low Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 85 10 50 50 10 0 85 9 17 9 10 0 0 0 0 25 0 25 25 50 0 200 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tWHGL tWHLL(3) tWHWL tWLWH Protection Timings tQVVPL tVPHWH tWHVPL Min 200 ns 1. Sampled only, not 100% tested. 2. Meaningful only if L is always kept low. 3. tWHEL and tWHLL have this value when reading in the targeted bank or when reading following a Set Configuration Register command. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the Configuration Register have been issued, tWHEL and tWHLL are 0 ns. 66/110 PROGRAM OR ERASE tAVAV BANK ADDRESS VALID ADDRESS tAVEH tEHAX VALID ADDRESS tLHAX tLLLH A0-A22 M58LT128HST, M58LT128HSB tAVLH L tELLH tEHWH W tWLEL G tGHEL tEHEL tEHGL E tELEH tEHDX COMMAND CMD or DATA tEHVPL tVPHEH tQVVPL STATUS REGISTER tWHEL tELQV tDVEH Figure 16. Write AC waveforms, Chip Enable controlled DQ0-DQ15 VPP tELKV K CONFIRM COMMAND OR DATA INPUT STATUS REGISTER READ 1st POLLING SET-UP COMMAND DC and AC parameters 67/110 Ai12890 DC and AC parameters Table 25. Symbol tAVAV tAVEH tAVLH tDVEH tEHAX Chip Enable Controlled Timings tEHDX tEHEL tEHGL tEHWH tELKV tELEH tELLH tELQV tGHEL tLHAX tLLLH tWHEL (2) M58LT128HST, M58LT128HSB Write AC characteristics, Chip Enable controlled(1) M58LT128HST/B Alt tWC Parameter 85 Address Valid to Next Address Valid Address Valid to Chip Enable High Address Valid to Latch Enable High tDS tAH tDH tCPH Data Valid to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Input Transition Chip Enable High to Chip Enable Low Chip Enable High to Output Enable Low tCH Chip Enable High to Write Enable High Chip Enable Low to Clock Valid tCP Chip Enable Low to Chip Enable High Chip Enable Low to Latch Enable High Chip Enable Low to Output Valid Output Enable High to Chip Enable Low Latch Enable High to Address Transition Latch Enable Pulse Width Write Enable High to Chip Enable Low tCS Write Enable Low to Chip Enable Low Chip Enable High to VPP Low Output (Status Register) Valid to VPP Low tVPS VPP High to Chip Enable High Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 85 50 10 50 0 0 25 0 0 9 50 10 85 17 9 10 25 0 200 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tWLEL Protection Timings tEHVPL tQVVPL tVPHEH Min 200 ns 1. Sampled only, not 100% tested. 2. tWHEL has this value when reading in the targeted bank or when reading following a Set Configuration Register command. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the Configuration Register have been issued, tWHEL is 0 ns. 68/110 M58LT128HST, M58LT128HSB Figure 17. Reset and power-up AC waveforms DC and AC parameters W, E, G, L tPHWL tPHEL tPHGL tPHLL tPLWL tPLEL tPLGL tPLLL RP tVDHPH VDD, VDDQ Power-Up Reset AI06976 tPLPH Table 26. Symbol tPLWL tPLEL tPLGL tPLLL tPHWL tPHEL tPHGL tPHLL tPLPH(1),(2) tVDHPH(3) Reset and power-up AC characteristics Parameter Reset Low to Write Enable Low, Chip Enable Low, Output Enable Low, Latch Enable Low Reset High to Write Enable Low Chip Enable Low Output Enable Low Latch Enable Low RP Pulse Width Supply Voltages High to Reset High Test condition During Program During Erase Read Other conditions Min Min Min Min 85 25 25 80 20 Unit s s ns s Min 30 ns Min Min 50 250 ns s 1. The device Reset is possible but not guaranteed if tPLPH < 50ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during power-up or reset. 69/110 Package mechanical M58LT128HST, M58LT128HSB 13 Package mechanical To meet environmental requirements, Numonyx offers the M58LT128HST and M58LT128HSB devices in ECOPACK(R) packages that have a lead-free, second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 18. TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, bottom view package outline D FD FE D1 SD E E1 SE ddd BALL "A1" A e b A1 A2 BGA-Z23 1. Drawing is not to scale. 70/110 M58LT128HST, M58LT128HSB Table 27. Package mechanical TBGA64 10 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package mechanical data millimeters inches Max 1.200 0.300 0.800 0.350 10.000 7.000 9.900 - 0.500 10.100 - 0.100 1.000 13.000 7.000 1.500 3.000 0.500 0.500 - 12.900 - - - - - - 13.100 - - - - - 0.0394 0.5118 0.2756 0.0591 0.1181 0.0197 0.0197 - 0.5079 - - - - - 0.3937 0.2756 0.200 0.350 0.0118 0.0315 0.0138 0.3898 - 0.0197 0.3976 - 0.0039 - 0.5157 - - - - - 0.0079 Typ Min Max 0.0472 0.0138 Symbol Typ A A1 A2 b D D1 ddd e E E1 FD FE SD SE Min 71/110 Part numbering M58LT128HST, M58LT128HSB 14 Part numbering Table 28. Example: Device type M58 Architecture L = multilevel, multiple bank, burst mode Operating voltage T = VDD = 1.7 V to 2.0 V, VDDQ = 2.7 V to 3.6 V Density 128 = 128 Mbit (x16) Technology H = 90nm technology Security S = Secure Parameter location T = Top boot B = Bottom boot Speed 8 = 85 ns Package ZA = TBGA64, 10 x 13 mm, 1 mm pitch Temperature range 6 = -40 to 85C Packing option E = ECOPACK(R) package, standard packing F = ECOPACK(R) package, tape & reel packing T = tape & reel packing Blank = standard packing Ordering information scheme M58LT128HST 8 ZA 6 E Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the Numonyx Sales Office nearest to you. 72/110 M58LT128HST, M58LT128HSB Block address tables Appendix A Table 29. Block address tables Top boot block addresses, M58LT128HST # 0 1 2 Parameter Bank 3 4 5 6 7 8 9 10 11 12 13 Bank 1 14 15 16 17 18 19 20 21 Bank 2 22 23 24 25 26 27 28 29 Bank 3 30 31 32 33 34 Size (Kword) 16 16 16 16 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address range 7FC000-7FFFFF 7F8000-7FBFFF 7F4000-7F7FFF 7F0000-7F3FFF 7E0000-7EFFFF 7D0000-7DFFFF 7C0000-7CFFFF 7B0000-7BFFFF 7A0000-7AFFFF 790000-79FFFF 780000-78FFFF 770000-77FFFF 760000-76FFFF 750000-75FFFF 740000-74FFFF 730000-73FFFF 720000-72FFFF 710000-71FFFF 700000-70FFFF 6F0000-6FFFFF 6E0000-6EFFFF 6D0000-6DFFFF 6C0000-6CFFFF 6B0000-6BFFFF 6A0000-6AFFFF 690000-69FFFF 680000-68FFFF 670000-67FFFF 660000-66FFFF 650000-65FFFF 640000-64FFFF 630000-63FFFF 620000-62FFFF 610000-61FFFF 600000-60FFFF Bank(1) 73/110 Block address tables Table 29. M58LT128HST, M58LT128HSB Top boot block addresses, M58LT128HST (continued) # 35 36 37 Bank 4 38 39 40 41 42 43 44 45 Bank 5 46 47 48 49 50 51 52 53 Bank 6 54 55 56 57 58 59 60 61 Bank 7 62 63 64 65 66 Size (Kword) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address range 5F0000-5FFFFF 5E0000-5EFFFF 5D0000-5DFFFF 5C0000-5CFFFF 5B0000-5BFFFF 5A0000-5AFFFF 590000-59FFFF 580000-58FFFF 570000-57FFFF 560000-56FFFF 550000-55FFFF 540000-54FFFF 530000-53FFFF 520000-52FFFF 510000-51FFFF 500000-50FFFF 4F0000-4FFFFF 4E0000-4EFFFF 4D0000-4DFFFF 4C0000-4CFFFF 4B0000-4BFFFF 4A0000-4AFFFF 490000-49FFFF 480000-48FFFF 470000-47FFFF 460000-46FFFF 450000-45FFFF 440000-44FFFF 430000-43FFFF 420000-42FFFF 410000-41FFFF 400000-40FFFF Bank(1) 74/110 M58LT128HST, M58LT128HSB Table 29. Block address tables Top boot block addresses, M58LT128HST (continued) # 67 68 69 Bank 8 70 71 72 73 74 75 76 77 Bank 9 78 79 80 81 82 83 84 85 Bank 10 86 87 88 89 90 91 92 93 Bank 11 94 95 96 97 98 Size (Kword) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address range 3F0000-3FFFFF 3E0000-3EFFFF 3D0000-3DFFFF 3C0000-3CFFFF 3B0000-3BFFFF 3A0000-3AFFFF 390000-39FFFF 380000-38FFFF 370000-37FFFF 360000-36FFFF 350000-35FFFF 340000-34FFFF 330000-33FFFF 320000-32FFFF 310000-31FFFF 300000-30FFFF 2F0000-2FFFFF 2E0000-2EFFFF 2D0000-2DFFFF 2C0000-2CFFFF 2B0000-2BFFFF 2A0000-2AFFFF 290000-29FFFF 280000-28FFFF 270000-27FFFF 260000-26FFFF 250000-25FFFF 240000-24FFFF 230000-23FFFF 220000-22FFFF 210000-21FFFF 200000-20FFFF Bank(1) 75/110 Block address tables Table 29. M58LT128HST, M58LT128HSB Top boot block addresses, M58LT128HST (continued) # 99 100 101 Bank 12 102 103 104 105 106 107 108 109 Bank 13 110 111 112 113 114 115 116 117 Bank 14 118 119 120 121 122 123 124 125 Bank 15 126 127 128 129 130 Size (Kword) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address range 1F0000-1FFFFF 1E0000-1EFFFF 1D0000-1DFFFF 1C0000-1CFFFF 1B0000-1BFFFF 1A0000-1AFFFF 190000-19FFFF 180000-18FFFF 170000-17FFFF 160000-16FFFF 150000-15FFFF 140000-14FFFF 130000-13FFFF 120000-12FFFF 110000-11FFFF 100000-10FFFF 0F0000-0FFFFF 0E0000-0EFFFF 0D0000-0DFFFF 0C0000-0CFFFF 0B0000-0BFFFF 0A0000-0AFFFF 090000-09FFFF 080000-08FFFF 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 000000-00FFFF Bank(1) 1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only; Bank Region 2 contains the banks that are made up of the parameter and main blocks (Parameter Bank). 76/110 M58LT128HST, M58LT128HSB Table 30. Bottom boot block addresses, M58LT128HSB # 130 129 128 Bank 15 127 126 125 124 123 122 121 120 Bank 14 119 118 117 116 115 114 113 112 Bank 13 111 110 109 108 107 106 105 104 Bank 12 103 102 101 100 99 Size (Kword) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Block address tables Bank(1) Address range 7F0000-7FFFFF 7E0000-7EFFFF 7D0000-7DFFFF 7C0000-7CFFFF 7B0000-7BFFFF 7A0000-7AFFFF 790000-79FFFF 780000-78FFFF 770000-77FFFF 760000-76FFFF 750000-75FFFF 740000-74FFFF 730000-73FFFF 720000-72FFFF 710000-71FFFF 700000-70FFFF 6F0000-6FFFFF 6E0000-6EFFFF 6D0000-6DFFFF 6C0000-6CFFFF 6B0000-6BFFFF 6A0000-6AFFFF 690000-69FFFF 680000-68FFFF 670000-67FFFF 660000-66FFFF 650000-65FFFF 640000-64FFFF 630000-63FFFF 620000-62FFFF 610000-61FFFF 600000-60FFFF 77/110 Block address tables Table 30. M58LT128HST, M58LT128HSB Bottom boot block addresses, M58LT128HSB (continued) # 98 97 96 Bank 11 95 94 93 92 91 90 89 88 Bank 10 87 86 85 84 83 82 81 80 Bank 9 79 78 77 76 75 74 73 72 Bank 8 71 70 69 68 67 Size (Kword) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address range 5F0000-5FFFFF 5E0000-5EFFFF 5D0000-5DFFFF 5C0000-5CFFFF 5B0000-5BFFFF 5A0000-5AFFFF 590000-59FFFF 580000-58FFFF 570000-57FFFF 560000-56FFFF 550000-55FFFF 540000-54FFFF 530000-53FFFF 520000-52FFFF 510000-51FFFF 500000-50FFFF 4F0000-4FFFFF 4E0000-4EFFFF 4D0000-4DFFFF 4C0000-4CFFFF 4B0000-4BFFFF 4A0000-4AFFFF 490000-49FFFF 480000-48FFFF 470000-47FFFF 460000-46FFFF 450000-45FFFF 440000-44FFFF 430000-43FFFF 420000-42FFFF 410000-41FFFF 400000-40FFFF Bank(1) 78/110 M58LT128HST, M58LT128HSB Table 30. Block address tables Bottom boot block addresses, M58LT128HSB (continued) # 66 65 64 Bank 7 63 62 61 60 59 58 57 56 Bank 6 55 54 53 52 51 50 49 48 Bank 5 47 46 45 44 43 42 41 40 Bank 4 39 38 37 36 35 Size (Kword) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address range 3F0000-3FFFFF 3E0000-3EFFFF 3D0000-3DFFFF 3C0000-3CFFFF 3B0000-3BFFFF 3A0000-3AFFFF 390000-39FFFF 380000-38FFFF 370000-37FFFF 360000-36FFFF 350000-35FFFF 340000-34FFFF 330000-33FFFF 320000-32FFFF 310000-31FFFF 300000-30FFFF 2F0000-2FFFFF 2E0000-2EFFFF 2D0000-2DFFFF 2C0000-2CFFFF 2B0000-2BFFFF 2A0000-2AFFFF 290000-29FFFF 280000-28FFFF 270000-27FFFF 260000-26FFFF 250000-25FFFF 240000-24FFFF 230000-23FFFF 220000-22FFFF 210000-21FFFF 200000-20FFFF Bank(1) 79/110 Block address tables Table 30. M58LT128HST, M58LT128HSB Bottom boot block addresses, M58LT128HSB (continued) # 34 33 32 Bank 3 31 30 29 28 27 26 25 24 Bank 2 23 22 21 20 19 18 17 16 Bank 1 15 14 13 12 11 10 9 8 Parameter Bank 7 6 5 4 3 2 1 0 Size (Kword) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 16 16 16 16 Address range 1F0000-1FFFFF 1E0000-1EFFFF 1D0000-1DFFFF 1C0000-1CFFFF 1B0000-1BFFFF 1A0000-1AFFFF 190000-19FFFF 180000-18FFFF 170000-17FFFF 160000-16FFFF 150000-15FFFF 140000-14FFFF 130000-13FFFF 120000-12FFFF 110000-11FFFF 1F0000-1FFFFF 0F0000-0FFFFF 0E0000-0EFFFF 0D0000-0DFFFF 0C0000-0CFFFF 0B0000-0BFFFF 0A0000-0AFFFF 090000-09FFFF 080000-08FFFF 070000-07FFFF 060000-06FFFF 050000-05FFFF 040000-04FFFF 030000-03FFFF 020000-02FFFF 010000-01FFFF 00C000-00FFFF 008000-00BFFF 004000-007FFF 000000-003FFF Bank(1) 1. There are two bank regions: bank region 2 contains all the banks that are made up of main blocks only; bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank). 80/110 M58LT128HST, M58LT128HSB Common Flash Interface Appendix B Common Flash Interface The Common Flash Interface is a JEDEC-approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information, and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 31, 32, 33, 34, 35, 36, 37, 38, 39 and 40 show the addresses used to retrieve the data. The query data is always presented on the lowest order data outputs (DQ0-DQ7), and the other outputs (DQ8-DQ15) are set to 0. The CFI data structure also contains a security area where a 64-bit unique security number is written (see Figure 4: Protection Register memory map). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by Numonyx. Issue a Read Array command to return to Read mode. Table 31. Offset 000h 010h 01Bh 027h P A 080h Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Alternate Algorithm-specific Extended Query table Security Code Area Query structure overview Sub-section name Description Reserved for algorithm-specific information Command set ID and algorithm data offset Device timing and voltage information Flash device layout Additional information specific to the primary algorithm (optional) Additional information specific to the alternate algorithm (optional) Lock Protection Register, unique device number and user-programmable OTP 1. The Flash memory displays the CFI data structure when the CFI Query command is issued. This table lists the main sub-sections detailed in Tables 32, 33, 34 and 35. Query data is always presented on the lowest order data outputs. 81/110 Common Flash Interface Table 32. Offset 000h 001h 002h-00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah M58LT128HST, M58LT128HSB CFI query identification string Sub-section name 0020h 88D6h 88D7h Reserved 0051h 0052h 0059h 0001h 0000h offset = P = 000Ah 0001h 0000h 0000h value = A = 0000h 0000h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended query table (see Table 35) Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported Address for Alternate Algorithm extended query table p = 10Ah Query unique ASCII string "QRY" Manufacturer code Device code Reserved "Q" "R" "Y" M58LT128HST M58LT128HSB Description Value Numonyx Top Bottom NA NA 82/110 M58LT128HST, M58LT128HSB Table 33. Offset Common Flash Interface CFI query system interface information Data Description VDD logic supply minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VDD logic supply maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts VPP [programming] supply minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts VPP [programming] supply maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts Typical timeout per single byte/word program = 2n s Typical timeout for Buffer Program = 2 s Typical timeout per individual block erase = Typical timeout for full chip erase = 2n ms Maximum timeout for word program = 2 times typical Maximum timeout for Buffer Program = 2n times typical n n n Value 01Bh 0017h 1.7V 01Ch 0020h 2V 01Dh 0085h 8.5V 01Eh 01Fh 020h 021h 022h 023h 024h 025h 026h 0095h 0004h 0009h 000Ah 0000h 0004h 0004h 0002h 0000h 9.5V 16s 512s 2n ms 1s NA 256 s 8192 s 4s NA Maximum timeout per individual block erase = 2 times typical Maximum timeout for chip erase = 2n times typical 83/110 Common Flash Interface Table 34. Offset 027h 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh TOP DEVICES 02Fh 030h 031h 032h 033h 034h 035h 038h 02Dh 02Eh BOTTOM DEVICES 02Fh 030h 031h 032h 033h 034h 035h 038h M58LT128HST, M58LT128HSB Device geometry definition Data 0018h 0001h 0000h 0006h 0000h 0002h 007Eh 0000h 0000h 0002h 0003h 0000h 0080h 0000h Description Device size = 2n in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of identical size erase block regions within the device bit 7 to 0 = x = number of Erase Block regions Erase Block Region 1 information Number of identical-size erase blocks = 007Eh+1 Erase Block Region 1 information Block size in Region 1 = 0200h * 256 byte Erase Block Region 2 information Number of identical-size erase blocks = 0003h+1 Erase Block Region 2 information Block size in Region 2 = 0080h * 256 byte Value 16 Mbytes x16 Async. 64 bytes 2 127 128 Kbyte 4 32 Kbyte NA 4 32 Kbytes 127 128 Kbytes NA Reserved Reserved for future erase block region information 0003h 0000h 0080h 0000h 007Eh 0000h 0000h 0002h Erase Block Region 1 information Number of identical-size erase block = 0003h+1 Erase Block Region 1 information Block size in Region 1 = 0080h * 256 bytes Erase Block Region 2 information Number of identical-size erase block = 007Eh+1 Erase Block Region 2 information Block size in Region 2 = 0200h * 256 bytes Reserved Reserved for future erase block region information 84/110 M58LT128HST, M58LT128HSB Table 35. Offset (P)h = 10Ah Common Flash Interface Primary algorithm-specific extended query table Data 0050h 0052h 0049h Primary Algorithm extended query table unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Extended query table contents for Primary Algorithm. address (P+5)h contains less significant bytes. bit 0 Chip Erase supported(1 = Yes, 0 = No) bit 1 Erase Suspend supported(1 = Yes, 0 = No) bit 2 Program Suspend supported(1 = Yes, 0 = No) bit 3 Legacy Protect/Unprotect supported(1 = Yes, 0 = No) bit 4 Queued Erase supported(1 = Yes, 0 = No) bit 5 Instant individual block protection supported(1 = Yes, 0 = No) bit 6 Protection bits supported(1 = Yes, 0 = No) bit 7 Page mode read supported(1 = Yes, 0 = No) bit 8 Synchronous read supported(1 = Yes, 0 = No) bit 9 Simultaneous operation supported(1 = Yes, 0 = No) bit 10 to 31 Reserved; undefined bits are `0'. If bit 31 is '1' then another 31 bit field of optional features follows at the end of the bit-30 field. Supported Functions after Suspend Read Array, Read Status Register and CFI Query Description Value "P" "R" "I" "1" "3" (P+3)h =10Dh (P+4)h = 10Eh (P+5)h = 10Fh 0031h 0033h 00E6h 0003h (P+7)h = 111h 0000h (P+8)h = 112h 0000h No Yes Yes No No Yes Yes Yes Yes Yes (P+9)h = 113h 0001h bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No) bit 7 to 1 Reserved; undefined bits are `0' Yes (P+A)h = 114h 0003h Block Protect Status Defines which bits in the Block Status Register section of the query are implemented. bit 0 Block protect Status Register Protect/Unprotect bit active (1 = Yes, 0 = No) bit 1 Block Protection Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are `0' VDD logic supply optimum Program/Erase voltage (highest performance) (P+B)h = 115h 0000h Yes No (P+C)h = 116h 0018h bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP supply optimum Program/Erase voltage 1.8V (P+D)h = 117h 0090h bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV 9V 85/110 Common Flash Interface Table 36. Offset (P+E)h = 118h (P+F)h = 119h (P+10)h = 11Ah (P+ 11)h = 11Bh (P+12)h = 11Ch (P+13)h = 11Dh (P+14)h = 11Eh (P+15)h = 11Fh (P+16)h = 120h (P+17)h = 121h (P+18)h = 122h (P+19)h = 123h (P+1A)h = 124h (P+1B)h = 125h (P+1C)h = 126h M58LT128HST, M58LT128HSB Protection Register information Data 0002h Description Number of Protection Register fields in JEDEC ID space. 0000h indicates that 256 fields are available. Value 2 80h 00h 8 bytes 8 bytes 89h Protection Register 2: protection description Bits 0-31 Protection Register address Bits 32-39 n number of factory programmed regions (lower byte) Bits 40-47 n number of factory programmed regions (upper byte) Bits 48-55 2n bytes in factory programmable region Bits 56-63 n number of user programmable regions (lower byte) Bits 64-71 n number of user programmable regions (upper byte) Bits 72-79 2n bytes in user programmable region 00h 00h 00h 0 0 0 16 0 16 0080h Protection Field 1: Protection description 0000h Bits 0-7 Lower byte of Protection Register address Bits 8-15 Upper byte of Protection Register address 0003h Bits 16-23 2n bytes in factory preprogrammed region 0003h Bits 24-31 2n bytes in user-programmable region 0089h 0000h 0000h 0000h 0000h 0000h 0000h 0010h 0000h 0004h Table 37. Offset Burst Read information Data Description Value (P+1D)h = 127h Page-mode read capability bits 0-7 n' such that 2n HEX value represents the number of 0003h read-page bytes. See offset 0028h for device word width to determine page-mode data output width. 0004h Number of Synchronous mode read configuration fields that follow. 8 bytes (P+1E)h = 128h 4 (P+1F)h = 129h Synchronous mode read capability configuration 1 bit 3-7 Reserved bit 0-2 n' such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear 0001h bursts that output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the read Configuration Register bit 0-2 if the device is configured for its maximum word width. See offset 0028h for word width to determine the burst data output width. 0002h Synchronous mode read capability configuration 2 0003h Synchronous mode read capability configuration 3 0007h Synchronous mode read capability configuration 4 4 (P+20)h = 12Ah (P-21)h = 12Bh (P+22)h = 12Ch 8 16 Cont. 86/110 M58LT128HST, M58LT128HSB Table 38. Bank and Erase Block region information(1) (2) Flash memory (bottom) Common Flash Interface Flash memory (top) Offset (P+23)h = 12Dh Data 02h Description Offset (P+23)h = 12Dh Data 02h Number of bank regions within the device 1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank regions. There are two bank regions, see Table 29 and Table 30. Table 39. Bank and Erase Block region 1 information M58LT128HSB (bottom) Offset (P+24)h = 12Eh (P+25)h = 12Fh Data 01h Number of identical banks within bank region 1 00h Number of program or erase operations allowed in bank region 1: Bits 0-3: Number of simultaneous Program operations Bits 4-7: Number of simultaneous Erase operations Number of Program or Erase operations allowed in other banks while a bank in same region is programming Bits 0-3: Number of simultaneous Program operations Bits 4-7: Number of simultaneous Erase operations Number of Program or Erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous Program operations Bits 4-7: Number of simultaneous Erase operations Types of Erase Block regions in bank region 1 n = number of Erase Block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region(2). Bank region 1 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical size erase blocks Bits 16-31: nx256 = number of bytes in Erase Block region Bank region 1 (Erase Block Type 1) Minimum block erase cycles x 1000 Description M58LT128HST (top) Offset (P+24)h = 12Eh (P+25)h = 12Fh Data 0Fh 00h (P+26)h = 130h 11h (P+26)h = 130h 11h (P+27)h = 131h 00h (P+27)h = 131h 00h (P+28)h = 132h 00h (P+28)h = 132h 00h (P+29)h = 133h 01h (P+29)h = 133h 02h (P+2A)h = 134h (P+2B)h = 135h (P+2C)h = 136h (P+2D)h = 137h (P+2E)h = 138h (P+2F)h = 139h 07h 00h 00h 02h 64h 00h (P+2A)h = 134h (P+2B)h = 135h (P+2C)h = 136h (P+2D)h = 137h (P+2E)h = 138h (P+2F)h = 139h 03h 00h 80h 00h 64h 00h 87/110 Common Flash Interface Table 39. M58LT128HST, M58LT128HSB Bank and Erase Block region 1 information (continued) M58LT128HSB (bottom) Offset Data Bank region 1 (Erase Block Type 1): bits per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank region 1 (Erase Block Type 1): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Bank region 1 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical size Erase Blocks Bits 16-31: nx256 = number of bytes in Erase Block region Bank region 1 (Erase Block Type 2) Minimum Block Erase cycles x 1000 Bank regions 1 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank region 1 (Erase Block Type 2): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Description M58LT128HST (top) Offset Data (P+30)h = 13Ah 01h (P+30)h = 13Ah 01h (P+31)h = 13Bh 03h (P+31)h = 13Bh 03h (P+32)h = 13Ch (P+33)h = 13Dh (P+34)h = 13Eh (P+35)h = 13Fh (P+36)h = 140h (P+37)h = 141h 06h 00h 00h 02h 64h 00h (P+38)h = 142h 01h (P+39)h = 143h 03h 1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank regions. There are two bank regions, see Table 29 to Table 30. 88/110 M58LT128HST, M58LT128HSB Table 40. Bank and Erase Block region 2 Information M58LT128HSB (bottom) Offset (P+3A)h = 144h (P+3B)h = 145h Data 0Fh Common Flash Interface M58LT128HST (top) Offset (P+32)h = 13Ch (P+33)h = 13Dh Data 01h 00h Description Number of identical banks within bank region 2 00h Number of Program or Erase operations allowed in bank region 2: Bits 0-3: Number of simultaneous Program operations Bits 4-7: Number of simultaneous Erase operations Number of Program or Erase operations allowed in other banks while a bank in this region is programming Bits 0-3: Number of simultaneous Program operations Bits 4-7: Number of simultaneous Erase operations Number of Program or Erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous Program operations Bits 4-7: Number of simultaneous Erase operations Types of Erase Block regions in Bank Region 2 n = number of Erase Block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(2) Bank region 2 Erase Block type 1 Information Bits 0-15: n+1 = number of same-size erase blocks Bits 16-31: nx256 = number of bytes in Erase Block region Bank region 2 (Erase Block type 1) Minimum Block Erase cycles x 1000 Bank region 2 (Erase Block type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in Erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved (P+34)h = 13Eh 11h (P+3C)h = 146h 11h (P+35)h = 13Fh 00h (P+3D)h = 147h 00h (P+36)h = 140h 00h (P+3E)h = 148h 00h (P+37)h = 141h 02h (P+3F)h = 149h 01h (P+38)h = 142h (P+39)h = 143h (P+3A)h = 144h (P+3B)h = 145h (P+3C)h = 146h (P+3D)h = 147h 06h 00h 00h 02h 64h 00h (P+40)h = 14Ah (P+41)h = 14Bh (P+42)h = 14Ch (P+43)h = 14Dh (P+44)h = 14Eh (P+45)h = 14Fh 07h 00h 00h 02h 64h 00h (P+3E)h = 148h 01h (P+46)h = 150h 01h 89/110 Common Flash Interface Table 40. M58LT128HST, M58LT128HSB Bank and Erase Block region 2 Information (continued) M58LT128HSB (bottom) Offset Data Bank region 2 (Erase Block type 1):Page mode and Synchronous mode capabilities (defined in Table 37) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Bank region 2 Erase Block type 2 Information Bits 0-15: n+1 = number of same-size erase blocks Bits 16-31: n x 256 = number of bytes in Erase Block region Bank region 2 (Erase Block type 2) Minimum Block Erase cycles x 1000 Bank region 2 (Erase Block type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in Erase region Bit 4: reserved for "internal ECC used" BIts 5-7: reserved Bank region 2 (Erase Block type 2): Page mode and Synchronous mode capabilities (defined in Table 37) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+48)h = 152h (P+43)h = 153h Feature Space definitions Reserved Description M58LT128HST (top) Offset Data (P+3F)h = 149h 03h (P+47)h = 151h 03h (P+40)h = 14Ah (P+41)h = 14Bh (P+42)h = 14Ch (P+43)h = 14Dh (P+44)h = 14Eh (P+45)h = 14Fh 03h 00h 80h 00h 64h 00h (P+46)h = 150h 01h (P+47)h = 151h 03h (P+48)h = 152h (P+49)h = 153h 1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank regions. There are two bank regions, see Table 29 and Table 30. 90/110 M58LT128HST, M58LT128HSB Flowcharts and pseudo codes Appendix C Flowcharts and pseudo codes Figure 19. Program flowchart and pseudo code Start program_command (addressToProgram, dataToProgram) {: Write 40h or 10h (3) writeToFlash (addressToProgram, 0x40); /*writeToFlash (addressToProgram, 0x10);*/ /*see note (3)*/ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram); "see note (3)"; /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ; YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End } NO Program to Protected Block Error (1, 2) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; Write Address & Data Read Status Register (3) SR7 = 1 AI06170b 1. Status check of SR1 (protected block), SR3 (VPP Invalid) and SR4 (program error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used. 91/110 Flowcharts and pseudo codes Figure 20. Blank Check flowchart and pseudo code Start M58LT128HST, M58LT128HSB blank_check_command (blockToCheck) { Write Block Address & BCh writeToFlash (blockToCheck, 0xBC); Write Block Address & CBh writeToFlash (blockToCheck, 0xCB); /* Memory enters read status state after the Blank Check Command */ do { Read Status Register (1) status_register = readFlash (blockToCheck); /* see note (1) */ /* E or G must be toggled */ } while (status_register.SR7==0); SR7 = 1 YES SR4 = 1 SR5 = 1 YES Command Sequence Error (2) if (status_register.SR4==1) && (status_register.SR5==1) /* command sequence error */ error_handler () ; NO SR5 = 0 NO Blank Check Error (2) if (status_register.SR5==1) /* Blank Check error */ error_handler () ; End } ai10520c 1. Any address within the bank can equally be used. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 92/110 M58LT128HST, M58LT128HSB Figure 21. Buffer Program flowchart and pseudo code Start Flowcharts and pseudo codes Buffer Program E8h Command, Start Address Read Status Register Buffer_Program_command (Start_Address, n, buffer_Program[] ) /* buffer_Program [] is an array structure used to store the address and data to be programmed to the Flash memory (the address must be within the segment Start Address and Start Address+n) */ { do {writeToFlash (Start_Address, 0xE8) ; status_register=readFlash (Start_Address); SR7 = 1 YES Write n(1), Start Address NO } while (status_register.SR7==0); writeToFlash (Start_Address, n); Write Buffer Data, Start Address writeToFlash (buffer_Program[0].address, buffer_Program[0].data); /*buffer_Program[0].address is the start address*/ X=0 x = 0; X=n NO YES while (x { writeToFlash (buffer_Program[x+1].address, buffer_Program[x+1].data); x++; X=X+1 } Program Buffer to Flash Confirm D0h writeToFlash (Start_Address, 0xD0); Read Status Register do {status_register=readFlash (Start_Address); SR7 = 1 YES Full Status Register Check(3) NO } while (status_register.SR7==0); full_status_register_check(); } End AI08913b 1. n + 1 is the number of data being programmed. 2. Next program data is an element belonging to buffer_Program[].data; next program address is an element belonging to buffer_Program[].address 3. Routine for Error Check by reading SR3, SR4 and SR1. 93/110 Flowcharts and pseudo codes M58LT128HST, M58LT128HSB Figure 22. Program Suspend & Resume flowchart and pseudo code Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/ Write B0h Read Status Register SR7 = 1 YES SR2 = 1 NO } while (status_register.SR7== 0) ; NO Program Complete if (status_register.SR2==0) /*program completed */ { writeToFlash (bank_address, 0xFF) ; read_data ( ) ; /*The device returns to Read Array (as if program/erase suspend was not issued).*/ } else { writeToFlash (bank_address, 0xFF) ; Write FFh YES Write FFh Read Data Read data from another address read_data ( ); /*read data from another address*/ Write D0h writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ Write 70h(1) } Program Continues with Bank in Read Status Register Mode } writeToFlash (bank_address, 0x70) ; /*read status register to check if program has completed */ AI10117b 1. The Read Status Register command (Write 70h) can be issued just before or just after the Program Resume command. 94/110 M58LT128HST, M58LT128HSB Figure 23. Block Erase flowchart and pseudo code Flowcharts and pseudo codes Start erase_command ( blockToErase ) { writeToFlash (blockToErase, 0x20) ; /*see note (2) */ writeToFlash (blockToErase, 0xD0) ; /* Memory enters read status state after the Erase Command */ Write 20h (2) Write Block Address & D0h Read Status Register (2) do { status_register=readFlash (blockToErase) ; /* see note (2) */ /* E or G must be toggled*/ SR7 = 1 NO } while (status_register.SR7== 0) ; YES SR3 = 0 YES SR4, SR5 = 1 NO SR5 = 0 YES SR1 = 0 YES End } NO Erase to Protected Block Error (1) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; NO Erase Error (1) if ( (status_register.SR5==1) ) /* erase error */ error_handler ( ) ; YES Command Sequence Error (1) if ( (status_register.SR4==1) && (status_register.SR5==1) ) /* command sequence error */ error_handler ( ) ; NO VPP Invalid Error (1) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; AI10976 1. If an error is found, the Status Register must be cleared before further Program/Erase operations. 2. Any address within the bank can equally be used. 95/110 Flowcharts and pseudo codes Figure 24. Erase Suspend & Resume flowchart and pseudo code M58LT128HST, M58LT128HSB Start Write B0h erase_suspend_command ( ) { writeToFlash (bank_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if erase has already completed */ Write 70h Read Status Register do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/ SR7 = 1 YES SR6 = 1 YES Write FFh NO } while (status_register.SR7== 0) ; NO Erase Complete if (status_register.SR6==0) /*erase completed */ { writeToFlash (bank_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/ Read data from another block, Program, Set Configuration Register or Block Protect/Unprotect/Lock else } { writeToFlash (bank_address, 0xFF) ; read_program_data ( ); /*read or program data from another address*/ writeToFlash (bank_address, 0xD0) ; /*write 0xD0 to resume erase*/ } } Write D0h Write FFh Erase Continues Read Data AI13893 1. The Read Status Register command (Write 70h) can be issued just before or just after the Erase Resume command. 96/110 M58LT128HST, M58LT128HSB Flowcharts and pseudo codes Figure 25. Protect/Unprotect operation flowchart and pseudo code Start Write 60h (1) protect_operation_command (address, protect_operation) { writeToFlash (address, 0x60) ; /*configuration setup*/ /* see note (1) */ if (protect_operation==PROTECT) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (protect_operation==UNPROTECT) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; Write 01h, D0h Write 90h (1) writeToFlash (address, 0x90) ; /*see note (1) */ Read Block Protect State Protection change confirmed? YES Write FFh (1) NO if (readFlash (address) ! = protection_state_expected) error_handler () ; /*Check the protection state (see Read Block Signature table )*/ writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/ /*see note (1) */ } End AI12895 1. Any address within the bank can equally be used. 97/110 Flowcharts and pseudo codes M58LT128HST, M58LT128HSB Figure 26. Protection Register Program flowchart and pseudo code Start Write C0h (3) protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0xC0) ; /*see note (3) */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram) ; /* see note (3) */ /* E or G must be toggled*/ NO } while (status_register.SR7== 0) ; Write Address & Data Read Status Register (3) SR7 = 1 YES SR3 = 0 YES SR4 = 0 YES SR1 = 0 YES End NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO Program to Protected Block Error (1, 2) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; } AI06177b 1. Status check of SR1 (protected block), SR3 (VPP Invalid) and SR4 (program error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used. 98/110 M58LT128HST, M58LT128HSB Flowcharts and pseudo codes Figure 27. Buffer Enhanced Factory Program flowchart and pseudo code Start Write 80h to Address WA1 SETUP PHASE Buffer_Enhanced_Factory_Program_Command (start_address, DataFlow[]) { writeToFlash (start_address, 0x80) ; Write D0h to Address WA1 writeToFlash (start_address, 0xD0) ; do { do { status_register = readFlash (start_address); Read Status Register NO SR7 = 0 YES NO SR4 = 1 Initialize count X=0 Write PDX Address WA1 if (status_register.SR4==1) { /*error*/ if (status_register.SR3==1) error_handler ( ) ;/*VPP error */ if (status_register.SR1==1) error_handler ( ) ;/* Protected Block */ PROGRAM AND } VERIFY PHASE while (status_register.SR7==1) x=0; /* initialize count */ do { writeToFlash (start_address, DataFlow[x]); Read Status Register SR3 and SR1for errors Exit Increment Count X=X+1 x++; NO X = 32 YES Read Status Register }while (x<32) do { status_register = readFlash (start_address); NO SR0 = 0 YES }while (status_register.SR0==1) NO Last data? YES Write FFFFh to Address = NOT WA1 } while (not last data) writeToFlash (another_block_address, FFFFh) EXIT PHASE Read Status Register do { status_register = readFlash (start_address) NO SR7 = 1 }while (status_register.SR7==0) YES Full Status Register Check End full_status_register_check(); } AI12898 99/110 Command Interface state tables M58LT128HST, M58LT128HSB Appendix D Table 41. Command Interface state tables Command Interface states - modify table, next state(1) Command Input Erase Confirm Read Buffer P/E Resume, Clear Electronic Blank Program, Read Block Status Check Program/ Status Register Signature Unprotect , Read confirm Erase Register (5) confirm, CFI Query (CBh) Suspend (70h) BEFP (50h) (B0h) (90h, 98h) Confirm(3)(4) (D0h) Current CI State Block Buffer BEFP Read Program Program Erase, (3)(4) Setup Array(2) Setup (3)(4) Setup(3)(4) (FFh) (80h) (10/40h) (E8h) (20h) Blank Check setup (BCh) Ready Ready Program Setup BP Setup Erase Setup BEFP Setup Blank Check setup Ready (unprotect block) OTP Busy Ready Protect/CR Setup Ready (Protect Error) Ready (Protect Error) Setup Busy OTP IS in OTP busy Setup IS in Program Program Program Busy Busy Busy IS in Program Busy OTP Busy IS in OTP Busy OTP busy IS in OTP Busy OTP Busy OTP Busy Program Busy Program Suspend Busy Program Busy Program Busy Program IS in Program Busy Suspend IS in PS Setup Buffer Load 1 Buffer Load 2 Confirm PS IS in PS PS IS in Program Suspend Program Busy PS Program Busy Program Suspend Program Suspend Buffer Program Load 1 (give word count load (N-1)); if N=0 go to Buffer Program Confirm. Else (N 0) go to Buffer Program Load 2 (data load) Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program fails at this point if any block address is different from the first address) Ready (error) BP Busy IS in BP Busy BP Busy IS in BP Busy BP Busy BP Busy Ready (error) BP Suspend Buffer Program Busy Buffer Program Busy IS in BP Busy Suspend IS in BP Suspend Buffer Program Busy BP BP BP IS in BP IS in BP Suspend Suspend Suspend Suspend Suspend BP busy Buffer Program Suspend Buffer Program Suspend 100/110 M58LT128HST, M58LT128HSB Table 41. Command Interface state tables Command Interface states - modify table, next state(1) (continued) Command Input Erase Confirm Read Buffer P/E Resume, Clear Electronic Blank Program, Read Block Status Check Program/ Status Register Signature Unprotect , Read confirm Erase Register (5) confirm, CFI Query (CBh) Suspend (70h) BEFP (50h) (B0h) (90h, 98h) Confirm(3)(4) (D0h) Erase Busy Erase Busy Ready (error) Erase Suspend Erase Busy Current CI State Block Buffer BEFP Read Program Program Erase, (3)(4) Setup Array(2) Setup (3)(4) Setup(3)(4) (FFh) (10/40h) (80h) (E8h) (20h) Blank Check setup (BCh) Setup Busy IS in Erase Busy Suspend IS in ES Setup IS in Program Program Busy in Busy in ES ES Erase Busy IS in Erase Busy Ready (error) Erase Busy IS in Erase Busy Erase Erase Busy Erase Program BP in ES Suspend in ES IS in Erase Suspend ES Erase Busy Erase Suspend Erase Suspend Program Busy in Erase Suspend Program Busy in ES Busy IS in Program Busy in ES Program Busy in ES PS in ES Program Busy in Erase Suspend Program IS in in Erase Program Suspend busy in ES Suspend PS in ES IS in PS in ES Setup Buffer Load 1 IS in PS in PS in ES ES Program busy in Erase Suspend IS in Program Suspend in ES PS in ES Program Busy in ES Program Suspend in Erase Suspend Program Suspend in Erase Suspend Buffer Program Load 1 in Erase Suspend (give word count load (N-1)); if N=0 go to Buffer Program confirm. Else (N 0) go to Buffer Program Load 2 Buffer Program Load 2 in Erase Suspend (data load) Buffer Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program Load 2 fails at this point if any block address is different from the first address) Confirm Buffer Program in Erase Suspend BP Busy in ES Erase Suspend (sequence error) IS in BP Busy in ES BP busy in ES IS in BP busy in ES BP Busy in ES Erase Suspend (sequence error) BP Suspend in ES Busy BP Busy in ES Buffer Program Busy in ES IS in BP busy in ES Buffer Program Busy in Erase Suspend BP BP IS in BP BP Suspend Suspend Suspend Suspend IS in BP Suspend Suspend in ES in ES in Erase Suspend in ES in ES IS in BP Suspend in ES BP Busy in Erase Suspend Buffer Program Suspend in Erase Suspend BP Suspend in Erase Suspend 101/110 Command Interface state tables Table 41. M58LT128HST, M58LT128HSB Command Interface states - modify table, next state(1) (continued) Command Input Erase Confirm Read Buffer P/E Resume, Clear Electronic Blank Program, Read Block Status Check Program/ Status Register Signature Unprotect , Read confirm Erase Register (5) confirm, CFI Query (CBh) Suspend (70h) BEFP (50h) (B0h) (90h, 98h) Confirm(3)(4) (D0h) Blank Check busy Blank Check busy Current CI State Block Buffer BEFP Read Program Program Erase, (3)(4) Setup Array(2) Setup (3)(4) Setup(3)(4) (FFh) (10/40h) (80h) (E8h) (20h) Blank Check setup (BCh) Setup Blank Check Busy Blank IS in Blank Check Check busy busy Blank Check busy Ready (error) Ready (error) IS in Blank Check busy Erase Suspend BEFP Busy BEFP Busy(6) Protect/CR Setup in Erase Suspend Buffer EFP Setup Busy Erase Suspend (Protect Error) Ready (error) Erase Suspend (Protect Error) Ready (error) 1. CI = Command Interface, CR = Configuration register, BEFP = Buffer Enhanced Factory program, P/E C = Program/Erase controller, IS = Illegal State, BP = Buffer Program, ES = Erase Suspend. 2. At power-up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data output. 3. The two cycle command should be issued to the same bank address. 4. If the Program/Erase Controller is active, both cycles are ignored. 5. The Clear Status Register command clears the SR error bits except when the Program/Erase Controller is busy or suspended. 6. BEFP is allowed only when Status Register bit SR0 is reset to '0'. BEFP is busy if block address is first BEFP address. Any other commands are treated as data. 102/110 M58LT128HST, M58LT128HSB Table 42. Command Interface state tables Command Interface states - modify table, next output state(1) (2) Command Input Erase Confirm P/E Resume, Block Blank Block Buffer Erase, BEFP Check (4) Setup Unprotect Program Setup (5) setup confirm, BEFP (5) (E8h) (80h) (BCh) (10/40h) Confirm(4)(5) (20h) (D0h) Read Clear Electronic Blank Program/ Read Status Status signature, Check Erase confirm Suspend Register Register Read CFI Query (CBh) (B0h) (70h) (50h) (90h, 98h) Current CI State Read Program Array Setup(4) (3) (FFh) Program Setup Erase Setup OTP Setup Program Setup in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Buffer Program Load 2 Buffer Program Confirm Buffer Program Setup in Erase Suspend Buffer Program Load 1 in Erase Suspend Buffer Program Load 2 in Erase Suspend Buffer Program Confirm in Erase Suspend Blank Check setup Protect/CR Setup Protect/CR Setup in Erase Suspend Status Register 103/110 Command Interface state tables Table 42. M58LT128HST, M58LT128HSB Command Interface states - modify table, next output state(1) (2) (continued) Command Input Erase Confirm Block P/E Resume, Blank Block Buffer Erase, BEFP (4) Setup Check Unprotect Program Setup (5) setup confirm, BEFP (5) (E8h) (80h) (BCh) (10/40h) Confirm(4)(5) (20h) (D0h) Read Clear Electronic Blank Program/ Read Status Status signature, Check Erase confirm Suspend Register Register Read CFI Query (CBh) (B0h) (70h) (50h) (90h, 98h) Status Register Current CI State Read Program Array Setup(4) (3) (FFh) OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend Buffer Program Suspend Program Busy in Erase Suspend Buffer Program Busy in Erase Suspend Program Suspend in Erase Suspend Buffer Program Suspend in Erase Suspend Blank Check busy Illegal State Output Unchanged Array Status Register Output Unchanged Output Status Unchang Electronic Register ed Signature/ CFI 1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank output state. 2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, Program/Erase Controller = Program/Erase Controller. 3. At power-up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data output. 4. The two cycle command should be issued to the same bank address. 5. If the Program/Erase Controller is active, both cycles are ignored. 104/110 M58LT128HST, M58LT128HSB Table 43. Command interface states - lock table, next state(1) Command Interface state tables Command Input Current CI State Protect/CR Setup(2) (60h) Protect/CR Setup OTP Setup(2) (C0h) OTP Setup Ready OTP Busy IS in OTP Busy OTP Busy Program Busy IS in Program Busy Program busy IS in PS Program Suspend N/A IS in PS Setup Buffer Load 1 Buffer Load 2 Confirm Buffer Program Busy IS in Buffer Program busy Suspend IS in BP Suspend Setup Busy Erase IS in Erase busy Suspend IS in ES Protect/CR Setup in ES IS in ES Erase Suspend IS in Erase Busy Erase Busy Erase Suspend N/A IS in BP Suspend IS in BP Busy Program Suspend Buffer Program Load 1 (give word count load (N-1)); Buffer Program Load 2(6) Exit see note (6) N/A N/A N/A N/A Buffer Program Busy Buffer Program Busy Buffer Program Suspend N/A Buffer Program Suspend Ready (error) Erase Busy N/A Ready IS ready Ready IS Ready Program Busy OTP Busy Block Protect Confirm (01h) Set CR Confirm (03h) Block Address (WA0)(3) (XXXXh) Ready Ready (Protect error) P/E C operation completed(5) N/A N/A N/A Ready IS Ready N/A Ready IS Ready Illegal Command(4) Ready Protect/CR Setup Setup OTP Busy IS in OTP busy Setup Busy Program IS in Program busy Suspend Ready (Protect error) Buffer Program Confirm when count =0; Else Buffer Program Load 2 (note: Buffer Program fails at this point if any block address is different from the first address) Ready (error) 105/110 Command Interface state tables Table 43. M58LT128HST, M58LT128HSB Command interface states - lock table, next state(1) (continued) Command Input Current CI State Protect/CR Setup(2) (60h) OTP Setup(2) (C0h) Block Protect Confirm (01h) Set CR Confirm (03h) Block Address (WA0)(3) (XXXXh) Illegal Command(4) P/E C operation completed(5) N/A ES IS in ES Setup Busy Program in Erase Suspend IS in Program busy in ES Suspend IS in PS in ES Setup Buffer Load 1 IS in PS in ES Program Busy in Erase Suspend IS in Program busy in ES Program Busy in Erase Suspend Program Busy in Erase Suspend Program Suspend in Erase Suspend N/A Program Suspend in Erase Suspend Buffer Program Load 1 in Erase Suspend (give word count load (N-1)) Buffer Program Load 2 in Erase Suspend(7) Exit see note (7) N/A Buffer Load 2 Buffer Program in Erase Suspend Buffer Program Confirm in Erase Suspend when count =0; Else Buffer Program Load 2 in Erase Suspend (note: Buffer Program fails at this point if any block address is different from the first address) Erase Suspend (sequence error) IS in BP busy in ES Buffer Program Busy in Erase Suspend BP busy in ES IS in BP suspend in ES Buffer Program Suspend in Erase Suspend Confirm Busy IS in BP busy in ES Suspend IS in BP Suspend in ES ES IS in ES N/A Buffer Program Suspend in Erase Suspend Ready (error) IS in Blank Check busy Erase Suspend (Protect error) Blank Check busy Erase Suspend Ready (error) BEFP Busy(8) Exit BEFP Busy(8) Erase Suspend (Protect error) N/A Ready N/A N/A N/A Blank Check Setup Blank Check busy Protect/CR Setup in ES Setup BEFP Busy 1. CI = Command Interface, CR = Configuration register, BEFP = Buffer Enhanced Factory program, P/E C = Program/Erase controller, IS = Illegal State, BP = Buffer program, ES = Erase suspend, WA0 = Address in a block different from first BEFP address. 2. If the Program/Erase Controller is active, both cycle are ignored. 3. BEFP exit when block address is different from first block address and data are FFFFh. 4. Illegal commands are those not defined in the command set. 5. N/A: not available. In this case the state remains unchanged. 6. If N=0 go to Buffer Program Confirm. Else (not = 0) go to Buffer Program Load 2 (data load) 7. If N=0 go to Buffer Program Confirm in Erase suspend. Else (not =0) go to Buffer Program Load 2 in Erase suspend. 8. BEFP is allowed only when Status Register bit SR0 is set to '0'. BEFP is busy if Block Address is first BEFP Address. Any other commands are treated as data. 106/110 M58LT128HST, M58LT128HSB Table 44. Command Interface state tables Command interface states - lock table, next output state (1) (2) Command Input Current CI State Protect/CR P. E./C. Blank OTP Blank Check Set CR BEFP Illegal Block Protect Setup(3) Operation Check confirm Setup(3) Confirm Exit(4) Command(5) Confirm (01h) (60h) Completed setup (BCh) (C0h) (CBh) (03h) (FFFFh) Program Setup Erase Setup OTP Setup Program Setup in Erase Suspend BEFP Setup BEFP Busy Buffer Program Setup Buffer Program Load 1 Status Register Buffer Program Load 2 Buffer Program Confirm Buffer Program Setup in Erase Suspend Buffer Program Load 1 in Erase Suspend Buffer Program Load 2 in Erase Suspend Buffer Program Confirm in Erase Suspend Blank Check setup Protect/CR Setup Protect/CR Setup in Erase Suspend Status Register Array Status Register Output Unchanged 107/110 Command Interface state tables Table 44. M58LT128HST, M58LT128HSB Command interface states - lock table, next output state (continued)(1) (2) Command Input Current CI State Protect/CR P. E./C. Blank OTP Blank Check Set CR BEFP Block Protect Illegal Setup(3) Operation Check Setup(3) confirm Confirm Exit(4) Confirm (01h) Command(5) Completed (60h) setup (BCh) (C0h) (CBh) (03h) (FFFFh) OTP Busy Ready Program Busy Erase Busy Buffer Program Busy Program/Erase Suspend Buffer Program Suspend Status Register Program Busy in Erase Suspend Buffer Program Busy in Erase Suspend Program Suspend in Erase Suspend Buffer Program Suspend in Erase Suspend Blank Check busy Illegal State Output Unchanged Output Unchanged Array Output Unchanged 1. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI mode, depending on the command issued. Each bank remains in its last output state until a new command is issued to that bank. The next state does not depend on the bank's output state. 2. CI = Command Interface, CR = Configuration Register, BEFP = Buffer Enhanced Factory Program, P/E. C. = Program/Erase Controller. 3. If the Program/Erase Controller is active, both cycles are ignored. 4. BEFP Exit when block address is different from first block address and data are FFFFh. 5. Illegal commands are those not defined in the command set. 108/110 M58LT128HST, M58LT128HSB Revision history Revision history Table 45. Date 02-Mar-2007 13-Jun Document revision history Revision 1 Initial release. - Modified WAIT de-assertion criteria on page 45. - Removed tELTV from waveforms in Figure 11 and Figure 13, and from Table 23. - Modified the tVDHPH parameter values in Table 26. - Added the T packaging option in part numbering information in Table 28. Applied Numonyx branding. Changes 27-Jun-2007 2 10-Dec-2007 3 109/110 M58LT128HST, M58LT128HSB Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 11/5/7, Numonyx, B.V., All Rights Reserved. 110/110 |
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