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ADJD-S311-CR999
Miniature Surface Mount RGB Digital Color Sensor
Data Sheet
Description
The ADJD-S311-CR999 is a cost effective, 4 channels (RGB+CLEAR)digitaloutputsensorinminiaturesurfacemount package with a mere size of 2.2 x 2.2 x 0.76mm. It is a CMOS IC with integrated RGB filters and analogto-digitalconverterfrontend.Thisdeviceisdesignedto cater for wide dynamic range of illumination level and is ideal for applications like portable or mobile devices, which demand higher integration, smaller size and low power consumption. Sensitivity control is performed by theserialinterfaceandcanbeoptimizedindividuallyfor thedifferentcolorchannel.Thesensorcanalsobeused inconjunctionwithawhiteLEDforreflectivecolormanagement.
Features
* FullyintegratedRGB+cleardigitalcolorsensor * 10bitresolutionperchanneloutput * Builtinoscillator/selectableexternalclock * Lowsupplyvoltage(VDD)2.5V * DigitalI/Ovia2-wireserialinterface * Adjustablesensitivityfordifferentlevelsof illumination * Lowpowermode(sleepmode) * Independentgainselectionforeachchannel * 0Cto70Coperatingtemperature * Industry'ssmallestformfactor -CSP2.2x2.2x0.76mm * Leadfreepackage
Applications
* Generalcolordetectionandmeasurement * Mobileappliancessuchasmobilephones,PDAs,MP3 players,etc. * Consumerappliances * Portablemedicalequipments * Portablecolordetector/reader
General Specifications
Feature Interface Supply Value 00kHz serial interface .6V digital (nominal), .6V analog (nominal)
Powering the Device
No voltage must be applied to IO's during power-up and power-down ramp time
VDDD / V DDA
0V t VDD_RAMP
ESD Protection Diode Turn-On During Power-Up and Power-Down
A particular power-up and power-down sequence must be used to prevent any ESD diode from turning on inadvertently.Thefigureabovedescribesthesequence.In general, AVDD and DVDD should power-up and powerdown together to prevent ESD diodes from turning on inadvertently. During this period, no voltage should be appliedtotheIO'sforthesamereason.
Ground Connection
AGNDandDGNDmustbothbesetto0Vandpreferably star-connected to a central power source as shown in theapplicationdiagram.Apotentialdifferencebetween AGND and DGND may cause the ESD diodes to turn on inadvertently.
Electrical Specifications Absolute Maximum Ratings (Notes 1 & 2)
Parameter Storage temperature Digital supply voltage, DVDD to DVSS Analog supply voltage, AVDD to AVSS Input voltage Solder Reflow Peak temperature Human Body Model ESD rating Symbol TSTG_ABS VDDD_ABS VDDA_ABS VIN_ABS TL_ABS ESDHBM_ABS Minimum -40 .5 .5 .5 Maximum 85 3.6 3.6 3.6 45 Units C V V V C kV All pins, human body model per JESD-A4-B All I/O pins Notes
Recommended Operating Conditions
Parameter Free air operating temperature Digital supply voltage, DVDD to DVSS Analog supply voltage, AVDD to AVSS Output current load high Output current load low Input voltage high level (Note 4) Input voltage low level (Note 4) Symbol TA VDDD VDDA IOH IOL VIH VIL 0.7VDDD 0 Minimum 0 .5 .5 Typical 5 .6 .6 Maximum 70 3.6 3.6 3 3 VDDD 0.3VDDD Units C V V mA mA V V
DC Electrical Specifications
OverRecommendedOperatingConditions(unlessotherwisespecified) Parameter Output voltage high level (Note 5) Output voltage low level (Note 6) Supply current (Note 7) Sleep-mode supply current (Note 7) Input leakage current Symbol VOH VOL IDD_STATIC IDD_SLP ILEAK Conditions IOH = 3mA IOH = 3mA (Note 8) (Note 8) -0 Minimum VDDD-0.8 Typical (Note 3) VDDD-0.4 0. 3.8 0 0.4 5 Maximum Units V V mA uA uA
AC Electrical Specifications
Parameter Internal clock frequency External clock frequency -wire interface frequency Symbol f_CLK_int f_CLK_ext f_wire 6 00 Conditions Minimum Typical (Note 3) 6 40 Maximum Units MHz MHz kHz
Optical Specification
Parameter Dark offset Symbol VD Conditions Ee = 0 Minimum Typical (Note 3) 0 Maximum Units LSB
3
Minimum sensitivity (note 3)
Parameter Irradiance Responsivity Symbol Re Conditions lP = 460 nm, B Refer Note 9 lP = 54 nm, G Refer Note 0 lP = 645 nm, R Refer Note lP = 645 nm, Clear Refer Note Minimum Typical (Note 3) 5 78 54 64 Maximum Units LSB/ (mWcm-)
Maximum sensitivity (note 3)
Parameter Irradiance Responsivity Symbol Re Conditions lP = 460 nm, B Refer Note 9 lP = 54 nm, G Refer Note 0 lP = 645 nm, R Refer Note lP = 645 nm, Clear Refer Note Minimum Typical (Note 3) 3796 475 688 6590 Maximum Units LSB/ (mWcm-)
Saturation Irradiance for minimum sensitivity (note 12)
Parameter Saturation Irradiance Symbol Conditions lP = 460 nm, B Refer Note 9 lP = 54 nm, G Refer Note 0 lP = 645 nm, R Refer Note lP = 645 nm, Clear Refer Note Minimum Typical (Note 3) 6.73 5.74 4.03 3.87 Maximum Units mW/cm
Saturation irradiance for maximum sensitivity (note 12)
Parameter Saturation Irradiance Symbol Conditions lP = 460 nm, B Refer Note 9 lP = 54 nm, G Refer Note 0 lP = 645 nm, R Refer Note lP = 645 nm, Clear Refer Note Minimum Typical (Note 3) 0.7 0. 0.6 0.6 Maximum Units mW/cm
Notes 1. The"Absolute Maximum Ratings" are those values beyond which damage to the device may occur. The device should not be operated at these limits. The parametric values defined in the"Electrical Specifications" table are not guaranteed at the absolute maximum ratings. The "RecommendedOperatingConditions"tablewilldefinetheconditionsforactualdeviceoperation. 2. Unlessotherwisespecified,allvoltagesarereferencedtoground. 3. Specifiedatroomtemperature(25C)andVDDD=VDDA=2.5V. 4. AppliestoallDIpins. 5. Appliestoalldigitaloutputpins.SDASLVgotri-statewhenoutputlogichigh.MinimumVOHdependsonthepull-upresistorvalue.
4
Notes:(continued) 6. Appliestoalldigitaloutputanddigitalinput-outputpins. 7. Referstototaldevicecurrentconsumption. 8. Outputandbidirectionalpinsarenotloaded. 9. Testconditionisbluelightofpeakwavelength(lP)460nmandspectralhalfwidth(l1/2)25nm. 10.Testconditionisgreenlightofpeakwavelength(lP)542nmandspectralhalfwidth(l1/2)35nm 11.Testconditionisredlightofpeakwavelength(lP)645nmandspectralhalfwidth(l1/2)20nm 12.Saturationirradiance=(MSB)/(Irradianceresponsivity)
1 Relative sensitivity 0.8 0.6 0.4 0.2 400 420 440 460 480 500
Spectral Response
520
540
560
580
600
620
640
660
680
Wavelength (nm)
Figure 1. Typical spectral response when the gains for all the color channels are set at equal.
Serial Interface Timing Information
Parameter SCL clock frequency (Repeated) START condition hold time Data hold time SCL clock low period SCL clock high period Repeated START condition setup time Data setup time STOP condition setup time Bus free time between START and STOP conditions Symbol fscl tHD:STA tHD:DAT tLOW tHIGH tSU:STA tSU:DAT tSU:STO tBUF Minimum 0 4 0 4.7 4.0 4.7 50 4.0 4.7 Maximum 00 3.45 Units kHz s s s s s ns s s
tHD:STA
tHIGH
tSU:DAT
tSU:STA
700
0
tBUF
SDA
SCL S tLOW tHD:DAT Sr tHD:STA P tSU:STO S
Figure 2. Serial Interface Bus Timing Waveforms
5
Serial Interface Reference Description
TheprogramminginterfacetotheADJD-S311isa2-wireserialbus.Thebusconsistsofaserialclock(SCL)andaserial data(SDA)line.TheSDAlineisbi-directionalonADJD-S311andmustbeconnectedthroughapull-upresistortothe positivepowersupply.Whenthebusisfree,bothlinesareHIGH. The2-wireserialbusonADJD-S311requiresonedevicetoactasamasterwhileallotherdevicesmustbeslaves.A masterisadevicethatinitiatesadatatransferonthebus,generatestheclocksignalandterminatesthedatatransfer whileadeviceaddressedbythemasteriscalledaslave.Slavesareidentifiedbyuniquedeviceaddresses. Bothmasterandslavecanactasatransmitterorareceiverbutthemastercontrolsthedirectionfordatatransfer.A transmitterisadevicethatsendsdatatothebusandareceiverisadevicethatreceivesdatafromthebus. TheADJD-S311serialbusinterfacealwaysoperatesasaslavetransceiverwithadatatransferrateofupto100kbit/s.
START/STOP Condition
The master initiates and terminates all serial data transfers.To begin a serial data transfer, the master must send a uniquesignaltothebuscalledaSTARTcondition.ThisisdefinedasaHIGHtoLOWtransitionontheSDAlinewhile SCLisHIGH. ThemasterterminatestheserialdatatransferbysendinganotheruniquesignaltothebuscalledaSTOPcondition. ThisisdefinedasaLOWtoHIGHtransitionontheSDAlinewhileSCLisHIGH. ThebusisconsideredtobebusyafteraSTART(S)condition.ItwillbeconsideredfreeacertaintimeaftertheSTOP(P) condition.ThebusstaysbusyifarepeatedSTART(Sr)issentinsteadofaSTOPcondition. TheSTARTandrepeatedSTARTconditionsarefunctionallyidentical.Seefigure3.
SDA
SCL
S START condition
P STOP condition
Figure 3. START/STOP Condition
Data Transfer
ThemasterinitiatesdatatransferafteraSTARTcondition.Dataistransferredinbitswiththemastergeneratingone clockpulseforeachbitsent.Foradatabittobevalid,theSDAdatalinemustbestableduringtheHIGHperiodofthe SCLclockline.OnlyduringtheLOWperiodoftheSCLclocklinecantheSDAdatalinechangestatetoeitherHIGHor LOW.
SDA
SCL Data valid Data change
Figure 4. Data Bit Transfer
6
TheSCLclocklinesynchronizestheserialdatatransmissionontheSDAdataline.Itisalwaysgeneratedbythemaster. ThefrequencyoftheSCLclocklinemayvarythroughoutthetransmissionaslongasitstillmeetstheminimumtiming requirements. ThemasterbydefaultdrivestheSDAdataline.TheslavedrivestheSDAdatalineonlywhensendinganacknowledge bitafterthemasterwritesdatatotheslaveorwhenthemasterrequeststheslavetosenddata. TheSDAdatalinedrivenbythemastermaybeimplementedonthenegativeedgeoftheSCLclockline.Themaster maysampledatadrivenbytheslaveonthepositiveedgeoftheSCLclockline.Figureshowsanexampleofamaster implementationandhowtheSCLclocklineandSDAdatalinecanbesynchronized.
P
SDA
MSB
LSB
ACK
MSB
LSB
NO ACK 9
Sr Sr or P
SCL
S or Sr
1
2
8
9
1
2
8
STARTorrepeated STARTcondition
STOPorrepeated STARTcondition
Figure 5. Data Byte Transfer
SDAdatasampledonthe positiveedgeofSCL SDA
SCL SDAdatadrivenonthe negativeedgeofSCL
Figure 6. Data Bit Synchronization
Acompletedatatransferis8-bitslongor1-byte.Eachbyteissentmostsignificantbit(MSB)firstfollowedbyanacknowledgeornotacknowledgebit.Eachdatatransfercansendanunlimitednumberofbytes(dependingonthedata format).
Acknowledge/Not acknowledge
Thereceivermustalwaysacknowledgeeachbytesentinadatatransfer.Inthecaseoftheslave-receiverandmastertransmitter,iftheslave-receiverdoesnotsendanacknowledgebit,themaster-transmittercaneitherSTOPthetransfer orgeneratearepeatedSTARTtostartanewtransfer.
SDApulledLOW byreceiver SDA (SLAVE-RECEIVER) SDA Acknowledge
(MASTER-TRANSMITTER)
LSB
SDAleftHIGH bytransmitter 9 Acknowledge clockpulse
SCL (MASTER)
8
Figure 7. Slave-Receiver Acknowledge
7
Inthecaseofthemaster-receiverandslave-transmitter,themastergeneratesanotacknowledgetosignaltheendof thedatatransfertotheslave-transmitter.ThemastercanthensendaSTOPorrepeatedSTARTconditiontobegina newdatatransfer. Inallcases,themastergeneratestheacknowledgeornotacknowledgeSCLclockpulse.
(SLAVE-TRANSMITTER)
SDA
LSB
SDAleftHIGH bytransmitter P SDAleftHIGH byreceiver Not acknowledge 9 Acknowledge clockpulse Sr
SDA (MASTER-RECEIVER) SCL (MASTER)
8
STOPorrepeated STARTcondition
Figure 8. Master-Receiver Acknowledge
Addressing
Eachslavedeviceontheserialbusneedstohaveauniqueaddress.Thisisthefirstbytethatissentbythemaster-transmitteraftertheSTARTcondition.Theaddressisdefinedasthefirstsevenbitsofthefirstbyte. Theeighthbitorleastsignificantbit(LSB)determinesthedirectionofdatatransfer.A`one'intheLSBofthefirstbyte indicatesthatthemasterwillreaddatafromtheaddressedslave(master-receiverandslave-transmitter).A`zero'inthis positionindicatesthatthemasterwillwritedatatotheaddressedslave(master-transmitterandslave-receiver). Adevicewhoseaddressmatchestheaddresssentbythemasterwillrespondwithanacknowledgeforthefirstbyte andsetitselfupasaslave-transmitterorslave-receiverdependingontheLSBofthefirstbyte. TheslaveaddressonADJD-S311is0x74(7-bits).
MSB A6 1 A5 1 A4 1 A3 0 A2 1 A1 0 A0 0 LSB R/W
Slaveaddress
Figure 9. Slave Addressing
8
Data format
ADJD-S311usesaregister-basedprogrammingarchitecture.Eachregisterhasauniqueaddressandcontrolsaspecific functioninsidethechip. To write to a register, the master first generates a START condition.Then it sends the slave address for the device it wantstocommunicatewith.Theleastsignificantbit(LSB)oftheslaveaddressmustindicatethatthemasterwantsto writetotheslave.Theaddresseddevicewillthenacknowledgethemaster. The master writes the register address it wants to access and waits for the slave to acknowledge.The master then writesthenewregisterdata.Once theslaveacknowledges, themaster generates aSTOPcondition toendthe data transfer.
Startcondition
S
Masterwillwritedata
A D7 D6 D5 D4 D3 D2 D1 D0 A
Stopcondition
D7 D6 D5 D4 D3 D2 D1 D0 A P
A6 A5 A4 A3 A2 A1 A0 W
Mastersends slaveaddress
Masterwrites registeraddress Slaveacknowledge
Masterwrites registerdata Slaveacknowledge
Slaveacknowledge
Figure 10. Register Byte Write Protocol
Toreadfromaregister,themasterfirstgeneratesaSTARTcondition.Thenitsendstheslaveaddressforthedeviceit wantstocommunicatewith.Theleastsignificantbit(LSB)oftheslaveaddressmustindicatethatthemasterwantsto writetotheslave.Theaddresseddevicewillthenacknowledgethemaster. The master writes the register address it wants to access and waits for the slave to acknowledge.The master then generatesarepeatedSTARTconditionandresendstheslaveaddresssentpreviously.Theleastsignificantbit(LSB)of theslaveaddressmustindicatethatthemasterwantstoreadfromtheslave.Theaddresseddevicewillthenacknowledgethemaster. Themasterreadstheregisterdatasentbytheslaveandsendsanoacknowledgesignaltostopreading.Themaster thengeneratesaSTOPconditiontoendthedatatransfer.
Startcondition
S
Masterwillwritedata
A
Repeatedstart condition
A Sr
Masterwillreaddata
A
Stopcondition
A P
A6 A5 A4 A3 A2 A1 A0 W
D7 D6 D5 D4 D3 D2 D1 D0
A6 A5 A4 A3 A2 A1 A0 R
D7 D6 D5 D4 D3 D2 D1 D0
Mastersends slaveaddress
Masterwrites registeraddress Slaveacknowledge Slaveacknowledge
Mastersends slaveaddress
Masterreads registerdata Slaveacknowledge Masternot acknowledge
Figure 11. Register Byte Read Protocol
9
Application Diagram
HOST SYSTEM SLEEP CLK_IO
DVDD
10k
10k
10k
10k
RESET SDASLV SCKSLV
HOST SYSTEM
RESET SDASLV SCKSLV AVDD AGND DGND DVDD
Voltage Regulator
Voltage Regulator
Figure 12. typical Application Diagram
Star connectedground
High Level Description
Thesensorneedstobeconfiguredbeforeitcanbeused. The gain selection needs to be set for optimum performance depending on light levels.The flowcharts below describethedifferentproceduresrequired.
Sensor operation flowchart
Sensor Operation
Sensor gain optimization flowchart
Sensor Gain Optimization Hardware reset
Select sensor gain setting Hardware reset Acquire and trim offset Select sensor gain setting
Acquire sensor reading
Acquire sensor output Stop
Sensor output optimum? Yes Stop
No
* Pleaserefertoapplicationnoteformoredetailedinformation.
0
Detail Description
A hardware reset (by asserting XRST) should be performedbeforestartinganyoperation.
Setup Value for Number of Integration Time Slot
Thefollowingvaluecanbewrittentoeachoftheintegration time registers to adjust the gain of the sensor.The defaultvalueafterresetfortheseregistersis00H.These registerscontrolthenumberofintegrationtimeselected foreachchannel.Theintegrationtimeslotcanbevaried from 00H to FFFH. More integration time slot will give highersensitivity.
Sensor Gain Settings
Thesensorgaincanbeadjustedbyvaryingthenumber of capacitors and integration time slot of the sensor manuallythroughthefollowingregisters. Address (Hex) Register 6 7 8 9 A C E 0 CAP_RED CAP_GREEN CAP_BLUE CAP_CLEAR INT_RED INT_GREEN INT_BLUE INT_CLEAR Description Number of red channel capacitors Number of green channel capacitors Number of blue channel capacitors Number of clear channel capacitors Number of red channel integration time slots Number of green channel integration time slots Number of blue channel integration time slots Number of clear channel integration time slots
Setup Value for Number of Capacitor
The following value can be written to each of the capacitor registers to adjust the gain of the sensor.The defaultvalueafterresetfortheseregistersis0FH.These registers control the number of capacitors selected for each channel. The maximum selectable capacitor is 16 with the registers starting from 0 (i.e. 0 to 15). Less capacitorwillgivehighersensitivity. Value (Hex) 00 0 0 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Number of Capacitor 3 4 5 6 7 8 9 0 3 4 5 6
Sensor ADC Output Registers
To obtain sensor ADC value,`01' Hex must be written to CTRLregister.Then,readthevaluefromCTRLregister.If valueis00H,canreadsensoroutputfromdataregister. Address (Hex) 00 40 4 4 43 44 45 46 47 Register CTRL DATA_RED_LO DATA_RED_HI DATA_GREEN_LO DATA_GREEN_HI DATA_BLUE_LO DATA_BLUE_HI DATA_CLEAR_LO DATA_CLEAR_HI Description Control register Red channel ADC data - low byte Red channel ADC data - high byte Green channel ADC data - low byte Green channel ADC data - high byte Blue channel ADC data - low byte Blue channel ADC data - high byte Clear channel ADC data - low byte Clear channel ADC data - high byte
* Pleaserefertoapplicationnoteformoredetailedinformation.
* Pleaserefertoapplicationnoteformoredetailedinformation.
Mechanical Drawing
Note: 1. Dimensionsareinmilimeters(mm) 2. Standardtolerances(unlessotherwisespecified) a.Lineartolerance=+/-0.1mm b.Angulartolerance=+/-1
Pin Configuration
A B C DVDD CLKIO DGND SCKSLV SDASLV RESET 3 AVDD SLEEP AGND
Dimensions
Description Package Body Dimension X Package Body Dimension Y Package Height Ball Diameter Total Pin Count Nominal (um) 00 00 760 50 9
Pin Information
Pin A A A3 B B B3 C C C3 Name DVDD SCKSLV AVDD CLKIO SDASLV SLEEP DGND RESET AGND Type Power Input Power Input Input/Output Input Ground Input Power Description Digital power pin Serial interface clock pin Analog power pin External clock input Bidirectional data pin. A pull-up resistor should be tied to SDASLV because it goes tri-state to output logic When SLEEP = , the device goes into sleep mode. In sleep mode, all analog circuits are powered down and the clock signal is gated away from the core logic resulting in very low current consumption. Tie to digital ground Global, asynchronous, active-low system reset. When asserted low, XRST resets all registers. Minimum reset pulse low is us and must be provided by external circuitry. Tie to analog ground
Recommended Underfill Type and Characteristic
* HenkelFP4548 * Lowmoistureabsorption * LowCTE * Underfillupto70-85%ofheight
Recommended stencil design
* Stencilthickness 5mils * Stenciltype NiElectroforming * StencilApertureType Square * StencilAperture * AdditionalFeature 310um Roundedsquareedge 310um
Height 70~85%
Underfill
PCB
Recommended PCB land pad design
* NiAuflashovercopperpad * PadDiameter(C)=0.20mm * NSMDDiameter(D)=0.25~0.30mm
NSMD
560um
After soldering or mounting precaution
PleaseensurethatallsolderedorreflowedCSPpackage thatismountedonthePCBisnotexposedtocompressionorloadingforcedirectlyperpendiculartotheflattop surface. Precaution: Excessiveloadingforcedirectlyperpendiculartotheflat topsurfacemaycausepre-maturefailure.
LoadingForce
PCB
3
Recommended Reflow Profile
ItisrecommendedthatHenkelPb-freesolderpasteLF310beusedforsolderingADJD-S311-CR999.Belowistherecommendedreflowprofile.
240 5C 217~220 C Delta-Flux max. 2 C/sec. Delta-Cooling max. 2 C/sec.
T-peak T-reflow
TEMPERATURE
T-max. T-min.
180C 160C
Delta-Ramp max. 2 C/sec.
100 ~ 140 sec.
t-comp t-pre
90 ~ 120 sec.
t-reflow
TIME
Recommendations for Handling and Storage of ADJD-S311-CR999
ThisproductisqualifiedasMoistureSensitiveLevel3perJedecJ-STD-020.Precautionswhenhandlingthismoisture sensitive product is important to ensure the reliability of the product. Do refer to Avago Application Note AN5305 HandlingOfMoistureSensitiveSurfaceMountDevicesfordetails.
A. Storage before use
* Unopenedmoisturebarrierbag(MBB)canbestoredat30Cand90%RHorlessformaximum1year * ItisnotrecommendedtoopentheMBBpriortoassembly(e.g.forIQC) * It should also be sealed with a moisture absorbent material (Silica Gel) and an indicator card (cobalt chloride) to indicatethemoisturewithinthebag
B. Control after opening the MBB
* Thehumidityindicatorcard(HIC)shallbereadimmediatelyuponopeningofMBB * The components must be kept at <30C/60%RH at all time and all high temperature related process including soldering,curingorreworkneedtobecompletedwithin168hrs
C. Control for unfinished reel
* Foranyunusedcomponents,theyneedtobestoredinsealedMBBwithdesiccantordesiccatorat<5%RH
D. Control of assembled boards
* IfthePCBsolderedwiththecomponentsistobesubjectedtootherhightemperatureprocesses,thePCBneedto bestoredinsealedMBBwithdesiccantordesiccatorat<5%RHtoensurenocomponentshaveexceededtheirfloor lifeof168hrs
E. Baking is required if:
* "10%"or"15%"HICindicatorturnspink * Thecomponentsareexposedtoconditionof>30C/60%RHatanytime. * Thecomponentsfloorlifeexceeded168hrs * Recommendedbakingcondition(incomponentform):125Cfor24hrs
4
Package Tape and Reel Dimensions
Reel Dimensions
65 R10.65 45 +1.5* 12.4 - 0.0
R5.2
45
55.0 0.5 178.0 0.5
176.0 EMBOSSED RIBS RAISED: 0.25 mm WIDTH: 1.25 mm
BACK VIEW
512
18.0 MAX.*
Notes: 1.*Measureathubarea. 2.Allflangeedgestoberounded.
Carrier Tape Dimensions
(E1)1.750.10 (F)5.500.05
(P0)4.000.10 1.50
+ 0.10 - 0.00
(P2)2.000.10
(T)0.300.05
(W)12.000.10
1.50 Min
R0.50
(P1)8.000.10
(B0)2.600.10
(K0)0.900.10
(A0)2.600.10
Notes: 1.AOandBOmeasuredat0.3mmabovebaseofpocket 2.10pitchescumulativetoleranceis0.2mm 3.Dimensionsareinmillimeters(mm)
5
FN
SENSOR
SAMPLE DATA
OFFSET DATA
6
WIDTH 2 3 N/A N/A N/A N/A N/A INT_RED[7:0] INT_RED[11:8] INT_GREEN[7:0] INT_GREEN[11:8] INT_BLUE[7:0] INT_BLUE[11:8] INT_CLEAR[7:0] INT_CLEAR[11:8] DATA_RED[7:0] N/A DATA_GREEN[7:0] N/A DATA_BLUE[7:0] N/A DATA_CLEAR[7:0] N/A SIGN_RED SIGN_GREEN SIGN_BLUE SIGN_CLEAR OFFSET_RED[6:0] OFFSET_GREEN[6:0] OFFSET_BLUE[6:0] OFFSET_CLEAR[6:0] sign = 1 is -ve DATA_CLEAR[9:8] DATA_BLUE[9:8] DATA_GREEN[9:8] 11/10-bit data DATA_RED[9:8] CAP_CLEAR[3:0] CAP_BLUE[3:0] CAP_GREEN[3:0] CAP_RED[3:0] 4 4 4 4 8 8 8 8 8 8 8 8 8 3 8 3 8 3 8 3 8 8 8 8 0 NUMBER R 0 NUMBER R 0 NUMBER R 0 NUMBER R 0 NUMBER R 0 NUMBER R 0 NUMBER R 0 NUMBER R 0 NUMBER R 0 NUMBER R 0 NUMBER R 0 NUMBER R 0 NUMBER R/W 0 NUMBER R/W 0 NUMBER R/W 0 NUMBER R/W 0 NUMBER R/W 0 NUMBER R/W 0 NUMBER R/W 0 NUMBER R/W 15 NUMBER R/W 15 NUMBER R/W 15 NUMBER R/W 15 NUMBER R/W 0 BITS R/W EXTCLK SLEEP TOFS 0 BITS R/W N/A GOFS GSSR RESET (DEC) TYPE ACCESS B7 B6 B5 B4 B3 B2 B1 B0 NOTES
Appendix A: Sensor Register List
ADD (DEC)
ADD (HEX)
MNEMONIC
0
0
CTRL
1
1
CONFIG
6
6
CAP_RED
7
7
CAP_GREEN
8
8
CAP_BLUE
9
9
CAP_CLEAR
10
A
INT_RED_LO
11
B
INT_RED_HI
12
C
INT_GREEN_LO
13
D
INT_GREEN_HI
14
E
INT_BLUE_LO
15
F
INT_BLUE_HI
16
10
INT_CLEAR_LO
17
11
INT_CLEAR_HI
64
40
DATA_RED_LO
65
41
DATA_RED_HI
66
42
DATA_GREEN_LO
67
43
DATA_GREEN_HI
68
44
DATA_BLUE_LO
69
45
DATA_BLUE_HI
70
46
DATA_CLEAR_LO
71
47
DATA_CLEAR_HI
72
48
OFFSET_RED
73
49
OFFSET_GREEN
74
4A
OFFSET_BLUE
75
4B
OFFSET_CLEAR
Appendix A: Sensor Register List
1)CTRL:ControlRegister
B7
B6
B5 N/A
B4
B3
B2
B1 GOFS
B0 GSSR
N/A GSSR GOFS
Notavailable. Getsensorreading.Activehighandautomaticallycleared.Resultisstoredinregisters64-71(DEC) Getoffsetreading.Activehighandautomaticallycleared.Resultisstoredinregisters72-75(DEC)
2)CONFIG:ConfigurationRegister
B7
B6
B5 N/A
B4
B3
B2 EXTCLK
B1 SLEEP
B0 TOFS
N/A EXTCLK SLEEP TOFS
Notavailable. Externalclockmode.Activehigh. Sleepmode.Activehighandexternalclockmodeonly.Automaticallyclearedifotherwise. Trimoffsetmode.Activehigh.
3)CAP_RED:CapacitorSettingsRegisterforRedChannel
B7 B6 N/A N/A CAP_RED Notavailable. Numberofredchannelcapacitors. B5 B4 B3 B2 B1 CAP_RED[3:0] B0
4)CAP_GREEN:CapacitorSettingsRegisterforGreenChannel
B7 B6 N/A N/A CAP_GREEN Notavailable. Numberofgreenchannelcapacitors. B5 B4 B3 B2 B1 B0
CAP_GREEN[3:0]
5)CAP_BLUE:CapacitorSettingsRegisterforBlueChannel
B7 B6 N/A N/A CAP_BLUE Notavailable. Numberofbluechannelcapacitors. B5 B4 B3 B2 B1 B0
CAP_BLUE[3:0]
6)CAP_CLEAR:CapacitorSettingsRegisterforClearChannel
B7 B6 N/A N/A CAP_CLEAR Notavailable. Numberofclearchannelcapacitors. B5 B4 B3 B2 B1 B0
CAP_CLEAR[3:0]
7
7)INT_RED:IntegrationTimeSlotSettingRegisterforRedChannel
B7 B6 B5 B4 INT_RED[7:0] B7 B6 N/A INT_RED Number of red channel integration time slots. B5 B4 B3 B2 INT_RED[11:8] B1 B0 B3 B2 B1 B0
8)INT_GREEN:IntegrationTimeSlotSettingRegisterforGreenChannel
B7 B6 B5 B4 B3 B2 B1 B0 INT_GREEN[7:0] B7 B6 N/A INT_GREEN Number of green channel integration time slots. B5 B4 B3 B2 B1 B0
INT_GREEN[11:8]
9)INT_BLUE:IntegrationTimeSlotSettingRegisterforBlueChannel
B7 B6 B5 B4 INT_BLUE[7:0] B7 B6 N/A INT_BLUE Number of blue channel integration time slots. B5 B4 B3 B2 B1 B0 B3 B2 B1 B0
INT_BLUE[11:8]
10)INT_CLEAR:IntegrationTimeSlotSettingRegisterforClearChannel
B7 B6 B5 B4 B3 B2 B1 B0 INT_CLEAR[7:0] B7 B6 N/A INT_CLEAR Number of clear channel integration time slots. B5 B4 B3 B2 B1 B0
INT_CLEAR[11:8]
11)DATA_RED_LO:LowByteRegisterofRedChannelSensorADCReading
B7 B6 B5 B4 B3 B2 B1 B0
DATA_RED[7:0] DATA_RED RedchannelADCdata.
8
12)DATA_RED_HI:HighByteRegisterofRedChannelSensorADCReading
B7 B6 B5 N/A
N/A DATA_RED Not available. Red channel ADC data.
B4
B3
B2
B1
B0
DATA_RED[9:8]
13)DATA_GREEN_LO:LowByteRegisterofGreenChannelSensorADCReading
B7 B6 B5 B4 B3 B2 B1 B0
DATA_GREEN[7:0] DATA_GREEN GreenchannelADCdata.
14)DATA_GREEN_HI:HighByteRegisterofGreenChannelSensorADCReading
B7 B6 B5 N/A
N/A DATA_GREEN Not available. Green channel ADC data.
B4
B3
B2
B1
B0
DATA_GREEN[9:8]
15)DATA_BLUE_LO:LowByteRegisterofBlueChannelSensorADCReading
B7 B6 B5 B4 B3 B2 B1 B0 DATA_BLUE[7:0] DATA_BLUE BluechannelADCdata.
16)DATA_BLUE_HI:HighByteRegisterofBlueChannelSensorADCReading
B7 B6 B5 N/A
N/A DATA_BLUE Not available. Blue channel ADC data.
B4
B3
B2
B1
B0
DATA_BLUE[9:8]
17)DATA_CLEAR_LO:LowByteRegisterofClearChannelSensorADCReading
B7 B6 B5 B4 B3 B2 B1 B0
DATA_CLEAR[7:0] DATA_CLEAR ClearchannelADCdata.
18)DATA_CLEAR_HI:HighByteRegisterofClearChannelSensorADCReading
B7 B6 B5 N/A
N/A DATA_CLEAR Not available. Clear channel ADC data.
B4
B3
B2
B1
B0
DATA_CLEAR[9:8]
9
19)OFFSET_RED:OffsetDataRegisterforRedChannel
B7 SIGN_RED SIGN_RED OFFSET_RED Signbit.0=POSITIVE,1=NEGATIVE. RedchannelADCoffsetdata. B6 B5 B4 B3 OFFSET_RED[6:0] B2 B1 B0
20)OFFSET_GREEN:OffsetDataRegisterforGreenChannel
B7 SIGN_GREEN SIGN_GREEN Signbit.0=POSITIVE,1=NEGATIVE. B6 B5 B4 B3 OFFSET_GREEN[6:0] B2 B1 B0
OFFSET_GREEN GreenchannelADCoffsetdata.
21)OFFSET_BLUE:OffsetDataRegisterforBlueChannel
B7 SIGN_BLUE SIGN_BLUE Signbit.0=POSITIVE,1=NEGATIVE. B6 B5 B4 B3 OFFSET_BLUE[6:0] B2 B1 B0
OFFSET_BLUE BluechannelADCoffsetdata.
22)OFFSET_CLEAR:OffsetDataRegisterforClearChannel
B7 SIGN_CLEAR SIGN_CLEAR Signbit.0=POSITIVE,1=NEGATIVE. B6 B5 B4 B3 OFFSET_CLEAR[6:0] B2 B1 B0
OFFSET_CLEAR ClearchannelADCoffsetdata.
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www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright (c) 007 Avago Technologies Limited. All rights reserved. AV0-09EN - July 30, 007

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