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STP16DP05
Low voltage 16-bit constant current LED sink driver with outputs error detection
Features

Low voltage power supply down to 3V 16 constant current output channels Adjustable output current through external resistor Short and open output error detection Serial Data IN/Parallel data OUT 3.3V micro driver-able Output current: 5-100mA 30MHz clock frequency Available in high thermal efficiency TSSOP exposed pad ESD protection 2.5kV HBM, 200V MM
TSSOP24 TSSOP24 (exposed pad) SO-24
The data detection results are loaded in the shift register and shifted out via the serial line output. The detection functionality is implemented without increasing the pin count number, through a secondary function of the output enable and latch pin (DM1 and DM2 respectively), a dedicated logic sequence allows the device to enter or leave from detection mode. Through an external resistor, users can adjust the STP16DP05 output current, controlling in this way the light intensity of LEDs, in addition, user can adjust LED's brightness intensity from 0% to 100% via OE/DM2 pin. The STP16DP05 guarantees a 20V output driving capability, allowing users to connect more LEDs in series. The high clock frequency, 30MHz, makes the device suitable for high data rate transmission. The 3.3V voltage supply is well useful for applications that interface any 3.3V micro. Compared with a standard TSSOP package, the TSSOP exposed pad increases heat dissipation capability by a 2.5 factor.
Description
The STP16DP05 is a monolithic, low voltage, low current power 16-bit shift register designed for LED panel displays. The device contains a 16-bit serial-in, parallel-out shift register that feeds a 16bitD-type storage register. In the output stage, sixteen regulated current sources were designed to provide 5-100mA constant current to drive the LEDs. The STP16DP05 features open and short LED detections on the outputs.The STP16DP05 is backward compatible with STP16C/L596.The detection circuit checks 3 different conditions that can occur on the output line: short to GND, short to VO or open line.
Table 1.
Device summary
Order codes STP16DP05MTR STP16DP05TTR STP16DP05XTTR Package SO-24 (Tape & reel) TSSOP24 (Tape & reel) TSSOP24 Exposed pad (Tape & reel) Packaging 1000 parts per reel 2500 parts per reel 2500 parts per reel
July 2007
Rev 3
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Contents
STP16DP05
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 2.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 4 5 6 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Equivalent circuit and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Detection mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1 7.2 7.3 7.4 Phase one: "entering in detection mode" . . . . . . . . . . . . . . . . . . . . . . . . . 16 Phase two: "error detection" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Phase three: "resuming to normal mode" . . . . . . . . . . . . . . . . . . . . . . . . . 19 Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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STP16DP05
Summary description
1
Summary description
Table 2. Typical current accuracy
Current accuracy Output voltage Between bits 1.3V 1.5% Between ICs 5% 20 to 100 mA 3.3V to 5V 25C Output current VDD temp.
1.1
Pin connection and description
Figure 1. Pin connection
Note:
The exposed pad is electrically not connected Table 3.
PIN N 1 2 3 4 5-20 21 22 23 24
Pin description
Symbol GND SDI CLK LE-DM1 OUT 0-15 OE-DM2 SDO R-EXT VDD Ground terminal Serial data input terminal Clock input terminal Latch input terminal - Detect mode 1 (see operation principle) Output terminal Input terminal of output enable (active low) - Detect mode 1 (see operation principle) Serial data out terminal Input terminal of an external resistor for constant current programing Supply voltage terminal Name and function
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Electrical ratings
STP16DP05
2
2.1
Electrical ratings
Absolute maximum ratings
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4.
Symbol VDD VO IO VI IGND fCLK Supply voltage Output voltage Output current Input voltage GND terminal current Clock frequency
Absolute maximum ratings
Parameter Value 0 to 7 -0.5 to 20 100 -0.4 to VDD 1600 50 Unit V V mA V mA MHz
2.2
Thermal data
Table 5.
Symbol TOPR TSTG
Thermal data
Parameter Operating temperature range Storage temperature range DIP-24 TSSOP24 Value -40 to +125 -55 to +150 60 85 37.5 75 Unit C C C/W C/W C/W C/W
RthJC
Thermal resistance junction-case
TSSOP24 Exposed Pad SO-24
(1)
1. The exposed pad should be soldered directly to the PCB to realize the thermal benefits.
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STP16DP05
Electrical ratings
2.3
Recommended operating conditions
Table 6.
Symbol VDD VO IO IOH IOL VIH VIL twLAT twCLK twEN
Recommended operating conditions
Parameter Supply voltage Output voltage Output current Output current Output current Input voltage Input voltage LE\DM1 pulse width CLK pulse width OE\DM2 pulse width VDD = 3.0V to 5.0V OUTn SERIAL-OUT SERIAL-OUT 0.7VDD -0.3 20 20 200 20 15 15 Cascade operation
(1)
Test conditions
Min 3.0
Typ
Max 5.5 20
Unit V V mA mA mA V V ns ns ns ns ns ns
5
100 +1 -1 VDD+0.3 0.3VDD
tSETUP(D) Setup time for DATA tHOLD(D) Hold time for DATA tSETUP(L) Setup time for LATCH fCLK Clock frequency
30
MHz
1. If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please consider the timings carefully.
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Electrical characteristics
STP16DP05
3
Table 7.
Symbol VIH VIL IOH VOL VOH IOL1 IOL2 IOL3 IOL1 IOL2 IOL3 RSIN(up)
Electrical characteristics
Electrical characteristics (VDD = 3.3V to 5V, T = 25C, unless otherwise specified.)
Parameter Input voltage high level Input voltage low level Output leakage current Output voltage (Serial-OUT) Output voltage (Serial-OUT) VOH = 20V IOL = 1mA IOH = -1mA VO = 0.3V, Rext = 3.9k Output current VO = 0.3V, Rext = 970 VO = 1.3V, Rext = 190 Output current error between bit (All Output ON) Pull-up resistor VO = 0.3VREXT = 3.9k VO = 0.3VREXT = 970 VO = 1.3VREXT =190 150 100 REXT = 970 OUT 0 to 15 = OFF Supply current (OFF) REXT = 240 OUT 0 to 15 = OFF REXT = 970 OUT 0 to 15 = ON Supply current (ON) IDD(ON2) Thermal Thermal protection (1) REXT = 240 OUT 0 to 15 = ON 11.7 170 13.5 C VOH -VDD = -0.4V 4.25 19 96 5 20 100 5 1.5 1.2 300 200 4 11.2 4.5 5.75 21 104 8 3 3 600 400 5 13.5 mA IDD(ON1) 5 K K % mA Test conditions Min 0.7VDD GND Typ Max VDD 0.3VDD 10 0.4 Unit V V A V V
RSIN(down) Pull-down resistor IDD(OFF1) IDD(OFF2)
1. Guaranteed by desing (not tested) The thermal protection switches OFF only the outputs current
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STP16DP05
Electrical characteristics
Table 8.
Symbol tPLH1
Switching characteristics (VDD = 5V, T = 25C, unless otherwise specified.)
Parameter Propagation delay time, CLK-OUTn, LE\DM1 = H, OE\DM2 = L Propagation delay time, LE\DM1 -OUTn, OE\DM2 = L Propagation delay time, OE\DM2-OUTn, LE\DM1 = H Propagation delay time, CLK-SDO Propagation delay time, CLK-OUTn, LE\DM1 = H, OE\DM2 = L Propagation delay time, LE\DM1 -OUTn, OE\DM2 = L Propagation delay time, OE\DM2-OUTn, LE\DM1 = H Propagation delay time, CLK-SDO Output rise time 10~90% of voltage waveform Output fall time 90~10% of voltage waveform CLK rise time (1) CLK fall time (1) Test conditions VDD = 3.3V VDD = 5V VDD = 3.3V VDD = 5V VDD = 3.3V VDD = 5V VDD = 3.3V VDD = 5V VDD = 3.3V VDD = 3.3 V VIL = GND IO = 20mA REXT = 1K VIH = VDD CL = 10pF VL = 3.0 V RL = 60 VDD = 5V VDD = 3.3V VDD = 5V VDD = 3.3V VDD = 5V VDD = 3.3V VDD = 5V VDD = 3.3V VDD = 5V VDD = 3.3V VDD = 5V Min Typ 70 45 61 41 69 50 14 8 34 23 27 22 23 20 15 9 42 35 10 9 Max 105 ns 65 90 ns 60 105 ns 70 20 ns 12 50 ns 35 40 ns 32 35 ns 30 25 ns 15 65 ns 55 16 ns 14 5000 5000 ns ns Unit
tPLH2
tPLH3
tPLH
tPHL1
tPHL2
tPHL3
tPHL
tON
tOFF tr tf
1. In order to achieve high cascade data transfer, please consider tr/tf timings carefully.
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Equivalent circuit and outputs
STP16DP05
4
Equivalent circuit and outputs
Figure 2. OE\DM2 terminal
Figure 3.
LE\DM1 terminal
Figure 4.
CLK, SDI terminal
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STP16DP05 Figure 5. SDO terminal
Equivalent circuit and outputs
Figure 6.
Block diagram
9/28
Timing diagrams
STP16DP05
5
Timing diagrams
Table 9.
CLOCK
Truth table
LE\DM1 H L H X X OE\DM2 L L L L H SERIAL-IN Dn Dn + 1 Dn + 2 Dn + 3 Dn + 3 OUT0 ............. OUT7 ................ OUT15 Dn ..... Dn - 7 ..... Dn -15 No Change Dn + 2 ..... Dn - 5 ..... Dn -13 Dn + 2 ..... Dn - 5 ..... Dn -13 OFF SDO Dn - 15 Dn - 14 Dn - 13 Dn - 13 Dn - 13
Note:
OUTn = ON when Dn = H OUTn = OFF when Dn = L Figure 7. Timing diagram
LE\DM1 OE\DM2
Note: 1 2 3
The latches circuit holds data when the LE\DM1 terminal is Low. When LE\DM1 terminal is at High level, latch circuit hold the data it passes from the input to the output. When OE\DM2 terminal is at Low level, output terminals OUT0 to OUT15 respond to the data, either ON or OFF. When OE\DM2 terminal is at High level, it switches off all the data on the output terminal.
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STP16DP05 Figure 8. Clock, serial-in, serial-out
Timing diagrams
Figure 9.
Clock, serial-in, latch, enable, outputs
LE\DM1
OE\DM2
11/28
Timing diagrams Figure 10. Outputs
STP16DP05
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STP16DP05
Typical characteristics
6
Typical characteristics
Figure 11. Output current-REXT resistor
Table 10.
Output current-REXT resistor
Rext (Ohm) 976 780 652 560 488 433 389 354 325 300 278 259 241 229 215 Output current (mA) 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
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Typical characteristics
STP16DP05
Conditions: Temperature = 25C, VDD = 3.3V; 5.0V, ISET = 3mA; 5mA; 10mA; 20mA; 50mA; 80mA. Figure 12. ISET vs drop out voltage (Vdrop)
800 700 600 500 400 300 200 100 0 0 20 40 Iset mA) 60 80
Vdrop (mV)
Avg @ 3.0V Avg @ 5.0V
Table 11.
ISET vs drop out voltage (Vdrop)
Iout (mA) 3 5 10 20 50 80 Avg @ 3.0V 19.33 36.67 77.33 158.67 406 692 Avg @ 5.0V 22.66 40.33 80 157.33 406 668
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STP16DP05
Typical characteristics
Figure 13. IDD ON\OFF
14 12 10 Idd (mA) 8 6 4 2 0 0 10 20 30 40 50 Iset (mA) 60 70 80 90
IddON Avg @ 5.5V IddON Avg @ 3.6V IddOFF Avg @ 5.5V IddOFF Avg @ 3.6V
Figure 14. Power dissipation vs temperature package
Note:
The Exposed-Pad should be soldered to the PBC to realize the thermal benefits.
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Detection mode functionality
STP16DP05
7
7.1
Detection mode functionality
Phase one: "entering in detection mode"
From the "Normal Mode" condition the device can switch to the "Error Mode" by a logic sequence on the OE\DM2 and LE/DM1 pins as showed in the following table and diagram: Table 12.
CLK OE/DM2 LE/DM1
Entering in detection truth table
1 H L 2 L L 3 H L 4 H H 5 H L
Figure 15. Entering in detection timing diagram
After these five CLK cycles the device goes into the "Error Detection Mode" and at the 6th rise front of CLK the SDI data are ready for the sampling.
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STP16DP05
Detection mode functionality
7.2
Phase two: "error detection"
The 16 data bits must be set "1" in order to set ON all the outputs during the detection. The data are latched by LE/DM1 and after that the outputs are ready for the detection process. When the Micro controller switches the OE\DM2 to LOW, the device drives the LEDs in order to analyze if an OPEN or SHORT condition has occurred. Figure 16. Detection diagram
The LEDs status will be detected at least in 1 microsecond and after this time the microcontroller sets OE\DM2 in HIGH state and the output data detection result will go to the microprocessor via SDO. Detection mode and normal mode use both the same format data. As soon as all the detection data bits are available on the serial line, the device may go back to normal mode of operation. To re-detect the status the device must go back in normal mode and reentering in error detection mode .
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Detection mode functionality Figure 17. Timing example for open and/or short detection
STP16DP05
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STP16DP05
Detection mode functionality
7.3
Phase three: "resuming to normal mode"
The sequence for re-entering in normal mode is showed in the following Table and diagram: Figure 18. Resuming to normal mode timing diagram
CLK OE/DM2 LE/DM1 1 H L 2 L L 3 H L 4 H L 5 H L
Note:
For proper device operation the "Entering in detection" sequence must be follow by a "Resume Mode" sequence, it is not possible to insert consecutive equal sequence.
7.4
Error detection conditions
Table 13.
SW-1 or SW-3b SW-2 or SW-3a
Detection conditions (VDD = 3.3 to 5 V temp. range -40 to 125C)
Open line or output ==> IODEC 0.5 x IO short to GND detected Short on LED or short ==> VO 2.4 V to V-LED detected No error detected ==> IODEC 0.5 x IO ==> VO 2.2 V
No error detected
Note:
Where: IO = the output current programmed by the REXT , IODEC = the detected output current in detection mode Figure 19. Detection circuit
16 STP16DP05
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Detection mode functionality Figure 20. Error detection sequence
During the error detection are necessary at least 2 CLK signal plus oneat the end
STP16DP05
16 CLK pulse are required to load the data setting 1 into shift register
Every CLK pulse shows the results of single Output results:Out15;14; 13 etc. etc
LE and OE Key Sequence necessary to Enter in EDM
The LE pulse latch the data loaded during the previous state
After OE signal turn High the SDO pin show the results of Error Detection (Open or Short in this case)
The OE Pulse put the device from EDM to Normal Mode
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STP16DP05
Package mechanical data
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
STP16DP05
Table 14.
Dim.
TSSOP24 mechanical data
mm. Min Typ Max 1.1 0.05 0.9 0.19 0.09 7.7 4.3 0.65 BSC 6.25 0 0.50 6.5 8 0.70 0.246 0 0.020 0.30 0.20 7.9 4.5 0.0075 0.0035 0.303 0.169 0.0256 BSC 0.256 8 0.028 0.15 0.002 0.035 0.0118 0.0079 0.311 0.177 Min inch Typ Max 0.043 0.006
A A1 A2 b c D E e H K L
Figure 21. TSSOP24 package dimensions
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STP16DP05 Table 15.
Dim. Min A C D N T Ao Bo Ko Po P 6.8 8.2 1.7 3.9 11.9 12.8 20.2 60 22.4 7 8.4 1.9 4.1 12.1 0.268 0.323 0.067 0.153 0.468 Typ Max 330 13.2 0.504 0.795 2.362 Min
Package mechanical data Tape and reel TSSOP24
mm. inch Typ Max 12.992 0.519
0.882 0.276 0.331 0.075 0.161 0.476
Figure 22. Reel dimensions
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Package mechanical data Table 16.
Dim. Min A a1 a2 b b1 C c1 D E e e3 F L S 7.40 0.50 15.20 10.00 1.27 13.97 7.60 1.27 0.291 0.020 (max.) 8 15.60 10.65 0.35 0.23 0.5 45(typ.) 0.598 0.393 0.050 0.550 0.1 Typ Max 2.65 0.2 2.45 0.49 0.32 0.014 0.009 0.020 0.004 Min Typ
STP16DP05
SO-24 mechanical data
mm. inch Max 0.104 0.008 0.096 0.019 0.012
0.614 0.419
0.300 0.050
Figure 23. SO-24 package dimensions
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STP16DP05 Table 17.
Dim. Min A C D N T Ao Bo Ko Po P 10.8 15.7 2.9 3.9 11.9 12.8 20.2 60 30.4 11.0 15.9 3.1 4.1 12.1 0.425 0.618 0.114 0.153 0.468 Typ Max 330 13.2 0.504 0.795 2.362 Min
Package mechanical data Tape and reel SO-24
mm. inch Typ Max 12.992 0.519
1.197 0.433 0.626 0.122 0.161 0.476
Figure 24. Reel dimensions
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Package mechanical data Table 18.
Dim. Min A A1 Typ Max 1.2 0.15 0.004 Min Typ
STP16DP05
TSSOP24 exposed-pad
mm inch Max 0.047 0.006
A2 b c D D1 E E1 E2 e K L
0.8 0.19 0.09 7.7
1
1.05 0.30 0.20
0.031 0.007 0.004 0.303 0.106
0.039
0.041 0.012 0.0089
7.8 2.7
7.9
0.307
0.311
6.2 4.3
6.4 4.4 1.5 0.65
6.6 4.5
0.244 0.169 0.059
0.252 0.173
0.260 0.177
0.0256 8 0 0.018 0.024 8 0.030
0 0.45 0.60
0.75
Figure 25. TSSOP24 dimensions
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STP16DP05
Revision history
9
Revision history
Table 19.
Date 9-Jan-2007 21-May-2007 10-Jul-2007
Revision history
Revision 1 2 3 First release Updated Table 7 on page 6 Updated Table 9: Truth table on page 10 Changes
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STP16DP05
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