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FPD750SOT343
LOW NOISE HIGH LINEARITY PACKAGED PHEMT
PACKAGE: FEATURES (1850MHZ):
* * * * * 0.5 dB N.F.min. 20 dBm Output Power (P1dB) 16.5 dB Small-Signal Gain (SSG) 37 dBm Output IP3 RoHS compliant (Directive 2002/95/EC)
Datasheet v3.0
ROHS:
GENERAL DESCRIPTION:
The FPD750SOT343 is a packaged depletion mode pseudomorphic High Electron Mobility Transistor (pHEMT). It utilizes a 0.25 m x 750 m Schottky barrier Gate. The Filtronic 0.25m process ensures class-leading noise performance. The use of a small footprint plastic package allows for cost effective system implementation.
TYPICAL APPLICATIONS:
* * * 802.11a,b,g and WiMax LNAs PCS/Cellular High Linearity LNAs Other types of wireless infrastructure systems.
TYPICAL PERFORMANCE1:
RF PARAMETER
Power at 1dB Gain Compression Small Signal Gain Power-Added Efficiency
SYMBOL
OP1dB SSG PAE
CONDITIONS
VDS = 3.3 V; IDS = 40mA VDS = 3.3 V; IDS = 40mA VDS = 3.3 V; IDS = 40mA POUT = P1dB
0.9GHZ 1.85GHZ 2.6GHZ
20 22 50 19 16.5 45 20 14 45
3.5GHZ
20.5 11 50
UNITS
dBm dB %
Maximum Stable Gain (|S21/S12|) Noise Figure Output Third-Order Intercept Point POUT = 9 dBm per Tone
MSG N.F. OIP3
VDS = 3.3 V; IDS = 40mA VDS = 3.3 V; IDS = 40mA VDS = 3.3V; IDS = 40mA VDS = 3.3V; IDS = 80mA
24 0.5 32 35
20 0.6 31 37
18 0.7 31 35
16 0.8 32 38
dB dB
dBm
ELECTRICAL SPECIFICATIONS2:
RF/DC PARAMETER
Frequency Power at 1dB Gain Compression Small Signal Gain Saturated Drain-Source Current Transconductance Pinch-Off Voltage Gate-Source Breakdown Voltage Gate-Drain Breakdown Voltage Thermal Resistivity (see Notes)
SYMBOL
f P1dB SSG IDSS GM |VP| |VBDGS| |VBDGD| JC
CONDITIONS
MIN
TYP
2.0
MAX
UNITS
GHz dBm dB
VDS = 3.3 V; IDS = 40mA VDS = 3.3 V; IDS = 40mA VDS = 1.3 V; VGS = 0 V VDS = 1.3 V; VGS = 0 V VDS = 1.3 V; IDS = 0.75 mA IGS = 0.75 mA IGD = 0.75 mA VDS > 3V
17 16 185 230 200 0.7 13 13 1.0 16 18 143 1.3 280
mA mS V V V C/W
Note: 1. Based on measured data taken on applications circuits. 2. All devices are 100% RF and DC tested at 2GHz with ZS = ZL = 50 Ohms 3. TAMBIENT = 22C 1
Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com
Tel: +44 (0) 1325 301111
Website: www.filtronic.com
FPD750SOT343
Datasheet v3.0
ABSOLUTE MAXIMUM RATING :
PARAMETER
Drain-Source Voltage Gate-Source Voltage Drain-Source Current Gate Current RF Input Power 2
1
SYMBOL
VDS VGS IDS IG PIN TCH TSTG 4 PTOT Comp. 3
TEST CONDITIONS
-3V < VGS < -0.5V 0V < VDS < +6V For VDS < 2V Forward or reverse current VDS = 3.3V Under any acceptable bias state Non-Operating Storage See De-Rating Note below Under any bias conditions 2 or more Max. Limits
ABSOLUTE MAXIMUM
6V -3V IDss 7.5mA 22dBm 175C -55C to 150C 1.1W 5dB 80%
Channel Operating Temperature Storage Temperature Total Power Dissipation Gain Compression Simultaneous Combination of Limits
Notes: 1 TAmbient = 22C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause permanent damage to the device 2 Max. RF Input Limit must be further limited if input VSWR > 2.5:1 3 Users should avoid exceeding 80% of 2 or more Limits simultaneously 4 Total Power Dissipation defined as: PTOT (PDC + PIN) - POUT, where PDC: DC Bias Power, PIN: RF Input Power, POUT: RF Output Power Total Power Dissipation to be de-rated as follows above 22C: PTOT= 1.1 - (1/jc) x TPACK where TPACK= source tab lead temperature above 22C & jc = 143C/W
BIASING GUIDELINES:
* Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is applied before Drain bias, otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for additional information. Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices. For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. Class A/B bias of 25-33% offers an optimised solution for NF and OIP3.
DC IV Curves FPD750SOT89
* *
0.30
0.25
0.20
0.15
0.10
VG=-1.50 VG=-1.25V VG=-1.00V VG=-0.75V VG=-0.50V VG=-0.25V VG=0V
Note: The recommended method for measuring IDSS, or any particular IDS, is to set the Drain-Source voltage (VDS) at 1.3V. This measurement point avoids the onset of spurious self-oscillation which would normally distort the current measurement (this effect has been filtered from the I-V curves presented above). Setting the VDS > 1.3V will generally cause errors in the current measurements, even in stabilized circuits.
Drain-Source Current (A)
0.05
0.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Drain-Source Voltage (V)
2
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Tel: +44 (0) 1325 301111
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FPD750SOT343
Datasheet v3.0
TYPICAL FREQUENCY REPONSE:
MSG & S21 vs Frequency Biased @ 3.3V, 40mA
MSG
N.F.min vs Frequency Biased @ 3.3V 1.20 1.00
28
MSG (dB)
24 20 16 12 8 4 0
S21
N.F.min (dB)
0.80 0.60 0.40 0.20
0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8
Mag S21
&
ID = 80mA ID = 40mA
5.4
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.5
Frequency (GHz)
Frequency (GHz)
NOTE: Typical Gain and Noise figure variation against frequency is shown above. The devices were biased nominally at VDS = 3.3V, IDS = 40mA. The test devices were tuned for minimum noise figure and maximum gain using tuners at the device input and output ports.
TYPICAL RF PERFORMANCE @
Power Transfer Characteristic VDS = 3.3V IDS = 40mA at f = 1.85GHz
23.0 21.0 19.0
Output Power (dBm)
Pout (dBm) Comp Point
1.85 GHZ:
Power Transfer Characteristic VDS = 3.3V IDS = 80mA at f = 1.85GHz
7.00 6.00
Gain Compression (dB)
23.0 21.0 19.0
Output Power (dBm)
Pout (dBm) Comp Point
17.0 15.0 13.0 11.0 9.0 7.0 -10.0
4.00 3.00 2.00 1.00 0.00 -1.00 10.0
17.0 15.0 13.0 11.0 9.0 7.0 -10.0
4.00 3.00 2.00 1.00 0.00 -1.00 12.0
-8.0
-6.0
-4.0
-2.0
0.0
2.0
4.0
6.0
8.0
-8.0
-6.0
-4.0
-2.0
0.0
2.0
4.0
6.0
8.0
10.0
Input Power (dBm)
Input Power (dBm)
NOTE: Typical power transfer curves at two bias conditions are shown above. The data is taken with the device mounted on evaluation board tuned at 1.85GHz for low noise and gain as shown in the reference design given on page 6.
3
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Gain Compression (dB)
5.00
6.0
7.00 6.00 5.00
0.00
FPD750SOT343
Datasheet v3.0
TYPICAL RF PERFORMANCE @
Typical Intermodulation Performance VDS = 3.3V IDS = 40mA at f = 1.85GHz
14
1.85 GHZ:
Typical Intermodulation Performance VDS = 3.3V IDS = 80mA at f = 1.85GHz
-24
14
-32
12
Pout (dBm) 3rds (dBc)
-30
3rd Order IM Products (dBc)
12
Pout (dBm) 3rds (dBc)
-38
3rd Order IM Products (dBc)
Output Power (dBm)
Output Power (dBm)
10
-36
10
-44
8
-42
8
-50
6
-48
6
-56
4
-54
4
-62
2 -12.3 -11.3 -10.3 -9.3 -8.3 -7.3 -6.3 -5.3 -4.3 -3.3
-60
2 -12.8 -11.8 -10.8 -9.8 -8.8 -7.8 -6.8 -5.8 -4.9 -3.9
-68
Input Power (dBm)
Input Power (dBm)
NOTE: Typical intermodulation performance is shown above. The data is taken with the device mounted on evaluation board tuned at 1.85GHz for low noise and gain as shown in the reference design given on page 6. The FPD750SOT343 has enhanced Intermodulation performance with an OIP3 value of up to P1dB+16dBm. This effect can be seen when the device is biased at ID=80mA by the bough in the 3rd order product plot line .
NOISE PARAMETERS:
Biased at VDS=3.3V, IDS=40mA Biased at VDS=3.3V, IDS=80mA
Freq. (GHz) 0.60 0.90 1.20 1.50 1.80 2.10 2.40 2.70 3.00 3.30 3.60 3.90 4.20 4.50 4.80 5.10 5.40 5.70 6.00
N.F.min (dB) 0.37 0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70 0.73 0.76 0.78 0.81 0.84 0.87 0.90
opt
Mag 0.770 0.689 0.614 0.546 0.485 0.431 0.383 0.342 0.307 0.280 0.258 0.244 0.236 0.236 0.242 0.254 0.273 0.299 0.332 Angle 12.2 21.2 30.6 40.4 50.6 61.1 72.1 83.4 95.1 107.2 119.8 132.7 146.0 159.6 173.7 -171.9 -157.0 -141.8 -126.1
Rn/50 0.108 0.100 0.092 0.084 0.077 0.069 0.063 0.057 0.053 0.049 0.046 0.043 0.042 0.040 0.040 0.041 0.044 0.050 0.061
Freq. (GHz) 0.60 0.90 1.20 1.50 1.80 2.10 2.40 2.70 3.00 3.30 3.60 3.90 4.20 4.50 4.80 5.10 5.40 5.70 6.00
N.F.min (dB) 0.39 0.42 0.46 0.50 0.53 0.57 0.60 0.64 0.68 0.71 0.75 0.79 0.83 0.86 0.90 0.94 0.97 1.01 1.05
opt
Mag. 0.732 0.644 0.564 0.492 0.428 0.372 0.324 0.283 0.251 0.227 0.210 0.202 0.201 0.208 0.223 0.247 0.277 0.317 0.364 Angle 11.5 22.1 33.0 44.2 55.9 67.9 80.2 93.0 106.2 119.7 133.6 147.9 162.5 177.5 -167.1 -151.4 -135.2 -118.7 -101.8
Rn/50 0.129 0.115 0.102 0.090 0.079 0.070 0.063 0.057 0.053 0.050 0.049 0.048 0.048 0.049 0.051 0.056 0.065 0.080 0.106
4
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Tel: +44 (0) 1325 301111
Website: www.filtronic.com
FPD750SOT343
Datasheet v3.0
REFERENCE DESIGN (0.9GHZ):
FREQUENCY Gain P1dB OIP31 N.F. S11 S22 Vd Vg Id GHZ dB dBm dBm dB dB dB V V mA 0.9 22 20 32 0.5 -5 -10 3.3 -0.4 to -0.6 40
1. OIP3 measured at Pout of 9dBm per tone
Measured Gain and Return Loss
BOARD LAYOUT:
Vg 15pF 0.01uF 15pF 20O Lg 33pF L1 L2 Ld 33pF 0.01uF Vd
+ 1.0uF +
Q1
0.63"
1.45"
Component Values
Component Lg Ld L1 L2 Value 56nH 56nH 15nH 4.7nH Description LL1608 Toko chip inductor LL1608 Toko chip inductor LL1608 Toko chip inductor LL1608 Toko chip inductor
FPD750SOT343 EVAL Board -Vg Schematic 0.01uF @ 900MHz 15pF
Vd
1.0uF 0.01uF 15pF 56 nH L2 33pF
RF OUT
20 Ohm 56 nH L1
33pF
RF IN
Eval board material - 31mil thick FR4 with 1/2 Ounce Cu on both sides
D.C. Blocking capacitors are ATC series 600S. A tantalum 1.0F is used at the drain terminal. All other capacitors are 0603 and 0805 standard chip capacitors. A 0603 size 20 Ohm Chip resistor from Vishay is used on the gate D.C. bias line for stability.
5
Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com
Tel: +44 (0) 1325 301111
Website: www.filtronic.com
FPD750SOT343
Datasheet v3.0
REFERENCE DESIGN (1.85GHZ):
FREQUENCY Gain P1dB OIP31 N.F. S11 S22 Vd Vg Id GHZ dB dBm dBm dB dB dB V V mA 1.85 16.5 19 31 0.6 -6 -10 3.3 -0.4 to -0.6 40
1.OIP3 measured at Pout of 9dBm per tone
Measured Gain and Return Loss
BOARD LAYOUT:
Vg 15pF 0.01uF 15pF 20O Lg 33pF L1 L2 Ld 33pF 0.01uF Vd
+ 1.0uF +
Q1
C2
0.63"
1.45"
Component Values
Component Lg Ld L1 L2 C2 Value 22nH 22nH 2.2nH 1.8nH 1.0pF Description LL1608 Toko chip inductor LL1608 Toko chip inductor LL1005 Toko chip inductor LL1005 Toko chip inductor ATC 600S Chip Capacitor
FPD750SOT343 EVAL Board -Vg Schematic 0.01uF @ 1.85GHz 15pF
Vd
1.0uF 0.01uF 15pF 22 nH L2 C2 33pF
RF OUT
20 Ohm 22 nH L1
33pF
RF IN
Eval board material - 31mil thick FR4 with 1/2 Ounce Cu on both sides
D.C. Blocking capacitors are ATC series 600S. A tantalum 1.0F is used at the drain terminal. All other capacitors are 0603 and 0805 standard chip capacitors. A 0603 size 20 Ohm Chip resistor from Vishay is used on the gate D.C. bias line for stability.
6
Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com
Tel: +44 (0) 1325 301111
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FPD750SOT343
Datasheet v3.0
REFERENCE DESIGN (2.6GHZ):
FREQUENCY Gain P1dB OIP31 N.F. S11 S22 Vd Vg Id GHZ dB dBm dBm dB dB dB V V mA 2.5 14.2 20 30.5 0.8 -20 -7 2.6 2.7
14 13.5 21 21 31 31 0.7 0.75 -25 -20 -8 -10 3.3 -0.4 to -0.6 40
1. OIP3 measured at Pout of 9dBm per tone
Measured Gain and Return Loss
BOARD LAYOUT:
Vg 15pF 0.01uF 15pF 20O Lg 33pF C1 L1 C2 Ld 33pF 0.01uF Vd
+ 1.0uF +
Q1
L2
0.63"
1.45"
Component Values
Component Lg Ld L1 L2 C1 C2 Value 18nH 18nH 1.2nH 2.7nH 1.0pF 1.8pF Description LL1608 Toko chip inductor LL1608 Toko chip inductor LL1005 Toko chip inductor LL1005 Toko chip inductor ATC 600S Chip Capacitor ATC 600S Chip Capacitor
FPD750SOT343 EVAL Board -Vg Schematic 0.01uF
Vd
2.6GHz
1.0uF 0.01uF
15pF 20 Ohm 18nH L1 18nH
15pF C2 L2 33pF
RF OUT
33pF
RF IN
C1
Eval board material - 31mil thick FR4 with 1/2 Ounce Cu on both sides
D.C. Blocking capacitors are ATC series 600S. A tantalum 1.0F is used at the drain terminal. All other capacitors are 0603 and 0805 standard chip capacitors. A 0603 size 20 Ohm Chip resistor from Vishay is used on the gate D.C. bias line for stability.
7
Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com
Tel: +44 (0) 1325 301111
Website: www.filtronic.com
FPD750SOT343
Datasheet v3.0
REFERENCE DESIGN (3.5GHZ):
FREQUENCY Gain P1dB OIP31 N.F. S11 S22 Vd Vg Id GHZ dB dBm dBm dB dB dB V V mA 3.5 11 20.5 32 0.75 -11 -11 3.3 -0.4 to -0.6 40
1. OIP3 measured at Pout of 9dBm per tone
Measured Gain and Return Loss
BOARD LAYOUT:
Vg 15pF 0.01uF 20O Lg L1 C1 15pF 0.01uF Vd
+ 1.0uF +
10pF
Ld
Q1
C2 L2
10pF
0.63"
1.45"
Component Values
Component Lg Ld L1 L2 C1 Value 18nH 18nH 1.0nH 2.7nH 0.3pF Description LL1608 Toko chip inductor LL1608 Toko chip inductor 0402CS Coil Cr. inductor 0402CS Coil Cr. inductor ATC 600S Chip Capacitor ATC 600S Chip Capacitor
FPD750SOT343 EVAL Board -Vg Schematic 0.01uF @ 3.5GHz 15pF
Vd
1.0uF 0.01uF 15pF 18 nH C2 L2 10pF
RF OUT
20 Ohm 18 nH L1
10pF
RF IN
C2 0.8pF Eval board material - 31mil thick Rogers 4003 with 1/2 Ounce Cu on both sides.
C1
D.C. Blocking capacitors are ATC series 600S. A tantalum 1.0F is used at the drain terminal. All other capacitors are 0603 and 0805 standard chip capacitors. A 0603 size 20 Ohm Chip resistor from Vishay is used on the gate D.C. bias line for stability.
8
Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com
Tel: +44 (0) 1325 301111
Website: www.filtronic.com
FPD750SOT343
Datasheet v3.0
S-PARAMETERS (BIASED @ 3.3V, 40mA)
Freq (GHz) 0.60 0.90 1.20 1.50 1.80 2.10 2.40 2.70 3.00 3.30 3.60 3.90 4.20 4.50 4.80 5.10 5.40 5.70 6.00 S11 Mag. 0.875 0.788 0.707 0.641 0.590 0.557 0.532 0.515 0.501 0.491 0.484 0.484 0.483 0.489 0.494 0.503 0.515 0.528 0.545 Ang. -51.0 -72.8 -92.2 -109.4 -124.7 -138.4 -151.0 -162.2 -172.8 178.2 169.6 161.3 153.4 145.3 136.9 128.7 120.5 112.3 104.4 S21 Mag. 12.561 11.024 9.608 8.377 7.354 6.547 5.881 5.341 4.886 4.519 4.202 3.950 3.728 3.525 3.340 3.173 3.020 2.874 2.725 S12 Ang. 139.4 123.3 110.0 98.5 88.5 79.6 71.5 64.0 56.9 50.2 43.6 37.2 30.7 24.1 17.5 11.1 4.5 -2.2 -8.8 Mag. 0.034 0.046 0.057 0.065 0.072 0.079 0.086 0.092 0.099 0.105 0.112 0.118 0.125 0.131 0.137 0.143 0.148 0.153 0.156 Ang. 67.2 59.0 53.0 48.1 44.2 40.6 37.5 34.3 31.2 28.2 24.9 21.5 17.9 14.0 9.8 5.6 1.2 -3.4 -8.0 Mag. 0.294 0.248 0.216 0.186 0.162 0.150 0.138 0.132 0.126 0.119 0.116 0.110 0.107 0.110 0.115 0.125 0.141 0.161 0.185 S22 Ang. -40.8 -59.5 -76.2 -91.7 -106.8 -121.3 -133.8 -145.4 -155.7 -164.8 -175.0 176.0 165.7 153.9 142.7 129.9 119.8 110.4 101.6
S-PARAMETERS (BIASED @ 3.3V, 80mA)
Freq (GHz) 0.60 0.90 1.20 1.50 1.80 2.10 2.40 2.70 3.00 3.30 3.60 3.90 4.20 4.50 4.80 5.10 5.40 5.70 6.00 S11 Mag. 0.852 0.755 0.671 0.605 0.556 0.525 0.502 0.487 0.475 0.465 0.459 0.458 0.459 0.464 0.469 0.479 0.492 0.506 0.524 Ang. -53.8 -76.0 -95.6 -112.6 -127.8 -141.4 -153.7 -164.7 -175.1 176.1 167.8 159.6 152.1 144.2 136.1 128.2 120.1 112.2 104.4 S21 Mag. 14.400 12.398 10.653 9.200 8.027 7.115 6.372 5.773 5.272 4.868 4.522 4.246 4.006 3.787 3.588 3.408 3.246 3.094 2.937 S12 Ang. 137.0 120.7 107.5 96.4 86.7 78.1 70.3 63.0 56.2 49.6 43.2 37.0 30.6 24.2 17.8 11.5 5.1 -1.5 -8.0 Mag. 0.029 0.039 0.048 0.056 0.063 0.071 0.078 0.085 0.091 0.098 0.105 0.112 0.119 0.126 0.132 0.138 0.144 0.149 0.153 Ang. 69.0 62.1 57.1 53.2 49.8 46.5 43.5 40.5 37.3 34.3 30.9 27.5 23.9 19.9 15.7 11.5 7.0 2.3 -2.3 Mag. 0.256 0.210 0.180 0.151 0.128 0.115 0.104 0.097 0.090 0.083 0.079 0.073 0.068 0.069 0.071 0.079 0.094 0.113 0.138 S22 Ang. -38.6 -55.1 -69.8 -82.8 -96.3 -109.7 -121.0 -132.3 -141.3 -149.7 -159.5 -167.0 -177.9 169.0 154.1 137.9 125.7 114.4 105.2
9
Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com
Tel: +44 (0) 1325 301111
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FPD750SOT343
Datasheet v3.0
PACKAGE OUTLINE:
(dimensions in millimeters - mm)
SOURCE
GATE
DRAIN
SOURCE
TAPE DIMENSIONS AND PART ORIENTATION
FWYN
FWYN
Leader tape with empty Cavities = 350mm(min.) Trailer tape with empty Cavities = 160mm(min.) Devices per reel = 3000
10
Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com
Tel: +44 (0) 1325 301111
Website: www.filtronic.com
FPD750SOT343
Datasheet v3.0
PCB FOOT PRINT
profile defined within IPC/JEDEC J-STD-020C, Moisture / Reflow sensitivity classification for non-hermetic solid state surface mount devices
APPLICATION NOTES & DESIGN DATA:
Application Notes and design data including Sparameters, noise parameters and device model are available on request.
RELIABILITY:
A MTTF of 4.2 million hours at a channel temperature of 150C is achieved for the process used to manufacture this device.
Units in inches
DISCLAIMERS:
This product is not designed for use in any space based or life sustaining/supporting equipment.
PREFERRED ASSEMBLY INSTRUCTIONS:
This package is compatible with both lead free and leaded solder reflow processes as defined within IPC/JEDEC J-STD-020C. The maximum package temperature should not exceed 260C.
ORDERING INFORMATION:
PART NUMBER
FPD750SOT343 FPD750SOT343E
DESCRIPTION
Packaged pHEMT Lead free Packaged pHEMT RoHS Compliant Packaged pHEMT
HANDLING PRECAUTIONS:
To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing.
FPD750SOT343CE
with enhanced passivation (Recommended for New Designs)
EB750SOT343-BB EB750SOT343-BA EB750SOT343-BC EB750SOT343-BE EB750SOT343-BG
0.9 GHz evaluation board 1.85 GHz evaluation board 2.0 GHz evaluation board 2.4 GHz evaluation board 2.6 GHz evaluation board 3.5 GHz evaluation board
ESD/MSL RATING:
These devices should be treated as Class 1A (250V - 500V) using the human body model as defined in JEDEC Standard No. 22-A114. The device has a MSL rating of Level 1. To determine this rating, preconditioning was performed to the device per, the Pb-free solder
11
EB750SOT343-AH
Tel: +44 (0) 1325 301111
Specifications subject to change without notice Filtronic Compound Semiconductors Ltd Fax: +44 (0) 1325 306177 Email: sales@filcs.com
Website: www.filtronic.com

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