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| (R) EL5421 Data Sheet August 2, 2007 FN7198.2 Quad 12MHz Rail-to-Rail Input-Output Buffer The EL5421 is a quad, low power, high voltage rail-to-rail input-output buffer. Operating on supplies ranging from 5V to 15V, while consuming only 500A per channel, the EL5421 has a bandwidth of 12MHz (-3dB). The EL5421 also provides rail-to-rail input and output ability, giving the maximum dynamic range at any supply voltage. The EL5421 also features fast slewing and settling times, as well as a high output drive capability of 30mA (sink and source). These features make the EL5421 ideal for use as voltage reference buffers in Thin Film Transistor Liquid Crystal Displays (TFT-LCD). Other applications include battery power, portable devices and anywhere low power consumption is important. The EL5421 is available in a space saving 10 Ld MSOP package and operates over a temperature range of -40C to +85C. Features * 12MHz -3dB bandwidth * Unity gain buffer * Supply voltage = 4.5V to 16.5V * Low supply current (per buffer) = 500A * High slew rate = 10V/s * Rail-to-rail operation * "Mini" SO package (MSOP) * Pb-free plus anneal available (RoHS compliant) Applications * TFT-LCD drive circuits * Electronics notebooks * Electronics games * Personal communication devices * Personal digital assistants (PDA) Pinout EL5421 (10 LD MSOP) TOP VIEW VOUTA 1 VINA 2 VS+ 3 VINB 4 VOUTB 5 10 VOUTD 9 VIND 8 VS7 VINC 6 VOUTC * Portable instrumentation * Wireless LANs * Office automation * Active filters * ADC/DAC buffers Ordering Information PART NUMBER EL5421CY EL5421CY-T7* EL5421CY-T13* EL5421CYZ (Note) EL5421CYZ-T7* (Note) PART MARKING F F F BCAAA BCAAA PACKAGE 10 Ld MSOP 10 Ld MSOP 10 Ld MSOP 10 Ld MSOP (Pb-Free) 10 Ld MSOP (Pb-Free) 10 Ld MSOP (Pb-Free) PKG. DWG. # MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 EL5421CYZ-T13* BCAAA (Note) *Please refer to TB347 for details on reel specifications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Elantec is a registered trademark of Elantec Semiconductor, Inc. Copyright Intersil Americas Inc. 2004, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5421 Absolute Maximum Ratings (TA = +25C) Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V, VS+ +0.5V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA Thermal Information Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Electrical Specifications PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN AV VS+ = +5V, VS- = -5V, RL = 10k and CL = 10pF to 0V, TA = +25C unless otherwise specified. CONDITION MIN (Note 4) TYP MAX (Note 4) UNIT DESCRIPTION Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain VCM = 0V (Note 1) VCM = 0V 2 5 2 1 1.35 12 mV V/C 50 nA G pF -4.5V VOUT 4.5V 0.995 1.005 V/V OUTPUT CHARACTERISTICS VOL VOH ISC Output Swing Low Output Swing High Short Circuit Current IL = -5mA IL = 5mA Short to GND (Note 2) 4.85 80 -4.92 4.92 120 -4.85 V V mA POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current (Per Buffer) VS is moved from 2.25V to 7.75V No load 60 80 500 750 dB A DYNAMIC PERFORMANCE SR tS BW CS Slew Rate (Note 3) Settling to +0.1% -3dB Bandwidth Channel Separation -4.0V VOUT 4.0V, 20% to 80% VO = 2V step RL = 10k, CL = 10pF f = 5MHz 7 10 500 12 75 V/s ns MHz dB 2 FN7198.2 August 2, 2007 EL5421 Electrical Specifications PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN AV Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain 0.5 VOUT 4.5V 0.995 VCM = 2.5V (Note 1) VCM = 2.5V 2 5 2 1 1.35 1.005 50 10 mV V/C nA GW pF V/V VS+ = +5V, VS- = 0V, RL = 10k and CL = 10pF to 2.5V, TA = +25C unless otherwise specified. CONDITION MIN (Note 4) TYP MAX (Note 4) UNIT DESCRIPTION OUTPUT CHARACTERISTICS VOL VOH ISC Output Swing Low Output Swing High Short Circuit Current IL = -5mA IL = 5mA Short to GND (Note 2) 4.85 80 80 4.92 120 150 mV V mA POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current (Per Buffer) VS is moved from 4.5V to 15.5V No load 60 80 500 750 dB A DYNAMIC PERFORMANCE SR tS BW CS Slew Rate (Note 3) Settling to +0.1% -3dB Bandwidth Channel Separation 1V VOUT 4V, 20% to 80% VO = 2V step RL = 10k, CL = 10pF f = 5MHz 7 10 500 12 75 V/s ns MHz dB 3 FN7198.2 August 2, 2007 EL5421 Electrical Specifications PARAMETER INPUT CHARACTERISTICS VOS TCVOS IB RIN CIN AV Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain 0.5 VOUT 14.5V 0.995 VCM = 7.5V (Note 1) VCM = 7.5V 2 5 2 1 1.35 1.005 50 14 mV V/C nA G pF V/V VS+ = +15V, VS- = 0V, RL = 10k and CL = 10pF to 7.5V, TA = +25C unless otherwise specified. CONDITION MIN (Note 4) TYP MAX (Note 4) UNIT DESCRIPTION OUTPUT CHARACTERISTICS VOL VOH ISC Output Swing Low Output Swing High Short Circuit Current IL = -5mA IL = 5mA Short to GND (Note 2) 14.85 80 80 14.92 120 150 mV V mA POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Supply Current (Per Buffer) VS is moved from 4.5V to 15.5V No load 60 80 500 750 dB A DYNAMIC PERFORMANCE SR tS BW CS NOTES: 1. Measured over the operating temperature range 2. Limits established by characterization and are not production tested. 3. Slew rate is measured on rising and falling edges 4. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested Slew Rate (Note 3) Settling to +0.1% -3dB Bandwidth Channel Separation 1V VOUT 14V, 20% to 80% VO = 2V step RL = 10k, CL = 10pF f = 5MHz 7 10 500 12 75 V/s ns MHz dB 4 FN7198.2 August 2, 2007 EL5421 Typical Performance Curves 1800 1600 QUANTITY (BUFFERS) 1400 1200 1000 800 600 400 200 0 -8 -6 -4 -2 -0 2 4 6 -12 -10 8 10 12 VS=5V TA=25C TYPICAL PRODUCTION DISTRIBUTION 70 VS=5V 60 QUANTITY (BUFFERS) 50 40 30 20 10 0 1 3 5 7 9 11 13 15 17 19 21 150 150 FN7198.2 August 2, 2007 TYPICAL PRODUCTION DISTRIBUTION INPUT OFFSET VOLTAGE (mV) INPUT OFFSET VOLTAGE DRIFT, TCVOS (V/C) FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION FIGURE 2. INPUT OFFSET VOLTAGE DRIFT 10 INPUT OFFSET VOLTAGE (mV) VS=5V INPUT BIAS CURRENT (nA) 2.0 VS=5V 5 0.0 0 -5 -50 0 50 100 150 -2.0 -50 0 50 100 TEMPERATURE (C) TEMPERATURE (C) FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE 4.97 OUTPUT HIGH VOLTAGE (V) OUTPUT LOW VOLTAGE (V) -4.91 -4.92 -4.93 -4.94 -4.95 -4.96 -4.97 0 50 100 150 -50 0 50 100 VS=5V IOUT=-5mA 4.96 4.95 4.94 VS=5V IOUT=5mA 4.93 -50 TEMPERATURE (C) TEMPERATURE (C) FIGURE 5. OUTPUT HIGH VOLTGE vs TEMPERATURE FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE 5 EL5421 Typical Performance Curves VS=5V 1.0005 VOLTAGE GAIN (V/V) SLEW RATE (V/s) 10.40 VS=5V 10.35 1.0000 10.30 0.9995 10.25 -50 0 50 100 150 -50 0 50 100 150 TEMPERATURE (C) TEMPERATURE (C) FIGURE 7. VOLTAGE GAIN vs TEMPERATURE FIGURE 8. SLEW RATE vs TEMPERATURE 700 VS=5V SUPPLY CURRENT (mA) SUPPLY CURRENT (A) 0.55 600 TA=25C 0.5 500 400 0.45 300 -50 0 50 100 150 0 5 10 15 20 TEMPERATURE (C) SUPPLY VOLTAGE (V) FIGURE 9. SUPPLY CURRENT PER CHANNEL vs TEMPERATURE FIGURE 10. SUPPLY CURRENT PER CHANNEL vs SUPPLY VOLTAGE MAGNITUDE (NORMALIZED) (dB) MAGNITUDE (NORMALIZED) (dB) 5 10k 0 1k 560 -5 150 20 RL=10k VS=5V 10 12pF 0 50pF -10 -20 -30 100K 100pF -10 CL=10pF VS=5V -15 100K 1M 10M 100M 1000pF 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 11. FREQUENCY RESPONSE FOR VARIOUS RL FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS CL 6 FN7198.2 August 2, 2007 EL5421 Typical Performance Curves 200 OUTPUT IMPEDANCE () TA=25C VS=5V 12 10 8 6 4 2 VS=5V TA=25C RL=10k CL=12pF DISTORTION <1% 100K 1M 10M 160 120 80 40 MAXIMUM OUTPUT SWING (VP-P) 0 10K 100K 1M 10M 0 10K FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 13. OUT PUT IMPEDANCE vs FREQUENCY FIGURE 14. MAXIMUM OUTPUT SWING vs FREQUENCY 80 PSRR+ 60 PSRR (dB) PSRRVOLTAGE NOISE (nV/Hz) 600 100 40 10 20 TA=25C VS=5V 0 100 1K 10K 100K 1M 10M 1 100 1K 10K 100K 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 15. PSRR vs FREQUENCY FIGURE 16. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY 0.010 0.009 0.008 THD+ N (%) 0.007 0.006 0.005 0.004 0.003 0.002 0.001 1K 10K FREQUENCY (Hz) 100K VS=5V RL=10k VIN=1VRMS X-TALK (dB) -60 DUAL MEASURED CH A TO B QUAD MEASURED CH A TO D OR B TO C OTHER COMBINATIONS YIELD IMPROVED REJECTION -80 -100 -120 VS=5V RL=10k VIN=220mVRMS 10K 100K FREQUENCY (Hz) 1M 6M -140 1K FIGURE 17. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY FIGURE 18. CHANNEL SEPARATION vs FREQUENCY RESPONSE 7 FN7198.2 August 2, 2007 EL5421 Typical Performance Curves 5 90 OVERSHOOT (%) 70 50 30 10 -5 10 100 LOAD CAPACITANCE (pF) 1K 0 200 400 600 800 VS=5V RL=10k VIN=50mV TA=25C VS=5V RL=10k CL=12pF TA=25C 0.1% 3 STEP SIZE (V) 1 -1 -3 0.1% SETTLING TIME (ns) FIGURE 19. SMALL SIGNAL OVERSHOOT vs LOAD CAPACITANCE FIGURE 20. SETTLING TIME vs STEP SIZE 1V 1s 50mV 200ns VS=5V TA=25C RL=10k CL=12pF VS=5V TA=25C RL=10k CL=12pF FIGURE 21. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 22. SMALL SIGNAL TRANSIENT REPOSNE 8 FN7198.2 August 2, 2007 EL5421 Pin Descriptions PIN NUMBER 1 PIN NAME VOUTA Buffer A Output FUNCTION EQUIVALENT CIRCUIT VS+ GND CIRCUIT 1 VS- 2 VINA Buffer A Input VS+ VSCIRCUIT 2 3 4 5 6 7 8 9 10 VS+ VINB VOUTB VOUTC VINC VSVIND VOUTD Positive Power Supply Buffer B Input Buffer B Output Buffer C Output Buffer C Input Negative Power Supply Buffer D Input Buffer D Output (Reference Circuit 2) (Reference Circuit 1) (Reference Circuit 1) (Reference Circuit 2) (Reference Circuit 2) (Reference Circuit 1) Applications Information Product Description The EL5421 unity gain buffer is fabricated using a high voltage CMOS process. It exhibits rail-to-rail input and output capability, and has low power consumption (500A per buffer). These features make the EL5421 ideal for a wide range of general-purpose applications. When driving a load of 10k and 12pF, the EL5421 has a -3dB bandwidth of 12MHz and exhibits 10V/s slew rate. voltage range even closer to the supply rails. Figure 23 shows the input and output waveforms for the device. Operation is from 5V supply with a 10k load connected to GND. The input is a 10VP-P sinusoid. The output voltage is approximately 9.985VP-P. 5V 10s Operating Voltage, Input, and Output The EL5421 is specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range of 4.5V to 16.5V. Most EL5421 specifications are stable over both the full supply range and operating temperatures of -40C to +85C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The output swings of the EL5421 typically extend to within 80mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output 5V VS=5V TA=25C VIN=10VP-P FIGURE 23. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT Short Circuit Current Limit The EL5421 will limit the short circuit current to 120mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power 9 FN7198.2 August 2, 2007 OUTPUT INPUT EL5421 dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds 30mA. This limit is set by the design of the internal metal interconnects. The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or: P DMAX = i [ V S x I SMAX + ( V S + - V OUT i ) x I LOAD i ] (EQ. 2) Output Phase Reversal The EL5421 is immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Figure 24 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur. 1V 10s when sourcing, and: P DMAX = i [ V S x I SMAX + ( V OUT i - V S - ) x I LOAD i ] (EQ. 3) when sinking. Where: i = 1 to 4 for quad VS = Total supply voltage ISMAX = Maximum supply current per channel VOUTi = Maximum output voltage of the application ILOADi = Load current If we set the two PDMAX equations equal to each other, we can solve for RLOADi to avoid device overheat. Figures 25 and 26 provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves. To ensure proper operation, it is important to observe the recommended derating curves shown in Figures 25 and 26. JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1 0.9 POWER DISSIPATION (W) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (C) 870mW M 11 SO 1V VS=2.5V TA=25C VIN=6VP-P FIGURE 24. OPERATION WITH BEYOND-THE-RAILS INPUT Power Dissipation With the high-output drive capability of the EL5421 buffer, it is possible to exceed the +125C 'absolute-maximum junction temperature' under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the buffer to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX - T AMAX P DMAX = ------------------------------------------- JA (EQ. 1) JA = P1 5 0 C/ W where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature JA = Thermal resistance of the package PDMAX = Maximum power dissipation in the package FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 10 FN7198.2 August 2, 2007 EL5421 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.6 POWER DISSIPATION (W) 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (C) 486mW Power Supply Bypassing and Printed Circuit Board Layout The EL5421 can provide gain at high frequency. As with any high-frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, a 0.1F ceramic capacitor should be placed from VS+ to pin to VS- pin. A 4.7F tantalum capacitor should then be connected in parallel, placed in the region of the buffer. One 4.7F capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. JA = SO P1 20 0 6 C/ W M FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Unused Buffers It is recommended that any unused buffer have the input tied to the ground plane. Driving Capacitive Loads The EL5421 can drive a wide range of capacitive loads. As load capacitance increases, however, the -3dB bandwidth of the device will decrease and the peaking increase. The buffers drive 10pF loads in parallel with 10k with just 1.5dB of peaking, and 100pF with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5 and 50) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a "snubber" circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 150 and 10nF are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain. 11 FN7198.2 August 2, 2007 EL5421 Mini SO Package Family (MSOP) 0.25 M C A B D N A (N/2)+1 MDP0043 MINI SO PACKAGE FAMILY MILLIMETERS SYMBOL A A1 MSOP8 1.10 0.10 0.86 0.33 0.18 3.00 4.90 3.00 0.65 0.55 0.95 8 MSOP10 1.10 0.10 0.86 0.23 0.18 3.00 4.90 3.00 0.50 0.55 0.95 10 TOLERANCE Max. 0.05 0.09 +0.07/-0.08 0.05 0.10 0.15 0.10 Basic 0.15 Basic Reference NOTES 1, 3 2, 3 Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. E E1 PIN #1 I.D. A2 b c B 1 (N/2) D E E1 e C SEATING PLANE 0.10 C N LEADS b H e L L1 N 0.08 M C A B L1 A c SEE DETAIL "X" 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. A2 GAUGE PLANE L DETAIL X 0.25 A1 3 3 12 FN7198.2 August 2, 2007 |
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