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CY2SSTV857-27
Differential Clock Buffer/Driver DDR333/PC2700-Compliant
Features
* Operating frequency: 60 MHz to 200 MHz * Supports 266, 333 MHz DDR SDRAM * 10 differential outputs from 1 differential input * Spread-Spectrum-compatible * Low jitter (cycle-to-cycle): < 75 * Very low skew: < 100 ps * Power management control input * High-impedance outputs when input clock < 10 MHz * 2.5V operation * Pin-compatible with CDC857-2 and -3 * 48-pin TSSOP package * Industrial temp. of -40 to +85C * Conforms to JEDEC DDR specification
Description
The CY2SSTV857-27 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications. The CY2SSTV857-27 generates ten differential pair clock outputs from one differential pair clock input. In addition, the CY2SSTV857-27 features differential feedback clock outputs and inputs. This allows the CY2SSTV857-27 to be used as a zero-delay buffer. When used as a zero-delay buffer in nested clock trees, the CY2SSTV857-27 locks onto the input reference and translates with near-zero delay to low-skew outputs.
Block Diagram
Pin Configuration
3 2
PD # AVDD
37 16
T est and P ow erdo w n L o gic
5 6 10 9 20 19 22 23 46 47 44 43
Y0 Y0# Y1 Y1# Y2 Y2# Y3 Y3# Y4 Y4# Y5 Y5# Y6 Y6# Y7 Y7# Y8 Y8# Y9 Y9# FBO UT FBO U T #
VSS Y0# Y0 VDDQ Y1 Y1# VSS VSS Y2# Y2 VDDQ VDDQ C LK C LK # VDDQ AVDD AVSS VSS Y3# Y3 VDDQ Y4 Y4# VSS
1 2 3 4 5 6
48 47 46 45 44 43
VSS Y5# Y5 VDDQ Y6 Y6# VSS VSS Y7# Y7 VDDQ PD# F B IN F B IN # VDDQ FBOUT# FBOUT VSS Y8# Y8 VDDQ Y9 Y9# VSS
CY2SSTV857-27
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
C LK C LK# F B IN F B IN #
13 14
39 40
PLL
36 35
29 30 27 26
32 33
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 8
www.SpectraLinear.com
CY2SSTV857-27
Pin Description
Pin Number 13, 14 35 36 3, 5, 10, 20, 22 2, 6, 9, 19, 23 27, 29, 39, 44, 46 26, 30, 40, 43, 47 32 Pin Name CLK, CLK# FBIN# FBIN Y(0:4) Y#(0:4) Y(9:5) Y#(9:5) FBOUT I/O[1] I I I O O O O O Pin Description Differential Clock Input. Electrical Characteristics LV Differential Input
Feedback Clock Input. Connect to FBOUT# for accessing the Differential Input PLL. Feedback Clock Input. Connect to FBOUT for accessing the PLL. Clock Outputs Clock Outputs Clock Outputs Clock Outputs Feedback Clock Output. Connect to FBIN for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Feedback Clock Output. Connect to FBIN# for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Power Down# Input. When PD# is set HIGH, all Q and Q# outputs are enabled and switch at the same frequency as CLK. When set LOW, all Q and Q# outputs are disabled Hi-Z and the PLL is powered down. 2.5V Power Supply for Output Clock Buffers. 2.5V Power Supply for PLL. When VDDA is at GND, PLL is bypassed and CLK is buffered directly to the device outputs. During disable (PD# = 0), the PLL is powered down. Common Ground Analog Ground 2.5V Nominal 2.5V Nominal Differential Outputs Differential Outputs Differential Outputs
33
FBOUT#
O
37
PD#
I
4, 11,12,15, 21, 28, 34, 38, 45 16
VDDQ AVDD
1, 7, 8, 18, 24, 25, 31, 41, 42, 48 17
VSS AVSS
0.0V Ground 0.0V Analog Ground When VDDA is strapped LOW, the PLL is turned off and bypassed for test purposes.
Zero-delay Buffer
When used as a zero-delay buffer the CY2SSTV857-27 will likely be in a nested clock tree application. For these applications the CY2SSTV857-27 offers a differential clock input pair as a PLL reference. The CY2SSTV857-27 then can lock onto the reference and translate with near-zero delay to low-skew outputs. For normal operation, the external feedback input, FBIN, is connected to the feedback output, FBOUT. By connecting the feedback output to the feedback input the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near-zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs.
Power Management
Output enable/disable control of the CY2SSTV857-27 allows the user to implement power management schemes into the design. Outputs are three-stated/disabled when PD# is asserted low (see Table 1).
Note: 1. A bypass capacitor (0.1 F) should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins, their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Rev 1.0, November 21, 2006
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CY2SSTV857-27
Table 1. Function Table Inputs AVDD GND GND X X 2.5V 2.5V 2.5V PD# H H L L H H H CLK L H L H L H < 10 MHz CLK# H L H L H L < 10 MHz Y L H Z Z L H Hi-Z Y# H L Z Z H L Hi-Z Outputs FBOUT L H Z Z L H Hi-Z FBOUT# H L Z Z H L HI-Z PLL BYPASSED/OFF BYPASSED/OFF Off OFF On On Off
CLKIN
FBIN t(phase error)
FBOUT
Yx tsk(o)
Yx
Yx tsk(o)
Figure 1. Phase Error and Skew Waveforms
CLKIN
Yx or FBIN
tpd
Figure 2. Propagation Delay Time tPLH, tPHL
Rev 1.0, November 21, 2006
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CY2SSTV857-27
Yx
tC(n) tC(n+1)
Figure 3. Cycle-to-cycle Jitter
= 2.5" DDR _SDRAM represents a capacitive load CLK 120 Ohm CLK# VTR FBIN 120 Ohm FBIN# FBOUT FBOUT# 0.3" VCP DDR SDRAM 120 Ohm PLL = 0.6" (Split to Terminator)
DDR SDRAM
Output load capacitance for 2 DDR-SDRAM Loads: 5 pF< CL< 8 pF
Figure 4. Clock Structure # 1
= 2.5" DDR-SDRAM represents a capacitive load CLK 120 Ohm CLK# PLL
= 0.6" (Split to Terminator)
DDR-SDRAM
DDR-SDRAM Stack
DDR-SDRAM
VTR 120 Ohm FBIN 120 Ohm
DDR-SDRAM
VCP
FBIN#
FBOUT
DDR-SDRAM
DDR-SDRAM Stack
FBOUT# 0.3"
Output load capacitancce for 4 DDR-SDRAM Loads: 10 pF < CL < 16 pF
Figure 5. Clock Structure # 1
Rev 1.0, November 21, 2006
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CY2SSTV857-27
VDDQ VDDQ
V D D Q /2 14 pF
OUT
60 O hm
VTR RT = 120 O hm
OUT#
60 O hm VCP
14 pF V D D Q /2
R e c e iv e r
Figure 6. Differential Signal Using Direct Termination Resistor
Rev 1.0, November 21, 2006
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CY2SSTV857-27
Absolute Maximum Conditions[2]
Input Voltage Relative to VSS:............................... VSS - 0.3V Input Voltage Relative to VDDQ or AVDD: ........... VDDQ + 0.3V Storage Temperature: ................................ -65C to + 150C Operating Temperature:.................................... 0C to +85C Maximum Power Supply: ................................................ 3.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDDQ.
DC Electrical Specifications
Parameter VDDQ VIL VIH VID VIX IIN IOL IOH VOL VOH VOUT VOC IOZ IDDQ IDD IDDS Cin Supply Voltage Input Low Voltage Input High Voltage
Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDDQ). (AVDD = VDDQ = 2.5v 5%, TA = 0C to +85C) [3] Condition Operating PD# 0.7 x VDDQ CLK, FBIN CLK, FBIN VIN = 0V or VIN = VDDQ VDDQ = 2.375V, VOUT = 1.2V VDDQ = 2.375V, VOUT = 1V VDDQ= 2.375V, IOL = 12 mA VDDQ = 2.375V, IOH = -12 mA 1.7 1.1 (VDDQ/2) - 0.2 VO = GND or VO = VDDQ All VDDQ, FO = 170 MHz VDDA only PD# = 0 and CLK/CLK# < 10 MHz -10 235 9 VDDQ/2 VDDQ - 0.4 (VDDQ/2) + 0.2 10 300 12 100 4 0.36 (VDDQ/2) - 0.2 -10 26 -28 35 -32 0.6 VDDQ/2 VDDQ + 0.3 (VDDQ/2) + 0.2 10 Min. 2.38 Typ. 2.5 Max. 2.63 0.3 x VDDQ Unit V V V V V A mA mA V V V V A mA mA A pF
Description
Differential Input Voltage[4] Differential Input Crossing Voltage[5] Input Current [CLK, FBIN, PD#] Output Low Current Output High Current Output Low Voltage Output High Voltage Output Voltage Swing[6] Output Crossing Voltage[7] High-Impedance Output Current Dynamic Supply Current[8] PLL Supply Current Standby Supply Current Input Pin Capacitance
AC Electrical Specifications (AVDD = VDDQ = 2.5V5%, TA = 0C to +85C) [9, 10]
Parameter fCLK tDC tLOCK DTYC tsl(o) Description Operating Clock Frequency Input Clock Duty Cycle Maximum PLL lock Time Duty Cycle[11] 60 MHz to 100 MHz 101 MHz to 170 MHz Output Clocks Slew Rate 20%-80% of VOD 49.5 49 1 50 Condition AVDD, VDDQ = 2.5V 0.2V Min. 60 40 Typ. Max. 200 60 100 50.5 51 2 Unit MHz % s % % V/ns
Notes: 2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Unused inputs must be held HIGH or LOW to prevent them from floating. 4. Differential input signal voltage specifies the differential voltage VTR-VCPI required for switching, where VTR is the true input level and VCP is the complementary input level. See Figure 6. 5. Differential cross-point input voltage is expected to track VDDQ and is the voltage at which the differential signal must be crossing. 6. For load conditions see Figure 6. 7. The value of VOC is expected to be (VTR + VCP)/2. In case of each clock directly terminated by a 120 resistor. See Figure 6. 8. All outputs switching load with 14 pF in 60 environment. See Figure 6. 9. Parameters are guaranteed by design and characterization. Not 100% tested in production. 10. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30kHz and 50 kHz with a down spread or -0.5%. 11. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = tWHC/tC, where the cycle time(tC) decreases as the frequency goes up.
Rev 1.0, November 21, 2006
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CY2SSTV857-27
AC Electrical Specifications (AVDD = VDDQ = 2.5V5%, TA = 0C to +85C)(continued)[9, 10]
Parameter tPZL, tPZH tPLZ, tPHZ tCCJ tjit(h-per) tPLH(tPD) tPHL(tPD) tSK(O) tPHASE Description Output Enable Time[12] (all outputs) Output Disable Time[12] (all outputs) Cycle to Cycle Jitter [10] Half-period jitter
[10, 13]
Condition
Min.
Typ. 3 3
Max. 25 8 75 100 7.5 7.5 100 50
Unit ns ns ps ps ns ns ps ps
f > 66 MHz f > 66 MHz Test Mode only
-75 -100 1.5 1.5 -50
- - 3.5 3.5
Low-to-High Propagation Delay, CLK to Y High-to-Low Propagation Delay, CLK to Y Any Output to Any Output Skew[14] Phase Error[14]
Notes: 12. Refers to transition of non-inverting output. 13. Period jitter and half-period jitter specifications are separate specifications that must be met independently of each other. 14. All differential input and output terminals are terminated with 120 /16 pF, as shown in Figure 5.
Rev 1.0, November 21, 2006
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CY2SSTV857-27
Ordering Information
Part Number CY2SSTV857ZC-27 CY2SSTV857ZC-27T CY2SSTV857ZI-27 CY2SSTV857ZI-27T 48-pin TSSOP 48-pin TSSOP-Tape and Reel 48-pin TSSOP 48-pin TSSOP-Tape and Reel Package Type Product Flow Commercial, 0 to 70 C Commercial, 0 to 70 C Industrial, -40 to +85C Industrial, -40 to +85C
Package Drawing and Dimension
48-lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z48
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 21, 2006
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