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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
June 2007
FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
Features
FastvCoreTM nonlinear control for fast transient and to minimizes the number of output caps required Selectable 2- or 3-phase operation at up to 1MHz per phase 7.7mV worst-case differential sensing error over temperature Active current balancing between output phases Power Good and Crowbar blanking supports on-the-fly VID code changes 0.5V to 1.6V output Usable for Intel(R) VR10 and VR11 designs Selectable VR10 extended (7-bit) and VR11 (8-bit) VID tables Programmable soft-start ramp Programmable short-circuit protection and latch-off delay
Description
The FAN50FC3 device is a multi-phase buck switching regulator controller optimized to convert a 12V input supply to the processor core voltage required by highperformance Intel(R) processors. It has an internal, 8-bit DAC that converts a digital voltage identification (VID) code sent from the processor, to set the output voltage between 0.5V and 1.6V in 6.25mV steps. It outputs PWM signals to external MOSFET drivers that drive the switching power MOSFETs. The switching frequency of the design is programmable by a single resistor value and the number of phases can be programmed to support 2- or 3-phase applications. The FAN50FC3 also includes programmable no-load offset and droop functions to adjust the output voltage as a function of the load current, as required by the Intel(R) specifications. The FAN50FC3 also provides an accurate and reliable short-circuit protection function with an adjustable over-current set point. FastvCoreTM technology greatly improves the fast transient response required by today's high-performance processors. This allows fewer output capacitors to be used in the application. The FAN50FC3 is specified over the commercial temperature range of 0C to +85C and is available in a 32-lead MLP package.
Applications
Desktop PC/Server processor power supplies for existing and next-generation Intel(R) processors VRM modules
Related Applications Notes
AN-6052 -- Instructions for the Multi-Phase VR11 (R) MathCad Design Tool
Ordering Information
Part Number
FAN50FC3MPX
Pb-Free
Yes
Operating Temperature Range
0 to 85C
Package
32-Lead, Molded Leadless Package (MLP)
Packing Method
Tape and Reel
(c) 2007 Fairchild Semiconductor Corporation FAN50FC3 Rev. 1.0.0
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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
Block Diagram
VCC RT RAMPADJ
UVLO SHUT DOWN & BIAS GND
OSCILLATOR
OD
SET EN
RESET Threshold EN DAC + OVP CSREF CURRENT BALANCE CIRCUIT RESET
PWM1
PWM2
RESET 2/3 PHASE LOGIC
PWM3
DAC - UVP
CROWBAR
CURR ENT LIMIT
PWRGD
DELAY SW1 SW2 SW3
VOSADJ
ILIMIT
DELAY
CURRENT LIMIT CIRCUIT
CSCOMP CSREF CSSUM
Z
+
+
COMP PRECISION REFERENCE
-
FBRTN
START UP CONTROL BOOT CONTROL
FB
+
VID DAC VIDSEL
DAC BUFF
SS VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
Figure 1. Block Diagram
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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
Pin Assignments
PWM1 PWM2 PWM3 SW1 SW2 18 SW3 17 VID7 24 VCC 23
22
21
20
19
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VIDSEL
25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8
16
VOSADJ OD# GND CSCOMP CSSUM CSREF RAMPADJ RT
Exposed Paddle on Bottom of Package
15 14 13 12 11 10 9
FAN50FC3
PWRGD
FBRTN
EN
FB
COMP
SS
DELAY
Figure 2. Pin Assignments
Pin Definitions
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13
Name
EN PWRGD FBRTN FB COMP SS DELAY ILIMIT RT RAMPADJ CSREF CSSUM CSCOMP
Description
Power Supply Enable Input. Analog comparator input with hysteresis. If the input voltage is higher than the internal threshold, the controller is enabled; if lower, the controller is disabled. Power Good Output. Open-drain output that pulls to GND when the output voltage is outside the proper operating range. Feedback Return. VID DAC and error amplifier reference for remote sensing output voltage. Feedback Input. Error amplifier input for remote sensing output voltage. A positive internal current source is connected to this pin to allow the output voltage to be offset lower than the DAC voltage. Error Amplifier Output. For loop compensation. Soft-Start Input. An external capacitor connected between this pin and GND sets the soft-start ramp-up time. Delay Timer Input. An external capacitor connected between this pin and GND sets the over-current latch-off delay time, BOOT voltage hold time, EN delay time, and PWRGD delay time. Current Limit Set. An external resistor from this pin to GND sets the current limit threshold of the converter. Frequency Set Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device. PWM Ramp Set Input. An external resistor connected between this pin and the converter input voltage sets the internal PWM ramp. Current-Sense Amplifier Positive Input. The voltage on this pin is used as the reference for the current-sense amplifier. The Power Good and Crowbar functions are internally connected to this pin. Current-Sense Amplifier Negative Input. Current-Sense Amplifier Compensation Output.
(c) 2007 Fairchild Semiconductor Corporation FAN50FC3 Rev. 1.0.0
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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
Pin Definitions (Continued)
14 15 16 17 to 19 GND OD# VOSADJ SW3 to SW1 PWM3 to PWM1 VCC VID7 to VID0 VIDSEL Exposed Paddle Ground. Biasing and logic output signals of the device are referenced to this ground. Output Disable. This pin is actively pulled LOW when the EN input is low or when VCC is below the UVLO threshold, to disable the external MOSFET drivers. FastvCoreTM VOS Adjustment Input. This signal is used as a control input for the FastvCoreTM circuit. Switching Node Current Balance Inputs. Sense the switching side of the inductor and used to measure the current level in each phase. The SW pins of unused phases should be left open. PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the FAN5109. Connecting the PWM3 output to VCC disables that phase, allowing the FAN50FC3 to operate as a 2-phase controller. Supply Voltage. Voltage Identification Code Inputs. These digital inputs are connected to the internal DAC and used to program the output voltage. These pins have 1A internal pull-down; if they are left open, the input state is decoded as logic LOW. VID Table Select Input. A logic LOW selects the extended VR10 DAC table and a logic HIGH selects the VR11 DAC table. This pin has a 1A internal pull-down; if left open, the input state is decoded as logic LOW. Internally Connected to Die Ground. May be connected to ground or left floating. Connect to ground for lowest package thermal resistance.
20 to 22 23 24 to 31
32
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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
Supply Voltage, VCC FBRTN RAMPADJ, PWM3 SW1 - SW3
Parameter
Min.
-0.3 -0.3 -0.3 -10 -0.3 0 -65
Max.
+15 +0.3 VCC +0.3 +25 +5.5 +125 +150 300 260 45
Unit
V V V V V C C C C C/W
All Other Inputs and Outputs TJ TSTG TLS TLI JA Operating Junction Temperature Storage Temperature Lead Soldering Temperature (10 Seconds) Lead Infrared Temperature (15 Seconds) Thermal Resistance, Junction-to-Ambient
(1)
Note: 1. Junction-to-ambient thermal resistance, JA, is a strong function of PCB material, board thickness, thickness and number of copper planes, number of via used, diameter of via used, available copper surface, and attached heat sink characteristics.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC TA
Parameter
Supply Voltage Ambient Temperature
Conditions
VCC to GND
Min.
9.6 0
Typ.
12.0
Max.
14.4 +85
Unit
V C
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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
Electrical Characteristics
VCC = 12V, FBRTN = GND, and TA = +25C. The * denotes specifications which apply over the full operating temperature range.
Symbol
Error Amplifier VCOMP VFB
Parameter
Output Voltage Range Accuracy
Conditions
Min. Typ. Max. Unit
* 0.5 4.0 V
Relative to nominal DAC output, referenced to FBRTN. (see Figure 3) VRM11 VID Range: 1.00625V to 1.60000V During Start-up CSREF-CSCOMP= 80mV (see Figure 5) VCC =10V to 14V
* *
-7.7
+7.7 mV V mV LSB % 16.5 95 A A A MHz V/s +250 mV 2 ms 0.4 3.3 0.4 3.3 -1 V V V V A ns ns
VFB(BOOT) Accuracy Load Line Droop Accuracy Differential Non-Linearity VFB IFB IFBRTN IO(ERR) Line Regulation Input Bias Current FBRTN Current Output Current Slew Rate VCSCOMP CSCOMP Voltage Range tBOOT VIL(VID) VIH(VID) VIL(VID) VIH(VID) IIN(VID) tDLY(VID) tDLY(CPU) Oscillator fOSC fPHASE VRT Frequency Frequency Variation Output Voltage BOOT Voltage Hold Time Input Low Voltage Input High Voltage Select VR10 Table Select VR11 Table Input Current, VID Low VID Transition Delay Time No CPU Detection Turn-off Delay Time VID Inputs and VIDSEL
1.092 1.1001.108 -80 0.05 -82 +1 15 70 500 20 25
* -78 * -1
* 13.5 * FB forced to VOUT -3% COMP = FB
(3)
GBW(ERR) Gain Bandwidth Product
COMP = FB(3) Relative to CSREF CDELAY = 10nF VIDx, VIDSEL VIDx, VIDSEL VIDSEL Logic LOW VIDSEL Logic HIGH VID code change to FB change(3) VID code change to off state to PWM going LOW(3) 0.8 * 200 * 200 * * 0.8 * -250
* 0.25 TA = 25C, RT= 200K, 3-phase RT =100k to GND * 1.9 2.0
4.50 MHz 2.1 +50 50 V mV A
-20% 400 20% kHz
VRAMPADJ RAMPADJ Output Voltage IRAMPADJ RAMPADJ Input Current Range Offset Voltage Input Bias Current (for CSSUM)
VRAMPADJ = VDAC + 2k * (VCC - VDAC) / (RRAMPADJ * -50 + 2K) 1
Current-Sense Amplifier VOS(CSA) IBIAS(CSSUM) CSSUM - CSREF (see Figure 4) * -1.0 * -50 Current drawn by CSREF Pin CSSUM = CSCOMP CCSCOMP = 10pF
(3) (3)
+1.0 mV +50 +3 10 10 nA A MHz V/s 3.2 V
IBIAS(CSREF) Input Current (for CSREF) GBW(CSA) Gain Bandwidth Product Slew Rate VCSACM Input Common-Mode Range
*
-3
CSSUM and CSREF
*
0
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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
Electrical Characteristics (Continued)
VCC = 12V, FBRTN = GND, and TA = +25C. The * denotes specifications which apply over the full operating temperature range.
Symbol
Parameter
Output Voltage Range
Conditions
Min. Typ. Max.
* 0.05 1 * -600 +200 50 3.3 65 5.0 +5 1.7 12 * 60 120 10 * * 12 1.6 12 15 1.7 15 850 100 1 18 1.8 18 900 130 140 * 100 1.8 3.20
Unit
V mA mV k A % V A A mV mV/A A A V A mV mV A ms
Current-Sense Amplifier (Continued) ICSCOMP VSW(x)CM RSW(x) ISW(x) ISW(x) VILIMIT IILIMIT VCL Delay Timer IDELAY IDELAY(CL) VDELAY(TH) Soft-Start I(SS) Enable Input VTH(EN) VHYS(EN) IIN(EN) tDELAY(EN) #OD Output VOL(ODB) VOH(ODB) VPWRGD(UV) VPWRGD(OV) VOL(PWRGD) t1PG(DLY) t2PG(DLY) t3PG(DLY) Output Voltage LOW Output Voltage HIGH Under-Voltage Threshold Over-Voltage Threshold Output Low Voltage Power Good Delay Time 1 Power Good Delay Time 2 Power Good Delay Time 3
(3)
Output Current Common Mode Range(3) Input Resistance Input Current Input Current Matching Output Voltage Output Current Maximum Output Current Current Limit Threshold Voltage Current Limit Setting Ratio Normal Mode Output Current Output Current in Current Limit Threshold Voltage Output Current Threshold Voltage Threshold Hysteresis Enable Input Current Turn-On Delay Start-up sequence, EN>950mV, CDELAY = 10nF IPWM(SINK) = 400A IPWM(SOURCE) = 400A Relative to Nominal DAC Output Relative to Nominal DAC Output IPWRGD(SINK) = -4mA Start-up Sequence; CDELAY = 10nF; Power Good Blanking Time * * 4 During Start-up VCSREF - VCSCOMP, RILIMT = 143k VCL / IILIMT SW(x) = 0V SW(x) = 0V SW(x) = 0V RILIMT = 143k RILIMT = 143k
Current Balance Circuit * * * * 35 1.6 -5 1.6
Current Limit Comparator
* 3.00 3.75 4.50
*
* 800 * 80
2
160 5
400
mV V mV mV mV ms s ns
Power-Good Comparator * -300 -250 -200 * 100 * * 150 200 2 250 200 200 300
VID Code Changing; CDELAY = 10nF; * 100 Power Good Blanking Time VID Code Static; CDELAY = 10nF; Power Good Blanking Time * 100
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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
Electrical Characteristics (Continued)
VCC = 12V, FBRTN = GND, and TA = +25C. The * denotes specifications which apply over the full operating temperature range.
Symbol
VCROWBAR VCR_RST t1CROWBAR
Parameter
Crowbar Trip Point Crowbar Reset Point Crowbar Delay Time 1
Conditions
Relative to Nominal DAC Output Relative to FBRTN * *
Min. Typ. Max. Unit
100 250 100 150 300 250 200 350 mV mV s
Power-Good Comparator (Continued)
VID Code Change Over-Voltage to PWM Going LOW * Crowbar Blanking Time VID Code Static Over-Voltage to PWM going LOW * Crowbar Blanking Time IPWM(SINK) = 400A IPWM(SOURCE) = 400A * *
t2CROWBAR PWM Outputs VOL(VRTM) VOH(VRTM) VDIS Input Supply IDC VUVLO VUVLO_HYS
Crowbar Delay Time 2
400
ns
Output Voltage Low Output Voltage High Phase Disable Voltage
160 4 5
400
mV V V
Applicable to PWM3 pins only. Connect this pin to VCC to disable * VCC -.1 the phase.(4) EN = Logic HIGH VCC Rising * * * 6.5 0.7 8 6.9 0.9 12 7.3 1.1
DC Supply Current UVLO Threshold UVLO Hysteresis
mA V V
Notes: 2. Limits at operating temperature extremes are guaranteed by design, characterization, and statistical quality control. 3. AC specifications are guaranteed by design and characterization; not production tested. 4. To operate the FAN50FC3 with fewer than three phases, PWM3 should be connected to VCC to disable this phase. See the Theory of Operation section for details.
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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
Test Diagrams
12 V
VCC VIDSEL
VID0 VID1 VID2 VID3 VID4 VID5 VID6 8
12 V 100nF
8 Bit Code
23
VCC
1.25 V 20k
EN CSCOMP 100nF CSSUM CSREF
13
CSCOMP
39k
12 CSSUM
CSA
1k
+ 11 CSREF
FB 1k COMP ILIMIT 250k 10nF 10nF SS DELAY GND FBRTN
VID7 SW1 SW2 SW3
+
V -
1V
14 GND
Figure 3. Closed-Loop Output Voltage Accuracy
Figure 4. Current-Sense Amplifier VOS
Rt as a function of Oscillator Frequency
12 V
23 VCC
62 41 4 30 8
1000
1000
8
5
COMP
10k
Rt (k)
4
FB
100
dV
+ +
13 CSCOMP
V
11 CSREF
V -
V
14 GND
10 0 2000 3000 4000 5000 Oscillator Frequency (kHz)
Figure 5. Droop Voltage Accuracy
Figure 6. RT Required to Set Oscillator Frequency
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20 1 17 0 14 7 12 9 11 5 10 4 94 86 79 72 67 62 58 54 51 48 45 43 40 38
24
3
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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
Table 1.
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
Output Voltage Programming Codes (extended VR10); 0 = logic LOW; 1 = logic HIGH.
VID3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VID2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VID1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1
10 of 21
VID0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1
VID5 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
VID6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
VOUT (V) OFF OFF OFF OFF 1.09375 1.10000 1.10625 1.11250 1.11875 1.12500 1.13125 1.13750 1.14375 1.15000 1.15625 1.16250 1.16875 1.17500 1.18125 1.18750 1.19375 1.20000 1.20625 1.21250 1.21875 1.22500 1.23125 1.23750 1.24375 1.25000 1.25625 1.26250 1.26875 1.27500 1.28125 1.28750 1.29375 1.30000 1.30625 1.31250 1.31875 1.32500 1.33125 1.33750 1.34375 1.35000 1.35625 1.36250 1.36875 1.37500 1.38125 1.38750 1.39375 1.40000 1.40625 1.41250 1.41875 1.42500 1.43125 1.43750 1.44375 1.45000 1.45625 1.46250 1.46875 1.47500
(c) 2007 Fairchild Semiconductor Corporation FAN50FC3 Rev. 1.0.0
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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VID3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VID2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VID1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
VOUT (V) 1.48125 1.48750 1.49375 1.50000 1.50625 1.51250 1.51875 1.52500 1.53125 1.53750 1.54375 1.55000 1.55625 1.56250 1.56875 1.57500 1.58125 1.58750 1.59375 1.60000 0.83125 0.83750 0.84375 0.85000 0.85625 0.86250 0.86875 0.87500 0.88125 0.88750 0.89375 0.90000 0.90625 0.91250 0.91875 0.92500 0.93125 0.93750 0.94375 0.95000 0.95625 0.96250 0.96875 0.97500 0.98125 0.98750 0.99375 1.00000 1.00625 1.01250 1.01875 1.02500 1.03125 1.03750 1.04375 1.05000 1.05625 1.06250 1.06875 1.07500 1.08125 1.08750
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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
Table 2.
HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
Output Voltage Programming Codes (8 Bit) 0 = logic LOW; 1 = logic HIGH. (MSB: VID7, LSB: VID0; 11110001b = F1h)
Tolerance HEX 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Voltage 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 0.82500 0.81875 Tolerance +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) +-15mV LL (0 - 110A) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) Monotonic DAC (6.25 mV) HEX 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Voltage 0.81250 0.80625 0.8 0.79375 0.7875 0.78125 0.775 0.76875 0.7625 0.75625 0.75 0.74375 0.7375 0.73125 0.725 0.71875 0.7125 0.70625 0.7 0.69375 0.6875 0.68125 0.675 0.66875 0.6625 0.65625 0.65 0.64375 0.6375 0.63125 0.625 0.61875 0.6125 0.60625 0.6 0.59375 0.5875 0.58125 0.575 0.56875 0.5625 0.55625 0.55 0.54375 0.5375 0.53125 0.525 0.51875 0.5125 0.50625 0.5 0.49375 0.4875 0.48125 0.475 0.46875 0.4625 0.45625 0.45 0.44375 0.4375 0.43125 0.425 0.41875 Tolerance Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Monotonic Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care HEX C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Voltage 0.4125 0.40625 0.40000 0.39375 0.38750 0.38125 0.37500 0.36875 0.36250 0.35625 0.35000 0.34375 0.33750 0.33125 0.32500 0.31875 0.31250 0.30625 0.30000 0.29375 0.28750 0.28125 0.27500 0.26875 0.26250 0.25625 0.25000 0.24375 0.23750 0.23125 0.22500 0.21875 0.21250 0.20625 0.20000 0.19375 0.18750 0.18125 0.17500 0.16875 0.16250 0.15625 0.15000 0.14375 0.13750 0.13125 0.12500 0.11875 0.11250 0.10625 0.10000 0.09375 0.08750 0.08125 0.07500 0.06875 0.06250 0.05625 0.05000 0.04375 0.03750 0.03125 OFF OFF Tolerance Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care Don't Care
Voltage OFF OFF 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875
+-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 +-15mV LL (0 -
(c) 2007 Fairchild Semiconductor Corporation FAN50FC3 Rev. 1.0.0
www.fairchildsemi.com 12 of 21
VTT Optional R20 0 C23 0.1uF S1 R24 680 R25 680 R27 680 R28 680 R30 680 R32 680 R34 680 R35 680
R20A
VIN
R9 10K
R10 2.2
Q1 BCW33
MMSZ4678 C20 4.7uF DIP20 VID0 1nF(X7R) PSI# C37 1uF/16V EN R22 1K
40 39 38 37 36 35 34 33 32
D1 VCC C175 VID1 VID2 VID3 VID4 VID5 VID6 VID7
D5 MMSD4148 SOD-123 VTTA
20 19 18 17 16 15 14 13 12 11 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 10 R52 Optional R68 Optional C25 0.1uF
PSI# VID0 VID1 VID2 VID3 VID4 VID5 VID6
1 2 3 4 5 6 7 8 9 10
Typical Applications
VIN R56
R15 3K
EN_B
R137 Optional C27 1nF 1 EN PWRGD FBRTN FB COMP SS DELAY VCORE VRHOT TTSENSE FAN50FC4 U10 2 3 PWM1 PWM2 PWM3 PWM4 SW1 SW2 SW3 SW4 ODB2 VOSADJ
VID7 VCC 31
VSNS_B
ILIMIT
RT
RAMPADJ
LLSET
CSREF
CSSUM
CSCOMP
GND
IOUT
ODB1
11
12
13
14
15
16
18
19
17
20
FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
(c) 2007 Fairchild Semiconductor Corporation FAN50FC3 Rev. 1.0.0
R59 Optional R69 Optional VIN R129 Optional PWRGD R21 680 GREEN D7 PWM1 30 29 28 27 26 25 24 23 22 21 ODB2 R169 Optional ODB1 R44 0 VIN TTSNS R138 0 R38 110K R39 182K VCC CSCOMP R153 0 RT4 Optional THERMISTOR 5% C29 6.8nF IOUT R154 0 R184 Optional C174 330nF IMON CSREF R40 200K C33 1800pF C35 1500pF R43 0 R46 53.6K RT2 100K THERMISTOR 5% R45 0 CSREFA R53 60.4K ODB1 R50 102K R55 102K R57 102K R58 102K R173 0 R47 R48 R49 R51 10 10 10 10 ODB2 PWM2 PWM3 PWM4 PWM1 PWM2 PWM3 PWM4 SW1 SW2 SW3 SW4 C19 Optional R13 C22 C21 R19 7 SS 8 9 10 C24 18nF C145 18nF C26 18nF COMP DELAY 30.1K 470pF 6 5 Optional R12 0 VR 1.21K 33pF 4 ILIMIT VRHOT D16 RED R128 3K
VR_VSSee
R1A Optional
R1
10
FBRTN
VR_VSSdie
R5
Optional
VR_VSSse
R2
0
Figure 7. Typical Three-Phase Design, Controller
Note: Contact a Fairchild representative for the latest VR11 reference designs.
13 of 21
VR_VCCse
R3
0
R11
VR_VCCdie
R6
Optional
VCORE
VCORE
R4
10
VR_VCCee
R2A Optional
GND
AGND
R7
0
R8
0
NOTES : 1. Optional parts are not populated unless otherwise specified.
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VIN
VIN
D3
Q5 FDD8780 D4
C100 22uF/16V Q9 FDD8780
C101 22uF/16V
C102 0.1uF
C16 22uF/16V Q9B FDD8780
C17 22uF/16V
C18 0.1uF
MMSD4148
Q5B FDD8780
SOD123
MMSD4148
SOD123
U2 4 VCC R74 10K SW2 SW2 L2 6 PGND C14 ODB2 0.1uF C6 1000pf FAN5109
9
4 HDRV SW1 SW1 L1 TP_L1 C13 4.7uF VCORE R36 10 OD Q10 FDD8796 C15 1000pf + BOOT CSREFA 3 1 R63 2.2 Q8 FDD8796 SW 7
VCC
HDRV
8
R70 10K U3 8
C2
4.7uF/16V 0.6uF/27A
R54 2.2
TP_L2
9
9
9
FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
(c) 2007 Fairchild Semiconductor Corporation FAN50FC3 Rev. 1.0.0
300nH/30A
R67 10 VCORE C4 R29 2.2 Q7 FDD8796 + C65 560uF PWM2 R75 10K PWM LDRV C67 560uF C69 560uF 2 5 + + R17 2.2 Q3 FDD8796 CSREFA 0.1uF
6
PGND
SW
7
ODB1
3
OD
BOOT
1
PWM1 R71 10K
2
PWM
LDRV
5
Typical Applications (Continued)
FAN5109
C75 560uF
+
C76 560uF
+
C77 560uF
VIN 1 2 3 4 COM COM COM COM +12V C72 1200uF/16V + + C73 1200uF/16V +12V +12V +12V +12V 8 7 6 5 C74 1200uF/16V +
J3
D2
Q4 FDD8780
C103 22uF/16V
C104 22uF/16V
C105 0.1uF
VIN
MOLEX_8B
MMSD4148
SOD123
Q4B FDD8780
U4
R72 10K GND
4 SW3 SW3 L3 TP_L3
VCC C30 22uF/6.3V VCORE R33 10 CSREFA C31 22uF/6.3V C32 22uF/6.3V C34 22uF/6.3V C36 22uF/6.3V
HDRV
8
C1
4.7uF/16V 0.6uH/27A
R26 2.2 0.1uF + R73 10K C5 1000pf C64 560uF C66 560uF C68 560uF C70 560uF C51 22uF/6.3V C50 22uF/6.3V C49 22uF/6.3V + + + Q6 FDD8796 C48 22uF/6.3V C47 22uF/6.3V
C39 22uF/6.3V
C40 22uF/6.3V
C41 22uF/6.3V
C42 22uF/6.3V
C58 22uF/6.3V
C59 22uF/6.3V
C60 22uF/6.3V
C61 22uF/6.3V
C62 22uF/6.3V
C63 22uF/6.3V
C52 22uF/6.3V
C53 22uF/6.3V
C54 22uF/6.3V
Figure 8. Typical Three-Phase Design, Drivers
Note: Contact a Fairchild representative for the latest VR11 reference designs.
14 of 21
C3 R16 2.2 Q2 FDD8796
6
PGND
SW
7
ODB2
3
OD
BOOT
1
PWM3
2
PWM
LDRV
5
Inside Socket C46 22uF/6.3V
C43 22uF/6.3V
C44 22uF/6.3V
C45 22uF/6.3V
C81 22uF/6.3V
C82 22uF/6.3V
C83 22uF/6.3V
C84 22uF/6.3V
C85 22uF/6.3V
C86 22uF/6.3V
C56 22uF/6.3V
C57 22uF/6.3V
C38 22uF/6.3V
FAN5109
VIN
Bottom Side Socket Optional
C106 22uF/16V Q11B FDD8780 C107 22uF/16V C108 0.1uF
D6
Q11 FDD8780
C87 22uF/6.3V
C88 22uF/6.3V
C89 22uF/6.3V
C90 22uF/6.3V
C91 22uF/6.3V
C92 22uF/6.3V
C93 22uF/6.3V
C94 22uF/6.3V
C95 22uF/6.3V
C96 22uF/6.3V
MMSD4148
SOD123
U5
4 SW4 SW4 L4 TP_L4
VCC
HDRV
8
R76 10K
Outside Socket Optional
C7
4.7uF/16V 0.6uF/27A
R37 10 R42 2.2 Q13 FDD8796 C9 1000pf
6 Q12 FDD8796
PGND C8
SW
7
VCORE
VCORE CSREFA P3 1 VCORE P4 1 GND
ODB2 0.1uF
3
OD
BOOT
1
R18 2.2
PWM4 R77 10K
2
PWM
LDRV
5
FAN5109
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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
Theory of Operation
Note: The values shown in this section are for reference only. See the parametric tables for actual values. The FAN50FC3 is a fixed-frequency PWM control with multi-phase logic outputs for use in 2- and 3-phase synchronous buck CPU power supplies. It has an internal VID DAC designed to interface directly with 8-bit VRD/VRM 11 and 7-bit VRD/VRM 10.x compatible CPUs. Multiphase operation is required for the high currents and low voltages of today's microprocessors that can require up to 150A of current. The integrated features of the FAN50FC3 ensure a stable, high-performance topology for: Balanced currents and thermals between phases High-speed response at the lowest possible switching frequency and output decoupling capacitors Tight load line regulation and accuracy High current output by allowing up to 3-phase designs Reduced output ripple due to multiphase operation Good PC board layout noise immunity Easily settable and adjustable design parameters with simple component selection 2- to 3-phase operation allows optimizing designs for cost/performance and support a wide range of applications.
SS VCC (Core) VReady VIDs
TD1 TD2
the pin is tied to VIN, the pin voltage is above 3V and that phase is disabled and put in a tri-state mode. Otherwise, the internal 100A current source pulls PWM pin below the 3V threshold. After channel detection, the current source is removed. Shorting PWM3 to VCC configures the system into 2phase operation.
12V VIN VTT DELAY
1.0V Vboot =1.1V Vcore = VID Vcore = Vboot 0.85V DELAY Threshold UVLO Threshold
TD3
TD4
TD5
50s Invalid Valid
Figure 9. Start-Up Sequence Timing After detection time is complete, the PWM outputs not sensed as "pulled HIGH" function as normal PWM outputs. PWM outputs sensed as "pulled HIGH" are put into a high-impedance state. The PWM signals are logic-level outputs intended for driving external gate drivers, such as the FAN5109. Since each phase is monitored independently; operation approaching 100% duty cycle is possible. More than one output can be on at the same time to allow phase overlap.
Start-Up Sequence
The start-up sequence is shown in Figure 9. Once the EN and UVLO conditions are met, the DELAY pin goes through one cycle (TD1), after which, the internal oscillator starts. The first two clock cycles are used for phase detection. The soft-start ramp is then enabled (TD2), raising the output voltage up to the boot voltage of 1.1V. The boot hold time (TD3) allows the processor VID pins to settle to the programmed VID code. After TD3 timing is finished, the output soft starts, either up or down, to the final VID voltage (during TD4). TD5 is the time between the output reaching the VID voltage and the PWRGD being presented to the system.
Master Clock Frequency
The clock frequency is set with an external resistor connected from the RT pin to ground. The frequency-toresistor relationship is shown in the graph in Figure 6. To determine the frequency per phase, divide the clock by the number of enabled phases.
Output Current Sensing
The FAN50FC3 provides a dedicated current-sense amplifier (CSA) to monitor the output current for proper voltage positioning and for current limit detection (see Figure 1). It differentially senses the voltage drop across the DCR of the inductors to give the total average current being delivered to the load. This method is inherently more accurate than peak current detection or sampling the voltage across the low-side MOSFETs. The CSA implementation can be configured for the objectives of the system. It can use output inductor DCR sensing without a thermistor for lowest cost or output inductor DCR sensing with a thermistor for improved accuracy with tracking of inductor temperature.
Phase-Detection Sequence
During start-up, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the FAN50FC3 operates as a 3-phase PWM controller. For 2-phase operation, connect the PWM3 pin to VCC. The PWM logic, which is driven by the master oscillator, directs the phase sequencer and channel detectors. Channel detection is carried out during the first two clock cycles after the chip is enabled. During the detection period, PWM3 is connected to a 100A sinking current source and two internal voltage comparators check the pin voltage of PWM3 versus a threshold of 3V typical. If
(c) 2007 Fairchild Semiconductor Corporation FAN50FC3 Rev. 1.0.0
www.fairchildsemi.com 15 of 21
FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
To measure the differential voltage across the output inductors, the positive input of the CSA (CSREF pin) is connected, using equal value resistors, to the output capacitor side of the inductors. The negative input of the CSA (CSSUM pin) is connected, using equal value resistors, to the MOSFET side of the inductors. The CSA's output (CSCOMP) is a voltage equal to the voltage dropped across the inductors, times the gain of the CSA, and is inversely proportional to the output current. The gain of the CSA is set by connecting an external feedback resistor between the CSA's CSCOMP and CSSUM pins. A capacitor, connected across the resistor, is used to create a low-pass filter to remove high frequency switching effects and create a RC pole to cancel the zero created by the L/DCR of the inductor. The end result is that the voltage between the CSCOMP and CSREF pins is inversely proportional to the output current (CSCOMP goes negative relative to CSREF as current increases) and the CSA gain sets the ratio of the CSA output voltage change as a function of output current change. This difference in voltage is used by the current limit comparator and by the droop amplifier to create the output load line. The CSA is designed to have a low offset input voltage. The sensing gain is determined by external resistors, so it can be made extremely accurate.
a few hundred ohms can make a noticeable increase in current, so use small steps. The amplitude of the internal ramp is set by a resistor connected between the input voltage and the RAMPADJ pin. This method also implements the voltage feedforward function.
Output Voltage Differential Sensing
The FAN50FC3 uses differential sensing in conjunction with a high-accuracy DAC and a low-offset error amplifier to maintain a worst-case specification of 7.7mV differential sensing accuracy over its specified operating range. A high gain-bandwidth error amplifier is used for the voltage control loop. The voltage on the FB pin is compared to the DAC voltage to control the output voltage. The FB voltage is also effectively offset by the CSA output voltage for accurately positioning the output voltage as a function of current. The output of the error amplifier is the COMP pin, which is compared to the internal PWM ramps to create the PWM pulse widths. The negative input (FB) is tied to the output sense location with a resistor RB and is used for sensing and controlling the output voltage at this point. Additionally a current source is connected internally to the FB pin, which causes a fixed DC current to flow through RB. This current creates a fixed voltage drop (offset voltage) across RB. The offset voltage adds to the sensed output voltage, which causes the error amplifier to regulate the actual output voltage lower than the programmed VID voltage by this amount. The main loop compensation is incorporated into the feedback by an external network connected between FB and COMP.
Load Line Impedance Control
The FAN50FC3 has an internal "Droop Amp" that effectively subtracts the voltage applied between the CSCOMP and CSREF pins from the FB pin voltage of the error amplifier, allowing the output voltage to be varied independent of the DAC setting. A positive voltage on CSCOMP (relative to CSREF) increases the output voltage and a negative voltage decreases it. Since the voltage between the CSA's CSCOMP and CSREF pins is inversely proportional to the output, current causes the output voltage to decrease an amount directly proportional to the increase in output current creating a droop or load line. The ratio of output voltage decrease to output current increase is the effective Ro of the power supply and is set by the DC gain of the CSA.
Delay Timer
The delay times for the start-up timing sequence are set with a capacitor from the DELAY pin to ground, as stated in the Start-Up Sequence section. In UVLO or when EN is logic LOW, the DELAY pin is held at ground. Once the UVLO and EN are asserted, a 15A current flows out of the DELAY pin to charge CDLY. A comparator, with a threshold of 1.7V, monitors the DELAY pin voltage. The delay time is therefore set by the 15A charging the delay capacitor from 0V to 1.7V. This DELAY pin is used for multiple delay timings (TD1, TD3, and TD5) during start-up. DELAY is also used for timing the current-limit latch-off, as explained in the Current Limit section.
Current Control Mode & Thermal Balance
The FAN50FC3 has individual SW inputs for each phase. They are used to measure the voltage drop across the bottom FETs to determine the current in each phase. This information is combined with an internal ramp to create a current balancing feedback system. This gives good current balance accuracy that takes into account, not only the current, but also the thermal balance between the bottom FETs in each phase. External resistors RSW1 through RSW3 can be placed in series with individual SW inputs to create an intentional current imbalance, such as in cases where one phase may have better cooling and can support higher currents. It is best to have the ability to add these resistors in the initial design, to ensure that placeholders are provided in the layout. To increase the current in a phase, increase RSW for that phase. Adding a resistor of
(c) 2007 Fairchild Semiconductor Corporation FAN50FC3 Rev. 1.0.0
Soft-Start
The soft-start times for the output voltage are set with a capacitor from the SS pin to ground. After TD1 and the phase-detection cycle are complete, the SS time (TD2 in Figure 9) starts. The SS pin is disconnected from GND and the capacitor is charged up to the 1.1V boot voltage by the SS amplifier, which has a limited output current of 15A. The voltage at the FB pin follows the ramping voltage on the SS pin, limiting the inrush current during start-up. The soft-start time depends on the value of the boot voltage and CSS.
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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
Once the SS voltage is within 100mV of the boot voltage, the boot voltage delay time (TD3) is started. The end of the boot voltage delay time signals the beginning of the second soft-start time (TD4). The SS voltage changes from the boot voltage to the programmed VID DAC voltage (either higher or lower) using the SS amplifier with the limited output current of 15A. The voltage of the FB pin follows the ramping voltage of the SS pin, limiting the inrush current during the transition from the boot voltage to the final DAC voltage. The second soft-start time depends on the boot voltage, the programmed VID DAC voltage, and CSS. If either EN is taken LOW or VCC drops below UVLO, DELAY and SS are reset to ground to be ready for another soft-start cycle. Figure 10 shows typical start-up waveforms for the FAN50FC3.
The latch-off function can be reset by cycling the supply voltage to the FAN50FC3 or by toggling the EN pin LOW for a short time. To disable the short-circuit latchoff function, an external resistor can be placed in parallel with CDLY to prevent the DELAY capacitor from charging up to the 1.7V threshold. The addition of this resistor causes a slight increase in the delay times. During start-up, when the output voltage is below 200mV, a secondary current limit is active. This secondary current limit clamps the internal COMP voltage at the PWM comparators to 1.5V. Typical overcurrent latch-off waveforms are shown in Figure 11.
Vcore
VOD#
Vcore
VDELAY VPHASE1
VVRREADY VEN VDELAY
Figure 11. Over-Current Latch-off Waveforms
FastvCoreTM Operation
Figure 10. Start-up Waveforms FastvCoreTM improves the transient response for a load step-up change. Normally a controller has to wait till the next clock cycle if a load step-up happens during between PWM signals. With FastvCoreTM, the controller is able to immediately respond to the load step change, so that the inductor current increases to the new load current in a shorter period of time. FastvCoreTM is adjusted by connecting a resistor (RSETOS) between pin 16 (VOSADJ) and AGND to set the threshold where FastvCoreTM is initiated. RSETOS = (VOS+LLTOB) * RT * 10 where: RT = VOS = the frequency set resistor the target FastvCoreTM detection threshold that is the voltage difference between the output voltage starting point and the voltage when the FastvCoreTM starts to respond to a load stepup change EQ. 1
Current-Limit, Short-Circuit, and Latch-Off Protections
The FAN50FC3 compares a programmable current-limit set point to the voltage from the output of the current sense amplifier. The current-limit level is set with the resistor from the ILIMIT pin to ground. During operation, the voltage on ILIMIT is 1.7V. The current through the external resistor is internally scaled to give a current limit threshold of 10mV/A. If the voltage between CSREF and CSCOMP rises above the current-limit threshold, the internal current-limit amplifier controls the internal COMP voltage to maintain the average output current at the limit. After TD5 has completed, an over-current (OC) event starts a latch-off delay timer. The delay timer uses the DELAY pin timing capacitor. During current limit, the DELAY pin current is reduced to 3.75A. When the voltage on the delay pin reaches 1.7V, the controller shuts down and latches off. The current limit latch-off delay time is therefore set by the current of 3.75A charging the delay capacitor 1.7V. This delay is four times longer than the delay time during the start-up sequence. If there is a current limit during start-up, the FAN50FC3 goes through TD1 to TD5 in current limit, then starts the latch-off timer. Because the controller continues to operate during the latch-off delay time, if the OC is removed before the 1.7V threshold is reached, the controller returns to normal operation and the DELAY capacitor is reset to GND.
(c) 2007 Fairchild Semiconductor Corporation FAN50FC3 Rev. 1.0.0
LLTOB= the socket load line tolerance band FastvCoreTM design example: If: RT = 267kohm VOS = 35mV LLTOB = +/-19mV Then: RSETOS = (VOS+LLTOB) * RT * 10 = (35mV+19mV) * 267kohm * 10 = 144.2kohm
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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
Dynamic VID
The FAN50FC3 has the ability to dynamically change the VID inputs while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as VID on-the-fly (OTF). A VID OTF can occur under light or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative. When a VID input changes state, the FAN50FC3 detects the change and ignores the DAC inputs for a minimum of 200ns. This time prevents a false code due to logic skew while the eight VID inputs are changing. Additionally, the first VID change initiates the PWRGD and CROWBAR blanking functions for a minimum of 100s to prevent a false PWRGD or CROWBAR event. Each VID change resets the internal timer.
output over-voltage is due to a short in the high-side MOSFET, this action current-limits the input supply, protecting the microprocessor.
Output Enable and UVLO
For the FAN50FC3 to begin switching, the input supply (VCC) to the controller must be higher than the UVLO threshold and the EN pin must be higher than its 0.85V threshold. This initiates a system start-up sequence. If either UVLO or EN is less than their respective thresholds, the FAN50FC3 is disabled; which holds the PWM outputs low, discharges the DELAY and SS capacitors, and forces PWRGD and OD# signals low. In the application circuit, the OD# pin should be connected to the OD# inputs of the FAN5009 or FAN5109 drivers. Pulling OD# LOW disables the drivers such that both DRVH and DRVL are driven low. This turns off the bottom MOSFETs to prevent them from discharging the output capacitors through the output inductors. If the bottom MOSFETs were left on, the output capacitors could ring with the output inductors and produce a negative output voltage to the processor.
NTC Resistance versus Temperature Normalized to 25C
Power Good Monitoring
The power good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specified based on the VID voltage setting. PWRGD goes low if the output voltage is outside of this specified range, if the VID DAC inputs are in no CPU mode, or whenever the EN pin is pulled low. PWRGD is blanked during a VID OTF event for a period of ~200s to prevent false signals during the time the output is changing. The PWRGD circuitry also incorporates an initial turn-on delay time (TD5) based on the DELAY timer. Prior to the SS voltage reaching the programmed VID DAC voltage, 100mV, the PWRGD pin is held low. Once the SS pin is within 100mV of the programmed DAC voltage, the capacitor on the DELAY pin begins to charge up. A comparator monitors the DELAY voltage and enables PWRGD when the voltage reaches 1.7V. The PWRGD delay time is therefore set by a current of 15A charging a capacitor from 0V to 1.7V.
1.0
0.8 Resistance (25C = 1)
0.6
0.4
0.2
0.0 25 50 75 Temperature (C) 100 125
Figure 12. Typical NTC Resistance vs. Temperature
Output Crowbar
As part of the protection for the load and output components of the supply, the PWM outputs are driven low (turning on the low-side MOSFETs) when the output voltage exceeds the upper crowbar threshold. This crowbar action stops once the output voltage falls below the release threshold of approximately 300mV. Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the
Applications and Component Selection
Please consult Fairchild Application Note: AN-6052 -- Instructions for the Multi-Phase VR11 MathCad(R) Design Tool
(c) 2007 Fairchild Semiconductor Corporation FAN50FC3 Rev. 1.0.0
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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
Layout and Component Placement
The following guidelines are recommended for optimal performance of a switching regulator in a PC system. precautions can result in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. Using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high-current demand with minimal voltage loss. Whenever a power dissipating component, for example, a power MOSFET, is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heatsink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation to the air around the board. To further improve thermal performance, use the largest possible pad area. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, a solid power ground plane should be used as one of the inner layers, extending fully under all the power components.
General Recommendations
For good results, a PCB with at least four layers is recommended. This should allow the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the remainder of the power delivery current paths. Keep in mind that each square unit of one-ounce copper trace has a resistance of ~0.53m at room temperature. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the FAN50FC3) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground plane should be around and under the FAN50FC3 as a reference for the components associated with the controller. This plane should be tied to the nearest output decoupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing in it. The components around the FAN50FC3 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB and CSSUM pins. The output capacitors should be connected as close as possible to the load (or connector); for example, a microprocessor core that receives the power. If the load is distributed, the capacitors should be distributed and generally be in proportion to where the load tends to be more dynamic. Avoid crossing any signal lines over the switching power path loop described in the following section.
Signal Circuitry Recommendations
The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connect to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Thus, the FB and FBRTN traces should be routed adjacent to each other on top of the power ground plane back to the controller. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be connected to the output voltage at the nearest inductor to the controller.
Power Circuitry Recommendations
The switching power path should be routed to encompass the shortest possible length radiated switching noise energy (i.e., conduction losses in the board. Failure to on the PCB to minimize EMI) and take proper
(c) 2007 Fairchild Semiconductor Corporation FAN50FC3 Rev. 1.0.0
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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
Physical Dimensions
Dimensions are in millimeters (inches) unless otherwise noted.
Figure 13. 32-Pin, Molded Leadless Package (MLP), JEDEC MO-220, 5mm Square
(c) 2007 Fairchild Semiconductor Corporation FAN50FC3 Rev. 1.0.0
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FAN50FC3 -- 8-Bit Programmable, 2- to 3-Phase FastvCoreTM Buck Controller
(c) 2007 Fairchild Semiconductor Corporation FAN50FC3 Rev. 1.0.0
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