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XR-T7288
...the analog plus company TM
CEPT1 Line Interface
June 1997-3
FEATURES D Fully Integrated 2.048Mbits/s Line Interface D Intended For Use In Systems That Must Comply With CCITT Specifications G.703, G.823, I.431, G.732, G.735, G.739 D Pin-Selectable 75 or 120 Operation D Monolithic Clock Recovery D Low Power Dissipation: 100mW for 120 Twisted Pair, Typical 108mW for 75 Coaxial, Typical D Minimal External Circuitry Required D Robust Frequency Acquisition/Phase-Locked Loop D Pin-Selectable HDB3 Encoder and Decoder D Loopback Modes for Fault Isolation D Multiple Link-Status and Alarm Features D Single-Rail/Dual-Rail Interface
GENERAL DESCRIPTION The XR-T7288 CEPT1 Line Interface is an integrated circuit that provides a 2.048 Mbits/s line interface to either twisted-pair or coaxial cable as specified in CCITT requirements G.703, G.823, I.431, G.732, and G.735 G.739. The device performs receive pulse regeneration, timing recovery, and transmit pulse driving functions. The ORDERING INFORMATION
Operating Temperature Range -40C to +85C -40C to +85C
XR-T7288 device is manufactured by using low-power CMOS technology and is available in a 28-pin, plastic DIP or in a 28-pin, plastic SOJ package for surface mounting. The XR-T7288 device is functionally compatible with the LC1135B device. The digital circuitry is shown in Figure 1.; the analog circuitry is shown in Figure 6.
Part No. XR-T7288IP XR-T7288IW
Package 28 Lead 300 Mil PDIP 28 Lead 300 Mil Jedec SOJ
Rev. 1.01
E1992
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017 1
XR-T7288
SD LOS LP1 LOC LP3 HDB3 Code Violation Detection HDB3/TNDATA
MUX
MUX
T1 Receive R1
MUX
Loss Of Clock Detection
Dual - To Single Rail Converter
HDB3 Decoder
MUX
Blue Signal (AIS) Generator
SR/DR MUX
HDB3/TNDATA
MUX
Transmit R2
MUX
T2
Single-to Dual Rail Converter
HDB3 Encoder
MUX
Blue (AIS) Signal Generator
All Analog Functions +5
ZS
LP2 TBC
BClk
ALMT
VDDA
Output Drivers And Logic +5 VDDD
Output Drivers And Logic GND GNDD
All Analog Functions
GND GNDA
Figure 1. Digital Block Diagram
Rev. 1.01 2
III III II III II I II II I II I II I II
MUX MUX MUX MUX
III III II III I II I I I I I I
MUX MUX MUX
Bipolar Violation Detection
II I IIIII I IIIII II I IIIII III III III III II II
MUX MUX
RBC SR/DR
FLM
MUX
RDATA/ RPDATA
II IIIIII IIIIII II II II II II IIIII II IIIII II
MUX
VIO/ RNDATA
RClk
TDATA/ TPDATA HDB3/ TNDATA TClk
XR-T7288
PIN CONFIGURATION
LOS LOC HDB3/TNDATA VIO/RNDATA RClk RDATA/RPDATA TClk TDATA/TPDATA LP1 LP2 LP3 ALMT RBC TBC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
T1 R1 SD GNDA VDDA ZS T2 VDDD R2 GNDD NC FLM SR/DR BClk
LOS LOC HDB3/TNDATA VIO/RNDATA RClk RDATA/RPDATA TClk TDATA/TPDATA LP1 LP2 LP3 ALMT RBC TBC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
T1 R1 SD GNDA VDDA ZS T2 VDDD R2 GNDD NC FLM SR/DR BClk
28 Lead PDIP (0.300")
28 Lead SOJ (Jedec, 0.300")
PIN DESCRIPTION
Pin # 1 2 Symbol LOS LOC Type O O Description Loss of Signal (Active-Low). This pin is cleared (0) upon loss of the data signal at the receiver inputs. Loss of Clock (Active-Low). This pin is cleared when SD = 1 and LOS= 0, indicating that a loss of clock has occurred. When LOC= 0, no transitions occur on the RClk and on either RDATA (for single-rail) or RPDATA and RNDATA (for dual-rail operation) outputs. A valid clock must be present at BClk for this function to operate properly. HDB3 Enable/N-Rail Transmit Data. If SR/DR = 0, this pin is set (1) to insert an HDB3 substitution code on the transmit side and to remove the substitution code on the receive side. If SR/DR = 1, this pin is used as the n-rail transmit input data (internal pull-down is included). Violation/N-Rail Receive Data. If SR/DR = 0 and HDB3 = 0, bipolar violations on the receive side input are detected, causing VIO to be set; if HDB3 = 1, HDB3 code violations cause VIO to be set. If SR/DR =1, this pin is used as the n-rail receive output data. Receive Clock. Output receive clock signal to the terminal equipment. Receive Data/P-Rail Receive Data. If SR/DR = 0, this pin is used for 2.048 Mbits/s unipolar output data with a 100% duty cycle. If SR/DR = 1, this pin is used as the p-rail receive output data. Transmit Clock. Input clock signal (2.048 MHz 80 ppm). Transmit Data/P-Rail Transmit Data. If SR/DR = 0, this pin is used as 2.048 Mbits/s unipolar input data. If SR/DR = 1, this pin is used as the p-rail transmit input data. Loopback 1 Enable (Active-Low). This pin is cleared for a full local loopback (transmit converter output to receive converter input). Most of the transmit and receive analog circuitry is exercised in this loopback (internal pull-up is included). Loopback 2 Enable (Active-Low). This pin is cleared for a remote loopback. In loopback 2, a high on TBC (pin 14) inserts the blue signal (AIS) on the transmit side (internal pull-up is included).
3
HDB3/ TNDATA VIO/ RNDATA RClk RDATA/ RPDATA TClk TDATA/ TPDATA LP1
I
4
O
5 6
O O
7 8 9
I I I
10
LP2
I
Rev. 1.01 3
XR-T7288
PIN DESCRIPTION (CONT'D)
Pin # 11 Symbol LP3 Type I Description Loopback 3 Enable (Active-Low). This pin is cleared for a digital local loopback. Only the transmit and receive digital sections are exercised in this loopback (internal pull-up is included). Alarm Test Enable (Active-Low). This pin is cleared, forcing LOS = 0, LOC= 0, and VIO = 1 for testing without affecting data transmission (internal pull-up is included). Receive Blue Control. This pin is set to insert the blue signal (AIS) on the receive side (internal pull-down is included). Transmit Blue Control. This pin is set to insert the blue signal (AIS) on the transmit side. This control has priority over a loopback 2 if both are operated (internal pull-down is included). Blue Clock. Blue clock (AIS) input signal (2.048MHz 80ppm). This clock can be independent of the transmit clock. Single-Rail (Active-Low)/Dual-Rail Operation. If SR/DR = 0 (internal pull-down is included), single-rail operation is selected; if SR/DR = 1, dual-rail operation is selected (see Tables 3-5). Framer Logic Mode. If FLM = 0 (internal pull-down is included), logic mode 1 operation occurs. If FLM = 1, logic mode 2 operation occurs (see Tables 3-5). No Connection. Test pin for manufacturing purposes only. This pin must be left floating or tied to GNDD. Digital Ground. O Transmit Bipolar Ring. Negative bipolar transmit output. 5V Digital Supply (10%). O I Transmit Bipolar Tip. Positive bipolar transmit output. Impedance Select. This pin is cleared for 75 coaxial cable operation and set for 120 shielded twisted-pair operation (internal pull-down is included) 5V Analog Supply (10%). Analog Ground. I Shutdown Enable. If this pin is high, a loss-of-signal detection (LOS= 0) forces LOC low and causes the following (see Table 2): For single-rail operation: RClk high, RDATA low. For dual-rail, logic mode 1 operation RClk high, RPDATA and RNDATA low. For dual-rail, logic mode 2 operation: RClk low, RPDATA and RNDATA high (internal pulldown is included). Receive Bipolar Ring. Negative bipolar receive input Receive Bipolar Tip. Positive bipolar receive input.
12 13 14 15 16
ALMT RBC TBC BClk SR/DR
I I I I I
17 18 19 20 21 22 23 24 25 26
FLM NC GNDD R2 VDDD T2 ZS VDDA GNDA SD
I
27 28
R1 T1
I I
Rev. 1.01 4
XR-T7288
ELECTRICAL CHARACTERISTICS
Symbol Parameter Input Voltage VIL VIH VOL VOH CI CL Low High Output Voltage1 Low High Input Capacitance Load Capacitance Output Pulse Amplitude 75 (ZS = 0) 120 (ZS = 1) Pulse Width (50%) Positive/Negative Pulse Imbalance Zero Level Output Transformer Turns Ratio Receiver Specifications Receiver Sensitivity3 Allowed Cable Loss at BER 10-9 No Interference Interfering PBRS, 18dB Below Transmitted PBRS PLL4 3dB Bandwidth Peaking ICO Free-running Frequency Error 28 0.24 0.5 7 kHz dB % 10 7 6 dB dB 0.7 4.2 Vp 1:1.33 1:1.36 2.14 2.70 219 2.37 3.00 244 2.60 3.30 269 5 102 1:1.39 V V ns % %2 GNDD 2.4 0.4 VDDD 20 40 V V pF pF 2.0mA Sink 80A Source GNDD 2.0 0.8 VDDD V V
Test Conditions: TA = -40C to +85C; VDD = 5V 10%
Min. Typ. Max. Unit Conditions
Logic Interface Electrical Characteristics
Transmitter Specifications
Notes 1 Digital outputs drive purely capacitive loads to full output levels (V D, GNDD) DD 2 Percentage of the nominal pulse amplitude. 3 Measured at T1, R1 (V peak-to-zero, GND reference) 4 Transfer characteristics (1/4 input) 5 All measurements are with a matched-impedance transmit interface (see Figure 3. and Figure 4.) and with V DD or GND applied to digital input leads. Internal pull-up devices are provided on the following input leads: LP1, LP2, LP3 and ALMT. Internal pull-down devices are provided on the following leads: SD, RBC, HDB3/TNDATA, TBC, SR/DR, FLM, and ZS. The internal pull-up or pull-down devices require the input to source or sink to be no more than 20A.
Specifications are subject to change without notice
Rev. 1.01 5
XR-T7288
ELECTRICAL CHARACTERISTICS (CONT'D)
Symbol Parameter Input Transformer Turns Ratio Input Resistance, RI or TI, Each Input to Ground Jitter (20Hz-100kHz) Receive Plus Transmit Jitter at T2/R2 Transmit Jitter at T2/R2 Power Dissipation5 Power Dissipation Pdis Pdis 75 (ZS = 0) 120 (ZS = 1) Power Dissipation: Pdis Pdis 75 (ZS = 0) 120 (ZS = 1) Power Dissipation: Pdis Pdis 75 (ZS = 0) 120 (ZS = 1) 108 100 mW mW PRBS (50% 1s) transmit and receive data, VDD=5.0V 170 150 mW mW All 1s transmit and receive data, VDD=5.0V 190 170 290 260 mW mW All 1s transmit and receive data, VDD=5.5V 0.06 0.012 0.09 0.04 U.I. peak-to-peak U.I. peak-to-peak Min. 1:1.9 0.9 Typ. 1:2.0 Max. 1:2.1 3.0 k Unit Conditions
Receiver Specifications (Cont'd)
(TA=-40C to +85C, VDD=5.0 V 10%)
Notes 1 Digital outputs drive purely capacitive loads to full output levels (V D, GNDD) DD 2 Percentage of the nominal pulse amplitude. 3 Measured at T1, R1 (V peak-to-zero, GND reference) 4 Transfer characteristics (1/4 input) 5 All measurements are with a matched-impedance transmit interface (see Figure 3. and Figure 4.) and with V DD or GND applied to digital input leads. Internal pull-up devices are provided on the following input leads: LP1, LP2, LP3 and ALMT. Internal pull-down devices are provided on the following leads: SD, RBC, HDB3/TNDATA, TBC, SR/DR, FLM, and ZS. The internal pull-up or pull-down devices require the input to source or sink to be no more than 20A.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS DC Supply Voltage (VDD) . . . . . . . . . . . -0.5V to +6.5V Power Dissipation (Pdis) . . . . . . . . . . . . . . . . . 500mW Storage Temperature (Tstg) . . . . . . . -65C to +125C Maximum Voltage (any pin) with Respect to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V Minimum Voltage (any pin) with Respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V Maximum Allowable Voltages (T1, R1) with Respect to GND . . . . . . -5.0V to 5.0V
Stresses in excess of the Absolute Maximum Ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operation sections of the data sheet. Exposure to Absolute Maximum Ratings for extended periods can adversely affect device reliability. pin assignment ordering information
Rev. 1.01 6
XR-T7288
Q2E 04 RP5H 330 11 10 8 9 VCC RPDATA B4 12 2 B6 12 2 B5 12 2 VCC 1
6 5 4 3 9 10 11 12 13 14 15 16 111111 5432109
L5
VIO/RDATA
J8
1 3
RPOS RRPOS RClk RRClk RNEG RRNEG
2 15 4 13 3 14
RPOS RRPOS
VCC BL
16 11 10
BL
Q2F 13
04 12
RP5G 7
L1 10
BL
J6
1 3
RClk
J7
1 3
RNDATA
XTAL2 Q3 RClk 2188 (Jitter Attenuator) RRClk XTAL1 RNEG XTAL RRNEG RST BDS TEST DJA
XTAL1 8.192MHz
9 7 12 5 6 1
TP1 XTALOUT SW2 RST BDS TEST DJA SRDR ZS SD FLM 16 15 14 13 12 11 10 9 VCC ON 1 2 3 4 5 6 7 8
8
GND
RP2A 10K B8 1 2
1 6
TNDATA
HDB3 SW1
RPDATA RClk RNDATA TNDATA
SR/DR 23 ZS 26 SD 17 FLM LOC LOS
2 1
16
1111111 65432109 10K 12345678 RP4A LOC LOS 2
Q2A 04 2 1 Q2B 3 J4 1 3 TWP 04 4
RP5C 330 3 14 RP5E 330 5 12
L3
LOC
VCC
8 7 6 5 4 3 2 1
L2
LOS
9 10 11 12 13 14
LP1 LP3 LP3 ALMT RBC TBC
R8 270 T2 PE-65415 B3 1 R16 200 RXIN 2
COAX R2 866
ON RP2B 10K
T1 Q1 XR-T7288 R1
28
27
2345678
2
J3
1 3
TWP
R5 270
2:1 T1 PE-64937 J2 2 1
RPDATA
B7 1 2 B9 1 2 3 EXT 1 J5
COAX R3 866 COAX TWP COAX TWP 3 1 3 1 J1 B2 TXOUT 2 2 1:1.36 1 RP5A 330 1 16 L4 PWR P2 GND P1 VCC
TPDATA 8
TPDATA T2
22
R13 R14
26.1 15.4 26.1 15.4
TClk
TClk
7
TClk
R2
20
R11 VCC R15
BLUE CLOCK
B1 1 2 R17 75
2 BClk 15
BClk
VCCA VCCD GNDA GNDD NC
24 21 25 19 18
C2 0.1uF
E1 22uF
C1 0.1uF
1
Figure 2. Suggested Application Circuit
Rev. 1.01 7
XR-T7288
SYSTEM DESCRIPTION The XR-T7288 device is a fully integrated line interface that requires only two transformers, three input termination resistors, and two output impedance-matching resistors to provide a bidirectional line interface between a 2.048 Mbits/s CEPT datalink and terminal equipment. Typical application diagrams are shown in Figure 3. and Figure 4. for 75 coaxial cable and 120 shielded twisted-pair operation, respectively. The circuit is divided into three main blocks: transmit
RECEIVE DATA
converter, receive converter, and logic. The transmit and receive converters process information signals through the device in the transmit and receive directions, respectively; the logic is the control and status interface for the device. Figure 3. and Figure 4. include a matched-impedance transmit-interface section in order to match the output impedance of the transmitter to the line. See Table 1 for the G.703/CH-PTT specifications for transmit-interface return loss.
200
1:2
Transmitted Data
Matched-impedance Transmit Interface
75
Load
1.36:1
Figure 3. Typical Application Diagram for Coaxial Environment
Rev. 1.01 8
II II II II II II II II II II II II II II II II
15.4 15.4
I I IIII I IIIIII III IIII IIIIII III
I I I I II
T1 Receive Input R1
270 270
RDATA/RPDATA VIO/RNDATA RClk VDDD +5V VDDA XR-T7288 CEPT1 Line Interface ZS GNDD GNDA 1F
T2 Transmit Output R2 TDATA/TPDATA HDB3/TNDATA TClk
XR-T7288
RECEIVE DATA
200
1:2
Transmitted Data
Matched-impedance Transmit Interface
120
Load
1.36:1
26.1
Figure 4. Typical Application Diagram for Shielded Twisted-Pair Environment
Interface Transmit 51 kHz to 102 kHz 102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz Receive 51 kHz to 102 kHz 102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz
Table 1. Return Loss (resistor tolerance: 1% on transmit side, 2% on receive side)
Rev. 1.01 9
II II II II II II
26.1
I I I I I I I I I I
T1 866 Receive Input 866 R1
RDATA/RPDATA VIO/RNDATA RClk VDDD +5V VDDA XR-T7288 CEPT1 Line Interface ZS GNDD GNDA 1F
II II II II II II II II II
T2 Transmit Output R2 TDATA/TPDATA HDB3/TNDATA TClk
Min
Typ
Max
Units
8 14 10
28 26 24
dB dB dB
12 18 14
32 31 30
dB dB dB
XR-T7288
Transmit Converter The line-interface transmission format is return-to-zero, bipolar alternate mark inversion (AMI), requiring transmission and sensing of alternately positive and negative pulses. The transmit converter accepts unipolar data and clock and converts the signal to a balanced bipolar data signal. Binary 1s in the data stream become pulses of alternating polarity transmitted between the two output rails, T2 and R2. Binary 0s are transmitted as null pulses. The output pulse waveform is nominally rectangular. The pulses are produced by a high-speed D/A converter and are driven onto the line by low-impedance output buffers. The positive and negative pulses meet CCITT specification G.703 template requirements. The normalized pulse template is shown in Figure 5. A block diagram of the analog circuitry is shown in Figure 6. The clock multiplier shown in Figure 6. uses a phase-locked loop (PLL) to produce the high-speed timing waveforms needed to produce a well-controlled pulse width. The clock multiplier also eliminates the need for the tightly.controlled transmit clock duty cycle usually required in discrete implementations. Transmitter specifications are shown in the Electrical Characteristics table.
269ns (244 + 25) 20% 10% V = 100% 10% 20% 194ns (244 - 50) Nominal pulse
50% 244ns 219ns (244 - 25)
10% 0% 10% 20%
10% 10%
488ns (244 + 244)
Note: V corresponds to the nominal peak value
Figure 5. CCITT G.703 Pulse Template
Rev. 1.01 10
XR-T7288
LP1 LOS SD
Analog Signal Detector T1 R1 Receiver Analog Input
PDATA NDATA RP
Digital Signal Detector
M U X
Data/Clock Recovery
RN RClk
RDATA/RPDATA VIO/RNDATA RClk Transmit and Receive Logic TDATA/TPDATA HDB3/TNDATA TClk
TP TN
T2 R2
Transmit Output Drivers
High Speed D/A 2 Timing Signals ZS Clock Multiplier
TClk
Figure 6. XR-T7288 Analog Block Diagram
RECEIVE CONVERTER The receive converter accepts bipolar input signals (T1, R1), with a maximum of 6dB loss at 1024kHz, through the interconnection cable. The received signal is rectified while the amplitude and rise time are restored. These input signals are peak-detected and sliced by the receiver front end, producing the digital signals PDATA and NDATA (see Figure 6.) Receive decision levels are automatically adjusted to be 50% of peak-to-zero signal levels. The timing is extracted by means of PLL circuitry that locks an internal, free-running, current-controlled oscillator (ICO) to the 2.048MHz component. The PLL employs a 3-state phase detector and a low-voltage/temperature coefficient ICO. The ICO free-running frequency is trimmed to within 2.5% of the data rate at wafer probe, with VDD = 5.0 V and TA = 25C. For all operating conditions (see Operating Conditions section), the free-running oscillator frequency deviates from the data rate by less than 7%, alleviating the problem of harmonic lock.
Rev. 1.01 11
For robust operation, the PLL is augmented with a frequency-acquisition capability. This feature detects if the recovered PLL clock (RClk) deviates by more than +1.7/-1.6% in frequency from a 2.048 MHz reference clock, which must be provided at BClk. If the RClk frequency is not within the prescribed range of the BClk frequency, the XR-T7288 device enters a training mode in which receive input data is disconnected from the PLL, and the RClk frequency is steered to equal the BClk frequency. After frequency acquisition is completed, the PLL reconnects to receive input data to acquire proper phase-lock and timing of RClk with respect to the incoming T1, R1 data. Valid data is available when proper phase-lock has been achieved. The frequency acquisition circuitry is intended to avoid improper harmonic locking during start-up situations, such as power-up or data interruption. Once the XR-T7288 device is phase-locked to data, the frequency-acquisition mode will not be activated.
XR-T7288
A continuous (i.e., ungapped, unswitched) 2.048 MHz reference clock must be present at BClk to enable the frequency-acquisition circuitry. However, the receive PLL will operate even in the absence of a 2.048 MHz clock at BClk. The 2.048 MHz clock at TClk can also be used to provide the 2.048 MHz reference at BClk. Because the clock output of the receive converter is derived from the ICO, a free-running clock can be present at the output of the receive converter without data being present at the input. A shutdown pin (SD) is provided to block this clock, if desired, to eliminate the free-running clock upon loss of the input signal. Both analog and digital methods of loss of signal detection are used in the XR-T7288 device. The analog signal detector shown in Figure 6. uses the output of the receiver peak detector to determine if a signal is present at T1 and R1. If the input amplitude drops below 0.25 V, typical, the analog detector output becomes active. Analog loss-of-signal is registered, at most, several milliseconds after a drop in signal level, depending on a variety of factors, such as initial signal amplitude.
Inputs
Hysteresis (140 mV, typical) is provided in the analog detector to eliminate LOS chattering. The digital signal detector counts 0s in the recovered data. If more than 32 consecutive 0s occur, the digital signal detector becomes active. In normal operation, the detector outputs are ORed together to form LOS; however, in loopback 1, only the digital signal detector is used to monitor the looped signal. Table 2 describes the operation of the shutdown, LOS, and LOC functions in normal operation and in loopback 1. The PLL is designed to accommodate large amounts of input jitter with high power supply rejection for operation in noisy environments. Low jitter sensitivity to power supply noise allows compact line-card layouts that employ many line interfaces on one board. The minimum input jitter tolerance, as specified in CCITT specification G.823, and the measured XR-T7288 device jitter tolerance are shown in Figure 7. Receiver specifications are shown on page 4. The XR-T7288 device satisfies the CCITT jitter transfer function requirement of recommendations G.735 G.739 (see Figure 8.)
Outputs Receive Side
LP1 1 1 1 1 0 0 0 0 x
SD 0 0 1 1 0 0 1 1 x
ALMT 1 1 1 1 1 1 1 1 0
Input Signal at T1, R1 Active No Signal Active No Signal x x x x x
Loopback 1 Signal x x x x Active No Signal Active No Signal x
LOS 1 0 1 0 1 0 1 0 0
LOC 1 1 1 0 1 1 1 0 0
Receive Data1 Normal Low 2 Normal Low 3 Low 4
RClk1 Normal Free-running ICO 2 Normal High
Active LOS Detectors Analog & Digital Analog & Digital Analog & Digital Analog & Digital Digital Only Digital Only Digital Only Digital Only x
Normal Loopback Normal Loopback Free-running ICO 4 High Unaffected
Normal Loopback Normal Loopback Low Unaffected
Notes: 1 These values apply for single-rail or dual-rail/logic mode 1. For dual-rail/logic mode 2, all logic-level outputs except for looped back data are the inverse of that shown above. 2 Activated by analog loss-of-signal (LOS) detection. 3 Digital LOS detection forces receive data low . Analog LOS detection merely forces receive data to stop transitions; receive data will be forced either high or low with analog LOS detection. 4 All-0s looped back data, no HDB3 operation. Sufficiently sparse looped back data (not HDB3 encoded) also causes the receive ICO to free run; therefore, properly timed loopback data is not guaranteed.
Table 2. Shutdown LOS and LOC Truth~Table x = don't care.
Rev. 1.01 12
XR-T7288
10 (1, 2.9) G.823 Specification XR-T7288 Measured Performance BER = 1E-6
Input Jitter Amplitude (U.I. Peak-to-Peak)
(20, 1.5) 1
(2.4K, 1.5)
0.1
1
0
-5
-10
-15
-20 0.1
Note: Equivalent binary content of input signal: 1000. Jitter input amplitude = 0.1 U.I. peak-to-peak.
Rev. 1.01 13
IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII IIIIIIIIIIIIIIII
20 Log (JOUT/JIN) (dB)
IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIII
Jitter Jitter Jitter Jitter Frequency Amplitude Frequency Amplitude (kHz) (U.I. pp) (kHz) (U.I. pp) 4 8 10 15 20 30 2.00 1.06 0.87 0.65 0.52 0.46 40 50 60 70 100 0.45 0.44 0.43 0.44 0.51 10 100 1k
(18k, 0.2)
(100k, 0.2)
10k
100k
Jitter Frequency (Hz)
Note: Measurement conditions random data, TA = 25C, VDD = 5V, 6dB cable loss, BClk clock present
Figure 7. Random Input Data Jitter Tolerance (HDB3 Encoded)
G.735-G.739 Specification (36K, 0.5dB)
-20dB/Decade
XR-T7288 Measured Performance
(100K, -8.4dB)
1
10
36
100
Frequency (kHz)
Figure 8. Receive Jitter Transfer Function
XR-T7288
Digital Logic The logic provides alarms, optional HDB3 coding, blue signal (AIS) insertion circuits, and maintenance loopbacks. It also optionally performs dual-rail to single-rail conversion of the data and provides an alternate logic polarity (logic mode 2) in dual-rail mode for receive clock and receive and transmit data. Single-Rail/Dual-Rail Interface and Alternate Logic Mode The XR-T7288 device supports either single-rail or dual-rail operation by setting the control pin SR/DR. In the single-rail mode (SR/DR = 0), the XR-T7288 receiver converts bipolar input signals (T1, R1) to a unipolar output signal on RDATA. The XR-T7288 transmitter converts a unipolar input signal on TDATA to a balanced bipolar data signal on pins T2 and R2. If desired, the HDB3 control pin can be used to set HDB3 encoding/decoding. Violation information is available on output pin VIO.
FLM 01 0 1 1 SR/DR 01 1 0 1
In the dual-rail mode (SR/DR = 1), the XR-T7288 receiver converts bipolar input signals (T1, R1) to p-rail and n-rail, nonreturn-to-zero output data on pins RPDATA and RNDATA, respectively. The XR-T7288 transmitter converts non-return-to-zero p-rail and n-rail input data on pins TPDATA and TNDATA, respectively, to a balanced bipolar data signal on pins T2 and R2. In the dual-rail mode, HDB3 encoding/decoding and bipolar violation output functions are unavailable. In the dual-rail mode, an alternate-logic polarity mode is available via control pin FLM. If FLM = 1, the XR-T7288 device operates in logic mode 2; RClk is inverted with respect to logic mode 1, and input and output data (TPDATA, TNDATA, RPDATA, and RNDATA) are active-low (see Figures 10-13). Internal pull-downs on signals SR/DR and FLM set default operation to single-rail, logic mode 1 (see Table 3)
Logic Mode 1 1 X2 2 Single Dual X2 Dual
Single-/Dual-Rail
Notes: 1 Default operation (identical with LC1135B) if both pins are unconnected. 2X = illegal option
Table 3. Rail Interface and Logic Mode Options
Pin 3 4 6 8 Name HDB3/TNDAT VIO/RNDATA RDATA/RPDATA TDATA/TPDATA Function HDB3 Enable VIO Violation RDATA Receive Data TDATA Transmit Data
Table 4. Single-Rail Operation (Default State) SR/DR = 0 (or left unconnected internal pull-down circuitry).
Pin 3 4 6 8 Name HDB3/TNDATA VIO/RNDATA RDATA/RPDATA TDATA/TPDATA Function N-rail Transmit Input Data N-rail Receive Output Data P-rail Receive Output Data P-rail Transmit Input Data
Table 5. Dual-Rail Operation SR/DR = 1
Rev. 1.01 14
XR-T7288
Alarms An independent loss-of-clock (LOC) output is provided so that loss of clock is detected when the shutdown option is in effect. LOS and LOC can be wire-ORed to produce a single alarm. A bipolar violation output is included if HDB3 = 0, giving an alarm (VIO) each time a violation occurs (two or more successive 1s on a rail). The violation alarm output is held in a latch for one cycle of the internal clock (RClk). In the HDB3 mode, HDB3 code violations are detected and an alarm is produced. An alarm test pin (ALMT) is provided to test the alarm outputs, LOS, LOC and VIO. Clearing this pin forces the alarm outputs to the alarm state without affecting data transmission. HDB3 Option The XR-T7288 device contains an HDB3 encoder and decoder (for single-rail mode only, i.e., SD/DR = 0) that can be selected by setting the HDB3 pin. This allows the encoder to substitute a zero-substitution code for four consecutive 0s detected in the data stream, as illustrated in Table 6 A "V" represents a violation of the HDB3 code, and a "B" represents a bipolar pulse of correct polarity. The decoder detects the zero-substitution code and reinserts four 0s in the data stream. Case 1: Preceding mark has a polarity opposite the polarity of the preceding violation and is not a violation itself. Case 2: Preceding mark has a polarity the same as the polarity of the preceding violation or is a violation itself.
Case 1 Before HDB3 After HDB3 0000 000V Case 2 0000 B00V Pin T1, R1 T2, R2 Max Value 20 mA 200 mA Width 1s to 1s 1s to 1s Avg Value 6 mA 40 mA
Blue Signal (AIS) Generators There are two blue signal (AIS) generators in this device. One (RBC = 1) substitutes an all-1s signal on RDATA output (SR/DR = 0) or RPDATA and RNDATA (SR/DR = 1) toward the terminal equipment. The other (TBC = 1) substitutes a bipolar, all-1s signal for the bipolar data out of the transmit converter which can be used to keep line repeaters active. Loopback Paths The XR-T7288 device has three independent loopback paths that are activated by clearing the respective control inputs, LP1, LP2 or LP3. Loopback 1 bridges the data stream from the transmit converter (transmit converter included) to the input of the receive converter. This maintenance loop includes most of the internal circuitry. Loopback 2 provides a loopback of data and recovered clock from the bipolar inputs (T1, R1) to the bipolar outputs of the transmit converter (T2, R2). The receive front end, receive PLL, and transmit driver circuitry are all exercised. The loop can be used to isolate failures between systems. TBC = 1 overrides this function. Loopback 3 loops the data stream as in loopback 1 but bypasses the transmit and receive converters. The blue signal (AIS) can be transmitted to the line when in this loopback. Loopbacks 2 and 3 can be operated simultaneously to provide transmission loops in both directions. Current Pulses With all other pins grounded, current pulses of maximum value and time widths are allowed on the T1/R1 and T2/R2 pins without damaging the device, as shown in Table 7. Also, to help ensure long-term reliability, the average value of a current-pulse train is specified.
Table 6. HDB3 Substitution Code
Table 7. Maximum Allowable Current
Rev. 1.01 15
XR-T7288
Handling Precautions Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. EXAR employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500, capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters:
HBM ESD Threshold Device XR-T7288 Voltage >2500 V
Table 8.
R1
P1
Regulated High Voltage Power Supply
C1
SOCKET
Notes: P10kV to 5kV DC power supply. R1At least 10 M, high-voltage, 1W carbon composition. RL1High-voltage (5 kV) relay of a bounceless type (mercury-wetted or equivalent). C1100pF, 5kV capacitor. R21500 5%, 1W carbon composition < 1pF shunt capacitance.
Figure 9. Circuit Schematic of Human-Body ESD Simulator
Rev. 1.01 16
IIIIIIII IIIIIIII II II I I IIIIIIII III I II III I I IIIIIIII III I III III I I IIIIIIII III III II III II II IIIIIIII III I
IIIII IIIII IIIII III IIIII II IIIII
RL1
R2 For Device Testing
IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII IIIIIII
XR-T7288
Timing Characteristics All duty-cycle and timing relationships are in reference to a TTL, 1.4V threshold level. Loss-of-Clock Indication Timing The clock must be absent 6.4 s to guarantee a loss-of-clock indication.However, a loss-of-clock indication can occur if the clock is absent for as little as 1.95s, depending on the timing relationship of the interruption with respect to the timing cycle. The returning clock must be present 3.91s to guarantee a normal condition on the loss-of-clock pin (LOC). However, the loss-of-clock indication can return to normal immediately, depending on the timing relationship of the signal return with respect to the timing cycle. TA = -40C to 85C; VDD = 5 V10%; load capacitance = 40 pF.
Symbol tTCLTCL tTCHTCL tTDVTCL tTCLTDV tr tf tRCLRCL tRCHRDV tRDVRCH tRCLRDV Description TCLK Clock Period TCLK Duty Cycle Data Setup Time, TDATA2 to TCLK Data Hold Time, TCLK to TDATA2 Min
1
Typ 488 50
Max
1
Unit ns % ns ns
40 50 40
60
Clock Rise Time (10% 90%) Clock Fall Time (10% 90%) RCLK Duty Cycle Data Hold Time, RCLK to RDATA, Data Setup Time, RDATA, VIO to VIO3 VIO3 RCLK3 40 171 131 50
40 40 60
ns ns % ns ns
Propagation Delay, RCLK to RDATA,
40
ns
Table 9. Clock Timing Relationships
Notes 1 A tolerance of 80 ppm. 2 DATA for single-rail mode; TPDATA and TNDATA for dual-rail mode. 3 RDATA and VIO for single-rail mode; RPDATA and RNDATA for dual-rail mode.
Rev. 1.01 17
XR-T7288
TIMING DIAGRAMS (Single-Rail or Dual-Rail, Logic Mode 1)
tr tTCLTCL
tf
TClk (TC)
TDATA or TPDATA TNDATA (TD) tTDVTCL
tTCLTDV
Figure 10. Transmit Timing
tr tRCLRDV
tf
RClk (RC)
tRDVRCH RDATA VIO or RPDATA RNDATA (RD) tRCHRDV
Figure 11. Receive Timing
Rev. 1.01 18
XR-T7288
TIMING DIAGRAMS (Dual-Rail, Logic Mode 2)
tr tTCLTCL tf
TClk (TC)
TPDATA TNDATA (TD) tTDVTCL tTCLTDV
ACTIVE LOW
Figure 12. Transmit Timing
tRCLRDV
tr
tf
RClk (RC)
RDATA VIO or RPDATA RNDATA (RD) tRCHRDV
Figure 13. Receive Timing
Rev. 1.01 19
II II II II
tRDVRCH
ACTIVE LOW
XR-T7288
TRANSFORMER REQUIREMENTS
Turns Ratio 1:1 1:1 1:1
Line Impedance 75 120 100
RLOAD 75 120 100
Turns Ratio 1:1 1:1.265 1:1.265
Line Impedance 75 120 100
ROUT 68 68 62
Table 10. Input Transformer Requirements Magnetic Supplier Information: Pulse Telecom Product Group P.O. Box 12235 San Diego, CA 92112 Tel. (619) 674-8100 Fax. (619) 674-8262
Table 11. Output Transformer Requirements
Transpower Technologies, Inc. 24 Highway 28, Suite 202 Crystal Bay, NV 89402-0187 Tel. (702) 831-0140 Fax. (702) 831-3521
Rev. 1.01 20
XR-T7288
28 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP)
Rev. 1.00
28 1 D
15 14 E1 E A2 A1
Seating Plane
A L B e
eA eB
C
B1
INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L MIN 0.145 0.015 0.115 0.014 0.030 0.008 1.345 0.300 0.265 MAX 0.210 0.070 0.195 0.024 0.070 0.014 1.400 0.325 0.310
MILLIMETERS MIN 3.68 0.51 2.92 0.36 0.76 0.20 34.16 7.62 7.11 MAX 5.33 1.78 4.95 0.56 1.78 0.38 35.56 8.26 7.49
0.100 BSC 0.300 BSC 0.310 0.115 0 0.430 0.150 15
2.54 BSC 7.62 BSC 7.87 2.92 0 10.92 3.81 15
Note: The control dimension is the inch column
Rev. 1.01 21
XR-T7288
28 LEAD SMALL OUTLINE J LEAD (300 MIL JEDEC SOJ)
Rev. 1.00
D
28
15
E
1 14
H
A2 Seating Plane e B A1 C R E1
A
INCHES SYMBOL A A1 A2 B C D E E1 e H R MIN 0.145 0.025 0.120 0.014 0.008 0.697 0.292 0.262 MAX 0.200 --- 0.140 0.020 0.013 0.712 0.300 0.272
MILLIMETERS MIN 3.60 0.64 3.05 0.36 0.20 17.70 7.42 6.65 MAX 5.08 --- 3.56 0.51 0.30 18.08 7.62 6.91
0.050 BSC 0.335 0.030 0.347 0.040
1.27 BSC 8.51 0.76 8.81 1.02
Note: The control dimension is the inch column
Rev. 1.01 22
XR-T7288 Notes
Rev. 1.01 23
XR-T7288
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1992 EXAR Corporation Datasheet June 1997 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.01 24

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