BR2CR  BR2CR  TB2OUT (from TMRB2) UART Mode Selector Selector Selector Divider
IMCLK/2 IMCLK/8 IMCLK/32 IMCLK/128 BR2CR  Baud Rate Generator IMCLK SCLK2 Input (Shared with P87) /2
SC2MOD0  Selector SC2CR 
SC2MOD0  SIOCLK
I/O Interface Mode
SCLK2 Output (Shared with P87) SC2MOD0  Receive Counter (/16 for UART) RXDCLK SC2MOD0  Receive Control SC2CR   Parity Control Receive Buffer 1 (Shift Register) SC2CR  Receive Buffer 2 (SC2BUF)
Interrupt Request INTRX2 Interrupt Request INTTX2 Transmit Counter (/16 for UART) TXDCLK Transmit Control SC2MOD0  CTS2 (Shared with P87)
Serial Channel Interrupt Control
RX2 (Shared with P85)
Transmit Buffer 1 (Shift Register) SC2CR  Transmit Buffer 2 (SC2BUF)
TX2 (Shared with P86)
Error Flag SC2CR 
IM-BUS
Receive FIFO
To Serial Channel Interrupt Control
Interrupt Request INTRX2 Interrupt Request INTTX2
Transmit FIFO
SC2FRC 
Receive Control
Transmit Control
SC2FRC  
SC2FR C 
FIFO Interrupt Control
SC2FTC 
SC2FTC 
SC2FTC  
Figure 12.2.1
SIO2 Block Diagram
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12.3 SIO Components (SIO2)
12.3.1 Prescaler
The SIO2 has a 7-bit prescaler that slows the rate of a clocking source to the serial clock generator. The prescaler clock source (IMCLK) can be programmed in the PRS2 bit of the CLKPRSC located within the clock generator. The prescaler can output four types of clocks to the baud rate generator: IMCLK/2, IMCLK/8IMCLK/32 and IMCLK/128. The serial clock is selectable from several clocks; the prescaler is only enabled when the baud rate generator output clock is selected as a serial clock. Table 12.3.1 shows prescaler output clock resolutions. Table 12.3.1 Prescaler Output Clock Resolutions
fc = 12 MHz (PLL output clock) Clock Gear Value CLKPRSC.PRS1 IMCLK Selection CLKPSC.PRS2 000 (fsys/2) 00 (fc/2) 010 (fsys/3) 100 (fsys/4) 110 (fsys/5) 000 (fsys/2) 01 (fc/4) 010 (fsys/3) 100 (fsys/4) 110 (fsys/5) 000 (fsys/2) 10 (fc/8) 010 (fsys/3) 100 (fsys/4) 110 (fsys/5) IMCLK/2 fc/8 (71.4 ns) fc/12 (107 ns) fc/16 (143 ns) fc/20 (178 ns) fc/16 (143 ns) fc/24 (187 ns) fc/32 (286 ns) fc/40 (357 ns) fc/32 (0.29 s) fc/48 (0.43 s) fc/64 (0.57 s) fc/80 (0.71 s) Prescaler Output Clock Resolution IMCLK/8 fc/32 (0.29 s) fc/48 (0.43 s) fc/64 (0.57 s) fc/80 (0.71 s) fc/64 (0.57 s) fc/96 (0.86 s) fc/128 (1.1 s) fc/160 (1.43 s) fc/128 (1.1 s) fc/192 (1.7 s) fc/256 (2.3 s) fc/320 (2.9 s) IMCLK/32 fc/128 (1.1 s) fc/192 (1.7 s) fc/256 (2.3 s) fc/320 (2.9 s) fc/256 (2.3 s) fc/384 (3.4 s) fc/512 (4.6 s) fc/640 (5.7 s) fc/512 (4.6 s) fc/768 (6.9 s) fc/1024 (9.1 s) fc/1280 (11.4 s) IMCLK/128 fc/512 (4.6 s) fc/768 (6.9 s) fc/1024 (9.1 s) fc/1280 (11.4 s) fc/1024 (9.1 s) fc/1524 (13.7 s) fc/2048 (18.3 s) fc/2560 (22.9 s) fc/2048 (18.3 s) fc/3048 (17.4 s) fc/4096 (36.6 s) fc/5120 (45.8 s)
Note: Do not change the clock gear value while the SIO is operating.
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TMP19A71 12.3.2 Baud Rate Generator
The frequency used to transmit and receive data through the SIO2 is derived from the baud rate generator. The clock source for the baud rate generator can be selected from the 7-bit prescaler outputs (IMCLK/2, IMCLK/8, IMCLK/32, IMCLK/128) through the programming of the PRE bit in the BR2CR. The baud rate generator contains a clock divider that can divide the selected clock by N (N = 1 to 16) or N+(16-K)/16 ( N = 2 to 15, K = 1 to 15). The clock divisor is programmed into the DVS and BR2S bits in the BR2CR and the BR2K bit in the BR2ADD. * I/O Interface mode I/O Interface mode cannot utilize the N + (16 - K)/16 clock division function. The DVS bit in the BR2CR must be cleared to 0. * UART mode 1) When BR2CR.DVS=0 When the BR2CR.DVS bit is cleared, the BR2ADD.BR2K field has no meaning or effect. In this case, the baud rate generator input clock is divided down by a value of N (1 to 16) programmed in the BR2CR.BR2S field. 2) When BR2CR.DVS=1 Setting the BR2CR.DVS bit to 1 enables the N + (16 - K)/16 division function. The baud rate generator input clock is divided down according to the value of N (2 to 15) programmed in the BR2CR.BR2S field and the value of K (1 to 15) programmed in the BR2ADD.BR2K field.
Note: Setting N to 1 or 16 disables the N + (16K)/16 clock division function. When N = 1 or 16, the BR2CR.DVS bit must be cleared to 0.
* Baud rate calculations 1) I/O Interface mode Baud rate generator input clock Baud rate = Baud rate generator divisor
/2
When the clock input to the baud rate benerator is IMCLK/2 (14 MHz) and the baud rate generator divisor is set to 2, the maximum baud rate is 3.5 Mbps.
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2) UART mode Baud rate =
Baud rate generator input clock Baud rate generator divisor
/ 16
When the clock input to the baud rate generator is IMCLK/2 (14 MHz), the maximum baud rate is 875 Kbps. The baud rate generator can be bypassed if the user wants to use the IMCLK clock as a serial clock. In this case, the maximum baud rate is 1.75 Mbps (at IMCLK = 28 MHz). * Calculation examples 1) Integral division (divide-by-N) IMCLK = 28 MHz Baud rate generator input clock: IMCLK/8 Clock divisor N (BR2CR.BR2S) = 4 BR2CR.DVS = 0 Clocking conditions System clock : 56 MHz IMCLK : 28 MHz (divide-by-2)
Baud rate =
IMCLK/8 / 16 4
= 28 x 106 / 8 / 4 / 16 = 54.7Kbps)
Note:
Clearing the BR2CR.DVS bit to 0 disables the N + (16 - K)/16 clock division function. At this time, the BR2ADD.BR2K field is ignored.
2) N + (16 - K)/16 clock division (UART mode only) IMCLK = 28 MHz Baud rate generator input clock: IMCLK/32 N (BR2CR.BR2S) = 5 K (BR2ADD.BR2K) = 5 BR2CR.DVS = 1 Clocking conditions System clock : 56 MHz IMCLK Baud rate = IMCLK/32 (16-5) 5+ 16 : 28 MHz (divide-by-2)
/ 16
= 28 x 106 / 32 / (5 + 11 ) / 16 = 9615 (bps) 16
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The SIO2 can use an external clock as a serial clock, bypassing the baud rate generator. When an external clock is used, the baud rate is determined as shown below. * Using an external clock as a serial clock 1) I/O Interface mode Baud rate = external clock input When double-buffering is used, the external clock period must be greater than 12/fsys. Therefore, when fsys = 56 MHz, the maximum baud rate is 4.7 Mbps (56 / 12). When double-buffering is not used, the exernal clock period must be greater than 16/fsys. Therefore, when fsys = 56 MHz, the maximum baud rate is 3.5 Mbps (56 / 16). 2) UART mode Baud rate = external clock input / 16 The external clock input must be greater than or equal to 4/fsys. Therefore, when fsys = 56 MHz, the maximum baud rate is 875 Kbps (56 / 4 / 16). Table 12.3.2 and Table 12.3.3 show baud rate setting examples in UART mode.
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Table 12.3.2 UART Baud Rate Selection
Logic Baud Rate (bps) 1200 2400 4800 9600 14400 19200 28800 31250 38400 57600 115200 230400 Generated Baud Rate (bps) 1202 2404 4808 9615 14403 19231 28689 31250 38462 57613 115702 229508 Prescaler IMCLK/128 IMCLK/128 IMCLK/32 IMCLK/32 IMCLK/8 IMCLK/8 IMCLK/8 IMCLK/8 IMCLK/8 IMCLK/2 IMCLK/2 IMCLK/2 Divisor N 11 5 11 5 15 11 7 7 5 15 7 3 Correction Value  10 5 10 5 13 10 6 None 5 13 7 3 Error (%) 0.16 0.16 0.16 0.16 0.02 0.16 0.39 0 0.16 0.02 0.44 0.39
Note 1: This table assumes: fsys = 56 MHz, IMCLK = fsys/2 (28 MHz). Note 2: When a baud rate slower than 600 bps is used, the input clock must be TMRB2.
Table 12.3.3 UART Baud Rate Selection TB2REG1 values when the TMRB2 timer trigger output (Internal TB2OUT) is used (TMRB2 input clock = IMCLK/4)
IMCLK Baud rate (bps) 100 150 200 300 400 500 600 28 MHz 4375 2916 2188 1458 1094 875 729 20 MHz 3125 2084 1563 1042 781 625 521 14 MHz 2188 1458 1094 729 547 438 365 10 MHz 1563 1042 781 521 391 313 260 7 MHz 1094 730 547 365 273 219 182
When the timer TMRB2 is used to generate a serial clock, the baud rate is determined by the following equation: Baud rate = IMCLK TB2REG1 x 4 x 16 (When the TMRB2 clock source is IMCLK/4)
Note: In I/O Interface mode, the SIO2 and SIO3 cannot utilize the trigger output signal (internal) from the timer TMRB2 as a serial clock.
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TMP19A71 12.3.3 Serial Clock Generator
This block generates a basic clock that controls the transmit and receive operations. * I/O Interface mode If the SCLK2 pin is configured as an output by clearing the SC2CR.IOC bit to 0, the output clock from the baud rate generator is divided by two to generate the basic clock. If the SCLK2 pin is configured as an input by setting the SC2CR.IOC bit to 1, the external SCLK2 clock is used as the basic clock; the SC2CR.SCLKS bit determines the active clock edge. * UART mode The basic clock (SIOCLK) is selected from a clock produced by the baud rate generator, the system clock (IMCLK/2), the internal output signal from the timer TMRB2, and the external SCLK2 clock, according to the setting of the SC2MOD0.SC field.
12.3.4
Receive Counter
The receive counter is a 4-bit binary up-counter used in UART mode. This counter is clocked by SIOCLK. The receiver utilizes 16 clocks for each received bit, and oversamples each bit three times around their center (with 7th to 9th clocks). The value of a bit is determined by voting logic which takes the value of the majority of three samples.
12.3.5
Receive Controller
* I/O Interface mode If the SCLK2 pin is configured as an output by clearing the SC2CR.IOC bit to 0, the receive controller samples the RX2 input at the rising edge of the shift clock driven out from the SCLK2 pin. If the SCLK2 pin is configured as an input by setting the SC2CR.IOC bit to 1, the receive controller samples the RX2 input at either the rising or falling edge of the SCLK2 clock, as programmed in the SC2CR.SCLKS bit. * UART mode The receive controller uses 16 clocks for receiving the start bit. It samples the 7th to 9th clocks to determine by voting logic whether or not the correct start bit is received. Receive operation is started upon reception of the correct start bit.
12.3.6
Receive Buffer
The receive buffer is double-buffered to prevent overrun errors. Received data is serially shifted bit by bit into Receive Buffer 1. When a whole frame is loaded into Receive Buffer 1, it is transferred to Receive Buffer 2 (SC2BUF), and the INTRX2 is generated. At this time, the Receive Buffer Full flag (SC2MOD2.RBFLL) is set to 1, indicatig that Receive Buffer 2 contains valid data. The TX19A core processor reads a frame from Receive Buffer 2 (SC2BUF), causing the Receive Buffer Full flag (SC2MOD2.RBFLL) to be cleared to 0. Receive Buffer 1
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can accept a new frame before the TX19A core processor picks up the previous frame in Receive Buffer 2 (SC2BUF). If the SCLK2 pin is configured as an output in I/O Interface mode, Receive Buffer 2 (SC2BUF) can be enabled or disabled by programming the WBUF bit in the SC2MOD2. Disabling Receive Buffer 2 (double-buffering) enables handshaking during data transfer; the SIO2 stops outputting the SCLK2 clock every time a single frame has been transmitted. In this case, the TX19A core processor reads a frame from Receive Buffer 1, causing the output of the SCLK2 clock to be restarted. If Receive Buffer 2 (double-buffering) is enabled, a received frame is transferred from Receive Buffer 1 to Receive Buffer 2. Once a next frame is received resulting in both Receive Buffers 1 and 2 containing valid data, the SIO2 stops outputting the SCLK2 clock. When the TX19A core processor reads a frame from Receive Buffer 2, the frame stored in Receive Buffer 1 is transferred to Receive Buffer 2, causing a receive-done interrupt (INTRX2) to occur and the SIO2 to restart outputting the SCLK2 clock. Consequently, no overrun error occurs if the SCLK2 pin is configured as an output in I/O Interface mode, regardless of the setting of the SC2MOD2.WBUF bit.
Note: In SCLK output mode, the OEER flag in the SC2CR has no meaning; it is read as undefined. When exiting SCLK output mode, first read the SC2CR to initialize this flag.
In other operating modes, Receive Buffer 2 is always enabled to improve performance during continuous transfer. However, the TX19A core processor must read Receive Buffer 2 (SC2BUF) before Receive Buffer 1 is filled with a new frame. Otherwise, an overrun error occurs, causing the frame previously stored in Receive Buffer 1 to be lost. Even in that case, the contents of Receive Buffer 2 and the SC2CR.RB8 bit are preserved. The SC2CR.RB8 bit holds the parity bit in 8-Bit UART mode and the most significant bit in 9-Bit UART mode. In 9-Bit UART mode, the receiver wake-up feature can be enabled for slave controllers by setting the SC2MOD0.WU bit to 1. The receiver generates the INTRX2 interrupt only when the SC2CR.RB8 bit is set to 1.
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12.3.7
Transmit Counter
The transmit counter is a 4-bit binary up-counter used in UART mode. Like the receive counter, the transmit counter is also clocked by SIOCLK. The transmitter generates a transmit clock (TXDCLK) pulse every 16 SIOCLK pulses.
SIOCLK 15 TXDCLK 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2
Figure 12.3.1 Transmit Clock Generation
12.3.8
Transmit Controller
* I/O Interface mode If the SCLK2 pin is configured as an output by clearing the SC2CR.IOC bit to 0, the transmit controller shifts out each bit in the transmit buffer to the TX2 pin at the falling edge of the shift clock driven out on the SCLK2 pin. If the SCLK2 pin is configured as an input by setting the SC2CR.IOC bit to 1, the transmit controller shifts out each bit in the transmit buffer to the TX2 pin at either the rising or falling edge of the SCLK2 input, as programmed in the SC2CR.SCLKS bit. * UART mode Once the TX19A core processor loads a frame into the transmit buffer, the transmit controller begins transmission at the next falling edge of TXDCLK, producing a transmit shift clock.
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Handshaking (SIO2 and SIO3 only) The SIO2 has a clear-to-send (CTS2) pin. If the CTS operation is enabled, a frame can be transmitted only when the CTS2 input is low. This feature can be used for flow control to prevent overrun errors in the receiver. The SC2MOD0.CTSE bit enables and disables the CTS operation. If the CTS2 pin goes high in the middle of a transmission, the transmit controller stops transmission upon completion of the current frame until CTS2 goes low again. If so enabled, the transmit controller generates the INTTX2 interrupt to notify the TX19A core processor that the transmit buffer is empty. After the next frame is loaded into the transmit buffer, the transmit controller remains in an idle state until it detects CTS2 going low. Although the SIO2 does not have the RTS pin, any general-purpose port pins can serve as the RTS pin. The receiving device uses the RTS output to control the CTS2 input of the transmitting device. Once the receiving device has received a frame, RTS should be set to high in the receive-done interrupt handler to temporarily stop the transmitting device from sending the next frame. This way, the user can easily implement a two-way handshake protocol.
TMP19A71 TMP19A71
TX2 CTS2 Transmitting Device
RX2 RTS2 (Any port) Receiving Device
Figure 12.3.2 Handshaking Signals
Write to Transmit Buffer No transmission during this (2) period 14 13
CTS2 (1) SIOCLK TXDCLK
15
16
1
2
3
14
15
16
1
2
3
TX2
start bit
bit 0
Note 1:
If the CTS2 signal goes high in the middle of a transmission, the transmitter sotps transmission after the current frame has been sent.
Note 2:
The transmitter starts transmission at the first falling edge of the TXDCLK clock after the CTS2 signal goes low.
Figure 12.3.3 Clear-To-Send (CTS) Signal Timing
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12.3.9
Generating a Waveform with a 50% Duty Cycle
When the UART bit in the SC2MOD1 is set to 1, the UART output and the internal transmit signal are ORed, as shown in Figure 12.3.4. When the baud rate generator divisor is set to a value of N in UART mode, a waveform with a 50% duty cycle is generated. The duty ratio varies when the N+ (16-K)/16 clock division function is used.
UART Output Internal Signal Output with a 50% Duty Cycle
Figure 12.3.4 Waveform Generation with a 50% Duty Cycle (Divide-by-N)
12.3.10
Accuracy of Waveform Generation with a 50% Duty Cycle
(A) When the baud rate generator divisor is set to a value of N A waveform with a 50% duty cycle is generated. (B) When the N + (16 - K)/16 clock division function is used The duty ratio is calculated as the ratio of low width to high width as shown below. K = 0 to 8 : (K x N) +8 - K) x (N + 1): 8 x (N + 1) K = 8 to 16 : 8 x N: (K - 8) x N + (16 - K) x (N + 1) The largest deviation occurs when K = 8 and N = 1. In this case, the ratio of low width to high width is 8:16 (33%:67%).
Example: Generating 9600 bps by using the N + (16 - K)/16 clock division function System clock : fsys = 56 MHz (IMCLK = 28 MHz) Input clock Baud rate Duty ratio : IMCLK/32 = 875 KHz : 9615 bps (N = 5, K = 5) : Low:High = 43:48 = 47.25%:52.75%
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12.3.11 Transmit Buffer
The transmit buffer is double-buffered. Double-buffering can be enabled or disabled by programming the WBUF bit in the SC2MOD2. If double-buffering is enabled, a frame is first written to Transmit Buffer 2 (SC2BUF) and then transferred to Transmit Buffer 1 (shift register), causing the INTTX2 interrupt to occur and the Transmit Buffer Empty flag (SC2MOD2.TBEMP) to be set. This flag indicates that Transmit Buffer 2 is empty and a next transmit frame can be written. Writing a next frame to Transmit Buffer 2 clears the TBEMP flag. When the SCLK2 pin is configured as an input in I/O Interface mode, an underrun error occurs upon completion of transmitting a frame from Transmit Buffer 1 if a next frame is not written to Transmit Buffer 2 before the clock pulse for the next frame is input. An underrun error is indicated by the parity/underrun flag (PERR) in the SC2CR. When the SCLK2 pin is configured as an output in I/O Interface mode, the SIO2 stops outputting the SCLK2 clock after transmitting a frame which has been transferred from Transmit Buffer 2 to Transmit Buffer 1. In this mode, therefore, no underrun error occurs.
Note: When the SCLK2 pin is configured as an output in I/O Interface mode, the PERR flag in the SC2CR has no meaning; it is read as undefined. When exiting SCLK output mode, first read the SC2CR to initialize this flag.
If double-buffering is disabled, the TX19A core processor writes a transmit frame to Transmit Buffer 1. The INTTX2 interrupt is generated upon completion of transmission. If handshaking is required, Transmit Buffer 2 must be disabled by clearing the WBUF bit in the SC2MOD2. For continuous transmission without handshaking, Transmit Buffer 2 can be enabled by setting the WBUF bit to improve performance. When double-buffering is not used, do not write to Transmit Buffer 1 while a frame is being transmitted.
12.3.12 Parity Controller
For transmit operations, setting the SC2CR.PE bit to 1 enables parity generation in 7and 8-Bit UART modes. The SC2CR.EVEN bit selects either even or odd parity. If enabled, the parity controller automatically generates parity for the frame in the transmit buffer (SC2BUF). In 7-Bit UART mode, the TB7 bit in the SC2BUF holds the parity bit. In 8-Bit UART mode, the TB8 bit in the SC2MOD holds the parity bit. The parity bit is set after the frame has been transmitted. The SC2CR.PE and SC2CR.EVEN bits must be programmed prior to a write to the transmit buffer. For receive operations, the parity controller automatically computes the expected parity when a frame in Receive Buffer 1 is transferred to Receive Buffer 2 (SC2BUF). The received parity bit is compared to the SC2BUF.RB7 bit in 7-Bit UART mode and to the SC2CR.RB8 bit in 8-Bit UART mode. If a frame is received with incorrect parity, the SC2CR.PERR bit is set. In I/O Interface mode, the SC2CR.PERR bit indicates an underrun error rather than a parity error.
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TMP19A71 12.3.13 Error Flags
The SIO2 has the following three error flags for improved data reception reliability. 1. Overrun error: SC2CR.OERR In UART and I/O Interface mode, an overrun error is reported with the OERR bit set to 1 if all bits of a new frame are received before the current frame is read from the receive buffer. Reading the flag causes it to be cleared. Note that an overrun error can only be cleared by reading the receive buffer or executing a software reset using the SC2MOD2.SWRST. When the SCLK2 pin is configured as an output in I/O Interface mode, however, no overrun error occurs so that the OERR flag has no meaning and is read as undefined. 2. Parity error/underrun error: SC2CR.PERR In UART mode, this flag indicates whether a parity error has occurred. A parity error is reported when the parity bit attached to a received frame does not match the expected parity computed from the frame. Reading the flag causes it to be cleared. In I/O Interface mode, this flag indicates whether an underrun error has occurred, only when double-buffering (Transmit Buffer 2) is enabled (SC2MOD2.WBUF = 1) with the SCLK2 pin configured as an input. An underrun error is reported upon completion of transmitting a frame from Transmit Buffer 1 if a next frame is not written to Transmit Buffer 2 before the clock pulse for the next frame is input. When the SCLK2 pin is configured as an output, no underrun error occurs so that the PERR flag nas no meaning and is read as undefined. Reading the flag causes it to be cleared. 3. Framing error: SC2CR.FERR In UART mode, this flag indicates whether a framing error has occurred. A framing error is reported if a 0 is detected where a stop bit was expected. (The middle three of the 16 samples are used to determine the bit value.) Reading the flag causes it to be cleared. During reception, only a single stop bit is detected regardless of the setting of the SBLEN bit in the SC2MOD2.
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Table 12.3.4
Operating Mode UART Error Flag OERR PERR FERR I/O Interface (SCLK Input) OERR PERR
Error Flags
Function Overrun error flag Parity error flag Framing error flag Overrun error flag Underrun error flag (WBUF=1) Fixed to 0 (WBUF=0)
FERR I/O Interface (SCLK Output) OERR PERR FERR
Fixed to 0 Undefined Undefined Fixed to 0
12.3.14 Bit Transfer Sequence
The DRCHG bit in Serial Mode Control Register 2 (SC2MOD2) determines whether the most significant bit (MSB) or least significant bit (LSB) is transmitted first in I/O Interface mode. The setting of the DRCHG bit cannot be modified while the SIO is transferring data.
12.3.15 Stop Bit Length
The SBLEN bit in the SC2MOD2 determines the number of stop bits (1 or 2) used in UART mode.
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12.3.16 Status Flag
The RBFLL bit in the SC2MOD2 indicates whether Receive Buffer 2 is full when double-buffering is enabled (SC2MOD2.WBUF = 1). It is set to 1 once a received frame is transferred from Receive Buffer 1 to Receive Buffer 2. The RBFLL bit is cleared to 0 when the TX19A core processor or DMAC reads data from Receive Buffer 2. When WBUF = 0, the RBFLL bit has no meaning; it should not be used as a status flag. The TBEMP bit in the SC2MOD2 indicates whether Transmit Buffer 2 is empty when double-buffering is enabled (SC2MOD2.WBUF = 1). It is set to 1 once a transmit frame is transferred from Transmit Buffer 2 to Transmit Buffer 1 (shift register). The TBEMP bit is cleared to 0 when the TX19A core processor or DMAC stores data in Transmit Buffer 2. When WBUF = 0, the TBEMP bit has no meaning; it should not be used as a status flag.
12.3.17 Transmit/Receive Buffer Configuration
Table 12.3.5 Transmit/Receive Buffer Configuration
WBUF = 0 UART I/O Interface (SCLK Input) I/O Interface (SCLK Output) Transmit Receive Transmit Receive Transmit Receive Single Double Single Double Single Single WBUF = 1 Double Double Double Double Double Double
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12.3.18 Transmit/Receive FIFO Buffers
As shown in Figure 12.3.5 and Figure 12.3.6, a total of 16 bytes of FIFO buffer is available both in UART mode (excluding 9-Bit UART mode) and I/O Interface mode. When the FIFO buffer is used for both transmit and receive operations, 8 bytes are assigned to each. When the FIFO buffer is required for only transmit or receive, all the 16 bytes can be used as transmit or receive buffers.
Receive Buffer 1 (Shift Register)
RX2 (P85)
Receive Buffer 2 (SC2BUF)
Receive FIFO
SC2FCNF. CNFG2
Internal Bus
Figure 12.3.5 Receive FIFO Block Diagram
Transmit FIFO Internal Bus
SC2FCNF. CNFG2
Transmit Buffer 2 (SC2BUF)
Transmit Buffer 1 (Shift Register)
TX2 (P86)
Figure 12.3.6 Transmit FIFO Block Diagram
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In SCLK Output mode (in I/O Interface mode), writing data in the transmit buffer starts a transmission in half-duplex mode. If the transmit buffer contains no data, transmit operation is halted. Setting the RXE bit in the SC2MOD0 to 1 starts receive operation in half-duplex mode. Receive operation can be stopped by clearing the SC2MOD0.RXE bit to 0 before reading the last frame. When the FIFO buffer is enabled, the following sequence must be executed to stop receive operation in half-duplex mode. 1. After receiving the last frame but one, disable the receive FIFO.
2. After receiving the last frame, disable receive operation by clearing the SC2MOD0.RXE bit. 3. Enable the receive FIFO with the same conditions as before. (When the transmit FIFO is enabled, it should be kept enabled.) 4. Read the data in the FIFO. 5. Disable the receive FIFO. 6. Read the last frame. Operation in full-duplex mode is the same as transmit operation in half-duplex mode. The received data must be read before a next transmit frame has been written.
Note 1:
When the transmit FIFO is used, do not access registers other than the SC2BUF, SC2FRS, and SC2FTS.
Note 2: Note 3:
When the receive FIFO is used, do not access the SC2CR or write to the SC2FRS. Do not write to the transmit FIFO when it is full. Before writing to the transmit FIFO, check the number of bytes stored in the transmit FIFO by using the SC2FTS.TLVL field.
Note 4:
Do not read from the receive FIFO when it is empty. Before reading the receive FIFO, check the number of bytes stored in the receive FIFO by using the SC2FRS.RLVL field.
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TMP19A71 12.3.19 Signal Generation Timing
(1) I/O Interface mode Table 12.3.6 Receive operation
Interrupt (WBUF = 0) Interrupt (WBUF = 1) SCLK Input Mode SCLK Output Mode SCLK Input Mode Immediately after the rising edge of the last SCLK pulse Immediately after the rising or falling edge of the last SCLK pulse, as programmed SCLK Output Mode Immediately after the rising edge of the last SCLK pulse (i.e., immediately after the frame is transferred to Receive Buffer 2) or immediately after the frame is read from Receive Buffer 2 Immediately after the rising or falling edge of the last SCLK pulse, as programmed (i.e., immediately after the frame is transferred to Receive Buffer 2) Overrun Error SCLK Input Mode Immediately after the rising or falling edge of the last SCLK pulse, as programmed
Signal Generation Timing in I/O Interface Mode
Transmit operation
Interrupt (WBUF = 0) Interrupt (WBUF = 1) SCLK Input Mode SCLK Output Mode Immediately after the rising edge of the last SCLK pulse SCLK Input Mode Immediately after the rising or falling edge of the last SCLK pulse, as programmed SCLK Output Mode Immediately after the rising edge of the last SCLK pulse or immediately after the frame is transferred to Transmit Buffer 1 Immediately after the rising or falling edge of the last SCLK pulse, as programmed or immediately after the frame is transferred to Transmit Buffer 1 Underrun error (WBUF=1) Note 1: SCLK Input Mode Immediately after the rising or falling edge of the next SCLK pulse, as programmed
Do not modify any control registers while data is being transmitted or received (receive operation is enabled).
Note 2:
Do not disable receive operation (SC2MOD0.RXE = 0) while data is being received.
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12-19
TMP19A71
(2) UART mode Table 12.3.7 Receive operation
8 Data Bits with No Parity, Mode Interrupt Framing Error Parity Error Overrun Error 9 Data Bits 8 Data Bits with Parity 7 Data Bits with Parity 7 Data Bits wih No Parity Middle of the first stop bit Middle of the first stop bit Middle of the stop bit  Middle of the stop bit Middle of the stop bit parity bit) Middle of the stop bit Middle of the stop bit Middle of the first stop bit Middle of the stop bit
Signal Generation Timing in UART Mode
Middle of the last bit (i.e., Middle of the last bit (i.e., parity bit)
Transmit operation
8 Data Bits with No Parity, Mode Interrupt (WBUF = 0) Interrupt (WBUF = 1) 9 Data Bits Simultaneously with transferring the stop bit Immediately after the frame is transferred to Transmit Buffer 1 (i.e., simultaneously with transferring the start bit) Note 1: 8 Data Bits with Parity Simultaneously with transferring the stop bit Immediately after the frame is transferred to Transmit Buffer 1 (i.e., simultaneously with transferring the start bit) 7 Data Bits with Parity, 7 Data Bits with No Parity Simultaneously with transferring the stop bit Immediately after the frame is transferred to Transmit Buffer 1 (i.e., simultaneously with transferring the start bit)
Do not modify any control registers while data is being transmitted or received (or receive operation is enabled).
Note 2: Note 3:
Do not disable receive operation (SC2MOD0.RXE = 0) while data is being received. The "middle" in the above table means the 9th bit of SIOCLK.
TMP19A71
12-20
TMP19A71
12.4 Register Descripsion (Only channel 2 registers are described.)
Table 12.4.1
Address 0xFFFF_C480 0xFFFF_C481 0xFFFF_C484 0xFFFF_C485 0xFFFF_C488 0xFFFF_C489 0xFFFF_C490 0xFFFF_C494 0xFFFF_C498 0xFFFF_C499 0xFFFF_C49C 0xFFFF_C49D 0xFFFF_C4A0 0xFFFF_C4A1 0xFFFF_C4A4 0xFFFF_C4A5 0xFFFF_C4A8 0xFFFF_C4A9 0xFFFF_C4B0 0xFFFF_C4B4 0xFFFF_C4B8 0xFFFF_C4B9 0xFFFF_C4BC 0xFFFF_C4BD Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Mnemonic SC0MOD0 SC0MOD1 SC0CR SC0MOD2 BR0CR BR0ADD SC0BUF SC0FCNF SC0FTC SC0FRC SC0FTS SC0FRS SC1MOD0 SC1MOD1 SC1CR SC1MOD2 BR1CR BR1ADD SC1BUF SC1FCNF SC1FTC SC1FRC SC1FTS SC1FRS
SIO Register Map
Register Name
Serial 0 Mode Control Register 0 Serial 0 Mode Control Register 1 Serial 0 Control Register Serial 0 Mode Control Register 2 Baud Rate Generator Control Register (SIO0) Baud Rate Generator Additional Control Register (SIO0) Serial 0 Transmit/Receive Buffer Register Serial 0 FIFO Configuration Register Serial 0 FIFO Transmit Control Register Serial 0 FIFO Receive Control Register Serial 0 FIFO Transmit Status Register Serial 0 FIFO Receive Status Register Serial 1 Mode Control Register 0 Serial 1 Mode Control Register 1 Serial 1 Control Register Serial 1 Mode Control Register 2 Baud Rate Generator Control Register (SIO1) Baud Rate Generator Additional Control Register (SIO1) Serial 1 Transmit/Receive Buffer Register Serial 1 FIFO Configuration Register Serial 1 FIFO Transmit Control Register Serial 1 FIFO Receive Control Register Serial 1 FIFO Transmit Status Register Serial 1 FIFO Receive Status Register
Note: Although these registers are 8-bit wide, two registers at consecutive addresses can be accessed simultaneously with a 16-bit access instruction.
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12-21
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Address 0xFFFF_C4C0 0xFFFF_C4C1 0xFFFF_C4C4 0xFFFF_C4C5 0xFFFF_C4C8 0xFFFF_C4C9 0xFFFF_C4D0 0xFFFF_C4D4 0xFFFF_C4D8 0xFFFF_C4D9 0xFFFF_C4DC 0xFFFF_C4DD 0xFFFF_C4E0 0xFFFF_C4E1 0xFFFF_C4E4 0xFFFF_C4E5 0xFFFF_C4E8 0xFFFF_C4E9 0xFFFF_C4E0 0xFFFF_C4F4 0xFFFF_C4F8 0xFFFF_C4F9 0xFFFF_C4FC 0xFFFF_C4FD
Bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Mnemonic SC2MOD0 SC2MOD1 SC2CR SC2MOD2 BR2CR BR2ADD SC2BUF SC2FCNF SC2FTC SC2FRC SC2FTS SC2FRS SC3MOD0 SC3MOD1 SC3CR SC3MOD2 BR3CR BR3ADD SC3BUF SC3FCNF SC3FTC SC3FRC SC3FTS SC3FRS
Register Name Serial 2 Mode Control Register 0 Serial 2 Mode Control Register 1 Serial 2 Control Register Serial 2 Mode Control Register 2 Baud Rate Generator Control Register (SIO2) Baud Rate Generator Additional Control Register (SIO2) Serial 2 Transmit/Receive Buffer Register Serial 2 FIFO Configuration Register Serial 2 FIFO Transmit Control Register Serial 2 FIFO Receive Control Register Serial 2 FIFO Transmit Status Register Serial 2 FIFO Receive Status Register Serial 3 Mode Control Register 0 Serial 3 Mode Control Register 1 Serial 3 Control Register Serial 3 Mode Control Register 2 Baud Rate Generator Control Register (SIO3) Baud Rate Generator Additional Control Register (SIO3) Serial 3 Transmit/Receive Buffer Register Serial 3 FIFO Configuration Register Serial 3 FIFO Transmit Control Register Serial 3 FIFO Receive Control Register Serial 3 FIFO Transmit Status Register Serial 3 FIFO Receive Status Register
Note: Although these registers are 8-bit wide, two registers at consecutive addresses can be accessed simultaneously with a 16-bit access instruction.
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12-22
TMP19A71
7
Bit Symbol SC2MOD0 Read/Write (0xFFFF_C4C0) Reset Value TB8 0
Serial 2 Mode Control Register 0 6 5 4 3
CTSE 0 RXE 0 control 0: Disable 1: Enable WU R/W 0 Wake-up function 0: Disable 1: Enable 0 SM
2
1
SC
0
0
0
0
Bit 8 of a Handshake Receive transmitted control character Function 0: Disable CTS operation 1: Enable CTS operation
Serial transfer mode (for SIO2, SIO3 only) 01: 7-bit UART mode 10: 8-bit UART mode 11: 9-bit UART mode
Serial clock (for UART) 01: Baud rate generator 10: Internal clock (IMCLK) 11: External clock (SCLK2 input)
(for SIO2, SIO3 only)
00: I/O Interface mode 00: Timer TB2OUT
Wake-up function 0 1 9-bit UART mode Interrupt on every received frame Interrupt only when RB8 = 1 Other modes Don't care
Handshake ( CTS ) control (for SIO2, SIO3 only) 0 1 Disable (Accept data streams at all times) Enable
Note 1: Note 2: Note 3: Note 4: Note 5:
In I/O Interface mode, the Serial Control Register (SC2CR) is used to select a serial clock. Like the SIO2, the SIO0, SIO1 and SIO3 allows use of the timer TB2OUT as a serial clock. The SC2MOD0, SC2MOD1 and SC2MOD2 registers must be set with the RXE bit cleared to 0. After setting these registers, set the RXE bit to 1. During transmit operation in half-duplex mode (SC2MOD1.FDPX=0) in I/O Interface mode (SC2MOD0.SM=00), do not set the RXE bit to 1. The TB8 bit is not double-buffered. Before writing to this bit, make sure that double-buffering is disabled and no transmit operation is in progress.
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12-23
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Serial 2 Mode Control Register 1 7
SC2MOD1 (0xFFFF_C4C1) Bit Symbol Read/Write Reset Value Function  R/W 0
6
FDPX R/W 0 Sync method 0: Half duplex 1: Full duplex
5
 R/W 0
4
UART R/W 0 UART output 0: Normal 1: 50% duty cycle
3
 0
2
 W 0
1
 0
0
 0
Note: When the N + (16 - K)/16 clock division function is used, the duty ratio varies with the value of K.
TMP19A71
12-24
TMP19A71
Serial 2 Mode Control Register 2
SC2MOD2 (0xFFFF_C4C5)
7
Bit Symbol Read/Write Reset Value TBEMP
6
5
TXRUN
4
SBLEN
3
2
WBUF 0 Doublebuffering 0: Disable 1: Enable
1
SWRST 
0
Function
RBFLL R 1 0 Transmit Receive buffer buffer full empty flag flag 0: Full 0: Empty 1: Empty 1: Full
DRCHG R/W 0 0 0 Transmit-in Number of Bit -progress stop bits sequence flag 0: 1 bit 0: LSB first 0: Stopped 1: 2 bits 1: MSB first 1: Transmitting
00 Software reset A write of 10 followed by a write of 01
Symbol SWRST
Function A write of 10 followed by a write of 01 to this field resets the module, thus initializing the RXE bit in the SC2MOD0, the TBEMP, RBFLL and TXRUN bits in the SC2MOD2, the OERR, PERR and FERR bis in the SC2CR, and the internal circuits.
WBUF
Enables or disables double-buffering for transmit (SCLK output or input) or receive (SCLK output) operation in I/O Interface mode and transmit operation in UART mode. For any other modes of operation, double-buffering is always enabled.
DRCHG
Specifies the bit transfer sequence in I/O Interface mode. In UART mode, the LSB is always transferred first.
SBLEN
Specifies the number of transmit stop bits in UART mode. For receive operation, a single stop bit is used regardless of the setting of this bit.
TXRUN
A status flag indicating whether transmit shift operation is in progress. When this bit is set to 1, transmit operation is in progress. When this bit is cleared to 0, transmit operation is completed (if TBEMP = 1) or the trnamit buffer contains a next frame and is ready for transmission (if TBEMP= 0).
RBFLL
A flag indicating whether Receive Buffer 2 is full. The RBFLL bit is set to 1 once a received frame is transferred from Receive Buffer 1 to Receive Buffer 2. It is cleared when the frame is read from Receive Buffer 2. When double-buffering is disabled, the RBFLL bit has no meaning.
TBEMP
A flag indicating whether Transmit Buffer 2 is empty. The TBEMP bit is set to 1 once a frame is transferred from Transmit Buffer 2 to Transmit Buffer 1. It is cleared when a next frame is written to Transmit Buffer 2. When double-buffering is disabled, the TBEMP bit has no meaning.
Note 1:
If the module needs to be reset while it is transmitting data, two consecutive software reset sequences (i.e., 10, 01, 10, 01) must be executed.
Note 2:
This register does not support bit manipulation instructions.
TMP19A71
12-25
TMP19A71
Serial 2 Control Register 5 4 3
PE
7
SC2CR (0xFFFF_C4C4) Bit Symbol Read/Write Reset Value RB8 R 0 Bit 8 of a received character
6
EVEN
2
1
SCLKS
0
IOC
Function
R/W 0 0 Parity type Parity 0: Odd 0: Enable 1: Even 1: Disable
OERR PERR FERR R (Cleared when read) 0 0 0 1: Error has occurred. Overrun Parity/ underrun Framing
R/W 0 0 0: SCLK2 0: Baud rate generator 1: SCLK2 1: SCLK2 input
Input clock in I/O Interface mode (for CH2, CH3 only) 0 1 Baud rate generator SCLK2 pin input
Active edge for SCLK2 input (for CH2, CH3 only) 0 1 Data is transmitted/received on the SCLK2 rising edge. Data is transmitted/received on the SCLK2 falling edge. These bits are cleared to 0 when read.
Framing error flag Parity error/underrun error flag Overrun error flag
Patiy type 0 1 Note 1: All error flags are cleared to 0 when read. Note 2: This register does not support bit manipulation instructions. Note 3: The SC2CR.FERR bit should not be polled; instead, it should be read in the INTRX2 interrupt routine before the receive buffer is read. For details, see the example in "12.5.3 8-Bit UART Mode". Odd parity Even parity
TMP19A71
12-26
TMP19A71
Baud Rate Generator Control Register 6 5 4 3
DVS 0 N+ division function 0: Disable 1: Enable 0 00: IMCLK/2 10: IMCLK/32 11: IMCLK/128 PRE R/W 0 Must be written as Function 0. 0 0 0 0 0
7
BR2CR (0XFFFF_C4C8) Read/Write Reset Value Bit Symbol 
2
BR2S
1
0
(16 - K)/16 01: IMCLK/8 Clock divisor value N
Clock source for baud rate generator 00 01 10 11 Internal clock IMCLK/2 Internal clock IMCLK/8 Internal clock IMCLK/32 Internal clock IMCLK/128
Baud Rate Generator Additional Control Register 7 6 5 4 3 2
BR2ADD (0xFFFF_C4C9) Bit Symbol Read/Write Reset Value 0 0 0 0 0 0 BR2K R/W
1
0
0
0
Function
Value K in N +16 - K)/16
Clock divisor value for the baud rate generator BR2CR.DVS= 1 BR2CR. BR2S BR2ADD. BR2K 0000 0001(K = 1) to 1111(K = 15) Prohibited Divide by N + (16 - K)
16
BR2CR.DVS= 0 0001 (N = 1) (UART only) to 1111N = 15 0000N = 16 Divide by N Divide by N
0000 (N = 16) to 0001 (N = 1) Prohibited
0010 (N = 2) to 1111 (N = 15) Prohibited
Note 1: The baud rate generator divisor cannot be set to 1 in UART mode if the N + (16 - K)/16 clock division function is enabled. In I/O Interface mode, do not set the baud rate generator divisor to 1; setting the divisor to 1 will cause incorrect operation. Note 2: To use the N + (16 - K)/16 clock division function, the value of K must be programmed in the BR2ADD.BR2K field before setting the BR2CR.DVS bit to 1. However, the N + (16 - K)/16 clock division function is not usable when BR2CR.BR2S = 0000 (N = 16) or 0001 (N = 1). Note 3: The N + (16 - K)/16 clock division function can only be used in UART mode. In I/O Interface mode, it must be disabled by clearing the BR2CR.DVS bit to 0.
TMP19A71
12-27
TMP19A71
Serial Transmit/Receive Buffer Register 7
Bit Symbol Read/Write Reset Value Function 0 0 0 0
6
5
4
TB W
3
2
1
0
0
0
0
0
Transmit buffer SC2BUF (0xFFFF_C4D0)
7
bit Symbol Read/Write Reset Value Function Note: 0
6
5
4
RB R
3
2
1
0
0
0
0
0
0
0
0
Receive buffer
In I/O Interface mode (SC2MOD0.SM = 0), do not write to the transmit buffer during receive operation in half-duplex mode (SC2MOD1.FDPX = 0).
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12-28
TMP19A71
Serial 2 FIFO Configuration Register 7
Bit Symbol SC2FCNF (0xFFFF_C4D4) Read/Write Reset Value Function  0
6
 0
5
 R 0
4
 0
3
 0
2
 0
1
CNFG R/W 00 FIFO 00: Disable
0
01: Transmit (16 bytes) 10: Receive (16 bytes) 11: Transmit/Receive (8 bytes each) Note: For continuous transmit/receive operations using the FIFO, double-buffering must be enabled (SC2MOD2.WBUF=1).
Serial 2 FIFO Receive Control Register 7
Bit Symbol SC2FRC (0xFFFF_C4D9) Read/Write Reset Value Interrupt level Function 0000: Interrupt is generated when the receive FIFO reaches 1 byte. 0001: Interrupt is generated when the receive FIFO reaches 2 bytes. 0010: Interrupt is generated when the receive FIFO reaches 3 bytes. 0011: Interrupt is generated when the receive FIFO reachs 4 bytes. ... 1111: Interrupt is generated when the receive FIFO reaches 16 bytes. Setting has no effect when CNFG=00/01. The most significant bit must be cleared to 0 when CNFG=11. RFIS: When RFIS=0, a receive FIFO interrupt is generated only when the number of bytes stored in the receive FIFO set in the SC2FRS.RLVL matches the interrupt generation level set in the SC2FRC.RIL. When RFIS=1, a receive FIFO interrupt is generated when the number of bytes stored in the receive FIFO set in the SC2FRS.RLVL is equal to or greater than the interrupt generation level set in the SC2FRC.RIL. Note: This register does not support bit manipulation instructions.
0: Interrupt generated only when RIL=RLVL 1: Interrupt generated when RILRLVL
6
RIL
5
R/W 0000
4
3
RFIS 0
Interrupt condition
2
RFCL W 0
FIFO clear Setting this bit to 1 clears FIFO value. (This bit is always read as 0.)
1
RFIE R/W 0
Receive FIFO interrupt 0: Disable 1: Enable
0
 R 0
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12-29
TMP19A71
Serial 2 FIFO Transmit Control Register 7
Bit Symbol SC2FTC (0xFFFF_C4D8) Read/Write Reset Value Interrupt level Function 0000: Interrupt is generated when the transmit FIFO reaches 1 byte. 0001: Interrupt is generated when the transmit FIFO reaches 2 bytes. 0010: Interrupt is generated when the transmit FIFO reaches 3 byes. 0011: Interrupt is generated when the transmit FIFO reaches 4 bytes. ... 1111: Interrupt is generated when the transmit FIFO reaches 16 bytes. Setting has no effect when CNFG=00/10. The most significant bit must be cleared to 0 when CNFG=11. TFIS: When TFIS=0, a transmit FIFO interrupt is generated only when the number of bytes stored in the transmit FIFO set in the SC2FTS.TLVL matches the interrupt generation level set in the SC2FTC.TIL. When TFIS=1, a transmit FIFO interrupt is generated when the number of bytes stored in the transmit FIFO set in the SC2FTS.TLVL is equal to or smaller than the interrupt generation level set in the SC2FTC.TIL. Note: This register does not support bit manipulation instructions.
When SC2FRC.RIL=0001 When SC2FTC.TIL=1110
6
TIL
5
R/W 0111
4
3
TFIS 0
Interrupt condition
2
TFCL W 0
FIFO clear Setting this
1
TFIE R/W 0
Transmit FIFO interrupt 0Disable 1: Enable
0
 R 0
0: Interrupt generated only when TIL=TLVL. 1: Interrupt generated when TILTLVL
bit to 1 clears the FIFO value. (This bit is always read as 0.)
RLVL=00000 Receive FIFO: 0 bytes
TLVL=10000 Transmit FIFO: 16 bytes
Data received
FIFO data read
Data transmitted
FIFO data written
RLVL=00001 Receive FIFO: 1 byte Interrupt generated (RFIS=0/1) Interrupt generated (TFIS=0/1)
TLVL=01111 Transmit FIFO: 15 bytes
Data received
FIFO data read
Data transmitted
FIFO data written
RLVL=00010 Receive FIFO: 2 bytes
TLVL=01110 Transmit FIFO: 14 bytes
Data received
FIFO data read  Interrupt generated (RFIS=1)
Data transmitted
FIFO data written  Interrupt generated (TFIS=1)
RLVL=00011 Receive FIFO: 3 bytes
TLVL=01101 Receive FIFO: 13 bytes
Data received
FIFO data read  Interrupt generated (RFIS=1)
Data transmitted
FIFO data written  Interrupt generated (TFIS=1)
   Data received
   Data transmitted
FIFO data read RLVL=10000 Receive FIFO: 16 bytes  Interrupt generated (RFIS=1) TLVL=00000 Receive FIFO: 0 bytes
FIFO data written  Interrupt generated (TFIS=1)
Figure 12.4.1
Example of Interrupt Generaton Timing when Using FIFO
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12-30
TMP19A71
Serial 2 FIFO Receive Status Register 7
Bit Symbol SC2FRS (0xFFFF_C4DD) Read/Write Reset Value Function RUR 0 This bit is set to 1 when the receive FIFO is full. RUR:
6
 0 Can be read as 0.
5
4
R
3
2
RLVL 00000
1
0
0 Can be read as 0. Receive FIFO byte count 00000: 0 bytes 00001: 1 byte 00010: 2 bytes 00011: 3 bytes ... 10000: 16 bytes
The RUR bit is set to 1 if an attempt to store a new value is made when the receive FIFO is already full. This bit is cleared to 0 when it is read while the receive FIFO buffer is not full.
Note: This register does not support bit manipulation instructions.
Serial 2 FIFO Transmit Status Register 7
SC2FTS (0xFFFF_C4DC) Bit Symbol Read/Write Reset Value Function 1 This bit is set to 1 when the transmit FIFO is empty. 0 Can be read as 0. 0 Can be read as 0. Transmit FIFO byte count 00000: 0 bytes 00001: 1 byte 00010: 2 bytes 00011: 3 bytes ... 10000: 16 bytes TUR: The TUR bit is set to 1 when the transmit FIFO becomes empty. When the first byte is stored in the transmit FOFO, it is immediately transferred to the transfer buffer (SC2BUF), causing the transmit FIFO to become empty and the TUR bit to be set to 1. This bit is automatically cleared to 0 when data is written to the transmit FIFO. TUR
6
5
4
R
3
2
TLVL 00000
1
0
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12-31
TMP19A71
12.5 Operating Modes
12.5.1 I/O Interface Mode
I/O Interface mode utilizes a synchronization clock (SCLK), which can be configured for either Output mode in which the SCLK clock is driven out from the TMP19A71 or Input mode in which the SCLK clock is supplied externally. (1) Transmit operation (half-duplex) SCLK Output mode When transmit double-buffering is disabled (SC2MOD2.WBUF = 0) in SCLK Output mode, each time the TX19A core processor writes a frame to the transmit buffer, the 8 bits of the frame are shifted out on the TXD2 pin, and the synchronization clock is driven out from the SCLK2 pin. When all the bits have been shifted out, the INTTX2 interrupt is generated. When transmit double-buffering is enabled (SC2MOD2.WBUF = 1), a frame is transferred from Transmit Buffer 2 to Transmit Buffer 1 (shift register) once the TX19A core processor writes the frame to Transmit Buffer 2 when no data is being transmitted or the last frame in Transmit Buffer 1 has been sent. At this time, the transmit buffer empty flag (SC2MOD2.TBEMP) is set to 1 and the INTTX2 interrupt is generated. If there is no data to be transferred from Transmit Buffer 2 to Transmit Buffer 1, however, the INTTX2 interrupt is not generated and SCLK2 output is stopped.
Transmit Data Write Timing SCLK2 Output TX2 (INTTX2) bit 0 bit 1 bit 6 bit 7 bit 0
TBRUN Figure 12.5.1 Transmit Operation in I/O Interface Mode (SCLK Output mode, double-buffering disabled)
Transmit Data Write Timing SCLK2 Output TX2 (INTTX2) TBRUN TBEMP bit 0 bit 1 bit 6 bit 7 bit 0
Figure 12.5.2 Transmit Operation in I/O Interface Mode (SCLK Output mode, double-buffer enabled, data in Transmit Buffer 2)
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Transmit Data Write Timing SCLK2 Output TX2 (INTTX2) TBRUN TBEMP bit 0 bit 1 bit 6 bit 7
Figure 12.5.3 Transmit Operation in I/O Interface mode (SCLK Output mode, double-buffering enabled, no data in Transmit Buffer 2)
SCLK Input mode When transmit double-buffering is disabled (SC2MOD2.WBUF = 0) in SCLK Input mode, the 8 bits of a frame in the transmit buffer are shifted out on the TX2 pin when the SCLK2 input becomes active (i.e., the first rising or falling edge, as programmed) with transmit data written in the transmit buffer. The TX19A core processor must load a next frame into the transmit buffer by point A (shown in Figure 12.5.4). When transmit double-buffering is enabled (SC2MOD2.WBUF = 1), a frame is transferred from Transmit Buffer 2 to Transmit Buffer 1 (shift register) once the TX19A core processor writes the frame to Transmit Buffer 2 before the SCLK2 input becomes active or once the last frame in Transmit Buffer 1 has been sent. At this time, the transmit buffer empty flag (SC2MOD2.TBEMP) is set to 1 and the INTTX2 interrupt is generated. If the SCLK2 input becomes active before a frame is written to Transmit Buffer 2, an underrun error occurs and 8 bits of dummy data (0xFF) are sent although the internal bit counter starts counting.
Transmit Data Write Timing SCLK2 Input (SCLKS = 0: Rising Edge) SCLK2 Input (SCLKS = 1: Falling Edge) TX2 (INTTX2) bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 A
Figure 12.5.4 Transmit Operation in I/O Interface Mode (SCLK Input mode, double-bufferig disabled)
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12-33
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Transmit Data Write Timing SCLK2 Input (SCLKS = 0: Rising Edge) SCLK2 Input (SCLKS = 1: Falling Edge) TX2 (INTTX2) TBRUN TBEMP bit 0 bit 1 bit 5 bit 6 bit 7 bit 0 bit 1 A
Figure 12.5.5 Transmit Operation in I/O Interface Mode (SCLK Input mode, double-buffering enabled, data in Transmit Buffer 2)
Transmit Data Write Timing SCLK2 Input (SCLKS = 0: Rising Edge) SCLK2 Input: (SCLKS = 1: Falling Edge) TX2 (INTTX2) TBRUN TBEMP PERR (Underrun error) bit 0 bit 1 bit 5 bit 6 bit 7  1 A
Figure 12.5.6 Transmit Operation in I/O Interface Mode (SCLK Input mode, double-buffering enabled, no data in Transmit Buffer 2)
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(2) Receive operation (half-duplex) SCLK Output mode When receive double-buffering is disabled (SC2MOD2.WBUF = 0) in SCLK Output mode, each time the TX19A core processor picks up the frame in Receive Buffer 1, the synchronization clock is driven out from the SCLK2 pin to shift the next frame into Receive Buffer 1. When a whole-8-bit frame has been received in Receive Buffer 1, the INTRX2 interrupt is generated. The SCLK output is initiated by setting the SC2MOD0.RXE bit to 1. When receive double-buffering is enabled (SC2MOD2.WBUF = 1), the frame received first is transferred to Receive Buffer 2 and then a next frame is received into Receive Buffer 1. Once a frame is transferred from Receive Buffer 1 to Receive Buffer 2, the Receive Buffer Full flag (SC2MOD2.RBFULL) is set to 1 and the INTRX2 interrupt is generated. After a frame has been transferred to Receive Buffer 2, the TX19A core processor or DMAC should read it before all 8 bits of a next frame are received. Otherwise, the INTRX2 interrupt is not generated and SCLK2 output is stopped. If the TX19A core processor or DMAC subsequently reads the frame in Receive Buffer 2 in this state, the next frame is transferred from Receive Buffer 1 to Receive Buffer 2, generating the INTRX2 interrupt to restart receive operation.
Receive Data Read Timing SCLK2 Output RX2 (INTRX2) bit 0 bit 1 bit 6 bit 7 bit 0
Figure 12.5.7 Receive Operation in I/O Interface Mode (SCLK Output mode, double-buffering disabled)
Receive Data Read Timing SCLK2 Output RX2 (INTRX2) RBFULL bit7 bit 0 bit 1 bit 6 bit 7 bit 0
Figure 12.5.8 Receive Operation in I/O Interface Mode (SCLK Output mode, double-buffering enabled, reading Receive Buffer 2)
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Receive Data Read Timing SCLK2 Output RX2 (INTRX2) RBFULL bit7 bit 0 bit 1 bit 6 bit 7
Figure 12.5.9 Receive Operation in I/O Interface Mode (SCLK Output mode, double-buffering enabled, not reading Receive Buffer 2) SCLK Input mode In SCLK Input mode, receive double-buffering is always enabled. A received frame is transferred to Receive Buffer 2 so that a next frame can be received continuously into Receive Buffer 1. The INTRX2 interrupt is generated every time a frame is transferred from Receive Buffer 1 to Receive Buffer 2.
Receive Data Read Timing SCLK2 Input (SCLKS = 0: Rising Edge) SCLK2 Input (SCLKS = 1: Falling Edge) RX2 (INTRX2) RBFULL bit 0 bit 1 bit 5 bit 6 bit 7 bit 0
Figure 12.5.10
Receive Operation in I/O Interface Mode
(SCLK Input mode, reading Receive Buffer 2)
Receive Data Read Timing SCLK2 Input (SCLKS = 0: Rising Edge) SCLK2 Input (SCLKS = 1: Falling Edge) RX2 (INTRX2) RBFULL OERR bit 0 bit 1 bit 5 bit 6 bit 7 bit 0
Figure 12.5.11
Receive Operation in I/O Interface Mode
(SCLK Input mode, not reading Receive Buffer 2)
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TMP19A71
Note: To perform receive operation, the SC2MOD0.RXE bit must be set to 1 in both SCLK Input and SCLK Output modes.
(3) Transmit/receive operation (full-duplex) Setting the SC2MOD1.FDPX2 bit to 1 enables full-duplex communication. SCLK Output mode When transmit/receive double-bufferig is disabled (SC2MOD2.WBUF = 0) in SCLK Output mode, each time the TX19A core processor writes a frame to the transmit buffer, the synchronization clock is driven out from the SCLK2 pin to shift an 8-bit frame into Receive Buffer 1, generating the INTRX2 interrupt. At the same time, the frame written to the transmit buffer is shifted out on the TX2 pin. When all the bits have been shifted out, the transmit-done interrupt (INTTX2) is generated and SCLK2 output is stopped. When the TX19A core processor subsequently picks up the frame in the receive buffer and writes a next frame to the transmit buffer, next transmit/receive operation starts, regardless of whether the TX19A core processor first reads the receive buffer or writes data to the transmit buffer. When transmit/receive double-buffering is enabled (SC2MOD2.WBUF = 1), each time the TX19A core processor writes a frame to Transmit Buffer 2, the synchronization clock is driven out from the SCLK2 pin to shift an 8-bit frame into Receive Buffer 1; it is then transferred to Receive Buffer 2, generating the INTRX2 interrupt. At the same time, the frame stored in Transmit Buffer 1 is shifted out on the TXD2 pin. When all the bits have been shifted out, the transmit-done interrupt (INTTX2) is generated and the next frame is transferred from Transmit Buffer 2 to Transmit Buffer 1. Durnig the above sequence, SCLK output is stopped if Transmit Buffer 2 becomes empty (SC2MOD2.TBEMP = 1) or if Receive Buffer 2 still contains data (SC2MOD2.RBFULL = 1). When the TX19A core processor suqsequently picks up the frame in Receive Buffer 2 and writes a next frame to Transmit Buffer 2, SCLK2 output is restarted so that next transmit/receive operation starts.
Receive Data Read Timing Transmit Data Write Timing SCLK2 Output TX2 RX2 (INTTX2) (INTRX2) bit 0 bit 0 bit 1 bit 1 bit 5 bit 5 bit 6 bit 6 bit 7 bit 7 bit 0 bit 0 bit 1 bit 1
Figure 12.5.12
Transmit/Receive Operation in I/O Interface Mode
(SCLK Output mode, double-buffering disabled)
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Receive Data Read Timing Transmit Data Write Timing SCLK2 Output TX2 RX2 (INTTX2) (INTRX2) bit 0 bit 0 bit 1 bit 1 bit 5 bit 5 bit 6 bit 6 bit 7 bit 7 bit 0 bit 0 bit 1 bit 1
Figure 12.5.13
Transmit/Receive Operation in I/O Interface Mode
(SCLK Output mode, double-buffering enabled, no next data)
Receive Data Read Timing Transmit Data Write Timing SCLK2 Output TX2 RX2 (INTTX2) (INTRX2) bit 0 bit 0 bit 1 bit 1 bit 5 bit 5 bit 6 bit 6 bit 7 bit 7
Figure 12.5.14
Transmit/Receive Operation in I/O Interface Mode
(SCLK Output mode, double-buffering enabled, continuous transfer)
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SCLK Input mode When transmit double-buffering is disabled (SC2MOD2. WBUF = 0) in SCLK Input mode (receive double-buffering is always enabled in this mode), the TX19A core processor must write a frame to the transmit buffer before the SCLK2 input becomes avtive. The 8 bits of a frame in the transmit buffer are shifted out on the TX2 pin, and the 8 bits of a received frame are shifted into Receive Buffer 1, synchronous to the programmed edge of the SCLK2 input. When all the bits have been shifted out, the transmit-done interrupt (INTTX2) is generated. When all the bits have been received, the frame is transferred from Receive Buffer 1 to Receive Buffer 2, generating the INTRX2 interrupt. The TX19A core processor must load a next frame into the transmit buffer before the SCLK signal for the next frame is input (i.e., by point A shown in Figure 12.5.15 below). The TX19A core processor must also pick up the frame in Receive Buffer 2 before a next frame has been received. When transmit/receive double-buffering is enabled (SC2MOD2.WBUF = 1), a frame is transferred from Transmit Buffer 2 to Transmit Buffer 1 once the last frame in Transmit Buffer 1 has been sent. At this time, the INTTX2 interrupt is generated. When the 8-bit frame, received in parallel with transmission, has been shifted into Receive Buffer 1, it is transferred to Receive Buffer 2, generating the INTRX2 interrupt. When the SCLK2 is subsequently activated, the frame stored in Transmit Buffer 1 is shifted out while a next frame is received into Receive Buffer 1. If the TX19A core processor does not read the frame from Receive Buffer 2 before the last bit of a next frame is received, an overrun error occurs. If the TX19A core processor does not write a frame to Transmit Buffer 2 before the SCLK2 input is subsequently activated, an underrun error occurs.
A
Receive Data Read Timing Transmit Data Write Timing SCLK2 input
TX2 RX2 (INTTX2) (INTRX2)
bit 0 bit 0
bit 1 bit 1
bit 5 bit 5
bit 6 bit 6
bit 7 bit 7
bit 0 bit 0
bit 1 bit 1
Figure 12.5.15
Transmit/Receive Operation in I/O Interface Mode
(SCLK Input mode, double-buffering disabled)
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Receive Data Read Timing Transmit Data Write Timing SCLK2 Input
TX2 RX2 (INTTX2) (INTRX2)
bit 0 bit 0
bit 1 bit 1
bit 5 bit 5
bit 6 bit 6
bit 7 bit 7
bit 0 bit 0
bit 1 bit 1
Figure 12.5.16
Transmit/Receive Operation in I/O Interface Mode
(SCLK Input mode, double-buffering enabled, no error occurred)
Receive Data Read Timing Transmit Data Write Timing SCLK2 Input
TX2 RX2 (INTTX2) (INTRX2) PERR (Underrun Error)
bit 0 bit 0
bit 1 bit 1
bit 5 bit 5
bit 6 bit 6
bit 7 bit 7
bit 0 bit 0
bit 1 bit 1
Figure 12.5.17
Transmit/Receive Operation in I/O Interface Mode
(SCLK Input mode, double-buffering enabled, an underrun error occurred)
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12.5.2
7-Bit UART Mode
Setting the SM field in the SC2MOD0 to 01 puts the SIO2 in 7-Bit UART mode. In this mode, the parity bit can be added to the transmitted frame, and the receiver can perform a parity check on incoming data. Parity can be enabled and disabled through the programming of the PE bit in the SC2CR. When the PE bit is set to 1 to enable parity, the SC2CR.EVEN bit selects even or odd parity. The SBLEN bit in the SC2MOD2 specifies the number of stop bits.
Example: Transmitting 7-bit UART frames with an even-parity bit
start
bit 0
1
2
3
4
5
6
even parity
stop
Clocking conditions:
System clock: IMBUS clock Prescaler clock Transfer rate
: 56 MHz : 1/2 (28 MHz) : IMCLK/32 : 4800 bps (fsys = 56 MHz)
765 P8CR -1- P8FR1 -1- SC2MOD0  X 0 - SC2CR X11 BR2CR 011 BR2ADD  0 0 0 IMR52 -10 SC2BUF  X * * Note: X = Don't care,
43210
----- ----- X0101
Configure the P86 pin as TX2. Select 7-Bit UART mode. Select even parity. N=11, and K is valid. IMCLK/32 Set the transfer rate to 4800 bps. (K = 10) Enable the INTTX2 interrupt and set its priority level to 4. Load the transmit buffer with a frame.
XXX00 010X1 01010 0-100 ***** -: No change
12.5.3
8-Bit UART Mode
Setting the SM field in the SC2MOD0 to 10 puts the SIO2 in 8-Bit UART mode. In this mode, the parity bit can be added to the transmitted frame, and the receiver can perform a parity check on incoming data. Parity can be enabled and disabled through the programming of the PE bit in the SC2CR. When the PE bit is set to 1 to enable parity, the SC2CR.EVEN bit selects even or odd parity.
Example: Transmitting 8-bit UART frames with an odd-parity bit
start
bit 0
1
2
3
4
5
6
7
odd parity
stop
Clocking conditions
System clock High-speed clock gear Prescaler clock Transfer rate
: 56 MHz : 1/2 (28 MHz) : IMCLK/32 : 9600 bps (fsys = 56 MHz)
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*
Settings in the main routine 76543210 P8IER P8FR1 SC2MOD0 SC2CR BR2CR BR2ADD IMR53 SC2MOD0
--0----- --1----- -00X1001 X01XXXXX 01100101 00000101 -100-100 --1X----
Configure the P85 pin as RX2. Select 8-Bit UART mode. Select odd parity. N=5, and K is valid. Set the transfer rate to 9600 bps. (K = 5) Enable the INTRX2 interrupt and set its priority level to 4. Enable reception.
*
Example of interrupt routine processing ICLR  0 1 1 0 1 0 1 0 0 Reg.  SC2CR AND 0x1C if Reg.  0 then error Reg.  SC2BUF End of interrupt processing Note: X = Don't care, -: No change Clear the interrupt request. Check for errors. Read received data.
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TMP19A71 12.5.4 9-Bit UART Mode
Setting the SM field in the SC2MOD0 to 11 puts the SIO2 in 9-Bit UART mode. In this mode, the parity bit cannot be used and must be disabled by clearing the SC2CR.PE bit to 0. For transmit operation, the most-significant bit (9th bit) is stored in the TB8 bit in the SC2MOD0. For receive operation, the most-significant bit is stored in the RB8 bit in the SC2CR. Reads and writes from and to the transmit and receive buffers must be done with the most-significant bit first, followed by the SC2BUF. The SBLEN bit in the SC2MOD2 specifies the number of stop bits. Wake-up feature In 9-Bit UART mode, the wake-up feature can be enabled for slave controllers by setting the WU bit in the SC2MOD0 to 1. When this feature is enabled, the INTRX2 interrupt is generated only when SC2CR.RB8 = 1.
TX2
RX2
TX2
RX2
TX2
RX2
TX2
RX2
Master
Slave 1
Slave 2
Slave 3
Note:
The TX2 pin of a slave controller must be configured as an open-drain output by programming the Port 8 Open-Drain Control Register (P8ODCR).
Figure 12.5.18
Serial Link Using the Wake-Up Feature
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Protocol (1) Put all the master and slave controllers in 9-Bit UART mode. (2) Enable the receiver in each slave controller by setting the SC2MOD0.WU bit to 1. (3) The master controller transmits an 8-bit address frame (i.e., select code) that identifies a slave controller. The most-significant bit (TB8) of an address frame is a 1.
start
bit 0
1
2
3
4
5
6
7
8 "1"
stop
Slave controller select code
(4) Each slave controller compares the received address to its station address and clears the WU bit to 0 if they match. (5) The master controller transmits a block of data to the selected salve controller (with SC2MOD.WU = 0). The most-significant bit (TB8) of a data frame is a 0.
start
bit 0
1
2
3 Data
4
5
6
7
bit 8 "0"
stop
(6) Slave controllers not addressed (with SC2MOD.WU = 1) continue to monitor the data stream but discard any frames with the most-significant bit (RB8) cleared to 0. Thus, the receive-done interrupt (INTRX2) is not generated. The addressed slave controller (with SC2MOD.WU = 0) can transmit data to the mater controller to notify that is has successfully received the message.
Example: Connecting a master controller with two slave controllers through a serial link using the IMCLK/2 clock as a serial clock
TX2
RX2 Master
TX2
RX2 Slave 1
TX2
RX2 Slave 2
Select Code 00000001
Select Code 00001010
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3) Master controller setings
Main routine P8IER P8CR P8FR1 IMR53 IMR52
    
- - - - -
---- ---- 11---- 100-10 100-10
10 10
- - -
1 0
Configure the P86 pin as TX2 and the P85 pin as RX2.
Enable INTRX2 and set its interrupt level to 5. Enable INTTX2 and set its interrupt level to 4. Select 9-Bit UART mode and select IMCLK as a serial clock. Load the select code for slave 1.
SC2MOD0  1 0 1 0 1 1 1 0 SC2BUF 00000001 Interrupt routine (INTTX2) ICLR  0 1 1 0 1 0 0 0 0 SC2MOD0  0 - - - - - - - SC2BUF ******** End of interrupt processing
Clear the interrupt request. Clear the TB8 bit to 0. Load transmit data.
4)
Slave controller settings
Main routine P8IER P8CR P8FR1 P8ODCR IMR53 IMR52 SC2MOD0
-10---- -10---- -11---- -1----- - - -
Set the P86 pin as TX2 (open-drain output) and the P85 pin as RX2.
- --110110 --110101 00111110
Enable INTTX2 and INTRX2. Select 9-Bit UART mode, select IMCLK as a serial clock and set the WU bit to 1.
Interrupt routine (INTRX2) ICLR Reg.  011010100  SC2CR AND 0x1C Clear the interrupt request. Check for errors.
if Reg.  0 then error Reg.  SC2BUF if Reg. = Select code Then SC2MOD0  - - - 0 - - - -
Clear the WU bit to 0.
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13. Analog-to-Digital Converters (ADCs)
The TMP19A71 contains two 10-bit successive-approximation analog-to-digital converters (ADCs). Both ADCs have two modes; Normal mode and PMD mode. While Normal mode supports typical AD conversion with two 8-channel inputs, PMD mode is specifically designed for AD conversion for motor control. In PMD mode, the ADCs have 8-channel and 11-channel inputs. The two ADCs can be programmed to operate independently, and the operating mode can be separately selected for each of the ADCs.
13.1 Features
13.1.1
1 2 3 4 5
Normal Mode
Two 8-channel, 10-bit AD converters are available. Each channel has a separate conversion result register. The two AD converters can be independently programmed for Fixed-Channel or Channel Scan mode. The two AD converters can be independently programmed for Single Conversion or Continuous Conversion mode. The INTAD0/1 interrupt is generated upon completion of a conversion. The interrupt interval is selectable. Setting register enables starting of an AD conversion under the following conditions: * TMRB interrupt (INTTB1) * * External trigger input (ADTRG0/1) Software trigger (ADSFT0)
The highest-priority conversion can interrupt the ongoing conversion in Channel Scan and Fixed-Channel Continuous Conversion modes (The highest-priority conversion can only initiated by software). 7 The INTADHP0/1 interrupt is generated upon completion of the highest-priority conversion. 8 AD conversions can be monitored via the Busy and Overrun flags. 9 In Channel Scan Continuous Conversion mode, the interval between conversions can be selected. 10 The conversion result can be compared to the two compare registers. The user can select whether or not to generate an interrupt when the conversion result equals the compare register. 6
13.1.2
1 2 3 4
PMD Mode
Two 10-bit AD converters are available. One has 8 conversion result registers, and the other has 11 conversion result registers. The conversion enable, input channel and PMD timing trigger can be programmed independently for each conversion result register. Conversions are started in ascending order from the smallest-numbered enabled conversion result register. The conversion interval can be increased by a maximum of 255 times the PMD trigger interval.
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13.2 Register Description
Each of the two ADCs contains a group of registers for both Normal mode and PMD mode as shown in Table 13.2.1. Table 13.2.1 ADC Register Map (1/3) Normal Mode (ADC0)
Address 0xFFFFC900 0xFFFFC904 0xFFFFC908 0xFFFFC90C 0xFFFFC910 0xFFFFC914 0xFFFFC918 0xFFFFC91C 0xFFFFC920 0xFFFFC924 0xFFFFC925 0xFFFFC928 0xFFFFC92C 0xFFFFC92C 0xFFFFC930 0xFFFFC934 0xFFFFC938 0xFFFFC93C 0xFFFFC940 Bits 16 16 16 16 16 16 16 16 16 8 8 16(8) 8 8 16 16 16 8 Mnemonic ADNRES0 ADNRES1 ADNRES2 ADNRES3 ADNRES4 ADNRES5 ADNRES6 ADNRES7 ADCHPR0 Register Name AD Normal Mode Result Register 0 AD Normal Mode Result Register 1 AD Normal Mode Result Register 2 AD Normal Mode Result Register 3 AD Normal Mode Result Register 4 AD Normal Mode Result Register 5 AD Normal Mode Result Register 6 AD Normal Mode Result Register 7 Highest-Priority Conversion Result Register (ADC0)
16(8) ADNMOD0 (L) AD Normal Mode Control Register (Low) (ADC0) ADNMOD0H AD Normal Mode Control Register High (ADC0) ADNCLK0 AD Normal Mode Clock Control Register (ADC0) CMPCTL0 (L) AD Monitor Control Register (Low) (ADC0) CMPCTL0H AD Monitor Control Register High (ADC0) ADCHPC0 ADCMP00 ADCMP01 Highest-Priority Conversion Control Register (ADC0) AD Compare Register 0(ADC0) AD Compare Register 1 (ADC0)
ADCBASN0 AD Normal Mode Basic Setting Register (ADC0) ADCSTART0 AD Software Start Register (ADC0)
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Table 13.2.2 ADC Register Map (2/3) Normal Mode (ADC1)
Address 0xFFFFC980 0xFFFFC984 0xFFFFC988 0xFFFFC98C 0xFFFFC990 0xFFFFC994 0xFFFFC998 0xFFFFC99C 0xFFFFC9A0 0xFFFFC9A4 0xFFFFC9A5 0xFFFFC9A8 0xFFFFC9AC 0xFFFFC9AC 0xFFFFC9B0 0xFFFFC9B4 0xFFFFC9B8 0xFFFFC9BC 0xFFFFC9C0 Bits 16 16 16 16 16 16 16 16 16 8 8 8 8 16 16 16 8 Mnemonic ADNRES8 ADNRES9 ADNRES10 ADNRES11 ADNRES12 ADNRES13 ADNRES14 ADNRES15 ADCHPR1 ADNMOD1H ADNCLK1 CMPCTL1H ADCHPC1 ADCMP10 ADCMP11 ADCBASN1 Register Name AD Normal Mode Result Register 8 AD Normal Mode Result Register 9 AD Normal Mode Result Register 10 AD Normal Mode Result Register 11 AD Normal Mode Result Register 12 AD Normal Mode Result Register 13 AD Normal Mode Result Register 14 AD Normal Mode Result Register 15 Highest-Priority Conversion Result Register (ADC1) AD Normal Mode Control Register High (ADC1) AD Normal Mode Clock Control Register (ADC1) AD Monitor Control Register High (ADC1) Highest-Priority Conversion Control Register (ADC1) AD Compare Register 0(ADC1) AD Compare Register 1 (ADC1) A/D Normal Mode Basic Setting Register (ADC1)
16(8) ADNMOD1 (L) AD Normal Mode Control Register (Low) (ADC1)
16(8) CMPCTL1 (L) AD Monitor Control Register (Low) (ADC1)
ADCSTART1 AD Software Start Register (ADC1)
PMD Mode (ADC0)
Address 0xFFFFCD00 0xFFFFCD04 0xFFFFCD08 0xFFFFCD0C 0xFFFFCD10 0xFFFFCD14 0xFFFFCD18 0xFFFFCD1C 0xFFFFCD40 0xFFFFCD41 0xFFFFCD48 0xFFFFCD49 0xFFFFCD4C 0xFFFFCD4D 0cFFFFCD58 0xFFFFCD5C 0xFFFFCD60 0xFFFFCD61 0xFFFFCD64 0xFFFFCD65 0xFFFFCD68 0xFFFFCD6C 0xFFFFCD70 Bits 16 16 16 16 16 16 16 16 16(8) 8 16(8) 8 16(8) 8 8 8 16(8) 8 16(8) 8 8 16 8 Mnemonic ADPRES0 ADPRES1 ADPRES2 ADPRES3 ADPRES4 ADPRES5 ADPRES6 ADPRES7 ADCSETT00H ADCSET00H ADCSET01H ADPCLK0 ADPMOD00 ADPMOD01H ADCNE0 (L) ADCNE0H ADCNT0 ADCBASP0 ADMODSEL0 Register Name AD PMD Mode Result Register 0 AD PMD Mode Result Register 1 AD PMD Mode Result Register 2 AD PMD Mode Result Register 3 AD PMD Mode Result Register 4 AD PMD Mode Result Register 5 AD PMD Mode Result Register 6 AD PMD Mode Result Register 7 AD Input Timing Trigger Register 0 High (ADC0) AD Input Port Select Register 0 High (ADC0) AD Input Port Select Register 1 High (ADC0) AD PMD Mode Clock Control Register (ADC0) AD PMD Mode Control Register 0 (ADC0) AD PMD Mode Control Register 1 High (ADC0) A/D Count Enable Register (Low) (ADC0) A/D Count Enable Register High (ADC0) A/D Conversion Count Setting Register (ADC0) A/DPMD Mode Basic Setting Register (ADC0) AD Mode Control Register (ADC0)
ADCSETT00 (L) AD Input Timing Trigger Register 0 (Low) (ADC0) ADCSET00 (L) AD Input Port Select Register 0 (Low) (ADC0) ADCSET01 (L) AD Input Port Select Register 1 (Low) (ADC0)
ADPMOD01 (L) AD PMD Mode Control Register 1 (Low) (ADC0)
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Table 13.2.3 ADC Register Map(3/3) PMD Mode (ADC1)
Address 0xFFFFCD80 0xFFFFCD84 0xFFFFCD88 0xFFFFCD8C 0xFFFFCD90 0xFFFFCD94 0xFFFFCD98 0xFFFFCD9C 0xFFFFCDA0 0xFFFFCDA4 0xFFFFCDA8 0xFFFFCDC0 0xFFFFCDC1 0xFFFFCDC4 0xFFFFCDC8 0xFFFFCDC9 0xFFFFCDCC 0xFFFFCDCD 0xFFFFCDD0 0xFFFFCDD1 0xFFFFCDD8 0xFFFFCDDC 0xFFFFCDE0 0xFFFFCDE1 0xFFFFCDE4 0xFFFFCDE5 0xFFFFCDE8 0xFFFFCDEC 0xFFFFCDF0 Bits 16 16 16 16 16 16 16 16 16 16 16 8 8 Mnemonic ADPRES8 ADPRES9 ADPRES10 ADPRES11 ADPRES12 ADPRES13 ADPRES14 ADPRES15 ADPRES16 ADPRES17 ADPRES18 ADCSETT10H ADCSETT11 Register Name AD PMD Mode Result Register 8 AD PMD Mode Result Register 9 AD PMD Mode Result Register 10 AD PMD Mode Result Register 11 AD PMD Mode Result Register 12 AD PMD Mode Result Register 13 AD PMD Mode Result Register 14 AD PMD Mode Result Register 15 AD PMD Mode Result Register 16 AD PMD Mode Result Register 17 AD PMD Mode Result Register 18 AD Input Timing Trigger Register 0 High (ADC1) AD Input Timing Trigger Register 1 (ADC1)
16(8) ADCSETT10 (L) AD Input Timing Trigger Register 0 (Low) (ADC1)
16(8) ADCSET10 (L) AD Input Port Select Register 0 (Low) (ADC1) 8 ADCSET10H AD Input Port Select Register 0 High (ADC1)
16(8) ADCSET11 (L) AD Input Port Select Register 1 (Low) (ADC1) 8 8 8 8 8 8 8 16 8 ADCSET11H ADCSET12H ADPCLK1 ADPMOD10 ADPMOD11H ADCNE1H ADCNT1 ADCBASP1 ADMODSEL1 AD Input Port Select Register 1 High (ADC1) AD Input Port Select Register 2 High (ADC1) AD PMD Mode Clock Control Register (ADC1) AD PMD Mode Control Register 0 (ADC1) AD PMD Mode Control Register 1 High (ADC1) A/D Counting Conversion Enable Register (Low) (ADC1) A/D Counting Conversion Enable Register High (ADC1) A/D Conversion Count Setting Register (ADC1) A/DPMD Mode Basic Setting Register (ADC1) AD Mode Control Register (ADC1) 16(8) ADCSET12 (L) AD Input Port Select Register 2 (Low) (ADC1)
16(8) ADPMOD11 (L) AD PMD Mode Control Register 1 (Low) (ADC1) 16(8) ADCNE1 (L)
Note 1: Some of 16-bit ADC registers is accessible in 8-bit system by dividing higher 8bits and lower 8 bits. i.e. ADNMOD0 becomes accessible in 8-bit system by making it be ADNMOD0L/ADNMOD0H.
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The MODSEL bit in the ADMODSEL0 register is used to select either Normal mode (MODSEL = 0) or PMD mode (MODSEL = 1). Normal mode provides the AD monitor and highest-priority conversion features. PMD mode is synchronous to the trigger inputs from a programmable motor driver (PMD). In Normal mode, the two ADCs are basically functionally equivalent; in the following description any references to ADC0 also apply to ADC1.
AD Mode Control Register (ADC0) 7
Bit Symbol ADMODSEL0 (0xFFFF_CD70) Read/Write Reset Value Function  0
6
 0
5
 0
4
 R/W 0
3
 0
2
 0
1
VREFON 0 VREF control 0: OFF 1: ON
0
MODSEL 0 ADC conversion mode 0: Normal mode 1: PMD mode
Note 1: The MDOSEL bit must not be changed during an AD conversion. If it is changed, operation cannot be guaranteed. Note 2: Registers other than those for the selected conversion mode must not be programmed. Before programming registers, the MODSEL bit must be programmed to select Normal or PMD mode. Note 3: The VREFON bit must be set 3 us before an AD conversion is started to ensure the stable internal reference voltage. If an AD conversion is started with VREFON= 0 or before the internal reference voltage has stabilized, conversion accuracy cannot be guaranteed. Note 4: The VREFON bit is automatically set to 1 after an AD conversion is started. However, conversion accuracy cannot be guaranteed until the reference voltage has stabilized (see Note 3).
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13.3
Normal Mode (ADMODSEL0.MODSEL=0)
AD Normal Mode Control Register (Low) (ADC0) 7 6 3
ADCH R/W 0
Must be set to 0.
4
3
LAT
2
ITM 0
1
REP 0
0
SCAN 0
Channel scan mode 0:FixedChannel 1: Channel Scan
Bit Symbol ADNMOD0(L) (0xFFFF_C924) Read/Write Reset Value Function
 0
0
0
0
Latency 0: None 1: Wait until the result register is read.
Analog input channel select
Interrupt in Continuous Fixedconversion Channel mode Continuous 0: Single Conversion 1: Continumode ous
Analog Input Channel Select
SCAN ADCH0 [2:0] 000 001 010 011 100 101 110 111 0 1 Interrupt in Fixed-Channel Continuous Conversion Mode Fixed-Channel Continuous Conversion Mode SCAN=0, REP=1 0 1 Generate an interrupt when a single conversion has been completed. Generate an interrupt when a sequence of four conversions has been completed. Fixed-Channel Mode Channel Scan Mode AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN0 AIN0 to AIN1 AIN0 to AIN2 AIN0 to AIN3 AIN0 to AIN4 AIN0 to AIN5 AIN0 to AIN6 AIN0 to AIN7 In ADC1, the input channels correspond as follows: AIN0AIN8 AIN1AIN9 AIN2AIN10 AIN3AIN11 AIN4AIN12 AIN5AIN13 AIN6AIN14 AIN7AIN15 Note 1: AIN7 pin (AIN15 pin for ADC1) may be used as ADTRG0 input pin. Therefore, when ADTRG0 is used in ADNMOD0= "10", do not set to ADNMOD0="111," and when ADTRG1 is used in ADNMOD1="11," do not set to ADNMOD1="111." Note 2: ADNMOD0 setting becomes effective only when it is in Continuous Conversion mode. When ADNMOD 0="1" is set, the next conversion does not start until the reading of the register stored at the end is finished. For example, when ADNMOD0="101," ADNMOD0="1," ADNMOD0="1," and
ADNMOD0="1," the next conversion does not start until reading of the result for ADNRES5 after Channel Scan conversion has finished. When ADNRES5 is read prior to ADNRES0 - 4, the next conversion starts as ADNRES5 starts to be read. And, when ADNMOD0="101," ADNMOD0="1," ADNMOD0="1," ADNMOD0="1," and ADNMOD0="0," the next conversion does not start until the results are stored four times in ADNRES5 and are read out.
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AD Normal Mode Control Register (High) (ADC0) 15
(ADNMOD0H) Bit Symbol (0xFFFF_C925) Read/Write Reset Value Function  0
14
 R 0
13
 0
12
 0 Must be set to 0.
11
 0 Must be set to 0.
10
TRGE R/W 0 Normal mode conversion trigger 0: Software 1: Hardware
9
TSEL
8
0 0 Hardware trigger source 00: Reserved 01: INTTBCOM11 10: ADTRG0 11: ADTRG1
Note 1: When ="1" is set, too, it can be started up by software. Note 2: ADC1 also can select INTTBCOM11 as a hardware starting source by setting ADNMOD1=01.
AD Software Start Register (ADC0) 7
ADCSTART0 bit Symbol (0xFFFF_C940) Read/Write Reset Value Function BUSY R 0
Normal mode AD conversion busy flag 0: Idle 1: Busy
6
EOS R/W 0
Conversion Complete flag 0: Don't care 1:Completed Write a 0 to clear this bit.
5
 0
4
 0
3
 R 0
2
 0
1
 0
0
ADSFT W 0
AD conversion start 0:Don't care 1:Start This bit is always read as 0.
Note: The BUSY bit indicates whether or not an AD conversion is in progress. Use the EOS bit to check whether or not an AD conversion has completed.
A/D Normal Mode Basic Setting Register (ADC0) 7
ADCBASN0 (0xFFFF_C93C) Bit Symbol Read/Write Reset Value Function 0 Must be set to 0. 0 Must be set to 0. 0 Must be set to 0. 0 Must be set to 0. 
6
5
4
 R/W
3
 0 Must be set to 0.
2
AZSEL
1
0
 0 Must be set to 0.
0 0 Must be Sample set to 0. Hold time 1: 6 clocks 0: 12 clocks
15
Bit Symbol Read/Write Reset Value Function 0 Must be set to 0. 
14
 0 Must be set to 0.
13
 0 Must be set to 0.
12
 R/W 1 Must be set to 1.
11
 0 Must be set to 0.
10
 0 Must be set to 0.
9
 0 Must be set to 0.
8
 0 Must be set to 0.
Note: The time taken for the conversion of ADC is derived from the equation, (the number of clocks selected in 27 clocks)/ADCLK.
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Highest-Priority Conversion Control Register (ADC0) 7
Bit Symbol ADCHPC0 (0xFFFF_C930) Read/Write Reset Value Function  0
6
 R 0
5
 0
4
HBSY 0
HighestPriority AD conversion busy flag 0: Completed 1: Busy
3
HPRQ
2
R/W
1
HPCH
0
0
HighestPriority conversion request 0: Don't care 1: Start highestpriority conversion
0
0
0
Highest-priority channel select
Highest-Priority Analog Input Channel Select SCAN ADCH [2:0] 000 001 010 011 100 101 110 111 0 Fixed-Channel Mode AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 In ADC1, the input channels correspond as follows: AIN0AIN8 AIN1AIN9 AIN2AIN10 AIN3AIN11 AIN4AIN12 AIN5AIN13 AIN6AIN14 AIN7AIN15
Note: AIN7 pin (AIN15 pin for ADC1) may be used as ADTRG0 input pin. Therefore, when ADTRG0 is used in ADNMOD0= "10," do not set to ADNMOD0="111," and when ADTRG1 is used in ADNMOD1="11," do not set to ADNMOD1="111."
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There are 16 conversion result registers numbered from 0 to 15, which are all identical. The following is a description of register 0. AD Normal Mode Conversion Result Register 0
7 ADNRES0 (0xFFFF_C91C) Bit Symbol Read/Write Reset Value Function 15 Bit Symbol Read/Write Reset Value Function 0 0 Conversio Overrun flag n result store flag 0: No 1: Stored overrun 1: Overrun 0 0 VAL 14 OVR 0 0 0 13  0 12  R 0 0 0 conversion result 0 Upper 2 bits of an AD 6 5 4 ADR R 0 11  0 10  0 9 ADR 0 8 Lower 8 bits of an AD conversion result 3 2 1 0
Note 1: This register must be accessed as a 16-bit or larger quantity. If it is accessed as an 8-bit quantity, operation cannot be guaranteed. Note 2: Bit 15 is an AD conversion result flag ADNRES0. 1 is set to this when AD conversion value is stored, and it is cleared to 0 when the ADNRES0 is read. Note 3: Bit 14 is an Overrun flag ADNRES0. 1 is set to this when it is overwritten before reading the conversion result register ADNRES0. This bit is cleared to 0 when a new conversion result is stored in ADNRES0 with VAL=0. Note 4: This register does not support bit manipulation instructions.
Highest-Priority Conversion Result Register (ADC0)
7 ADCHPR0 (0xFFFF_C9020) Bit Symbol Read/Write Reset Value Function 15 Bit Symbol Read/Write Reset Value Function 0 0 Conversion Overrun result store flag 0: No flag overrun 1: Stored 1: Overrun 0 0 VAL 14 OVR Lower 8 bits of an AD conversion result 13  12  R 0 0 0 conversion result 0 Upper 2 bits of an AD 11  10  9 ADR 8 0 0 0 0 6 5 4 ADR R 0 0 0 0 3 2 1 0
Note 1: This register must be accessed as a 16-bit or larger quantity. If it is accessed as an 8-bit quantity, operation cannot be guaranteed. Note 2: Bit 15 is an AD conversion result flag ADNRES0. 1 is set to this when AD conversion value is stored, and it is cleared to 0 when the ADNRES0 is read. Note 3: Bit 14 is an Overrun flag ADNRES0. 1 is set to this when it is overwritten before reading the conversion result register ADNRES0. This bit is cleared to 0 when a new conversion result is stored in ADNRES0 with VAL=0. Note 4: This register does not support bit manipulation instructions.
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AD Normal Mode Clock Control Register 1 7
ADNCLK0 (0xFFFF_C928) Bit Symbol Read/Write Reset Value Function 0 0 
6
5
 R 0
4
 0
3
 0
2
1
ADCCK R/W
0
0 0 0 Prescaler clock output select 001: IMCLK/2 010: IMCLK/4 011: IMCLK/8 100: IMCLK/16 Other: IMCLK
Note 1: AD conversion is performed at the clock frequency selected in this register. To assure conversion accuracy, however, the conversion clock frequency must be 14 MHz or slower (which results in a conversion time of 2.36 s or longer with 6-clock sample hold). Note 2: The conversion clock must not be changed while AD conversion is in progress. Wait at least 2 ADCLK clocks after AD conversion has completed before changing the conversion clock.
ADCCK IMCLK /2 /4 /8 /16
ADCLK0 (AD Conversion Clock)
Figure 13.3.1 Clock Control Circuit
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A/D Monitor Control Register (ADC0)
7 Bt Symbol CMPCTL0(L) (0xFFFF_C92C) Read/Write Reset Value Function  R 0 0 6  5 4 CMCH0 3 R/W 0 0 0 0 0 0 AD input channel 0 to be compared A/D Monitor A/D Monitor A/D Monitor
Interrupt setting is 0. 0:Under Compare Register 1: More than Compare Register Interrupt setting is 0. 0: disable 1: enable Interrupt flag is 0. 0:Monitoring Non-generated interrupt 1:Monitoring Generated Interrupt
2 CMOP0
1 IRQEN0
0 CMCAP0
AD Input Channel To Be Compared CNCH 000 001 010 011 100 101 110 111 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 In ADC1, the input channels correspond as follows: AIN0AIN8 AIN1AIN9 AIN2AIN10 AIN3AIN11 AIN4AIN12 AIN5AIN13 AIN6AIN14 AIN7AIN15
AD Monitor Control Register (ADC0)
15 (CMPCTL0H) (0xFFFF_C92D) Bit Symbol Read/Write Reset Value Function 0  R 0 14  13 12 CMCH1 11 R/W 0 0 0 0 0 0 AD input channel 1 to be compared A/D Monitor A/D Monitor A/D Monitor
Interrupt setting is 1. 0:Under Compare Register 1: More than Compare Register Interrupt setting is 1.
0: disable 1: enable
10 CMOP1
9 IRQEN1
8 CMCAP1
Interrupt flag is 1. 0:Monitoring Non-generated interrupt 1:Monitoring Generated Interrupt
AD Input Channel To Be Compared CNCH 000 001 010 011 100 101 110 111 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7
In ADC1, the input channels correspond as follows: AIN0AIN8 AIN1AIN9 AIN2AIN10 AIN3AIN11 AIN4AIN12 AIN5AIN13 AIN6AIN14 AIN7AIN15
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Note: CMCAPx is cleared to 0 by writing data in "1" or in ADCMPxx. Because interrupt requests are continuously sent until this register is cleared, it must be cleared within the Monitor Interrupt routine.
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A/D Conversion Result Compare Register (ADC0)
7 ADCMP00 (0xFFFF_C934) Bit Symbol Read/Write Reset Value Function 15 Bit Symbol Read/Write Reset Value Function 0 0 0  14  0 0 6 5 4 ADR0 R/W 0 0 0 0 A/D conversion result compare value 0 is stored. 13  R 0 0 0 0 0 12  11  10  0 9 ADR0 0 8 3 2 1 0
A/D Conversion Result Compare Register (ADC0)
7 ADCMP01 (0xFFFF_C938) Bit Symbol Read/Write Reset Value Function 15 Bit Symbol Read/Write Reset Value Function 0 0 0  14  0 0 6 5 4 ADR1 R/W 0 0 0 0 A/D conversion result compare value 1 is stored. 13  R 0 0 0 0 0 12  11  10  0 9 ADR1 0 8 3 2 1 0
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TMP19A71 13.4.1 13.4.1.1 Operation (Normal Mode) Analog Reference Voltage
Clearing the VREFON bit in the ADMODSEL0 turns off the switch between the VREFH and FREFL pins. Once the VREFON bit is cleared, the internal reference voltage requires a recovery time of 3 s to stabilize after the VREFON bit is again set to 1. Before starting an AD conversion, therefore, be sure to wait for 3 s after setting the VREFON bit to 1. If an AD conversion is started before this stabilization period has elapsed, conversion accuracy cannot be guaranteed.
13.4.1.2
Selecting an Analog Input Channel(s)
Selection of the analog input channel(s) to be used varies according to the operating mode of the AD converter. (1) Normal AD Conversion * When an analog input is used in Channel Fixed mode (ADNMOD0="0") Among the analog input from AIN0 to AIN 7, select one channel according to the ADNMOD0 setting. * When an analog input is used in Channel Scan mode (ADNMOD0="1") Select one Scan mode among the eight types Scan modes according to the ADNMOD0 setting. (2) Highest Priority AD Conversion Among the analog input from AIN0 to AIN 7, select one channel according to the A/DCHPC0 setting. After resetting, ADNMOD0 is initialized to 0, and ADNMOD0to 0000, which makes the selection be in processing, and Channel Fixed mode input of AIN0 pin is selected. Note that pins not used as analog input channels can be used as normal ports (a part of them are for input only), however, the conversion accuracy may get worse. When the highest-priority AD conversion is started during the normal AD conversion, the highest-priority one starts in a break, the normal AD conversion resumes at the end of the highest-priority one is over. Example: When the highest-priority conversion of AIN7 is started in ADCHP0=111 during the Continuous Scan conversion of the Channel from AIN0 to AIN3 in ADNMOD0=11 and ADNMOD0=00011.
Highest-priority AD Conversion Startup (Software Startup) Conversion CH Ch0 Ch1 Ch2 Ch7 Ch3 Ch0 Ch1
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13.3.1.1
Starting of AD Conversion
AD conversion has two types; Normal AD conversion and Highest-Priority AD conversion. A Normal AD conversion starts up in software by setting 1 to ADCSTART0. Also, the Highest-Priority conversion starts up in software by setting 1 to ADCHPC0. A For Normal AD conversion, one operating mode among the four operating modes specified by ADNMOD0. An operating mode of the Highest-Priority conversion is Channel-Fixed Single conversion only. A Normal AD conversion can start up with hardware starting source selected by ADNMOD0 by setting 1 to ADNMOD0. When this bit is "10/11," a Normal AD conversion starts up at the rising edge of ADTRG0 pin, and when "01," it starts up with INTTBCOM11 of the timer from 16-bit quantity. It can start in software even if the startup in hardware becomes enabled. When a Normal AD conversion starts, 1 is set to an AD conversion Busy flag (ADCSTART0) indicating that the conversion is in progress. When the Highest-Priority AD conversion starts, 1 is set to an AD conversion Busy flag (ADCHPC0). At this time, a Busy flag for Normal AD conversion retains the value before a starting of the Highest-Priority AD conversion. A conversion end flag ADCSTART0 for Normal AD conversion, also, retains the value before a starting of the Highest-Priority AD conversion. Since ADCSTART0 is a flag showing the conversion operation, it has an interval of being 0 between the conversions such as those in the Continuous conversion mode. When palling the end of conversion, ADCSTART0 must not be used. When 1 is set to ADCHPC0 during a Normal AD conversion, the Highest-Priority AD conversion starts upon the storage of result register of the ongoing conversion, and AD conversion (Channel-Fixed Single conversion) of the cannel specified by ADCHPC0 starts. When this result is stored in the result register ADCHPR0, a Normal AD conversion resumes operation from the part suspended.
13.3.1.2
Restart
A Normal AD conversion restarts when 1 is set to ADCSTART0 during the Channel-Fixed Normal Conversion, or it is started with hardware source. At the time of restarting, a Normal AD conversion performed till then starts conversion after a lapse of conversion time, however, the result that has been converted at the moment of restarting is not stored. Restarting does clear neither the flags of  nor .
Note 1: When Continuous conversion is in process, stop it first (ADNMOD0=0) and restart after all of the conversions ended. Note 2: When Channel Scan mode conversion is in process, restart after all of the conversions ended.
13.3.1.3
Stop Repeat
Changing the ADNMOD0 bit in  from 1 to 0 enables the stop of repeating after the Continuous conversion made one-cycle repeat. In Channel-Fixed Continuous conversion mode (interrupts after four conversions), as an interrupt generates after conversion is performed four times, the Continuous conversion stops. In Channel Scan Continuous conversion mode, after the conversions performed as much as specified number of channels, the Continuous conversion stops as an interrupt is generated.
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13.3.1.4
AD Conversion Mode and Interrupt in the End of AD Conversion
The normal mode has the four operating modes shown in Table 13.3.1. Normal AD Conversion can select a mode according to the ADNMOD0 setting while the Highest-Priority AD conversion can select only Channel-Fixed single conversion regardless of the ADNMOD0 setting.
Table 13.3.1 Relations of AD Conversion Mode, Interrupt Generation Timing, and Flag Behavior
Conversion Mode Interrupt Generation Timing EOS Set Timing (Note 1) BUSY (after an interrupt has generated) Fixed-Channel Single Conversion Channel Scan Single Conversion Fixed-Channel Continuous Conversion After a conversion ends After a Scan conversion ends Every time of conversion Every fur times of conversion Channel Scan Continuous Conversion Note 1: Write 0 and clear EOS. Every time of Scan conversion After a conversion ends After a Scan conversion ends After a conversion ends. After a conversion ends four times After a Scan conversion ends. 1 1 1 1 1 1 0 1 0 0 0 1 0 0 0 ITM ADNMOD0 REP SCAN
(1) Normal AD Conversion ADNMOD0 selects an operating mode. As an AD conversion starts, 1 is set to ADCSTART0. After a specified AD conversion ends, 1 is set to ADCSTART0 that indicates the AD conversion ended, and then an AD conversion end interrupt (INTAD0) generates.  is cleared to 0 as  is set when ="0." There are timings to be 0 at the intervals of each channel conversion when ="1." a) Fixed-Channel Single Conversion Mode This mode is selected by programming the REP and SCAN bits in the ADNMOD0 register to 00. In this mode, the ADC performs a single conversion on a single selected channel. When a conversion is completed, the ADC sets 1 to the ADCSTART0.EOS bit, clears the ADCSTART0.BUSY bit in 0 and generates the INTAD0 interrupt. The EOS bit must be cleared by writing 0. b) Channel Scan Single Conversion Mode This mode is selected by programming the REP and SCAN bits in the ADNMOD0 register to 01. In this mode, the ADC performs a single conversion on each selected group of channels. When a single conversion sequence is completed, the ADC sets 1 to the ADCSTART0.EOS bit, clears the ADCSTART0.BUSY bit in 0 and generates the INTAD0 interrupt. The EOS bit must be cleared by writing 0.
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c) Fixed-Channel Continuous Conversion Mode This mode is selected by programming the REP and SCAN bits in the ADNMOD0 register to 10. In this mode, the ADC repeatedly converts a single selected channel. When a conversion process is completed, the ADC sets 1 to the ADCSTART0.EOS bit. A generation timing of an interrupt request is selectable according to the ADNMOD0 setting. The setting timing of EOS is associated with the timing of an interrupt. The EOS bit must be cleared by writing 0. When ITM=0, the ADC generates an interrupt request every time a conversion ends. In this case, the conversion result is stored in the corresponding conversion result register to a selected channel, which makes 1 be set to the EOS bit. When ITM=1, the ADC generates an interrupt after every four conversions completed. The conversion result is stored in the corresponding conversion result register to a selected channel. After the result of the fourth conversion is stored, 1 is set to the EOS bit. And then, a conversion starts again. The EOS bit must be cleared by writing 0. ADNMOD0 setting can make the next conversion of the conversion in Continuous conversion mode wait until the result register is read. When ITM=0, the time taken until a conversion starts after a previous conversion ends is controlled, and when ITM=1, the time taken until a conversion starts after previous conversion ends four times is controlled. d) Channel Scan Continuous Conversion Mode This mode is selected by programming the REP and SCAN bits in the ADNMOD0 register to 11. In this mode, the ADC repeatedly converts the selected group of channels. Every time a Scan conversion ends, 1 is set to ADNMOD0, and an interrupt request of INTAD0 generates. ADNMOD0 has a timing that becomes 0 at the interval of each channel conversion. The EOS bit must be cleared by writing 0. To stop the operation of conversion of Continuous conversion modes, described in c) and d), 0 shall be written to ADNMOD0. The mode ends as an ongoing conversion ends, and ADNMOD0 is cleared to 0. Stop AD conversions and set 0 to ADMODSEL0 before transferring to a Stop mode. The electricity is carried even it is in the Stop mode unless the transfer is made stopping a conversion. If the transfer is made with an AD conversion in performing, the result come out after the releasing of the Stop mode is not guaranteed. (2) The Highest-Priority AD Conversion ADNMOD0 setting has no effect on the Highest-Priority AD conversion. Its operation mode is Channel-Fixed Single conversion mode only. When the starting condition is met, the Highest-Priority AD conversion of a specified channel in ADCHPC0 is performed only one time. As the conversion ends, an interrupt of the Highest-Priority AD conversion end generates, and ADCHPC0 is cleared to 0.
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13.3.1.5 Highest-Priority Conversion Mode The Highest-Priority AD conversion can interrupt a Normal AD conversion. The Highest-Priority AD conversion can start by setting 1 to ADCHPC0. If the Highest-Priority AD conversion starts during the Normal AD conversion, AD conversion result during the conversion process is stored in a result register, and after that, a channel specified by ADCHPC0is single-converted. That result is stored in ADCHPR0, and the Highest-Priority AD conversion interrupt generates. Then, the Normal AD conversion resumes from the part continued from the previous time. If the Highest-Priority AD conversion restarts during the Highest-Priority AD conversion process, the conversion in process is finished, and then the Highest-Priority Conversion starts newly. For example, if the Continuous conversion of the channels from AIN0 to AIN7 is active, and 1 is set to  while AIN3 is converted, the channel specified by  is converted as soon as the AIN3 conversion ends, and the result is stored in ADCHPR0, and then the Continuous conversion restarts from AIN4. 13.3.1.6 AD Monitoring Each AD converter has two AD monitoring functions and can compare a conversion value and two setting value simultaneously. When 1 is set to CMPCTL0, an AD monitoring is enabled. When the contents of a conversion result register specified by CMPCTL0 is more than or under the value of compare register (it is specified by ), AD monitoring interrupt (INTADM0) generates. CMPCTL0 can determine which setting condition is met. Also, this comparing operates every time a result is stored in the relevant conversion result register, and as the condition is met, an interrupt generates. Note that since a register assigned to AD monitoring is not read in software in general, the overrun flag ADNRES0 and the conversion result flag ADNRES0 are always set. Therefore, to use the AD monitoring, do not use the flag of a relevant conversion result register. 13.3.1.7 AD Conversion Time One AD conversion takes 27 clocks excluding sampling clocks. In ADCBASN0,6 or 12 clocks can be selected as sampling clocks, thus the sum of AD conversion clocks may be 33 or 39. ADNCLK0 selects an AD conversion clocks among the AD pre-scaler output; IMCLK, IMCLK/2, IMCLK/4, IMCLK/8, and IMCLK/16.To assure the accuracy, it is necessary to set the AD conversion clock less than 14MHz, i.e. under 2.36s (if Sample Hold is 6 clocks). 13.3.1.8 Storage and Read of AD Conversion Result AD conversion results are stored in the result register of a Normal AD conversion (from ADNRES0 to ADNRES7). Correspondence of result registers and analog input channels are the same in any operating mode if they are in normal mode. For example, the result of AIN0 conversion is always stored in the ADNRES0 register. Table 13.3.2 shows the correspondence of analog input channels and AD conversion result registers.
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Table 13.3.2 Analog Input Channel and AD Conversion Register
Analog Input Channel AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Conversion Result Register ADNRES0 ADNRES1 ADNRES2 ADNRES3 ADNRES4 ADNRES5 ADNRES6 ADNRES7
13.3.1.9
Data Polling To process an AD conversion result by polling data without using any interrupt, ADNMOD0 is to be polled. When this flag is set, a conversion result is stored in a predetermined AD conversion result register. Therefore AD conversion result register must be read after checking the set. To detect an overrun at the time, the conversion result register must be read in 16-bit system. If the result were =0 and =1, a conversion result not overwritten would be gained.
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13.4.1
PMD Mode (MODSEL=1)
In PMD mode, the ADC performs AD conversions synchronous to a PMD trigger. The PMD trigger can be selected from three types: PMDTRG00 to PMDTRG02. The ADC0 has 8 conversion result registers while the ADC1 has 11 conversion result registers. For each of these result registers, an analog input port and a PMD trigger can be programmed separately, and AD conversions can be enabled and disabled separately for each register. Also, each of ADC unit has a counter, and the two cycles; every time and the specified number can be set to the counter. As all the programs enabled are converted completely, an ADC interrupt generates.
AD Input Timing Trigger Register (ADC0) 7
ADCSETTOO(L) Bit Symbol (0xFFFF_CD40) Read/Write Reset Value Function ADST3
6
5
ADST2
4
R/W
3
ADST1
2
1
ADST0
0
0 0 0 0 Input timing trigger for Input timing trigger for result register 2 result register 3 00: PMDTRG00 00: PMDTRG00 01: PMDTRG01 01: PMDTRG01 10: PMDTRG02 10: PMDTRG02 11: Reserved 11: Reserved
0 0 Input timing trigger for result register 1 00: PMDTRG00 01: PMDTRG01 10: PMDTRG02 11: Reserved
0 0 Input timing trigger for result register 0 00: PMDTRG00 01: PMDTRG01 10: PMDTRG02 11: Reserved
15
(ADCSETTOOH) Bit Symbol (0xFFFF_CD41) Read/Write Reset Value Function ADST7
14
13
ADST6
12
R/W
11
ADST5
10
9
ADST4
8
0 0 Input timing trigger for result register 7 00: PMDTRG00 01: PMDTRG01 10: PMDTRG02 11: Reserved
0 0 Input timing trigger for result register 6 00: PMDTRG00 01: PMDTRG01 10: PMDTRG02 11: Reserved
0 0 Input timing trigger for result register 5 00: PMDTRG00 01: PMDTRG01 10: PMDTRG02 11: Reserved
0 0 Input timing trigger for result register 4 00: PMDTRG00 01: PMDTRG01 10: PMDTRG02 11: Reserved
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AD Input Timing Trigger Register 0 (ADC1) 7
ADCSETT1O(L) Bit Symbol (0xFFFF_CDC0) Read/Write Reset Value Function ADST11 0 0 Input timing trigger for result register 11 00: PMDTRG10 01: PMDTRG11 10: PMDTRG12 11: Reserved
6
5
ADST10
4
R/W
3
ADST9
2
1
ADST8
0
0 0 Input timing trigger for result register 10 00: PMDTRG10 01: PMDTRG11 10: PMDTRG12 11: Reserved
0 0 Input timing triffer for result register 9 00: PMDTRG10 01: PMDTRG11 10: PMDTRG12 11: Reserved
0 0 Input timing triffer for result register 8 00: PMDTRG10 01: PMDTRG11 10: PMDTRG12 11: Reserved
15
(ADCSETT1OH) Bit Symbol (0xFFFF_CDC1) Read/Write Reset Value Function ADST15
14
13
12
ADST14 R/W
11
ADST13
10
9
ADST12
8
0 0 Input timing trigger for result register 15 00: PMDTRG10 01: PMDTRG11 10: PMDTRG12 11: Reserved
0 0 Input timing trigger for result register 14 00: PMDTRG10 01: PMDTRG11 10: PMDTRG12 11: Reserved
0 0 Input timing trigger for result register 13 00: PMDTRG10 01: PMDTRG11 10: PMDTRG12 11: Reserved
0 0 Input timing triggr for result register 12 00: PMDTRG10 01: PMDTRG11 10: PMDTRG12 11: Reserved
AD Input Timing Trigger Register 1(ADC1) 7
Bit Symbol ADCSETT11 (0xFFFF_CDC4) Read/Write Reset Value Function  0
6
 0
5
ADST18
4
R/W
3
ADST17
2
1
ADST16
0
0 0 Input timing trigger for result register 10 00: PMDTRG10 01: PMDTRG11 10: PMDTRG12 11: Reserved
0 0 Input timing trigger for result register 9 00: PMDTRG10 01: PMDTRG11 10: PMDTRG12 11: Reserved
0 0 Input timing trigger for result register 8 00: PMDTRG10 01: PMDTRG11 10: PMDTRG12 11: Reserved
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AD Input Port Select Register 0 (ADC0) 7
ADCSET0O(L) Bit Symbol (0xFFFF_CD48) Read/Write Reset Value Function  0 Must be written as 0.
6
5
ADSI1
4
R/W
3
 0 Must be written as 0.
2
1
ADSI0
0
0 0 0 Input port for result register 1 000: AIN0 001: AIN1 010: AIN2 011: AIN3 100: AIN4 101: AIN5 110: AIN6 111: AIN7
0 0 0 Input port for result register 0 000: AIN0 001: AIN1 010: AIN2 011: AIN3 100: AIN4 101: AIN5 110: AIN6 111: AIN7
15
(ADCSET0OH) Bit Symbol (0xFFFF_CD49) Read/Write Reset Value Function  0 Must be written as 0.
14
13
ADSI3
12
R/W
11
 0 Must be written as 0.
10
9
ADSI2
8
0 0 0 Input port for result register 3 000: AIN0 001: AIN1 010: AIN2 011: AIN3 100: AIN4 101: AIN5 110: AIN6 111: AIN7
0 0 0 Input port for result register 2 000: AIN0 001: AIN1 010: AIN2 011: AIN3 100: AIN4 101: AIN5 110: AIN6 111: AIN7
AD Input Port Select Register 1 (ADC0) 7
Bit Symbol ADCSET01(L) (0xFFFF_CD4C) Read/Write Reset Value Function  0 Must be written as 0.
6
5
ADSI5
4
R/W
3
 0 Must be written as 0.
2
1
ADSI4
0
0 0 0 Input port for result register 5. 000: AIN0 001: AIN1 010: AIN2 011: AIN3 100: AIN4 101: AIN5 110: AIN6 111: AIN7
0 0 0 Input port for result register 4 000: AIN0 001: AIN1 010: AIN2 011: AIN3 100: AIN4 101: AIN5 110: AIN6 111: AIN7
15
Bit Symbol (ADCSET01H) (0xFFFF_CD4D) Read/Write Reset Value Function  0 Must be written as 0.
14
13
ADSI7
12
R/W
11
 0 Must be written as 0.
10
9
ADSI6
8
0 0 0 Input port for result register 7 000: AIN0 001: AIN1 010: AIN2 011: AIN3 100: AIN4 101: AIN5 110: AIN6 111: AIN7
0 0 0 Input port for result register 6 000: AIN0 001: AIN1 010: AIN2 011: AIN3 100: AIN4 101: AIN5 110: AIN6 111: AIN7
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AD Input Port Select Register 0(ADC1) 7
Bit Symbol ADCSET1O(L) (0xFFFF_CDC8) Read/Write Reset Value Function
6
ADSI9
5
4
R/W
3
2
ADSI8
1
0
0 0 0 Input port for result register 9 0000: AIN8 0001: AIN9 0010: AIN10 0011: AIN11 0100: AIN12 0101: AIN13 0110: AIN14 0111: AIN15 1000: AIN16 1001: AIN17 1010: AIN18 Other: Reserved
0
0 0 0 Input port for result register 8 0000: AIN8 0001: AIN9 0010: AIN10 0011: AIN11 0100: AIN12 0101: AIN13 0110: AIN14 0111: AIN15 1000: AIN16 1001: AIN17 1010: AIN18 Other: Reserved
0
(ADCSET1OH) (0xFFFF_CDC9)
15
Bit Symbol Read/Write Reset Value Function
14
ADSI11
13
12
R/W
11
10
ADSI10
9
8
0 0 0 Input port for result register 11 0000: AIN8 0001: AIN9 0010: AIN10 0011: AIN11 0100: AIN12 0101: AIN13 0110: AIN14 0111: AIN15 1000: AIN16 1001: AIN17 1010: AIN18 Other: Reserved
0
0 0 0 Input port for result register 10 0000: AIN8 0001: AIN9 0010: AIN10 0011: AIN11 0100: AIN12 0101: AIN13 0110: AIN14 0111: AIN15 1000: AIN16 1001: AIN17 1010: AIN18 Other: Reserved
0
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AD Input Port Select Register 1 (ADC1) 7
ADCSET11(L) (0xFFFF_CDCC) Bit Symbol Read/Write Reset Value Function 0 0 0 Input port for result register 13 0000: AIN8 0001: AIN9 0010: AIN10 0011: AIN11 0100: AIN12 0101: AIN13 0110: AIN14 0111: AIN15 1000: AIN16 1001: AIN17 1010: AIN18 Other: Reserved 0
6
ADSI13
5
4
R/W
3
2
ADSI12
1
0
0 0 0 Input port for result register 12 0000: AIN8 0001: AIN9 0010: AIN10 0011: AIN11 0100: AIN12 0101: AIN13 0110: AIN14 0111: AIN15 1000: AIN16 1001: AIN17 1010: AIN18 Other: Reserved
0
15
(ADCSET11H) (0xFFFF_CDCD) Bit Symbol Read/Write Reset Value Function
14
ADSI15
13
12
R/W
11
10
ADSI14
9
8
0 0 0 Input port for result register 15 0000: AIN8 0001: AIN9 0010: AIN10 0011: AIN11 0100: AIN12 0101: AIN13 0110: AIN14 0111: AIN15 1000: AIN16 1001: AIN17 1010: AIN18 Other: Reserved
0
0 0 0 Input port for result register 14 0000: AIN8 0001: AIN9 0010: AIN10 0011: AIN11 0100: AIN12 0101: AIN13 0110: AIN14 0111: AIN15 1000: AIN16 1001: AIN17 1010: AIN18 Other: Reserved
0
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TMP19A71
AD Input Port Select Register 2 (ADC1) 7
ADCSET12(L) (0xFFFF_CDD0) Bit Symbol Read/Write Reset Value Function 0 0 0 Input port for result register 17 0000: AIN8 0001: AIN9 0010: AIN10 0011: AIN11 0100: AIN12 0101: AIN13 0110: AIN14 0111: AIN15 1000: AIN16 1001: AIN17 1010: AIN18 Other: Reserved 0
6
ADSI17
5
4
R/W
3
2
ADSI16
1
0
0 0 0 Input port for result register 16 0000: AIN8 0001: AIN9 0010: AIN10 0011: AIN11 0100: AIN12 0101: AIN13 0110: AIN14 0111: AIN15 1000: AIN16 1001: AIN17 1010: AIN18 Other: Reserved
0
15
(ADCSET12H) (0xFFFF_CDD1) Bit Symbol Read/Write Reset Value Function 0 
14
 0
13
 0
12
 R/W 0
11
10
ADSI18
9
8
0 0 0 Input port for result register 18 0000: AIN8 0001: AIN9 0010: AIN10 0011: AIN11 0100: AIN12 0101: AIN13 0110: AIN14 0111: AIN15 1000: AIN16 1001: AIN17 1010: AIN18 Other: Reserved
0
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TMP19A71
AD PMD Mode Control Register 0 (ADC0) 7
ADPMOD00 (0xFFFF_CD5C) Bit Symbol Read/Write Reset Value Function 0
Conversion Complete flag 0: Completed 1: In progress or not started yet
6
 0
5
 0
4
 R 0
3
 0
2
 0
1
 0
0
ADEN0 R/W 0
AD conversion 0: Disable 1: Enable
ADF0
(ADPMOD10 used by ADC1 also applies to these contents.)
Note 1:  must be 1 as the starting condition, and it becomes 0 when all the conversions enabled are completed. Note 2: If 0 is set to =0 while the conversion is in progress, the value is set to the result register after the ongoing channel conversion ends, and the operation stops. The next conversion starts not from the part where it stopped but from a channel of the very beginning.
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TMP19A71
AD PMD Mode Control Register 1 (used in ADC0) 7
ADPMOD01(L) Bit Symbol (0xFFFF_CD60) Read/Write Reset Value Function ADPE7 0 Result register 7 enable 0: Disable 1: Enable
6
ADPE6 0 Result register 6 enable 0: Disable 1: Enable
5
ADPE5 0 Result register 5 enable 0: Disable 1: Enable
4
ADPE4 R/W 0 Result register 4 enable 0: Disable 1: Enable
3
ADPE3 0 Result register 3 enable 0: Disable 1: Enable
2
ADPE2 0 Result register 2 enable 0: Disable 1: Enable
1
ADPE1 0 Result register 1 enable 0: Disable 1: Enable
0
ADPE0 0 Result register 0 enable 0: Disable 1: Enable
15
(ADPMOD01H) Bit Symbol (0xFFFF_CD61) Read/Write Reset Value Function  0 Must be written as 0.
14
 0 Must be written as 0.
13
 0 Must be written as 0.
12
 R/W 0 Must be written as 0.
11
 0 Must be written as 0.
10
 0 Must be written as 0.
9
 0 Must be written as 0.
8
 0 Must be written as 0.
AD PMD Mode Control Register 1 (used in ADC1) 7
Bit Symbol ADPMOD11(L) (0xFFFF_CDE0) Read/Write Reset Value Function ADPE15 0 Result register 15 enable 0: Disable 1: Enable
6
ADPE14 0 Result register 14 enable 0: Disable 1: Enable
5
ADPE13 0 Result register 13 enable 0: Disable 1: Enable
4
ADPE12 0 Result register 12 enable 0: Disable 1: Enable R/W
3
ADPE11 0 Result register 11 enable 0: Disable 1: Enable
2
ADPE10 0 Result register 10 enable 0: Disable 1: Enable
1
ADPE9 0 Result register 9 enable 0: Disable 1: Enable
0
ADPE8 0 Result register 8 enable 0: Disable 1: Enable
15
Bit Symbol (ADPMOD11H) (0xFFFF_CDE1) Read/Write Reset Value Function  0 Must be written as 0.
14
 0 Must be written as 0.
13
 0 Must be written as 0.
12
 R/W 0 Must be written as 0.
11
 0 Must be written as 0.
10
ADPE18 0 Result register 18 enable 0: Disable 1: Enable
9
ADPE17 0 Result register 17 enable 0: Disable 1: Enable
8
ADPE16 0 Result register 16 enable 0: Disable 1: Enable
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TMP19A71
AD Count Enable Register 0 7
ADCNE0(L) Bit Symbol (0xFFFF_CD64) Read/Write Reset Value Function ADCNE7 0 Convert the conversion register 7 after the count 0:Always enable 1:Enable after the count
6
ADCNE6 0 Convert the conversion register 6 after the count 0:Always enable 1:Enable after the count
5
ADCNE5 0 Convert the conversion register 5 after the count 0:Always enable 1:Enable after the count
4
ADCNE4 0 Convert the conversion register 4 after the count 0:Always enable 1:Enable after the count R/W
3
ADCNE3 0 Convert the conversion register 3 after the count 0:Always enable 1:Enable after the count
2
ADCNE2 0 Convert the conversion register 2 after the count 0:Always enable 1:Enable after the count
1
ADCNE1 0 Convert the conversion register 1 after the count 0:Always enable 1:Enable after the count
0
ADCNE0 0 Convert the conversion register 0 after the count 0:Always enable 1:Enable after the count
(ADCNE0H) (0xFFFF_CD65)
15
Bit Symbol Read/Write Reset Value Function 0 
14
 0
13
 0
12
 R/W 0
11
 0
10
 0
9
 0
8
 0
AD Count Enable Register 1 7
ADCNE1(L) (0xFFFF_CDE4) Bit Symbol Read/Write Reset Value Function 0 Convert the conversion register 15 after the count 0:Always enable 1:Enable after the count 0 Convert the conversion register 14 after the count 0:Always enable 1:Enable after the count 0 Convert the conversion register 13 after the count 0:Always enable 1:Enable after the count ADCNE15
6
ADCNE14
5
ADCNE13
4
ADCNE12 0 Convert the conversion register 12 after the count 0:Always enable 1:Enable after the count R/W
3
ADCNE11 0 Convert the conversion register 11 after the count 0:Always enable 1:Enable after the count
2
ADCNE10 0 Convert the conversion register 10 after the count 0:Always enable 1:Enable after the count
1
ADCNE9 0 Convert the conversion register 9 after the count 0:Always enable 1:Enable after the count
0
ADCNE8 0 Convert the conversion register 8 after the count 0:Always enable 1:Enable after the count
ADCNE1(H) (0xFFFF_CDE5)
15
Bit Symbol Read/Write Reset Value Function 0 
14
 0
13
 0
12
 R/W 0
11
 0
10
ADCNE18 0 Convert the conversion register 18 after the count 0:Always enable 1:Enable after the count
9
ADCNE17 0 Convert the conversion register 17 after the count 0:Always enable 1:Enable after the count
8
ADCNE16 0 Convert the conversion register 16 after the count 0:Always enable 1:Enable after the count
Note 1: At least one channel must always be converted in the unit ADC1. If all the channels are converted after counting, the conversion is not skipped properly.
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TMP19A71
AD Conversion Count Setting Register 0 (used in ADC0) 7
Bit Symbol ADCNT0 (0xFFFF_CD68) Read/Write Reset Value Function 0 0 0 0
6
5
4
CMPCNT R/W
3
2
1
0
0
0
0
0
When the cycle value becomes the same value as the value set here, a channel set after counting is also converted.
(ADCNT1 used by ADC1 applies to these contents.) Example of Actual Operation Setting ADPMOD01="1011_0111" ADCNE0 ="1111_0000" ADCNT0 ="0000_1111"
: Conversion Enabled(CH0,1,2,4,5,7) : Always Convert (CH0,1,2,3) or after counting (CH4,5,6,7) : Count Value(16 counts)
Note 1: These are premised on that the amount of PMDTRG capable of converting all the channels within a certain cycle is available.
A channel changes from CH0 to CH1, and CH1 to CH2, then INTAD0 generates. The count value decrements by one. Goes to the step 1) if the count value is not 0, and to 4) if the value is 0 (after 16 cycles of conversion). A channel changes from CH0 to CH1, CH1 to CH2, and so on till becomes CH7, then INTAD0 generates. 5) Loads the register value set as count set value. 6) Goes back to the step 1).
1) 2) 3) 4)
AD PMD Mode Basic Setting Register (ADC0) 7
Bit Symbol ADCBASP0 (0xFFFF_CD6C) Read/Write Reset Value Function  0 Must be written as 0.
6
 0 Must be written as 0.
5
 0 Must be written as 0.
4
 R/W 0 Must be written as 0.
3
 0 Must be written as 0.
2
AZSEL 0 Sample hold time
1:6 clocks 0:12 clocks
1
 0 Must be written as 0.
0
 0 Must be written as 0.
15
Bit Symbol Read/Write Reset Value Function 0 Must be written as 0. 
14
 0 Must be written as 0.
13
 0 Must be written as 0.
12
 R/W 1 Must be written as 1.
11
 0 Must be written as 0.
10
 0 Must be written as 0.
9
 0 Must be written as 0.
8
 0 Must be written as 0.
(ADCBASP1 used by ADC1 applies to these contents.)
Note 1: The conversion time of ADC is derived from the equation; (the number of clocks selected in 27 clocks)/ADCLK.
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AD PMD Mode Clock Control Register 0 (used by ADC0) 7
Bit Symbol ADPCLK0 (0xFFFF_CD58) Read/Write Reset Value Function  0
6
 0
5
 R 0
4
 0
3
 0
2
1
ADPCK R/W
0
0 0 0 Prescaler clock output select 000: IMCLK 001: IMCLK /2 010: IMCLK /4 011: IMCLK /8 100: IMCLK /16 101: fsys Other: Reserved
(ADPCLK1 used by ADC1 applies to these contents.)
Note 1: ADC conversions are executed with clocks selected by above-mentioned registers. To guarantee the accuracy, it is necessary to select a conversion clock to make the conversion time less than 36 s (less than 14 MHz in an AD clock). Note 2: A conversion clock must not be changed during an AD conversion in progress. More than two clocks of ADCLK after the conversion stops, it must be changed.
ADPCK0 IMCLK /2 /4 /8 /16
ADCLK
(Clock for AD Conversion)
fsys
Figure 13.3.2 Clock Control Circuit
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13-30
TMP19A71
There are the same registers from 0 to 18 as the result registers. Here the register 0 is described. AD PMD Mode Result Register 0 7
ADPRES0 Bit Symbol (0xFFFF_CD00) Read/Write Reset Value Function ADR07 0
6
ADR06 0
5
ADR05 0
4
ADR04 R 0
3
ADR03 0
2
ADR02 0
1
ADR01 0
0
ADR00 0
Lower 8 bits of an AD conversion result
15
Bit Symbol Read/Write Reset Value Function 0 Result store flag 1: Stored VAL
14
OVR 0 Overrun flag 0: No overrun 1: Overrun
13
 0
12
 R 0
11
 0
10
 0
9
ADR09 0
8
ADR08 0
Upper 2 bits of an AD conversion result
Note 1: To access this register, the system of more than 16-bit is to be used. When accessed by 8-bit system, the operation shall not be guaranteed. Note 2: Bit 15 is an AD conversion result flag . When an AD conversion value is stored, 1 is set to it. When this register (ADPRES) is read, it is cleared to 0. Note 3: Bit 14 is an overrun flag. 1 is set to this flag when a conversion result is overwritten before reading the conversion result register (ADPRES). It is cleared to 0 with a flag reading. Note 4: This register is not accessible with any bit operation instruction.
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13-31
TMP19A71 13.4.2 13.4.2.1 Operation (PMD Mode) Analog Reference Voltage
By writing 0 to the ADMODSEL0 bit, a switch between VREFH and VREFL can be turned off. To start an AD conversion, 1 must be written to the  bit, and then it must be waited for more than 3 s until an internal reference voltage is stabilized. The conversion accuracy when the conversion is started waiting for less than 3s shall not be guaranteed.
13.4.2.2
Basic Operation
In PMD mode, a conversion result register becomes the reference of AD conversions. Each conversion result register sets Conversion Enabled (ADPMOD01), Conversion Trigger (ADCSETT00), and Input Ports (ADCSET0x). Setting 1 to ADPMOD00 causes the wait state of a conversion trigger. As a conversion trigger from PMD is accepted, AD conversion is executed in ascending order from the conversion result register of the smallest number set in the conversion enabled. An accepted conversion trigger is retained inside until the conversions of a whole unit are completed. When a conversion result register to be executed next is set to the trigger already accepted, a conversion starts immediately.
13.4.2.3
AD Conversion Counting
In PMD mode, there is an AD conversion count function that enables a skip a conversion trigger (PMDTRG) of a specific result register for the set number of times. By using this function, both a result register whose conversion is desired in every cycle and a result register whose conversion cycle may delay can be controlled in the same unit. The skip, however, is not possible for all the result registers whose conversions are enabled in the unit. Figure 13.3.3 shows an AD conversion operation in PMD mode.
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13-32
TMP19A71
Set 1 to ADPMOD00.
YES Set a certain value to ADCNT0
ADCNT="0" NO
A skip of this conversion register is invalid? (ADCNEx=0?)
NO
YES Any setting input trigger YES AD Conversion starts NO
The last conversion register? YES an interrupt generation conversion register number=0 circuit retaining trigger is cleared ADCNT0 is changed to -1
NO
Figure 13.3.3 PMD Mode Operation
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13.4.2.4
AD Conversion Time
The number of clocks of AD conversion for one cycle is 27 excluding sampling clocks. Since the ADCBASP0 bit can select a sampling clock from 6 or 12 clocks, the sum of AD conversion clocks becomes 33 or 39. ADPCLK0 selects an AD conversion clock among an AD prescaler output fsys, IMCLK, IMCLK/2, IMCLK/4, IMCLK/8, and IMCLK/16. To ensure its accuracy, AD conversion clock must be set less than14MHz, i.e. more than 2.36 s of AD conversion time (when Sample Hold is 6 clocks).
13.4.2.5
Data Polling
To process an AD conversion result by polling data without using any interrupt, ADPMOD00 should be polled. When this flag is cleared to 0, a conversion result is stored in a prescribed AD conversion result register. Therefore the result resister must be read after checking the set. To detect any overrun at this time, a conversion result register must be read in 16-bit system. If the result came out as =0 and =1, a conversion result that was not overwritten would be gained.
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TMP19A71
13.5 Operating Timing
In PMD trigger mode, setting ADPMOD00 enables the acceptance of a PMD trigger, and inputting PMDTRG00/01 starts a converting operation. After all the program conversions end, ADF is cleared as an interrupt request is output, and then the next input of PMDTRG00/01 is waited. When ADEN is cleared, ADF is cleared without waiting for the end of all the program conversions. Inputting of the same PMD trigger whose conversion is in process is ignored, while a different input is retained. A program conversion of a different PMD trigger is processed continuously immediately after the one of the previous trigger.
ADEN ADF INTAD PMDTRG00 PMDTRG01
1 2 3 1 2 3 1
Figure 13.5.1 Timing Chart 1 in PMD Mode
ADEN ADF INTAD PMDTRG00 PMDTRG01
1 2 3 1 2 3 1
Figure 13.5.2
Timing Chart 2 in PMD Mode
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13.6 Example of Use
13.6.1 PWM Peak Synchronization (Read once)
Example of Use: Connect a U-phase current CT output to AIN0, and V-phase current CT output to AIN1. A conversion is processed at the PWM carrier peaks (PWM counter=MDPRD). A result of AIN0 is stored in ADPRES0, and a result of AIN1 to ADPRES1.
PWM Counter=max(MDPRD)
Triangular Wave PWM Counter=1 PWM U-phase V-phase W-phase Conversion Timing ADF Result Processing
Figure 13.6.1
AD Converter
Example of Use 1
Timing
Setting ADMODSEL0 = **** **** **** ***1: PMD mode ADPMOD00 = **** **** **** ***1 : ADC enabled ADPMOD01 = 0000 0000 0000 0011:Select result register 1 or 2 ADCSET00= **** **** 0001 0000 : Select AIN ADCSETT00= **** **** **** 0000 : Select PMDTRG0 TRGCR0 = **** **** **** *100 : PMD trigger setting Operation At the first PWM carrier peak after 1 is set to ADEN, a conversion starts. ADF becomes 1. It, however, does not start when a triangular wave (PWM counter) is in idle state. A conversion is processed in ascending order from the smallest program number (conversion register number). Program 0 converts with AIN0 as an input and put the result in ADPRES0. Program 1 converts with AIN1 as an input and put the result in ADPRES1. As ADF becomes 0, an interrupt INTAD0 generates. Result Processing Read ADPRES0 and ADPRES1 after checking if ADF is 0 or in the interrupt processing of finishing all AD conversions, use them as a U-phase and V-phase currents.
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TMP19A71 13.6.2 PWM Peak Synchronization (Read once)
Example of Use: Connect U-phase current to AIN1, V-phase current to AIN2, and W-phase current to IN3. The conversion is supposed to be performed at the peak of a triangular wave (PWM counter=max). The result of AIN1 is store in ADPRES0 and 3, the result of AIN2 in ADPRES1 and 4, and the result of AIN3 in ADPRES2 and 5.
PWM Counter=max(MDPRD)
Triangular Wave
PWM Counter=1
PWM U-phase V-phase W-phase
i)Setting
Setting Timing Conversion Timing ADF Result Processing
ii)Setting
Figure 13.6.2
AD Converter
Example of Use 2 Timing
i) Setting ADMODSEL0 = **** **** **** ***1: PMD mode ADPMOD00 = **** **** **** ***1 : ADC enabled ADPMOD01 = 0000 0000 0011 1111: Select result register 0,1,2,3,4,or 5 ADCSET00= 0001 0011 0010 0001 : Select AIN ADCSET01= **** **** 0011 0010 : Select AIN ADCSETT00= **** 0000 0000 0000: Select PMDTRG0 TRGCR0 = **** **** **** *100 : PMD trigger setting i) Operation A conversion starts at the first peak of triangular wave after 1 is set to ADEN. ADF becomes 1. Program 0 converts with AIN1 as an input and put the result in ADPRES0. Program 1 converts with AIN2 as an input and put the result in ADPRES1. Program 2 converts with AIN3 as an input and put the result in ADPRES2. Program 3 converts with AIN1 as an input and put the result in ADPRES3. Program 4 converts with AIN2 as an input and put the result in ADPRES4. Program 5 converts with AIN3 as an input and put the result in ADPRES5. Since the settings of ADPE7 and 6 are off, all programs end. ADF becomes 0.
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TMP19A71
13.6.3
Synchronization to an Optional Timing of PWM Cycle (Read twice)
Example of Use: Connect the DC-shunt output to AIN1. A single shunt system executes conversions at the timing where all U, V, W are other than H or L. Output data is to be updated every PWM cycle, and a current is to be detected every PWM cycle.
PWM Counter=max(MDPRD)
U
W U V
V U
Triangular Wave PWM U-phase V-phase W-phase Setting Timing
V W
W
PWM Counter=1
Conversion Timing ADF Result Processing
Figure 13.6.3
AD Converter
Example of Use 3 Timing
i) Setting ADMODSEL0 = **** **** **** ***1: PMD mode ADPMOD00 = **** **** **** ***1: ADC enabled ADPMOD01 = 0000 0000 0000 1111: Select a conversion register0, 1, 2, or 3 ADCSET00= 0001 0001 0001 0001 : Select AIN ADCSETT00= **** **** 0101 0000 : Select PMDTRG0 or 1 TRGCR0 = **** **** **00 1001 : PMD trigger setting TRGCMP00 = Any of CMPU-CMPV: PMD trigger timing setting TRGCMP01 = Any of CMPV-CMPW: PMD trigger timing setting i) Operation TRG0MD and TRG1MD are 001 after 1 is set to ADEN, and TRGCMP00 and 01 have effect at the max of a PWM counter. A conversion starts when PWM counter= TRGCMP00. ADF becomes 1. Program 0 and 1 with PMDTRG0 selected convert with AIN1 as an input and put the results in ADPRES0 and 1 each. A conversion starts when PWM counter=TRGCMP01. Program 2 and 3 with PMDTRG1 selected convert with AIN1 as an input and put the results in ADPRES2 and 3 each. Since the settings of AD7-4 are off, the program ends here. ADF becomes 0. i) Result Processing Iu=(ADPRES0+ADPRES1)/2
Iw=(ADPRES2+ADPRES3)/2
ii) Setting ADMODSEL0 = **** **** **** ***1: PMD mode ADPMOD00 = **** **** **** ***1: ADC enabled ADPMOD01 = 0000 0000 0000 1111:Program 0, 1, 2, and 3 enabled ADCSET00= 0001 0001 0001 0001 : Select AIN ADCSETT00= **** **** 0101 0000 : Select PMDTRG0 or 1
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TMP19A71
TRGCR0 = **** **** **00 1001 : PMD trigger setting TRGCMP00 = Any of CMPW - CMPU: PMD trigger timing setting TRGCMP01 = Any of CMPU - CMPV: PMD trigger timing setting ii) Operation Since TRG0MD/TRG1MD=001 TRGCMP00 and 01 have effect where PWM counter is the max. A conversion starts when PWM counter=TRGCMP00. ADF becomes 1. Program 0 and 1 with PMDTRG0 selected converts with AIN1 as an input and put the result in ADPRES0 and 1 each.  A conversion starts when PWM counter=TRGCMP01. Program 2 and 3 with PMDTRG1 selected convert with AIN1 as an input and put the results in ADPRES2 and 3 each. Since the settings of AD7-4 are off, the program ends here. ADF becomes 0. ii) Result Processing Iw=(ADPRES0+ADPRES1)/2 Iv=(ADPRES2+ADPRES3)/2
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TMP19A71
14. Motor Control Circuit (PMD: Programmable Motor Driver)
The TMP19A71 contains a two-channel programmable motor driver (PMD). In addition to a 3-phase waveform generation circuit, the PMD also has a sync sampling signal generation circuit for sampling operations of the AD converter. By implementing these functions by hardware, the load on software can be reduced, and vector control of brushless DC motors can easily be implemented.
14.1 Functional Block Diagram Port
PMD
3-phase Waveform Generation Circuit
U to Z
IM Bus
TX19A Core Processor
EMG
Sync Sampling Signal Generation Circuit
Port EMG
TRG AD Converter AIN
Figure 14.1.1
PMD Functional Block Diagram
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14-1
TMP19A71
14.2 PMD Registers
Table 14.2.1
Address 0xFFFF_C300 0xFFFF_C304 0xFFFF_C308 0xFFFF_C30C 0xFFFF_C310 0xFFFF_C314 0xFFFF_C318 0xFFFF_C31C 0xFFFF_C320 0xFFFF_C324 0xFFFF_C328 0xFFFF_C32C 0xFFFF_C330 0xFFFF_C340 0xFFFF_C344 0xFFFF_C348 0xFFFF_C34C 0xFFFF_C350 0xFFFF_C354 0xFFFF_C358 0xFFFF_C35C 0xFFFF_C360 0xFFFF_C364 0xFFFF_C368 0xFFFF_C36C 0xFFFF_C370 Bits 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 MDCR0 MDCNT0 MDPRD0 CMPU0 CMPV0 CMPW0 MDOUT0 EMGREL0 EMGCR0 TRGCR0 TRGCMP00 TRGCMP01 TRGCMP02 MDCR1 MDCNT1 MDPRD1 CMPU1 CMPV1 CMPW1 MDOUT1 EMGREL1 EMGCR1 TRGCR1 TRGCMP10 TRGCMP11 TRGCMP12
PMD Register Map
Register Name PMD0 Control Register PMD0 Count Register PMD0 Period Register PMD0 Compare Register U PMD0 Compare Register V PMD0 Compare Register  PMD0 Output Register EMG0 Release Register EMG0 Control Register Trigger Control Register (PMD0) Trigger Compare 0 Register (PMD0) Trigger Compare 1 Register (PMD0) Trigger Compare 2 Register (PMD0) PMD1 Control Register PMD1 Count Register PMD1 Period Register PMD1 Compare Register U PMD1 Compare Register V PMD1 Compare Register W PMD1 Output Register EMG1 Release Register EMG1 Control Register Trigger Control Register (PMD1) Trigger Compare 0 Register (PMD1) Trigger Compare 1 Register (PMD1) Trigger Compare 2 Register (PMD1)
Mnemonic
Note: These registers must be accessed as a 16-bit quantity, unless otherwise noted. These registers do not support bit manipulation instructions.
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14.3 PMD Components
The two PMD channels are, essentially, functionally equivalent so that only PMD0 is explained here.
14.3.1
Three-Phase Waveform Generation Circuit
MDCR0
MDOUT0
EMGCR0
MDCR0
EMGREL0
MDPRD0 CMPU0 CMPV0 CMPW0 INTPMD0
PWM
PWMU PWMV PWMW
Conduction Control
u x v y w z
Protection Control
u' x' v' y' w' z'
Dead Time Control
Port Control
U X V Y W Z
EMG0
PWMsync
MDCNT0
INTEMG0
Figure 14.3.1 Three-Phase Waveform Generation Circuit
The 3-phase waveform generation circuit consists of a pulse width modulation (PWM) circuit, a conduction control circuit, an EMG protection (emergency stop) circuit and a dead time control circuit. The pulse width modulation circuit generates independent 3-phase PWM waveforms with the same PWM carrier wave. The conduction control circuit determines the output pattern for each of the upper and lower sides of the U, V and W phases. The EMG protection circuit enables emergency output stop by EMG0 input. The dead time control circuit prevents a short circuit which may occur when the upper side and lower side are switched.
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TMP19A71 14.3.2 Pulse Width Modulation Circuit (PWM Waveform Generation Unit)
PMD Control Register MDCR0
15-8 |7|6|-|-|3,2,1|0
3
PWM Counter Register MDCNT0
15-0
PWM Control
PWM Sync Clock
PWM Interrupt INTPWM0
PWMsync IMCLK
Up/Down
PWM Counter
Selector 0x0001 PWM Period Register MDPRD0
15-0
Selector/ Latch
PWM Compare Register CMPU0
15-0
BufferU
  
PWMU0
CMPV0
15-0
PWMV0 BufferV
Figure 14.3.5
CMPW0
15-0
PWMW BufferW
To Sync Sampling Signal Generation Circuit
Figure 14.3.2 Pulse Width Modulation Circuit
The pulse width modulation circuit has a 16-bit up-/down-counter (PWM counter) and generates PWM carrier waves with a resolution of 35.7 ns (IMCLK = 28 MHz). The PWM carrier wave mode can be selected from the following two modes: PWM Mode 0 : Edge PWM (Sawtooth wave modulation) PWM Mode 1 : Center PWM (Triangular wave modulation) The MDPRD0 register is used to specify the PWM period. The MDPRD0 is double-buffered and the comparator input is updated at every PWM period or at every half PWM period. Sawtooth wave PWM IMCLK [Hz] : MDPRD0 register value =  PWM frequency [Hz] IMCLK [Hz] : MDPRD0 register value =  PWM frequency x 2 [Hz]
Triangular wave PWM
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TMP19A71
The pulse width modulation circuit compares the PWM compare registers of the 3 phases (CMPU0, CMPV0, CMPW0) and the carrier wave generated by the PWM counter (MDCNT0) to determine which is larger to generate PWM waveforms with the desired duty. The PWM compare register of each phase has a compare register (double-buffer structure). The PWM compare register value is loaded into the corresponding compare register at every PWM period (when the internal counter value matches the MDPRD0 value). It is also possible to update the compare register at every half PWM period.
[Sawtooth wave] MDCNT0
[MDPRD0] [CMPU0]
MDCNT0 counts up to the MDPRD0 value and it is then cleared to 0 in the next cycle.
Time on
PWMU waveform
off
When down-counting switches to up-counting, the value 1 continues for two cycles. When up-counting switches to down-counting, the peak value (MDPRD0) continues for two cycles.
[Triangular
wave]
MDCNT0
[MDPRD0] [CMPU0]
Time
PWMU waveform
on off
Figure 14.3.3 PWM Waveforms Three-phase PWM waveforms can be generated in the following two modes: (1) 3-phase independent mode: Each of the PWM compare registers for the three phases is set independently to generate independent PWM waveforms for each phase. This mode is used to generate drive waveforms such as sinusoidal waves. (2) 3-phase common mode: Only the U-phase PWM compare register is set to generate identical PWM waveforms for all the three phases. This mode is used for rectangular wave drive of brushless DC motors.
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The pulse width modulation circuit generates PWM interrupt requests in synchronization with PWM waveforms. The PWM interrupt period can be set to half a PWM period, one PWM period, two PWM periods, or four PWM periods. When the PWM interrupt period is set to two or four PWM periods, the first interrupt after the counter is started occurs at any timing in the specified period. For example, if an interrupt is to be generated at every four PWM periods, the first interrupt will be generated any time during the first to fourth PWM periods with the second and subsequent interrupts generated at every fourth PWM period.
MDCNT0 MDPRD0=0x105 MDPRD0=0x100
If the MDPRD0 is reloaded during this period, the counter counts up to the value previously set in the MDPRD0 and then starts counting down from the new value.
Time PWM period MDPRD0 PWM counter MDCNT0 INTPMD0 INTPRD0=0x0 (0.5 period)
0x100 0x105
0x003 0x002 0x001 0x001 0x002  0x097 0x098 0x099 0x100 0x105 0x104 0x103 0x102
Figure 14.3.4 MDPRD0 Reload Timing (Triangular Wave, Interrupt at Every 0.5 PWM Period)
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PMD0 Control Register 7 MDCR0 (0xFFFF_C300) Bit Symbol Read/Write Reset Value Function 15 Bit Symbol Read/Write Reset Value 14 13 12 DTR R/W 0x00 11 10 9 8 UPDWN R 0 6 SYNCEN R/W 0 5 DTYMD R/W 0 4 PINT R/W 0 3 INTPRD R/W 0 2 1 PWMMD R/W 0 0 PWMEN R/W 0
Symbol UPDWN SYNCEN DTYMD
Name PWM counter flag PMD synchronized start Duty mode 0: Up-counting 1: Down-counting 0: Disable synchronized start 1: Enable synchronized start 0: 3-phase common mode 1: 3-phase independent mode
Function
0: Interrupt request when PWM counter = 1 1: Interrupt request when PWM counter = MDPRD PINT PWM interrupt timing [PWM counter = MDPRD when edge mode is selected (PWMMD=0). PWM counter = 1 or MDPRD when 0.5 PWM period is selected (INTPRD=00).] 00: Interrupt request at every 0.5 PWM period (PWM mode1: triangular waves only) INTPRD PWM interrupt period 01: Interrupt request at every PWM period 10: Interrupt request at every 2 PWM periods 11: Interrupt request at every 4 PWM periods PWMMD PWMEN PWM mode PWM counter start 0: PWM Mode 0: edge PWM (sawtooth waves) 1: PWM Mode 1: center PWM (triangular waves) 0: Stop & clear 1: Start
Note: The settings in the MDCR0 register must be changed while the PWMEN bit is 0. It is also not allowed to change the MDCR0 settings at the same time as writing to the PWMEN bit to start or stop the PWM counter.
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PMD0 Count Register 15 Bit Symbol MDCNT0 (0xFFFF_C304) Read/Write Reset Value Function 14 13 12 11 10 9 8 R 0x0000 PWM counter value: 0x0001 to 0xFFFF 7 6 5 4 3 2 1 0 MDCNT
PMD0 Period Register 15 Bit Symbol MDPRD0 (0xFFFF_C308) Read/Write Reset Value Function
MDPRD0.
14
13
12
11
10
9
8 R/W
7
6
5
4
3
2
1
0
MDPRD 0x0000 PWM carrier wave period (Must be within 0x0010 to 0xFFFF.)
Note: This register is double-buffered; the value written to this register takes effect when MDCNT0 =
PMD0 Compare Registers (U, V, W) 15 CMPU0 (0xFFFF_C30C) CMPV0 (0xFFFF_C310) CMPW0 (0xFFFF_C314) CMPU0 CMPV0 CMPW0 PWM Compare U Register PWM Compare V Register PWM Compare W Register
cycle waveform is generated. Note 2 : These registers are double-buffered; the values written to these registers take effect when MDCNT0 = MDPRD0.
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Symbol
CMPU CMPV CMPW
Read/Write Reset Value
R/W 0x0000
0x0000 to 0xFFFF: U-phase pulse width duty 0x0000 to 0xFFFF: V-phase pulse width duty 0x0000 to 0xFFF: W-phase pulse width duty
Note 1 : When CMPx0=0, a 0%-duty cycle waveform is generated. When CMPx0  MDPRD0, a 100%-duty
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Detailed Description of the PMD0 Registers
Symbol UPDWN SYNCEN DTYMD PINT INTPRD Name PWM counter flag PMD synchronized start Duty mode PWM interrupt timing PWM interrupt period Function Indicates whether the PWM counter is up-counting or down-counting. When edge PWM is selected, this bit is always read as 0. Enables the PMD synchronized start function. Selects whether to make duty setting independently for each phase or to use the CMPU register setting for all three phases. Selects whether to generate an interrupt when PWM counter equals 1 or the MDPRD value. Selects the PWM interrupt period from 0.5 PWM period, one PWM period, two PWM periods and four PWM periods. If this bit is changed during operation, an interrupt may occur at that time. PWMMD PWMEN PWM mode Waveform generation circuit enable/disable Selects PWM Mode 0 (edge PWM, sawtooth wave) or PMW Mode 1 (center PWM, triangular wave). When this bit is cleared to stop and clear the PWM counter, output ports become high-impedance. Before setting this bit to 1 to start the PWM counter, it is necessary to set all the other bits in the MDCR0 register. While this bit is set to 1, do not change the MDCR0 settings other than the PWMEN bit. MDCNT MDPRD PWM counter PWM period A 16-bit counter for reading the PWM period count value. A 16-bit register for specifying the PWM period. This register is double-buffered and can be changed even when the PWM counter is counting. The buffer is loaded at every PWM period. (That is, when the PWM counter matches the MDPRD value. When 0.5 PWM period is selected, loading is performed when the PWM counter matches 1 or MDPRD0.) See Figure 14.3.4. CMPU CMPV CMPW PWM pulse width 16-bit compare registers for determining the output pulse width of U, V and W phases. These registers are double-buffered. Pulse width is determined by comparing the buffer and the PWM counter to evaluate which is larger. When CMPx0 = 0, a 0% duty-cycle waveform is generated. When CMPx0 >= MDPRD0, a 100% duty-cycle waveform is generated. (To be loaded when the PWM counter matches the MDPRD value. When 0.5 period is selected, loading is performed when the PWM counter matches 1 or MDPRD.)
Setting the SYNCEN bit of the MDCR0 register to 1 enables the PMD synchronized start function. When the PWMEN bit of the MDCR0 is set to 1 with the PMD synchronized start function enabled, PMD0 is put on standby for starting as soon as the PWMEN bit of the MDCR1 is set to 1 to start PMD1. By setting the SYNCEN and PWMEN bits simultaneously, PMD0 can be put on standby for synchronized start. When the synchronized start function is enabled for both PMD0 and PMD1 (MDCR0.SYNCEN=1, MDCR1.SYNCEN=1), the channel that is enabled first (MDCRx.PWMEN bit=1) is put on standby and starts operating as soon as the other channel is enabled. Even when the synchronized start function is enabled, registers are set independently for each channel. To operate PMD0 and PMD1 with the same conditions, it is necessary to set the PMD0 and PMD1 registers identically.
Example: To start PMD0 in synchronization with PMD1 MDCR0 = 0y********_*1*****1 MDCR1 = 0y********_*******1 ; SYNCEN=1 (Enable the synchronized start function.) ; PWMEN=1 (Put PMD0 on standby.) ; PWMEN=1 (Start PMD1.)
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TMP19A71 14.3.3 Conduction Control Circuit
PMD Output Register MDOUT0
-- 12, 11 10, 9, 8 7, 6 5, 4, 3, 2, 1, 0
2
2
Fig.12.3.7
S
3
6
PWM sync IMCLK
Selector
Latch
u PWMU x
Continued from Fig.12.3.2
v PWMV y
Continue to Fig. 14.3.6
w PWMW z
Figure 14.3.5 Conduction Control Circuit
The conduction control circuit performs output port control according to the settings made in the PMD output register (MDOUT0). The MDOUT0 register bits are divided into two parts: settings for the synchronization signal for port output and settings for port output. The latter part is double-buffered and update timing can be set as synchronous or asynchronous to PWM. The output settings for six port lines are made independently for each of the upper and lower phases through the POLH and POLL bits of the MDOUT0 register. In addition, the UOC, VOC and WOC bits of the MDOUT0 register are used to select PWM or H/L output for each of the U, V, and W phases. When PWM output is selected, PWM waveforms are output. When H/L output is selected, output is fixed to either a high or low level. Table 14.3.1 shows a summary of U-phase port outputs according to port output and polarity settings in the MDOUT0.
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PMD0 Output Register 7 MDOUT0 (0xFFFF_C318) Bit Symbol Read/Write Reset Value 15 Bit Symbol Read/Write Reset Value  R 0 PSYNS R/W 0 14  R 0 13  R 0 6 5 WOC R/W 0 12 POLH R/W 0 11 POLL R/W 0 4 3 VOC R/W 0 10 WPWM R/W 0 9 VPWM R/W 0 2 1 UOC R/W 0 8 UPWM R/W 0 0
Symbol POLH POLL WPWM VPWM UPWM
Name Upper phase port polarity Lower phase port polarity W-phase PWM output V-phase PWM output U-phase PWM output 0: Low active 1: High active 0: Low active 1: High active 0: H/L output 1: PWM waveform output 0: H/L output 1: PWM waveform output 0: H/L output 1: PWM waveform output 00: Async to PWM
Function
PSYNCS
MDOUT transfer timing
01: Load when PWM counter  1 10: Load when PWM counter = MDPRD 11: Load when PWM counter = 1 or MDPRD
WOC VOC UOC
Note 1:
-phase output control -phase output control -phase output control
Before changing the POLH, POLL and PSYNCS bits of the MDOUT0 register, make sure that the MDCR0.PWMEN bit is cleared to 0.
See Table 14.3.1.
Note 2:
The xPWM and xOC bits of the MDOUT0 register are double-buffered; the values written to these bits take effect according to the timing selected in the MDOUT0.PSYNCS field.
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Table 14.3.1
Summary of U-Phase Port Outputs according to the UOC and UPWM Settings
Polarity: Active low (POLH, POLL=0)
MDOUT Bit 1 0 Bit 0 0 MDOUT0 0: H/L output 1: PWM output U output X output U output X output H H PWM
Polarity: Active high (POLH, POLL=1
MDOUT Bit 1 0 Bit 0 0 MDOUT0 0: H/L output 1: PWM output U output X output U output X output L L
PWM
L
PWM
PWM PWM
H
0
1
L
H
PWM
0
1
H
L
H
1
0
H
L
PWM
L
1
0
L
H
PWM PWM
1
1
H
H
PWM
PWM
1
1
L
L
PWM
The VOC and VPWM bits and the WOC and WPWM bits should be set for the V phase and the W phase, respectively, as shown in the above table. Name Output port polarity Port output sync setting U-, V-, W-phase output control POLL, POLH PSYNCS UOC, VOC, WOC, UPWM, VPWM, WPWM Symbol when MDCR0.PWMEN=0. Select port output timing for the U, V and W phases. Select either MDCNT0 (PMD0 compare register) peak/bottom sync or async. Specify port output settings for the U, V and W phases (see Table 14.3.1). Function Select the output port polarity for the upper and lower phases. Set these bits
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14.3.4
EMG Protection Circuit
EMG Control Register EMG Release Register
PWM
-
EMGCR0
-|2|1|0
3
EMGREL0
7,6,5,4,3,2,1,0
8
EMG Protection Control
PEMG0 EMG Signal from EMG
Port
INTEMG0 EMG Interrupt Request
u
u'
x
x' v'
Continued from Figure 12.3.5
v y
To continue to
y'
Figure 12.3.7
w
w'
z
z'
Figure 14.3.6 EMG Protection Circuit
The EMG protection circuit is activated when the EMG input from the EMG0 (PA6) pin becomes the active state specified in the port A EMG control register (PAECR). When the PA6 pin is not configured as an EMG input pin, the EMG protection circuit does not function. The EMG protection circuit offers an emergency stop mechanism: when the EMG input is asserted, an EMG interrupt request (INTEMG0) is generated and the PMDTRG0 output to the AD converter is disabled. When only the PMD is protected with the EMG input pin enabled, all six port output lines output inactive signals. EMG protection is set through the EMG control register (EMGCR0). A read value of 1 in the EMGST bit of the EMGCR0 indicates that the EMG protection circuit is active. In this state, EMG protection can be released by setting all the port output lines inactive (MDOUT[10:0]= 00000000000) and then setting the EMGRS bit of the EMGCR0 to 1. To disable the EMG protection function, the following sequence of operations must be performed consecutively. This sequence becomes invalid if it is interrupted by any operation on the EMGCR0 or EMGREL0 register before it is completed. 1) Write 0x5A in the EMGREL0 register. 2) Write 0xA5 in the EMGREL0 register. 3) Clear the EMGEN bit of the EMGCR0 register to 0. If protection is released in the EMG protection circuit while the EMG input pin is asserted, protection is applied again. For details about the port settings related to the EMG protection function, see section 8.12 Notes on Using the EMG Input Pins (PA6, PA8).
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EMG0 Release Register 7 Bit Symbol EMGREL0 (0xFFFF_C31C) Read/Write Reset Value Function 6 5 4 EMGREL W 0x00 The EMG protection circuit can be disabled by writing 0x5A and 0xA5 in this order to this register and then clearing EMGCR0.EMGEN bit to 0. 3 2 1 0
EMG0 Control Register Bit Symbol EMGCR0 (0xFFFF_C320) Read/Write Reset Value 7  R 0 6  R 0 5  R 0 4  R 0 3  R 0 2 EMGST R 0 1 EMGRS W 0 0 EMGEN R/W 1
Symbol EMGST EMGRS EMGEN
Name EMG protection state EMG protection release EMG protection circuit enable/disable 0:  1: Protected 0:  1: Release protection 0: Disable 1: Enable
Function
Detailed Description of the EMG Control Register
Name EMG protection state EMG protection release Symbol EMGST EMGRS Function The EMG protection state can be known by reading this bit. EMG protection can be released by setting MDOUT[10:0] to 00000000000 and then setting the EMGRS bit to 1. EMG protection circuit enable/disable EMGEN The EMG protection circuit is enabled by setting this bit to 1. In the initial state, the EMG protection circuit is enabled. To disable this circuit, write 0x5A and 0xA5 in this order to the EMGREL0 register and then clear the EMGEN bit to 0.
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TMP19A71 14.3.5 Dead Time Control Circuit
PMD Control Register MDCR0
158|-|-|-|-|-|-|-|-
PMD Output Register MDOUT0
- - - 12,11 -,-,- -,- -,-,-,-,-,-
IMCLK
1/2
ON Delay Circuit
U X
u' x'
ON Delay Circuit
V Y
Continued from Figure 14.3.6
v' y'
ON Delay Circuit w' z'
W
Z
Dead Time Unit
Output Polarity Switching Unit
Figure 14.3.7 Dead Time Control Circuit
The dead time control circuit consists of a dead time unit and an output polarity switching unit. For each of the U, V, and W phases, the ON delay circuit introduces a delay (dead time) when the upper and lower phases are switched to prevent a short circuit. The dead time is set to the DTR field in the MDCR0 register as an 8-bit value with a resolution of 71.4 ns (at IMCLK = 28 MHz). No delay time is inserted when DTR=0x00. The output polarity switching unit allows the polarity (active high or active low) of the upper and lower phases to be independently set through the POLH and POLL bits of the MDOUT0 register.
PMD0 Control Register
7 MDCR0 (0xFFFF_C300) Bit Symbol Read/Write Reset Value Function 15 Bit Symbol Read/Write Reset Value Function UPDWN R 0 to 0. 14 13 12 DTR R/W 0x00 Dead time: 71.4 ns x 8 bits (max. 18.2 sIMCLK = 28 MHz 11 10 9 8 6 R/W 0 Must be set 5 DTYMD R/W 0 4 PINT R/W 0 3 INTPRD R/W 0 2 1 PWMMD R/W 0 0 PWMEN R/W 0
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14.3.6
Sync Sampling Signal Generation Circuit
3-Phase Waveform Generation Circuit MDCNT0 PWM Sync Signal
TRGCR0
TRGCMP00 PWM Sync
TBUF00
Slope Selection
PMDTRG00
AD Converter Control Circuit
TRGCMP01 PWM Sync
TBUF01
PMDTRG01
TRGCMP02 PWM Sync
TBUF02
PMDTRG02
Figure 14.3.8 Sync Sampling Signal Generation Circuit
The sync sampling signal generation circuit generates trigger signals for starting ADC sampling in synchronization with PWM. The ADC trigger signal (PMDTRG0) is generated by a match between the MDCNT0 and TRGCMP0. The signal generation timing can be selected from up-count match, down-count match, and up-/down-count match. When the edge PWM mode is selected, the ADC trigger signal is generated on an up-count match. When PWM output is disabled (MDCR0.PWMEN=0) or EMG protection is applied, trigger output is also disabled.
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Trigger Control Register (PMD0) 15 Bit Symbol TRGCR0 (0xFFFF_C324) Read/Write Reset Value  R 0 14  R 0 13  R 0 12  R 0 11  R 0 10  R 0 9  R 0 8 7 TRG2MD R/W 000 6 5 4 TRG1MD R/W 000 3 2 1 TRG0MD R/W 000 0
Symbol TRG2MD
Name PMDTRG2 mode setting
Function
000: Trigger output disabled 001: Trigger output on down-count match 010: Trigger output on up-count match
TRG1MD
PMDTRG1 mode setting
011: Trigger output on up-/down-count match 100: Trigger output at PWM carrier peak 101: Trigger output at PWM carrier bottom 110: Trigger output at PWM carrier peak/bottom
TRG0MD
PMDTRG0 mode setting
111:
Note: The TRG0MD, TRG1MD and TRG2MD fields must be set while MDCR0.PWMEN=0.
Trigger Compare Registers (PMD0) 15 TRGCMP02 (0xFFFF_C330) TRGCMP01 (0xFFFF_C32C) TRGCMP00 (0xFFFF_C328)
Note1: The trigger compare registers must be set to satisfy the following conditions: 1  RGCMP00, TRGCMP01, TRGCMP02 MDPRD0 Note 2: These registers are double-buffered; the values written to these registers take effect at the following timings: TRGxMD=001: The register values take effect when MDCNT0=MDPRD0. TRGxMD=010: The register values take effect when MDCNT0=0. TRGxMD=011: The register values take effect when MDCNT0=MDPRD0 or 0.
14
13
12
11
10
9
8 
7 R/W
6
5
4
3
2
1
0
Bit Symbol Read/Write Reset Value Function
0x0000 PMDTRG0 is output on a match between this register and MDCNT0.
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15. Encoder Input Circuit
15.1 Functional Overview
(1) (2) (3) (4) (5) Allows direct input of the incremental encoder signal. Contains a x4 multiplier circuit and a rotation direction control circuit. Contains an absolute position detection counter. Generates an interrupt on a match with the encoder pulse position set value. Incorporates noise filters in the signal input part.
ENCA ENCB ENCZ
Noise Filter Noise Filter Noise Filter Select Decoder Interrupt Request Control
Interrupt Request INTENC
Figure 15.1.1 Block Diagram of the Encoder Input Circuit
Note: Unless otherwise specified, the registers for the encoder input circuit must be accessed as a 16-bit quantity. Bit manipulation instructions cannot be used on these registers.
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15.2 Register Description
Encoder Input Control Register
7 ENTNCR Bit Symbol (0xFFFF_C400) Read/Write Reset Value Bit Symbol Read/Write Reset Value ZEN 0 15 ENCLR W 0 0 0 0 6 CUNEN 0 14 U/D 13 ZDET 5 NR1 00 12  4 NR0 R/W 0 11  R 0 0 0 0 0 10  0 9  0 8  3 ENCAP 2  1  0 
Symbol ENCLR U/D ZDET ZEN CUNEN
Name Encoder pulse counter clear Encoder rotation direction Phase Z detection state Counter clear by phase Z Encoder pulse counter enable 1: CW 0: CCW 1: Phase Z is detected.
Function Writing a 1 and then a 0 to this bit clears the encoder counter.
0: The CUNEN bit is set to 1 or a reset is applied. 1: Enable 0: Disable 1: Enable 0: Disable 00: No filter 01: Eliminate pulses of less than 31/IMCLK as noise 10: Eliminate pulses of less than 63/IMCLK as noise 11: Eliminate pulses of les than 127/IMCLK as noise 1: Enable 0: Disable
NR[1:0]
Noise filter
ENCAP
Encoder interrupt request enable
Note 1: The ENTNCR register must be set after all the other relevant registers have been set. Note 2: Do not change the settings in this register other the ENCLR and CUNEN bits while the encoder counter is operating. Note 3: If the CUNEN bit is cleared to 0 when ENCNT=ENINT, the INTENC interrupt is generated. Note 4: To re-enable the encoder counter after disabling it by CUNEN=0, clear the counter value by using the ENCLR bit.
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Table 15.2.1 Detailed Description of the Encoder Input Control Register
Name Encoder pulse counter clear Encoder rotation direction Symbol ENCLR U/D starts counting again. When the motor is rotating in CW direction (phase A of the incremental encoder signal is 90 degrees ahead of phase B), this bit is set to 1. When the motor is rotating in CCW direction (phase A is 90 degrees behind phase B), this bit is cleared to 0. Z phase detection state ZDET This bit is cleared to 0 when a 1 is written to the CUNEN bit and at reset. It is set to 1 on the next ZDETECT--the signal to be output on the rising edge (CW direction) or falling edge (CCW direction) of the incremental encoder signal phase Z. (This bit is independent of the ZEN value.) Counter clear by phase Z ZEN When the motor is rotating in CW direction, this bit is cleared to 0 on the rising edge of phase Z (ZDETECT). When the motor is rotating in CCW direction, this bit is cleared to 0 on the falling edge of phase Z (ZDETECT). If ENCLK (a clock obtained by multiplying the phase A and phase B signals by 4) and ZDETECT coincide with each other, the counter is cleared to 0 without counting. Encoder pulse counter enable Noise filter CUNEN NR1,0 When CUNEN=1, the ZDET bit is cleared to 0 and the encoder counter (ENCNT) is enabled. When CUNEN=0, the encoder counter is disabled. 00: No filter 01: Eliminate pulses of less than 31/IMCLK as noise (1.11 s IMCLK = 28 MHz) 10: Eliminate pulses of less than 63/IMCLK as noise (2.25 s IMCLK = 28 MHz) 11: Eliminate pulses of less than 127/IMCLK as noise (4.54 s IMCLK = 28 MHz) Encoder interrupt request ENCAP ENCAP=1 enables interrupt request signal generation. ENCAP=0 disables interrupt request signal generation. Function Writing a 1 and then a 0 to this bit clears the encoder counter to 0. Then, the counter
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Encoder Counter Reload Register 15 ENRELOAD Bit Symbol Reset Value Function (0xFFFF_C404) Read/Write 14 13 12 11 10 9 8  R/W 0x0000 Encoder counter target value: 0x0000 to 0xFFFF (input pulse count multiplied by 4) When phase Z is used: Set the number of pulses required for one rotation When phase Z is not used: Set the number of pulses required for one rotation minus one 7 6 5 4 3 2 1 0
When the encoder counter (ENCNT) is up-counting, the counter is zero-cleared on the next ENCLK timing after the count value reaches the ENRELOAD value. When the encoder counter (ENCNT) is down-counting, it is re-loaded with the ENRELOAD value on the next ENCLK timing after the counter value reaches 0.
Encoder Compare Register 15 ENINT Bit Symbol Reset Value Function (0xFFFF_C408) Read/Write 14 13 12 11 10 9 8  R/W 0x0000 Interrupt request generation position: 0x0000 to 0xFFFF When the encoder counter matches the value set in this register, an interrupt request is generated. 7 6 5 4 3 2 1 0
When the encoder counter (ENCNT) value reaches the ENINT value, an interrupt request (INTENC ) is generated. When ZEN=1, however, an interrupt request is not generated until the ZDET bit is set to 1.
Encoder Counter 15 ENCNT Bit Symbol Reset Value Function (0xFFFF_C40C) Read/Write 14 13 12 11 10 9 8  R 0x0000 0x0000 to 0xFFFF: Up-/down counter that counts encoder pulses 7 6 5 4 3 2 1 0
When the motor is rotating in CW direction, the encoder counter is an up-counter to be zero-cleared on the next ENCLK timing after the count value reaches the ENRELOAD value. When the motor is rotating in CCW direction, the encoder counter is a down-counter to be re-loaded with the ENRELOAD value on the next ENCLK timing after the count value reaches 0.
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15.3 Operation
Phase A Input ENCA
Phase B Input ENCB
Phase Z Input ENCZ
Motor Rotation Direction
CW
CCW
Rotation Direction State U/D Encoder Pulse ENCLK Phase Z Detection ZDETECT
Encoder Counter ENCNT
0x100 0x101  0x0
0x1
0x2
0x3
0x4
 0x1
0x2
0x1
0x0 0x0 0x5DB 0x5DA
Initial rotation (ZDET=0)
INTENC ENINT=0x2
Figure 15.3.1 Encoder Input Circuit Timing Chart (1) (ZEN=1, ENRELOAD=0x05DB)
Phase A Input ENCA
Phase B Input ENCB Motor Rotation Direction Rotation Direction State U/D Encoder Pulse ENCLK
CW
CCW
Counter Clear
Encoder Counter ENCNT
Set ENCLR
Set ENCLR
0x100 0x101 0x102 0x103 0x0
0x1
0x2
0x1
0x2
0x1
0x0 0x0 0x5DB 0x5DA
INTENC ENINT=0x2
Figure 15.3.2 Encoder Input Circuit Timing Chart (2) (ZEN=0, ENRELOAD=0x5DB)
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(1) Each incremental encoder signal is connected to phase A, phase B, and phase Z, respectively. This signal is multiplied by four for being counted. (2) When the motor is rotating in CW direction (phase A is 90 degrees ahead of phase B), the encoder counter operates as an up-counter. When the count value reaches the ENERELOAD value, the counter is zero-cleared on the next ENCLK timing for counting up. (3) When the motor is rotating in CCW direction (phase A is 90 degrees behind phase B), the encoder counter operates as a down-counter. When the count value reaches 0, the counter is re-loaded with the ENRELOAD value on the next ENCLK timing for counting down. (4) When ZEN=1, the encoder counter is zero-cleared on the rising edge of phase Z (ZDETECT) while the motor is rotating in CW direction and on the falling edge of phase Z (ZDETECT) in the case of CCW direction. When ENCK and ZDETECT coincide with each other, no count operation is performed and the counter is zero-cleared. (5) When a 0 is written to the ENCLR bit, the counter is zero-cleared. (6) An interrupt request can be generated when the counter value reaches the ENINT value. When ZEN=1, however, an interrupt request cannot be generated until the ZDET bit is set to 1. (7) The ZDET bit is zero-cleared when a 1 is written to the CUNEN bit and at reset, and it is set to 1 on the next ZDETECT timing (regardless of the ZEN value). (8) The U/D bit is set to 1 when CW rotation is detected and to 0 when CCW rotation is detected.
TMP19A71
15-6
TMP19A71
15.4 How to Use the Encoder Input Circuit
15.4.1 Using the Encoder Interrupt Request
(1) Set the encoder pulse count. Assuming that the encoder requires 1200 pulses for one rotation, the pulse count (after being multiplied by 4) is set as follows:
ENRELOAD=1200x4=0x12C0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 1 1
(2) Set the encoder compare register value. For generating an interrupt request at counter value = 1000 (03E8H), the encoder compare register is set as follows:
ENINT=0x03E8 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0
(3) Enable the encoder counter, interrupt request, and Z-phase detection.
15 ENTNCR 14 13 12 11 10 9 8 7  6  5 4 3  2 1 0 -
(4) Operation 1. As the encoder rotates, the encoder decoder outputs x4 pulses (ENCLK) and rotation direction (U/D). 2. The encoder counter counts ENCLK pulses. Whether to count up or down is determined by rotation direction. 3. When phase Z is detected, the encoder counter is cleared. In the case of up-counting, when the count value matches the ENRELOAD register value, the counter is zero-cleared on the next ENCLK timing. In the case of down-counting, when the count value reaches 0, the counter is re-loaded with the ENRELOAD register value on the next ENCLK timing. 4. Up to the first Z-phase detection, the encoder counter value indicates not the absolute position of the actual encoder but the relative position from count start time. When phase Z is detected, the ZDET is set to 1 and the counter value now indicates the absolute position. 5. When a match occurs between the encoder compare register (ENINT) value and the encoder count value and the ZDET is set to 1, an ENINT interrupt request is generated. This interrupt request is generated regardless whether the counter is counting up or down.
TMP19A71
15-7
Under Development
TMP19A71
16. ROM Correction
This chapter describes the ROM correction function supported by the TMP19A71.
Note: The registers for the ROM correction function must be accessed as a 32-bit quantity. Bit manipulation instructions cannot be used on these registers.
16.1 Features
* * Up to eight 8-word sequences of data can be replaced. When the physical address stored in an address register (ADDREGn) matches the program counter (PC) value or the address generated by the DMAC (the lower five bits of the address are "don't care"), the data at the specified address in the on-chip ROM is replaced with the data from the RAM area corresponding to the address register. Writing an address to an address register causes ROM correction for the address to be enabled automatically. A reset is required to disable the ROM correction function. A correction requiring the replacement of more than eight words can be performed by replacing the ROM data with an instruction code which makes a branch to a specified location in the RAM area which contains substitution data.
* *
16.2 Operation
To correct data in a ROM area (or a projected ROM area), store the physical address of the area in an address register (ADDREGn). Store the substitution data in the RAM area corresponding to the address register. Writing an address to an address register causes ROM correction for the address to be enabled automatically. Upon reset, the ROM correction function is disabled. If the initial routine executed upon reset is used to correct ROM data, write a physical address to the relevant address register after a reset is released. The address registers to which addresses are written are enabled for ROM correction. When the stored address matches the PC value (if the TX19A core processor owns the bus) or the source or destination address issued by the DMAC (if the DMAC owns the bus), the data at the specified address in the ROM is replaced with the data stored in the corresponding RAM area. For example, storing addresses in the ADDREG0 and ADDREG3 enables correction for the respective ROM areas, so that the ROM correction circuit block constantly monitors the PC and DMAC-issued addresses for a match with a specified address and, if a match is detected, replaces data, while ignoring the ADDREG2 and ADDREG4 to ADDREG7. Each address register has bits 31:5 although only bits 17:5 are used for address comparison, in order to simplify the circuit. A match detected in the ROM correction circuit is internally ANDed with the ROMCS signal, which indicates a specified ROM address block, to determine an exact match. ROM addresses specified for correction must be located on eight-word boundaries, i.e., the lower five bits are 0. In other words, ROM data is always replaced in 32-byte units. If only part of 32 bytes needs to be replaced, substitution RAM data corresponding to the other bytes must be the same as the current data in the corresponding ROM addresses.
TXMP9A70
16-1
TMP19A71
The following table shows the relationship between the address registers and RAM areas. Table 16.2.1 Relationship between the ADDREGn Registers and RAM Areas
Address Register ADDREG0 ADDREG1 ADDREG2 ADDREG3 ADDREG4 ADDREG5 ADDREG6 ADDREG7 RAM Area 0xFFFF_BF00 to 0xFFFF_BF1F 0xFFFF_BF20 to 0xFFFF_BF3F 0xFFFF_BF40 to 0xFFFF_BF5F 0xFFFF_BF60 to 0xFFFF_BF7F 0xFFFF_BF80 to 0xFFFF_BF9F 0xFFFF_BFA0 to 0xFFFF_BFBF 0xFFFF_BFC0 to 0xFFFF_BFDF 0xFFFF_BFE0 to 0xFFFF_BFFF
G-BUS
Address Registers ADDREGx Compare Enable Compare Address [17:5] Compare Circuit
TX19A Core Processor
Load/Fetch Address [17:5]
Conversion Enable Converter Conversion Address Address
RAM
ROM
RAM Data
RAMCS Signal
ROMCS Signal
ROM Data
Figure 16.2.1 ROM Correction Block Diagram
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Under Development
TMP19A71
16.3 Registers
(1) ADDREG0 (0xFFFF_E540) Address Registers 7 Bit Symbol Read/Write Reset Value Function ADD07 0 6 ADD06 0 5 ADD05 0 4  R/W 1 1 1 1 1 3  2  1  0 
15 Bit Symbol Read/Write Reset Value Function ADD015 0
14 ADD014 0
13 ADD013 0
12
11
10 ADD010 0
9 ADD09 0
8 ADD08 0
ADD012 ADD011 R/W 0 0
23 Bit Symbol Read/Write Reset Value Function ADD023 0
22 ADD022 0
21 ADD021 0
20 Add020 0
19 ADD019 R/W 0
18 ADD018 0
17 ADD017 0
16 ADD016 0
31 Bit Symbol Read/Write Reset Value Function ADD031 0
30 ADD030 0
29 ADD029 0
28
27
26 ADD026 0
25 ADD025 0
24 ADD024 0
ADD028 ADD027 R/W 0 0
7 ADDREG1 (0xFFFF_E544) Bit Symbol Read/Write Reset Value Function ADD17 0
6 ADD16 0
5 ADD15 0
4  R/W 1
3  1
2  1
1  1
0  1
15 Bit Symbol Read/Write Reset Value Function ADD115 0
14 ADD114 0
13 ADD113 0
12 ADD112 0
11 ADD111 R/W 0
10 ADD110 0
9 ADD19 0
8 ADD18 0
23 Bit Symbol Read/Write Reset Value Function ADD123 0
22 ADD122 0
21 ADD121 0
20 ADD120 0
19 ADD119 R/W 0
18 ADD118 0
17 ADD117 0
16 ADD116 0
31 Bit Symbol Read/Write Reset Value Function ADD131 0
30 ADD130 0
29 ADD129 0
28 ADD128 0
27 ADD127 R/W 0
26 ADD126 0
25 ADD125 0
24 ADD124 0
TXMP9A70
16-3
TMP19A71
7 ADDREG2 (0xFFFF_E548) Bit Symbol Read/Write Reset Value Function ADD27 0
6 ADD26 0
5 ADD25 0
4  R/W 1
3  1
2  1
1  1
0  1
15 Bit Symbol Read/Write Reset Value Function ADD215 0
14 ADD214 0
13 ADD213 0
12 ADD212 0
11 ADD211 R/W 0
10 ADD210 0
9 ADD29 0
8 ADD28 0
23 Bit Symbol Read/Write Reset Value Function ADD223 0
22 ADD222 0
21 ADD221 0
20 ADD220 0
19 ADD219 R/W 0
18 ADD218 0
17 ADD217 0
16 ADD216 0
31 Bit Symbol Read/Write Reset Value Function ADD231 0
30 ADD230 0
29 ADD229 0
28 ADD228 0
27 ADD227 R/W 0
26 ADD226 0
25 ADD225 0
24 ADD224 0
7 ADDREG3 (0xFFFF_E54C) Bit Symbol Read/Write Reset Value Function ADD37 0
6 ADD36 0
5 ADD35 0
4  R/W 1
3  1
2  1
1  1
0  1
15 Bit Symbol Read/Write Reset Value Function ADD315 0
14 ADD314 0
13 ADD313 0
12 ADD312 0
11 ADD311 R/W 0
10 ADD310 0
9 ADD39 0
8 ADD38 0
23 Bit Symbol Read/Write Reset Value Function ADD323 0
22 ADD322 0
21 ADD321 0
20 Add320 0
19 ADD319 R/W 0
18 ADD318 0
17 ADD317 0
16 ADD316 0
31 Bit Symbol Read/Write Reset Value Function ADD331 0
30 ADD330 0
29 ADD329 0
28 ADD328 0
27 ADD327 R/W 0
26 ADD326 0
25 ADD325 0
24 ADD324 0
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Under Development
TMP19A71
7 ADDREG4 (0xFFFF_E550) Bit Symbol Read/Write Reset Value Function ADD47 0
6 ADD46 0
5 ADD45 0
4  R/W 1
3  1
2  1
1  1
0  1
15 Bit Symbol Read/Write Reset Value Function ADD415 0
14 ADD414 0
13 ADD413 0
12 ADD412 0
11 ADD411 R/W 0
10 ADD410 0
9 ADD49 0
8 ADD48 0
23 Bit Symbol Read/Write Reset Value Function ADD423 0
22 ADD422 0
21 ADD421 0
20 ADD420 0
19 ADD419 R/W 0
18 ADD418 0
17 ADD417 0
16 ADD416 0
31 Bit Symbol Read/Write Reset Value Function ADD431 0
30 ADD430 0
29 ADD429 0
28 ADD428 0
27 ADD427 R/W 0
26 ADD426 0
25 ADD425 0
24 ADD424 0
7 ADDREG5 (0xFFFF_E554) Bit Symbol Read/Write Reset Value Function ADD57 0
6 ADD56 0
5 ADD55 0
4  R/W 1
3  1
2  1
1  1
0  1
15 Bit Symbol Read/Write Reset Value Function ADD515 0
14 ADD514 0
13 ADD513 0
12 ADD512 0
11 ADD511 R/W 0
10 ADD510 0
9 ADD59 0
8 ADD58 0
23 Bit Symbol Read/Write Reset Value Function ADD523 0
22 ADD522 0
21 ADD521 0
20 ADD520 0
19 ADD519 R/W 0
18 ADD518 0
17 ADD517 0
16 ADD516 0
31 Bit Symbol Read/Write Reset Value Function ADD531 0
30 ADD530 0
29 ADD529 0
28 ADD528 0
27 ADD527 R/W 0
26 ADD526 0
25 ADD525 0
24 ADD524 0
TXMP9A70
16-5
TMP19A71
7
ADDREG6 (0xFFFF_E558) Bit Symbol Read/Write Reset Value Function ADD67 0
6
ADD66 0
5
ADD65 0
4
 R/W 1
3
 1
2
 1
1
 1
0
 1
15
Bit Symbol Read/Write Reset Value Function ADD615 0
14
ADD614 0
13
ADD613 0
12
ADD612 0
11
ADD611 R/W 0
10
ADD610 0
9
ADD69 0
8
ADD68 0
23
Bit Symbol Read/Write Reset Value Function ADD623 0
22
ADD622 0
21
ADD621 0
20
ADD620 0
19
ADD619 R/W 0
18
ADD618 0
17
ADD617 0
16
ADD616 0
31
Bit Symbol Read/Write Reset Value Function ADD631 0
30
ADD630 0
29
ADD629 0
28
ADD628 0
27
ADD627 R/W 0
26
ADD626 0
25
ADD625 0
24
ADD624 0
7
ADDREG7 Bit Symbol (0xFFFF_E55C) Read/Write Reset Value Function ADD77 0
6
ADD76 0
5
ADD75 0
4
 R/W 1
3
 1
2
 1
1
 1
0
 1
15
Bit Symbol Read/Write Reset Value Function ADD71 5 0
14
ADD714
13
ADD713
12
ADD712
11
ADD711 R/W
10
ADD710
9
ADD79
8
ADD78
0
0
0
0
0
0
0
23
Bit Symbol Read/Write Reset Value Function ADD72 3 0
22
ADD722
21
ADD721
20
ADD720
19
ADD719 R/W
18
ADD718
17
ADD717
16
ADD716
0
0
0
0
0
0
0
31
Bit Symbol Read/Write Reset Value Function ADD73 1 0
30
ADD730
29
ADD729
28
ADD728
27
ADD727 R/W
26
ADD726
25
ADD725
24
ADD724
0
0
0
0
0
0
0
Note: DMA transfer cannot be performed to an address register. DMA transfer can be performed to a data area in the RAM which contains substitution data. The ROM correction function can be used when either the TX19A core processor or DMAC owns the bus.
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TMP19A71
17. Flash Memory
This chapter describes the hardware configuration and operation of the flash memory contained in the TMP19A71.
17.1
Overview
Features
1) Memory capacity The TMP19A71 contains 2 Mbits (256 Kbytes) of flash memory, which is divided into two 128-Kbyte blocks. Each block can be independently protected from program and erase operations. While the TX19A core processor can access the flash memory through a full 32-bit data bus, an external flash programmer can only access the flash memory through a 16-bit data bus. Program and erase times Chip program time (including verify): 5 seconds (typ.) Chip erase time (including verify): 20 seconds (typ.)
Note: These program and erase times are typical values not including data transfer overhead. The actual chip program and erase times depend on the programming method used.
17.1.1
2)
3)
Programming modes The TMP19A71 flash memory can be programmed while mounted on a user board (On-Board Programming mode) or by using an EPROM programmer (Programmer mode).
* On-Board Programming modes
1) User Boot mode A user-created programming algorithm can be used. 2) Single Boot mode A Toshiba-defined serial interface protocol is used. * Programmer mode A general-purpose programmer can be used. (T. B. D)
5) Programming method Programming operations of the TMP19A71 flash memory are controlled by commands except for a few functions. The TMP19A71 contains a command sequencer which recognizes programming commands and automatically executes corresponding sequences of operation. This feature eliminates the need for the user to code complex program and erase sequences. The TMP19A71 provides an anti-programmer security feature for protecting the on-chip flash memory from being read by programming equipment. The TMP19A71 also allows the user to protect individual blocks of the flash memory from program or erase operations. This block protection feature is implemented by software; the hardware method (high voltage application) is not supported. The anti-programmer security feature is automatically enabled when both of the two blocks are placed under protection. When the Unprotect command is executed, the flash memory is automatically erased before block protection is lifted to ensure data security.
TMP19A71
17-1
TMP19A71
Table 17.1.1 Modified/Deleted Auto Programming Features
Available Auto Programming Features * Auto Program * Auto Chip Erase * Auto Block Erase * Auto Multi-Block Erase * Data Polling Modified/Deleted Features Modified: Block protection is available only under software control. Deleted: Erase Resume/Suspend mode
17.1.2
Block Diagram
Internal Address Bus Internal Data Bus Internal Control Bus
Mode Setting Internal Signal
Mode Control Control
ROM Controller Address Data Flash Memory
Control Logic Command Sequencer RDY/BSY Output
Address Latch
Data Latch
Column Decoder/Sense Amp Row Decoder
Flash Memory Array 256 KB
Erase Block Decoder
Figure 17.1.1
Flash Memory Block Diagram
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17-2
TMP19A71
17.2
Operating Modes
The TMP19A71 offers a total of four operating modes as shown in the table below. Table 17.2.1 Operating Modes Operating Mode Description
After a reset, the TX19A core processor executes out of the on-chip flash memory.
Single-Chip Mode
Normal Mode
Single-Chip mode is further divided into Normal mode in which the user application executes and User Boot mode which allows for re-programming of the flash memory while the TMP19A71 is installed on a printed circuit board. The user can freely define how to switch between Normal mode and User Boot mode. For example, the logic state on Port 00 can be used to determine whether to put the flash memory in Normal mode or User Boot mode. In this case, the user must include a routine in the application program to test the state of that port. After a reset, the TX19A core processor executes out of the on-chip boot ROM (which is a mask ROM). The boot ROM contains a routine to aid users in performing on-board programming of the flash memory via a serial port of the TMP19A71. The serial port is connected to an external host which transfers new data according to a prescribed protocol. This mode allows for re-programming of the flash memory with a general-purpose EPROM programmer. Use the programmer and programming adaptor recommended by Toshiba.
User Boot Mode
Single Boot Mode
Programmer Mode
The on-chip flash memory can be programmed in one of the following three modes: User Boot mode, Single Boot mode and Programmer mode. Of these modes, User Boot mode and Single Boot mode allow the flash memory to be programmed while the TMP19A71 is mounted on a printed circuit board. These two modes are collectively referred to as on-board programming modes.
TMP19A71
17-3
TMP19A71
The logic states on the TEST0, P90 to P93 and P94 (BOOT) pins during a reset sequence determine the mode of operation for the flash memory, as shown in Table 17.2.2. After the reset state is released, P94 (BOOT) and P90 to P93 can be configured as general-purpose I/O pins. After a reset, the TX19A core processor operates in compliance with the selected mode. When Programmer mode is selected, however, the RESET pin must be held at logic 0. The input pins listed in Table 17.2.2 must remain stable once the flash memory is put in a given mode of operation. Table 17.2.2 Modes of Operation
Operating Mode (1) Single-Chip Mode (2) Single Boot Mode (3) Programmer Mode Input Pins RESET 01 01 0 P90
(Note ) (Note )
P91
(Note ) (Note )
P92
(Note ) (Note )
P93
(Note ) (Note )
BOOT 1 0
(Note )
1
1
0
0
TEST0 0 0 1
TEST1 0 0 0
Note: Don't care. The pins must be held at 0 or 1.
(3) Programmer Mode Any condition other than (3)  RESET = 0 (1) RESET = 0 (2)
Reset
RESET = 0 Single-Chip Mode Single Boot Mode
Normal Mode
User Boot Mode
User-defined condition
On-Board Programming Mode
Parenthesized numbers indicate that the relevant pins are at the logic states shown in Table 17.2.2.
Figure 17.2.1 Mode Transitions
17.2.1
Reset Operation
To reset the TMP19A71, the RESET input must be kept at logic 0 at least for 10 ms after power-up.
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17-4
TMP19A71 17.2.2 Memory Maps
The memory map for the TMP19A71 varies according to the mode of operation selected for the on-chip flash memory, as shown below.
Single-Chip Mode On-Chip Peripherals
On-Chip RAM (10KB)
Single Boot Mode 0xFFFF_FFFF On-Chip Peripherals On-Chip RAM (Reserved) Used for debugging (Reserved) (Reserved) (Reserved) On-Chip Flash ROM Inaccessible 0x2000_0000 0x1FC3_FFFF (512 MB) 0x2000_0000 0xFFFF_FFFF
Programmer Mode Inaccessible 0xFFFF_FFFF
0xFFFF_BFFF 0xFFFF_9800 0xFF3F_FFFF 0xFF20_0000 0xFF00_0000 0xC000_0000 0xBF00_0000 0x4003_FFFF 0x4000_0000
0xFFFF_BFFF 0xFFFF_9800 0xFF3F_FFFF 0xFF20_0000 0xFF00_0000 0xC000_0000 0xBF00_0000 0x4003_FFFF 0x4000_0000 Inaccessible (512 MB) Inaccessible 0x2000_0000 0x4000_0000 Inaccessible 0xC000_0000
(Reserved) Used for debugging (Reserved) (Reserved) (Reserved) On-Chip ROM Shadow Inaccessible (512 MB)
User Program Area Maskable Interrupt Area Exception Vector Area
Boot MROM (KB) 0x1FC0_0000 0x0000_0000
0x1FC0_1FFF 0x1FC0_0000 0x0000_0000 On-Chip Flash ROM 0x0003_FFFF
0x0000_0000
Note: The addresses shown above are physical addresses.
Figure 17.2.2 TMP19A71 Memory Maps
When the TMP19A71 is started in Single Boot mode, the boot ROM (mask ROM) is mapped to an 8-Kbyte area starting from the reset vector (0x1FC0_0000), and the flash memory is mapped from 0x4000_0000. When the TMP19A71 is started in Single-Chip mode, the flash memory is mapped from the reset vector, and the flash memory shadow is mapped from 0x4000_0000. The following descriptions use virtual addresses, unless otherwise noted.
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17-5
TMP19A71
As shown in Figure 17.2.3, the TMP19A71 flash memory is comprised of two 128-Kbyte blocks.
256KB 128KB 128KB Block 0 Block 1
Figure 17.2.3 Flash Memory Block Architecture Table 17.2.3
Single-Chip mode Block 0 Block 1 0xBFC0_0000 to 0xBFC_FFFF (Shadow: 0x0000_0000 to 0x0001_FFFF) 0xBFC2_0000 to 0xBFC3_FFFF (Shadow: 0x0002_0000 to 0x0003_FFFF)
Block Addresses Based on Mode Setting
Single Boot mode 0x0000_0000 to 0x000_FFFF 0x0002_0000 to 0x0003_FFFF Programmer mode 0x0000_0000 to 0x0001_FFFF 0x0002_0000 to 0x0003_FFFF
17.2.3
Block Protection
The TMP19A71 flash memory is comprised of two 128-Kbyte blocks. To protect stored data from any program and erase operations, each block has a protect bit, which can be set by executing the Block Protect command sequence. Blocks in protection mode are protected from even the Chip Erase and Multi-Block Erase commands; these commands erase only unprotected blocks. Since protection status is stored in flash memory cells, it is retained if the chip is powered off. When both blocks are protected, the data stored in them cannot be read in Programmer mode, which provides a security feature (hereinafter referred to as the anti-programmer security feature).
17.2.4
Security Features When the TX19A Core Processor Is Active
Table 17.2.4 shows the security features available when the TX19A core processor is active. BLKA indicates Block 0 (at addresses 0xBFC0_0000 to 0xBFC1_FFFF), and BLKB indicates Block 1 (at addresses 0xBFC2_0000 to 0xBFC3_FFFF). In Programmer mode in which a general-purpose EPROM programmer is used, the security features available differ from those shown in the table below.
Table 17.2.4 Security Features of the TX19A Core Processor
DSU Function BLKA Write Protect BLKB Write Protect Use of DSU BLKA Read BLKB Read BLKA Program (Write) BLKB Program (Write) BLKA Erase BLKB Erase Chip Erase BLK Protect BLK Protect Unprotect (All Blocks) ID Read/Protect Verify Enabled Disabled OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON Yes Yes Yes ----No Yes Yes Yes ----Yes Yes Yes Yes ----Yes Yes Yes No ----No Yes No Yes ----No Yes Yes x ----No Yes No Yes ----No Yes Yes*1Yes*1 ----No Yes Yes Yes ----Yes Yes Yes Yes ---Yes Yes Yes Yes ----Yes Yes Yes Yes ----Yes
Yes: Can be used No: Cannot be used --: Not supported *1: The Chip Erase command erases only unprotected blocks.
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17-6
TMP19A71 DSU (EJTAG)-Probe Interface
The DSU-probe interface is used solely for software debugging using an external DSU-probe unit. Consult the DUS-probe operation manual for the details on debugging using the DSU-probe. When the TMP19A71 is in DUS (EJTAG) mode, the on-chip flash memory provides a security feature. (1) Permitting and prohibiting the use of a DSU-probe The TMP19A71 supports on-board debugging while it is installed on a printed circuit board. The TMP19A71 provides a feature to prohibit the use of a DSU-probe to prevent intrusive access to the flash memory. In DSU Prohibit mode, a DSU-probe is denied access to the entirety of the flash memory. (2) DSU Prohibit mode (Disabling debugging with a DSU-probe) Once program debugging is completed, write the Protect command to both blocks. This turns on the anti-programmer security feature. While the flash memory is in the secure state, a DSU-probe cannot read its contents. When the chip is powered off and powered on again, the flash memory is put in DSU Prohibit mode, which disables debugging using a DSU-probe until the flash memory exits DSU Prohibit mode. (3) DSU Permit mode (Enabling debugging with a DSU-probe) The flash memory can only be brought out of DSU Prohibit mode by clearing the DSUOFF bit in the SEQMOD to 0 and then writing a special code (0x0000_00C5) to the DSU Security Control (SEQCNT) register. This prevents runaway software from inadvertently turning off the DSU Prohibit feature. When the flash memory exits DSU Prohibit mode, the DSU interface is enabled. The flash memory can be secured again by setting the DSUOFF bit in the SEQMOD to 1 and writing 0x0000_00C5 to the SEQCNT while the chip is powered. DSU Security Mode Register
7 SEQMOD (0xFFFF_E510) Bit Symbol Read/Write Reset Value Function 15 Bit Symbol Read/Write Reset Value Function 23 Bit Symbol Read/Write Reset Value Function 31 Bit Symbol Read/Write Reset Value Function Note 1: The setting of the DSUOFF bit takes effect after the SEQCNT register is set. Note 2: This register must be accessed as a 32-bit quantity. Bits 1 to 31 are read as 0. Note 3: In the flash-version device, this register is initialized by a power-on reset. Note 4: This register does not support bit manipulation instructions.  R 0 30  R 0 29  R 0 28  R 0 27  R 0 26  R 0 25  R 0 24  R 0  R 0 22  R 0 21  R 0 20  R 0 19  R 0 18  R 0 17  R 0 16  R 0  R 0 14  R 0 13  R 0 12  R 0 11  R 0 10  R 0 9  R 0  R 0 6  R 0 5  R 0 4  R 0 3  R 0 2  R 0 1  R 0 0 DSUOFF R/W 1 1: DSU disabled 0: DSU enabled 8  R 0
TMP19A71
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TMP19A71
DSU Security Control Register
7 SEQCNT (0xFFFF_E514) Bit Symbol Read/Write Reset Value Function 15 Bit Symbol Read/Write Reset Value Function 23 bit Symbol Read/Write Reset Value Function 31 Bit Symbol Read/Write Reset Value Function 30 29 22 21 14 13 6 5 4 3 2 1 0  W  Must be written as 0x0000_00C5. 12 11 10 9 8  W  Must be written as 0x0000_00C5. 20 19 18 17 16  W  Must be written as 0x0000_00C5. 28 27 26 25 24  W  Must be written as 0x0000_00C5.
Note 1: This register must be accessed as a 32-bit quantity. Note 2: This register does not support bit manipulation instructions.
(4) Application example The following flowchart shows an example of how to use the security feature with a DSU-probe.
TMP19A71
DUS prohibited at power-up
(In mask ROM version, DSU is prohibited by reset.)
External port data, etc.
DSU permission judgment routine (user-created)
N
Exit DUS Prohibit mode? Y Program SEQMOD and SEQCNT to exit DSU Prohibit mode
[DSU Prohibit mode] The DSU-probe cannot be used.
[DSU Permit mode] The DSU -probe can be used until the chip is powered off.
Figure 17.2.4 Using the DSU Prohibit Feature
TMP19A71
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TMP19A71
17.3
On-Board Programming Mode
On-board programming allows re-programming of the flash memory while the TMP19A71 is soldered on a printed circuit board. The TMP19A71 provides two types of on-programming mode. In Single Boot mode, new data comes from a serial port under control of a Toshiba-provided routine in the boot ROM. User Boot mode allows you to create an algorithm of your own for flash memory erase and program operations. The TMP19A71 flash memory provides an anti-programmer security feature to prevent intrusive access to the flash memory while in Programmer mode. This security feature can be enabled upon completion of on-board programming to protect ROM data from being read by third parties.
17.3.1
User Boot Mode (Single-Chip Mode)
User Boot mode allows you to create a programming algorithm of your own. User Boot mode is one of the two submodes in Single-Chip mode; the other submode is Normal mode in which the TX19A core processor executes the user application. To re-program the flash memory, the mode of operation must be switched from Normal mode to User Boot mode. The user application code must include a mode judgment routine. The user must define the conditions for mode switching, based on the logic states on I/O ports of the TMP19A71. Additionally, the user must incorporate a programming algorithm into the user application code. After User Boot mode is entered, this programming algorithm is copied into the on-chip RAM to re-program the flash memory. The flash memory cannot be read while it is being erased or programmed. While the flash memory is being erased or programmed, all interrupts including nonmaskable interrupts must be disabled. Once re-programming is complete, it is recommended to protect flash memory blocks as required from accidental corruption. The pages that follow describe the general procedures for two cases where the programming routine is: a) stored within the TMP19A71 flash memory, and b) loaded from an external controller. For a detailed description of program and erase operations, see Section 17.4 On-Board Programming and Erasure.
TMP19A71
17-9
TMP19A71
User Boot Mode (1-A) Method 1: Storing a programming routine in the flash memory (1) Determine the conditions (e.g., pin states) required for the flash memory to enter User Boot mode and the I/O bus to be used to transfer new program code. Create hardware and software accordingly. Before installing the TMP19A71 on a printed circuit board, write the following program routines into a flash block using programming equipment. (a) Mode judgment routine: Code to determine whether or not to switch to User Boot mode (b) Programming routine: Code to download new program code from a host controller and (c) Copy routine: re-program the flash memory Code to copy the flash programming routine from the TMP19A71 flash memory to the TMP19A71 on-chip RAM
Routines (a), (b) and (c) are collectively called the programming procedure.
Host Controller
New Application Program Code
TMP19A71
Flash Memory Old Application Program Code [Programming Procedure]
(a) Mode Judgment Routine
I/O
(b) Programming Routine (c) Copy Routine
RAM
(2) The mode judgment routine written in one of the blocks in the flash memory determines whether to put the TMP19A71 flash memory in User Boot mode. If the specified conditions are met, the flash memory enters User Boot mode.
Host Controller
New Application Program Code
TMP19A71
Flash Memory Old Application Program Code [Programming Procedure]
(a) Mode Judgment Routine
I/O 0  1 RESET
(b) Programming Routine (c) Copy Routine
Conditions for entering User Boot mode (defined by the user) RAM
TMP19A71
17-10
TMP19A71
(3) Once User Boot mode is entered, execute the copy routine to copy the flash programming routine to the TMP19A71 on-chip RAM.
Host Controller
New Application Program Code
TMP19A71
Flash Memory Old Application Program Code
I/O
(b) Programming Routine
[Programming Procedure]
(a) Mode Judgment Routine
(b) Programming Routine (c) Copy Routine
RAM
(4) Jump program execution to the flash programming routine in the on-chip RAM to erase the flash block containing the old application program code. All interrupts including RESET and NMI must be disabled until new application program code has been written to the flash memory.
Host Controller I/O
New Application Program Code
TMP19A71
Flash Memory (Erased)
(b)  (b) Programming Routine
[Programming Procedure]
(a) Mode Judgment Routine
(b) Programming Routine (c) Copy Routine
RAM
TMP19A71
17-11
TMP19A71
(5) Continue executing the flash programming routine to download new application program code from the host controller and program it into the erased flash block. Once programming is complete, turn on the protection of that flash block.
Host Controller
New Application Program Code
TMP19A71
Flash Memory New Application Program Code [Programming Procedure]
(a) Mode Judgment Routine
I/O
(b)  (b) Programming Routine
(b) Programming Routine (c) Copy Routine
RAM
(6) Drive the RESET pin low to reset the TMP19A71 and enter Normal mode or jump to an arbitrary address to execute the new user application program.
Host Controller
TMP19A71
Flash Memory New Application Program Code [Programming Procedure]
(a) Mode Judgment Routine
I/O 0  1 RESET
Set to Normal mode
(b) Programming Routine (c) Copy Routine
RAM
TMP19A71
17-12
TMP19A71
(1-B) Method 2: Transferring a programming routine from an external host (1) Determine the conditions (e.g., pin states) required for the flash memory to enter User Boot mode and the I/O bus to be used to transfer new program code. Create hardware and software accordingly. Before installing the TMP19A71 on a printed circuit board, write the following program routines into a flash block using programming equipment. (a) Mode judgment routine: (b) Transfer routine: Code to determine whether or not to switch to User Boot mode Code to download new program code from a host controller
Routines (a) and (b) are collectively called the programming procedure. Also, prepare the following routine on the host controller. (c) Programming routine: Code to re-program the flash memory
Host Controller I/O
New Application Program Code
(c) Programming Routine
TMP19A71
Flash Memory Old Application Program Code [Programming Procedure]
(a) Mode Judgment Routine
RAM
(b) Transfer Routine
(2) The mode judgment routine written in one of the blocks in the flash memory determines whether to put the TMP19A71 flash memory in User Boot mode. If the specified conditions are met, the flash memory enters User Boot mode.
Host Controller I/O
New Application Program Code
(c) Programming Routine
TMP19A71
Flash Memory Old Application Program Code [Programming Procedure]
(a) Mode Judgment Routine
0  1 RESET
RAM
Conditions for entering User Boot mode (defined by the user)
(b) Transfer Routine
TMP19A71
17-13
TMP19A71
(3) Once User Boot mode is entered, execute the transfer routine to download the flash programming routine from the host controller to the TMP19A71 on-chip RAM.
Host Controller I/O
New Application Program Code
(c) Programming Routine
TMP19A71
Flash Memory Old Application Program Code
(c) Programming Routine
[Programming Procedure]
(a) Mode Judgment Routine
RAM
(b) Transfer Routine
(4) Jump program execution to the flash programming routine in the on-chip RAM to erase a flash block containing the old application program code. All interrupts including RESET and NMI must be disabled until new application program code has been written to the flash memory.
Host Controller I/O
New Application Program Code
(c) Programming Routine
TMP19A71
Flash Memory (Erased) (c) Programming Routine [Programming Procedure]
(a) Mode Judgment Routine
RAM
(b) Transfer Routine
TMP19A71
17-14
TMP19A71
(5)
Continue executing the flash programming routine to download new application program code and program it into the erased flash block. Once programming is complete, turn on the protection on that flash block.
Host Controller I/O
New Application Program Code
(c) Programming Routine
TMP19A71
Flash Memory New Application Program Code
(c) Programming Routine
[Programming Procedure]
(a) Mode Judgment Routine
RAM
(b) Transfer Routine
(6) Drive the RESET pin low to reset the TMP19A71 and enter Normal mode or jump to an arbitrary address to execute the new user application program.
Host Controller I/O
TMP19A71
Flash Memory New Application Program Code
0  1 RESET
Set to Normal mode [Programming Procedure]
(a) Mode Judgment Routine
RAM
(b) Transfer Routine
TMP19A71
17-15
TMP19A71 17.3.2 Single Boot Mode
In Single Boot mode, the flash memory can be re-programmed by using a program contained in the TMP19A71 on-chip boot ROM. This boot ROM is a masked ROM. When Single Boot mode is selected upon reset, the boot ROM is mapped to the address region including the interrupt vector table while the flash memory is mapped to an address region different from it (see Figure 17.2.2). Single Boot mode allows for serial programming of the flash memory. The SIO (SIO2) of the TMP19A71 is connected to an external host controller. Via this serial link, a programming routine is downloaded from the host controller to the TMP19A71 on-chip RAM. Then, the flash memory is re-programmed by executing the programming routine. The host sends out both commands and programming data to re-program the flash memory. Communications between the SIO2 and the host must follow the prescribed protocol described later. To secure the contents of the flash memory, password verification is performed before a programming routine is downloaded into the on-chip RAM. If password verification fails, the transfer of a programming routine itself is aborted. All interrupts including nonmaskable interrupts must be disabled while the boot program is executed. Once re-programming is complete, it is recommended to protect flash memory blocks as required from accidental corruption during subsequent operation in Single-Chip (Normal) mode. For a detailed description of erase and program operations, see section 17.4 On-Board Programming and Erasure.
TMP19A71
17-16
TMP19A71
Single Boot Mode (2-A) General procedure: Using a programming algorithm in the on-chip boot ROM (1) The flash block containing the older version of the program code need not be erased before executing the programming routine. Since a programming routine and programming data are transferred via the UART2 or SIO2, the UART 2 or SIO2 pins must be connected to a host controller. Prepare a programming routine on the host controller. (The SIO2 is used here.)
Host Controller I/O
New Application Program Code
(a) Programming Routine
TMP19A71
Boot ROM Flash Memory SIO2
Old Application Program Code (or Erased State)
RAM
(2)
Reset the TMP19A71 with the mode setting pins held at appropriate logic values for re-booting from the on-chip boot ROM. In Single Boot mode, the 12-byte password transferred from the host controller is first compared to the password stored in the user application program in the flash memory. (If the flash memory has already been erased, password verification is performed using the erased data.)
Host Controller I/O New Application Program Code
(a) Programming Routine
TMP19A71
Boot ROM Flash Memory SIO2
0  1 RESET
Old Application Program Code (or Erased State)
RAM
TMP19A71
17-17
TMP19A71
(3)
If password verification is successful, the boot program loads the programming routine from the host controller into the on-chip RAM. The programming routine must be stored in the address range of 0xFFFF_9800 to 0xFFFF_AFFF.
Host Controller I/O
New Application Program Code
(a) Programming Routine
TMP19A71
Boot ROM Flash Memory SIO2
Old Application Program Code (or Erased State)
(a) Programming Routine
RAM
(4) The TX19A core processor jumps to the programming routine in the on-chip RAM to erase the flash block containing the old application program code. (The Block Erase or Chip Erase command may be used.)
Host Controller I/O
New Application Program Code
(a) Programming Routine
TMP19A71
Boot ROM Flash Memory SIO2
(a) Programming Routine
Erased RAM
TMP19A71
17-18
TMP19A71
(5) Next, the programming routine loads new application program code from the host controller into the erased flash block. Once programming is complete, the flash block is placed under protection. In the example below, new program code comes from the same host controller via the same SIO channel as for the programming routine. However, once the programming routine has begun to execute, the transfer path and the source of the transfer can be changed as desired. Create board hardware and a programming routine to suit your particular needs.
Note: The boot ROM provides no vector area for all maskable interrupts and NMI. While the programming routine is executed, no exception should be allowed to occur.
Host Controller I/O
New Application Program Code
(a) Programming Routine
TMP19A71
Boot ROM Flash Memory SIO2
New Application Program Code
(a) Programming Routine
RAM
(6)
When the flash memory has been programmed, power off the board and disconnect the cable connecting the host controller. Then, turn on the power again and re-boot the TMP19A71 in Single-Chip mode (Normal mode) to execute the new application program.
Host Controller
TMP19A71
Boot ROM Flash Memory SIO2
0  1 RESET
New Application Program Code RAM
Set to Single-Chip mode (Normal mode)
TMP19A71
17-19
TMP19A71
(1) Connection examples in Single Boot mode In Single Boot mode, serial transfer is used to re-program the flash memory while the TMP19A71 is installed on a printed circuit board. In this mode, the SIO (channel 2) of the TMP19A71 is connected to a host controller (programming tool). The host controller issues commands to the target board to perform programming operations. Figure 17.3.1 and Figure 17.3.2 show examples of host-to-target connection.
Host Controller AC 100V VCC Target Board
Reg.
VCC Mode Control
VCC
Reg. TMP19A71
MCU
DVCC2
NMI RESET Boot Mode Selection Logic
RESET
Mode Control
TMODE
BOOT
ROM
RAM
RX
RX2 (P85)
RS232C
TX
TX2 (P86)
VSS
DVSS
PC
Figure 17.3.1
Example of Connection between a Host Controller and a Target Board in Single Boot Mode (when the SIO2 is configured for UART mode)
TMP19A71
17-20
TMP19A71
Host Controller AC 100V VCC
Target Board
Reg.
VCC Mode Control
VCC
Reg. TMP19A71
DVCC2
MCU
NMI
RESET
RESET Boot Mode Selection Logic
Mode Control
TMODE
BOOT
ROM
RAM TCK
RX
SCLK2 (P87)
RX2 (P85)
RS232C
TX
TX2 (P86)
TBUSY
VSS
P80
DVSS
PC
Figure 17.3.2
Example of Connection between a Host Controller and a Target Board in Single Boot Mode (when the SIO2 is configured for I/O Interface mode)
TMP19A71
17-21
TMP19A71
(2) Configuring for Single Boot mode To perform on-board programming, boot up the TMP19A71 in Single Boot mode, as shown below. TEST0 BOOT RESET =0 =0 =01
While the RESET pin is held at logic 0, set the TEST0 and BOOT (P94) pins at the logic values shown above. Then, driving the RESET pin high boots up the TMP19A71 in Single Boot mode. (3) Memory map Figure 17.3.3 shows a comparison of the memory maps in Single-Chip (Normal) mode and Single Boot mode. In Single Boot mode, the on-chip flash memory is mapped to physical addresses 0x4000_0000 through 0x400F_FFFF and virtual addresses 0x0000_0000 through 0x000F_FFFF. The on-chip boot ROM (mask ROM) is mapped to physical addresses 0x1FC0_0000 through 0x1FC0_1FFF.
Normal Mode
On-Chip Peripherals
On-Chip RAM (10KB)
Single Boot Mode
0xFFFF_FFFF On-Chip Peripherals
On-Chip RAM (10KB)
0xFFFF_FFFF
0xFFFF_BFFF 0xFFFF_9800 0xFF3F_FFFF 0xFF20_0000 0xFF00_0000 0xC000_0000 0xBF00_0000 0x400F_FFFF 0x4000_0000
0xFFFF_BFFF 0xFFFF_9800 0xFF3F_FFFF 0xFF20_0000 0xFF00_0000 0xC000_0000 0xBF00_0000 0x4003_FFFF 0x4000_0000
(Reserved) Used for debugging (Reserved) (Reserved) (Reserved) On-Chip ROM Shadow Inaccessible (512 MB)
(Reserved) Used for debugging (Reserved) (Reserved) (Reserved) On-Chip Flash ROM Inaccesible
0x2000_0000 0x1FC3_FFFF 0x1FC0_0400
(512 MB)
0x2000_0000
User Program Area Internal ROM Maskable Interrupt Area Exception Vector Area
Boot MROM (6 KB) 0x1FC0_0000 0x0000_0000
0x1FC0_1FFF 0x1FC0_0000 0x0000_0000
Note: The addresses shown above are physical addresses.
Figure 17.3.3 Memory Maps for Normal and Single Boot Modes
TMP19A71
17-22
TMP19A71
(4) Interface Specifications In Single Boot mode, an SIO channel is used for communications with a programming controller. Both UART (asynchronous) and I/O Interface (synchronous) modes are supported. To perform on-board programming, the interface specifications shown below must also be set on the controller side. * UART mode Communications channel Transfer mode Data length Parity bit STOP bit Baud rate Others * I/O Interface mode Communications channel Transfer mode Synchronization signal (SCLK2) Handshaking signal Baud rate Others : UART2 : UART (asynchronous) mode, full-duplex : 8 bits : None : 1 bit : Up to 437.5 kbps (at 56 Hz) Up to 312.5 kbps (at 40 Hz) : LSB first, SC2MOD2.WBUF=0
: SIO2 : I/O Interface mode, half-duplex SCLK input mode (SC2CR = 0x01) : P80 configured as an output : Up to 3 Mbps (at 56 Hz) Up to 2.5 Mbps (at 40 MHz) : LSB first, SC2MOD2.WBUF = 0
Table 17.3.1 Required Pin Connections
Pin UART Mode Power Supply Pins Mode Setting Pin
Reset Pin Communications Pins
Interface I/O Interface Mode Required Required Required
Required Required Required Required (Input Mode) Required (Output Mode)
DVCC3 DVSS
BOOT
RESET
Required Required Required
Required Required Required Not Required Not Required
TX2 RX2 SCLK2 P80
(5) Data Transfer Format Table 17.3.2 lists the commands to be issued from the host controller to the target board in Single Boot mode. Tables 17.3.3 to 17.3.5 illustrate the sequence of two-way communications that should occur in response to each command.
Table 17.3.2
Code 0x10 0x20 0x30
Single Boot Mode Commands
Command RAM Transfer Show Flash Memory Sum Show Product Information
TMP19A71
17-23
TMP19A71
Table 17.3.3 Transfer Format for the RAM Transfer Command
Byte Boot ROM 1st byte Data Transferred from the Controller to the TMP19A71 Serial operation mode and baud rate For UART mode 0x86 For I/O Interface mode (Note 2) 0x30  Baud Rate Specified baud rate (Note 1) Data Transferred from the TMP19A71 to the Controller
2nd byte
3rd byte 4th byte
Command code
(0x10)
5th byte to 16th byte 17th byte 18th byte
Password sequence (12 bytes) (0x0000_0474 to 0x0000_047F) Checksum value for 5th to 16th bytes (Note 4) 
ACK for the serial operation mode byte For UART mode Normal acknowledge 0x86 (The boot program aborts if the baud rate cannot be set correctly.) For I/O Interface mode Normal acknowledge 0x30  ACK for the command code byte (Note 3) Normal acknowledge 0x30 Negative acknowledge 0x11 Communication error 0x18 
19th byte 20th byte 21st byte 22nd byte 23rd byte 24th byte 25th byte 26th byte
RAM storage start address 31 to 24 (Note 5) RAM storage start address 23 to 16 (Note 5) RAM storage start address 15 to 8 (Note 5) RAM storage start address 7 to 0 (Note 5) RAM storage byte count 15 to 8 (Note 5) RAM storage byte count 7 to 0 (Note 5) Checksum value for 19th to 24th bytes (Note 4) 
27th byte RAM storage data to mth byte (m + 1)th byte Checksum value for 27th to mth bytes (Note 4) (m + 2)th byte 
 ACK for the checksum byte (Note 3) Normal acknowledge 0x10 Negative acknowledge 0x11 Communication error 0x18        ACK for the checksum byte (Note 3) Normal acknowledge 0x10 Negative acknowledge 0x11 Communication error 0x18 
RAM
(m + 3)th byte
 ACK for the checksum byte (Note 3) Normal acknowledge 0x10 Negative acknowledge 0x11 Communication error 0x18 Jump to RAM storage start address
Note 1: Note 2:
In I/O Interface mode, the baud rate for transferring the 1st and 2nd bytes must be 1/16 of the specified baud rate. In I/O interface mode, a waveform that allows the serial operation mode to be determined should be generated.
Note 3: In case of any negative acknowledgment, the boot program returns to a state in which it waits for a command code (3rd byte). In I/O Interface mode, no acknowledgment is returned for a communicaion error. Note 4: The checksum value is obtained by adding all the bytes of transmitted data together, dropping the carries, and taking the two's complement of the total sum. Note 5: The 19th to 24th bytes must be within the RAM address range 0xFFFF_9800 to 0xFFFF_AFFF.
TMP19A71
17-24
TMP19A71
Table 17.3.4 Transfer Format for the Show Flash Memory SUM Command
Byte Boot ROM 1st byte Data Transferred from the Controller to the TMP19A71 Serial operation mode and baud rate For UART mode 0x86 For I/O Interface mode (Note 2) 0x30  Baud Rate Specified baud rate (Note 1) Data Transferred from the TMP19A71 to the Controller
2nd byte
3rd byte 4th byte
Command code
(0x20)
5th byte 6th byte 7th byte 8th byte
   (Wait for the next command code.)
ACK for the serial operation mode byte For UART mode Normal acknowledge 0x86 (The boot program aborts if the baud rate cannot be set correctly.) For I/O Interface mode Normal acknowledge 0x30  ACK for the command code byte (Note 3) Normal acknowledge 0x20 Negative acknowledge 0x21 Communication error 0x28 SUM (upper byte) SUM (lower byte) Checksum value for 5th and 6th bytes (Note 4) 
Note 1: Note 2: Note 3:
In I/O Interface mode, the baud rate for transferring the 1st and 2nd bytes must be 1/16 of the specified baud rate. In I/O Interface mode, a waveform that allows the serial operation mode to be determined should be generated. In case of any negative acknowledgment, the boot program returns to a state in which it waits for a command code (3rd byte). In I/O Interface mode, no acknowledgment is returned for a communication error.
Note 4: The checksum value is obtained by adding all the bytes of transmitted data together, dropping the carries, and taking the two's complement of the total sum. Note 5: The SUM value is the lower 16 bits of a value obtained by adding all the bytes in the flash memory together. SUM (high) = SUM[ 15 : 8 ], SUM (low) = SUM[ 7 : 0 ]
TMP19A71
17-25
TMP19A71
Table Byte Boot ROM 1st byte
17.3.5
Transfer Format for the Show Product Information Command (1/2)
Baud Rate Specified baud rate (Note 1) Data Transferred from the TMP19A71 to the Controller
Data Transferred from the Controller to the TMP19A71 Serial operation mode and baud rate For UART mode 0x86 For I/O Interface mode (Note 2) 0x30 
2nd byte
3rd byte 4th byte
Command code
(0x30)
5th byte 6th byte 7th byte 8th byte 9th byte to 20th byte 21st byte to 24th byte 25th byte to 28th byte 29th byte to 32nd byte 33rd byte to 36th byte 37th byte to 40th byte 41st byte to 44th byte 45th byte to 46th byte 47th byte to 50th byte 51st byte to 54th byte 55th byte to 56th byte 57th byte to 60th byte
    
ACK for the serial operation mode byte For UART mode Normal acknowledge 0x86 (The boot program aborts if the baud rate cannot be set correctly.) For I/O Interface mode Normal acknowledge 0x30  ACK for the command code byte (Note 3) Normal acknowledge 0x30 Negative acknowledge 0x31 Communication error 0x38 Flash memory data (at address 0x0000_0470) Flash memory data (at address 0x0000_0471) Flash memory data (at address 0x0000_0472) Flash memory data (at address 0x0000_0473) Product name (12-byte ASCII code) `TX19A71FY' + 0x20, 0x20, 0x20 from the 9th byte Password comparison start address (4 bytes) 0x74, 0x04, 0x00, 0x00 from the 21st byte RAM start address (4 bytes) 0x00,0x98, 0xFF, 0xFF from the 25th byte Dummy data (4 bytes) 0xFF, 0xA7, 0xFF, 0xFF from the 29th byte RAM end address (4 bytes) 0xFF, 0xBF, 0xFF, 0xFF from the 33rd byte Dummy data (4 bytes) 0x00, 0xA8, 0xFF, 0xFF from the 37th byte Dummy data (4 bytes) 0xFF, 0xAF, 0xFF, 0xFF from the 41st byte Fuse information (2 bytes) 0x00, 0x00 from the 45th byte Flash memory start address (4 bytes) 0x00, 0x00, 0x00, 0x00 from the 47th byte Flash memory end address (4 bytes) 0xFF, 0xFF, 0x03, 0x00 from the 51st byte Flash memory block count (2 bytes) 0x02, 0x00 from the 55th byte Start address of a group of the same-size flash blocks (4 bytes) 0x00, 0x00, 0x00, 0x00 from the 57th byte


TMP19A71
17-26
TMP19A71
Table 17.3.5 Transfer Format for the Show Device Information Command (2/2)
Byte Root ROM 61st byte to 64th byte 65th byte 66th byte 67th byte Data Transferred from the Controller to the TMP19A71
Baud Rate
Data Transferred from the TMP19A71 to the Controller Size (in half words) of the same-size flash blocks (4 bytes) 0x00, 0x00, 0x01, 0x00 from the 61st byte Number of flash blocks of the same size (1 byte) 0x02 Checksum value for the 5th to 65th bytes (Note 4) 
  (Wait for the next command code.)
Note 1: Note 2: Note 3:
In I/O Interface mode, the baud rate for transferring the 1st and 2nd bytes must be 1/16 of the specified baud rate. In I/O Interface mode, a waveform that allows the serial operation mode to be determined should be generated. In case of any negative acknowledgment, the boot program returns to a state in which it waits for a command code (3rd byte). In I/O Interface mode, no acknowledgment is returned for a communication error.
Note 4:
The checksum value is obtained by adding all the bytes of transmitted data together, dropping the carries, and taking the two's complement of the total sum.
TMP19A71
17-27
TMP19A71
(6) Overview of the boot program commands When Single Boot mode is selected, the boot program is automatically executed on startup. The boot program offers the following three commands (each command is explained in detail in the subsections that follow): 1. RAM Transfer command The RAM Transfer command stores program code transferred from a host controller to the on-chip RAM and executes the program once the transfer is successfully completed. The maximum program size is 6 Kbytes (0xFFFF_9800 to 0xFFFF_AFFF). The RAM Transfer command enables the user to control on-board programming of the flash memory in a unique manner by providing the means for downloading a user-created programming routine. The programming routine must use the flash memory command sequences described in section 17.4 On-Board Programming and Erasure. Before initiating a transfer, the RAM Transfer command checks a password sequence coming from the controller against the password stored in the flash memory. If they do not match, the RAM Transfer command aborts. 2. Show Flash Memory Sum command The Show Flash Memory Sum command adds the contents of the flash memory and returns the lower 16 bits of the result. The boot program does not provide a command to read out the contents of the flash memory. Instead, the Show Flash Memory Sum command can be used for software revision management. 3. Show Product Information command The Show Product Information command provides product information, such as the product name and on-chip memory configuration, stored at addresses 0x0000_0470 to 0x0000_0473 in the flash memory. In addition to the Show Flash Memory Sum command, this command can be used for software revision management.
TMP19A71
17-28
TMP19A71
1) RAM Transfer command (see Table 17.3.3) 1. The 1st byte specifies which one of the two serial operation modes is used. For a detailed description of how the serial operation mode is determined, see subsection 5) Determination of a serial operation mode. If it is determined as UART mode, the boot program then checks if the SIO2 is programmable to the baud rate at which the 1st byte was transferred. The 1st byte is transferred with receive operation disabled (SC2MOD.RXE = 0). * To communicate in UART mode The controller sends 86H to the target board in UART data format at the desired baud rate. If the serial operation mode is determined as UART, then the boot program checks if the SIO2 can be programmed to the baud rate at which the 1st byte was received. The time (number of instruction execution cycles) required for this operation varies with the operating frequency and baud rate used. If the desired baud rate cannot be used, the boot program aborts, disabling any subsequent communication. In this case, a reset is required. If necessary, the controller should set a time limit for transferring the 2nd byte as appropriate to the baud rate used. * To communicate in I/O Interface mode The controller sends the 1st byte to the target board to generate a waveform that allows the serial operation mode to be determined as I/O Interface mode. (For details, see subsection 5) Determination of a serial operation mode.) When the boot program determines that communications can be performed in I/O Interface mode at the desired baud rate, the handshake pin is driven high. If the high level is not detected on the handshake pin within the expected time period, this indicates that the boot program has aborted after determining that the SIO2 is not programmable to the desired baud rate. In this case, a reset is required. The command sequence must be started again from the 1st byte at another baud rate. In I/O Interface mode, the TX19A core processor sees the serial receive pin as if it were a general-purpose input port and monitors its logic transitions. If the baud rate of incoming data is high or the chip's operating frequency is high, the TX19A core processor may not be able to keep up with the speed of logic transitions. To prevent such situations, the 1st and 2nd bytes must be transferred at 1/16 of the desired baud rate; then the boot program calculates 16 times that as the desired baud rate. At this time, the transmission of one byte should be completed before an overflow occurs in the TMRB0 (see Figure 17.3.6). When the serial operation mode is determined as I/O Interface mode, the SIO2 is configured for SCLK Input mode. Beginning with the 3rd byte, the controller must ensure that the AC timing restrictions are satisfied at the selected baud rate. In I/O Interface mode, the boot program does not check the receive error flag; thus there is no such thing as error acknowledge (bit 3) (18H). 2. The 2nd byte, transmitted from the target board to the controller, is an acknowledge response to the 1st byte. The boot program echoes back the first byte: 86H for UART mode and 30H for I/O Interface mode. * UART mode If the SIO2 can be programmed to the baud rate at which the 1st byte was
TMP19A71
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TMP19A71
transferred, the boot program programs the BR2CR and BR2ADD registers and sends back 86H to the controller as an acknowledge. If the SIO2 is not programmable at that baud rate, the boot program simply aborts with no error indication. Following the 1st byte, the controller should allow for a time-out period. If it does not receive 86H within the allotted time-out period, the controller should give up the communication. The boot program sets the RXE bit in the SC2MOD to 1 to enable reception before loading the transmit buffer with 86H. * I/O Interface mode The boot program programs the SC2MOD and SC2CR registers to configure the SIO2 in I/O Interface mode and writes 30H to the SC2BUF. Then, the SIO2 waits for the SCLK2 signal to come from the controller. Following the transmission of the 1st byte, the controller must wait for the rising edge of the handshaking pin before sending the SCLK clock. This must be done at 1/16 of the desired baud rate. If the controller receives 30H as the 2nd byte, this should be taken as the go-ahead. The controller must then deliver the 3rd byte to the target board at a rate equal to the desired baud rate. The boot program sets the SC2MOD.RXE bit to 1 before 30H is written to the transmit buffer. In I/O Interface mode, receive errors are not checked. 3. The 3rd byte, which the target board receives from the controller, is a command. The code for the RAM Transfer command is 10H. The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. Before sending back the acknowledge response, the boot program checks for a receive error. If there was a receive error, the boot program transmits x8H and returns to the state in which it waits for a command again. In this case, the upper four bits of the acknowledge response are undefined--they hold the same values as the upper four bits of the preceding command. If the 3rd byte is equal to any of the command codes listed in Table 17.3.2, the boot program echoes it back to the controller. When the RAM Transfer command was received, the boot program echoes back a value of 10H and then branches to the RAM Transfer routine. Once this branch is taken, a password check is done. Password checking is detailed later in this subsection. If the 3rd byte is not a valid command, the boot program sends back 11H to the controller to indicate a command error and returns to the state in which it waits for a command. In this case, the upper four bits of the response are undefined--they hold the same values as the upper four bits of the preceding command. 5. The 5th to 16th bytes, which the target board receives from the controller, are a 12-byte password. The 5th byte is compared to the contents of address 0x0000_0474 in the flash memory; the 6th byte is compared to the contents of address 0x0000_0475 in the flash memory; likewise, the 16th byte is compared to the contents of address 0x0000_047F in the flash memory. The 17th byte is a checksum value for the password sequence (5th to 16th bytes). To calculate the checksum value for the 12-byte password, add the 12 bytes together, drop the carries and take the two's complement of the total sum. Transmit this
4.
6.
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checksum value from the controller to the target board. The checksum calculation is described in detail later in this section. 7. The 18th byte, transmitted from the target board to the controller, is an acknowledge response to the 5th to 17th bytes. First, the RAM Transfer routine checks for a receive error in the 5th to 17th bytes. If there was a receive error, the boot program sends back 18H and returns to the state in which it waits for a command (i.e., 3rd byte) again. In this case, the upper four bits of the acknowledge response are the same as those of the preceding command (i.e., all 1s). Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the 5th to 17th bytes together must result in zero (with the carries dropped). If it is not zero, the RAM Transfer routine sends back 11H to the controller to indicate a checksum error and returns to the state in which it waits for a command (i.e., the 3rd byte) again. Finally, the RAM Transfer routine examines the result of the password check. If a password error is determined, the RAM Transfer routine sends back 11H to the controller and returns to the state in which it waits for a command (i.e., the 3rd byte) again. For data sequences that can be used as a password, see subsection 6) Password. When all the above checks have been successful, the RAM transfer routine returns a normal acknowledge response (10H) to the controller. 8. The 19th to 22nd bytes, which the target board receives from the controller, indicate the start address of the RAM region where subsequent data should be stored. The 19th byte corresponds to bits 31 to 24 of the address, and the 22nd byte corresponds to bits 7 to 0 of the address. The 23rd and 24th bytes, which the target board receives from the controller, indicate the number of bytes that will be transferred from the controller to be stored in the RAM. The 23rd byte corresponds to bits 15 to 8 of the transfer byte count, and the 24th byte corresponds to bits 7 to 0 of the transfer byte count.
9.
10. The 25th byte is a checksum value for the 19th to 24th bytes. To calculate the checksum value, add all these bytes together, drop the carries and take the two's complement of the total sum. Transmit this checksum value from the controller to the target board. The checksum calculation is described later in this section. 11. The 26th byte, transmitted from the target board from the controller, is an acknowledge response to the 19th to 25th bytes. First, the RAM Transfer routine checks for a receive error in the 19th to 25th bytes. If there was a receive error, the RAM Transfer routine sends back 18H and returns to the state in which it waits for a command (i.e., the 3rd byte). In this case, the upper four bits of the acknowledge response are the same as those of the preceding command (i.e., all 1s). Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the 19th to 25th bytes together must result in zero (with the
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carries dropped). If it is not zero, the RAM transfer routine sends back 11H to the controller to indicate a checksum error and returns to the state in which it waits for a command (i.e., the 3rd byte). * The RAM storage addresses must be within the range of 0xFFFF_9800 to 0xFFFF_AFFF. Although the boot program does not perform address checks, RAM transfer may not be performed properly if other RAM address locations are specified as they are used in the program. When the above checks have been successful, the RAM Transfer routine returns a normal acknowledge response (10H) to the controller. 12. The 27th to m'th bytes from the controller are stored in the on-chip RAM of the TMP19A71. Storage begins at the address specified by the 19th to 22nd bytes and continues for the number of bytes specified by the 23rd and 24th bytes. 13. The (m + 1)th byte is a checksum value. To calculate the checksum value, add the 27th to m'th bytes together, drop the carries and take the two's complement of the total sum. Transmit this checksum value from the controller to the target board. The checksum calculation is described in detail later in this section. 14. The (m + 2)th byte is an acknowledge response to the 27th to (m+1)th bytes. First, the RAM Transfer routine checks for a receive error in the 27th to (m+1)th bytes. If there was a receive error, the RAM Transfer routine sends back 18H and returns to the state in which it waits for a command (i.e., the 3rd byte) again. In this case, the upper four bits of the acknowledge response are the same as those of the preceding command (i.e., all 1s). Next, the RAM Transfer routine performs the checksum operation to ensure data integrity. Adding the 27th to (m+1)th bytes together must result in zero (with carries dropped). If it is not zero, the RAM Transfer routine sends back 11H to the controller to indicate a checksum error and returns to the state in which it waits for a command (i.e., the 3rd byte) again. If all the above checks are successful, the RAM Transfer routine returns a normal acknowledge response (10H) to the controller.
15. If the (m + 2)th byte was a normal acknowledge response, a branch is made to the address specified by the 19th to 22nd bytes in 32-bit ISA mode.
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2) Show Flash Memory Sum command (see Table 17.3.4) 1. The processing of the 1st and 2nd bytes are the same as for the RAM Transfer command. The 3rd byte, which the target board receives from the controller, is a command. The code for the Show Flash Memory Sum command is 20H. The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. The processing of the 4th byte is the same as for the RAM Transfer command except that the command code is 20H. The Show Flash Memory Sum routine adds all the bytes of the flash memory together. The 5th to 6th bytes, transmitted from the target board to the controller, indicate the upper and lower bytes of this total sum, respectively. The sum calculation is described in detail later in this section. The 7th byte is a checksum value for the 5th and 6th bytes. To calculate the checksum value, add the 5th and 6th bytes together, drop the carry and take the two's complement of the sum. Transmit this checksum value from the controller to the target board. The 8th byte is the next command code.
2.
3.
4.
5.
6.
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3) Show Product Information Command (see Table 17.3.5) 1. The processing of the 1st and 2nd bytes are the same as for the RAM Transfer command. The 3rd byte, which the target board receives from the controller, is a command. The code for the Show Product Information command is 30H. The 4th byte, transmitted from the target board to the controller, is an acknowledge response to the 3rd byte. The processing of the 4th byte is the same as for the RAM Transfer command except that the command data is 30H. The 5th to 8th bytes, transmitted from the target board to the controller, are the data read from addresses 0x0000_0470 to 0x0000_0473 in the flash memory. Software revision management is possible by storing software information such as an ID in these locations. The 9th to 20th bytes, transmitted from the target board to the controller, indicate the product name, which is `TX19A71FY' in ASCII code followed by 20H, 20H, and 20H (12 bytes). The 21st to 24th bytes, transmitted from the target board to the controller, indicate the start address of the flash memory area containing the password (74H, 04H, 00H , 00H ). The 25th to 28th bytes, transmitted from the target board to the controller, indicate the start address of the on-chip RAM (00H, 98H, FFH, FFH). The 29th to 32nd bytes, transmitted from the target board to the controller, are dummy data (FFH, A7H, FFH, FFH). The 33rd to 36th bytes, transmitted from the target board to the controller, indicate the end address of the on-chip RAM (FFH, FFH, BFH, FFH).
2.
3.
4.
5.
6.
7.
8.
9.
10. The 37th to 40th bytes, transmitted from the target board to the controller, are 00H, A8, FFH and FFH. The 41st to 44th bytes, transmitted from the target board to the controller, are FFH, AFH, FFH and FFH. 11. The 45th and 46th bytes, transmitted from the target board to the controller, indicate whether the security and protect bits are available and whether the flash memory is divided into blocks. Bit 0 indicates the presence or absence of the security bit; it is 0 if the security bit is available. Bit 1 indicates the presence or absence of the protect bits; it is 0 if the protect bits are available. If bit 2 is 0, it indicates that the flash memory is divided into blocks. The remaining bits are undefined. The 45th and 46th bytes are 00H, 00H. 12. The 47th to 50th bytes, transmitted from the target board to the controller, indicate the start address of the on-chip flash memory (00H, 00H, 00H, 00H).
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13. The 51st to 54th bytes, transmitted from the target board to the controller, indicate the end address of the on-chip flash memory (FFH, FFH, 03H, 00H). 14. The 55th and 56th bytes, transmitted from the target board to the controller, indicate the number of flash blocks available (02H, 00H). 15. The 57th to 92nd bytes, transmitted from the target board to the controller, contain information about the flash blocks. Flash blocks of the same size are treated as a group. Information about the flash blocks indicate the start address of a group, the size of the blocks in that group (in half words) and the number of the blocks in that group. The 57th to 65th bytes are the information about 128-Kbyte blocks (Block 0 and Block 1). See Table 17.3.5 for the values of bytes transmitted. 16. The 66th byte, transmitted from the target board to the controller, is a checksum value for the 5th to 65th bytes. The checksum value is calculated by adding all these bytes together, dropping the carries and taking the two's complement of the total sum. 17. The 67th byte is the next command code.
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4) Acknowledge responses
The boot program returns to the controller specific codes to notify processing states. Table 17.3.6 to Table 17.3.8 show the values of possible acknowledge responses to the received data. The upper four bits of the acknowledge response are equal to those of the command being executed. Bit 3 of the code indicates a receive error. Bit 0 indicates an invalid command error, a checksum error or a password error. Bit 1 and bit 2 are always 0. Receive error checking is not performed in I/O Interface mode. Table 17.3.6
Return Value 0x86 0x30
ACK Response to the Serial Operation Mode Bytes
Meaning
The SIO can be configured to operate in UART mode. (Note) The SIO can be configured to operate in I/O Interface mode.
Note: If the serial operation mode is determined as UART, the boot program checks if the SIO can be programmed to the baud rate at which the operation mode byte was transferred. If the baud rate is not possible, the boot program aborts without sendig back any response.
Table 17.3.7
Return Value 0xN8 (Note) 0xN1 (Note) 0x10 0x20 0x30
ACK Response to the Command Byte
Meaning
A receive error occurred while a command code was being received. An undefined command code was received. (Reception was completed normally.) The RAM Transfer command was received. The Show Flash Memory Sum command was received. The Show Product Information command was received.
Note: The four high-order bits of the ACK response are the same as those of the preceding command code.
Table 17.3.8
Return Value 0xN8 (Note) 0xN1 (Note) 0xN0 (Note)
ACK Response to the Checksum Byte
Meaning
A receive error occurred. A checksum or password error occurred. The checksum was correct.
Note: The four high-order bits of the ACK response are the four high-order bits of the preceding command code. They are 1 if a password error occurred.
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5) Determination of a serial operation mode
The first byte from the controller determines the serial operation mode. To use UART mode for communications between the controller and the target board, the controller must first send a value of 86H at a desired baud rate to the target board. To use I/O Interface mode, the controller must send the first byte with a waveform satisfying tAB > tCD (30H is sent here) at 1/16 of the desired baud rate. Figure 17.3.4 shows the waveforms for the first byte.
Start Point A
UART (0x86)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Stop
Point B
Point C
Point D
tAB
tCD
bit 0 Point A I/O Interface
(0x30)
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7 Point D
Point B
Point C
tAB
tCD
Figure 17.3.4
Serial Operation Mode Byte
After the reset state is released, the boot program monitors the first serial byte from the controller with the SIO reception disabled, and calculates the intervals of tAB, tAC and tAD shown in Figure 17.3.4. Figure 17.3.5 shows a flowchart describing the steps to determine the intervals of tAB, tAC and tAD. As shown in the flowchart, the boot program captures timer counts each time a logic transition occurs in the first serial byte. Consequently, the calculated tAB, tAC and tAD intervals are bound to have slight errors. If the transfer goes at a high baud rate, the TX19A core processor might not be able to keep up with the speed of logic transitions at the serial receive pin. In particular, I/O Interface mode is more prone to this problem since its baud rate is generally much higher than that for UART mode. To avoid such a situation, the controller should send the first serial byte at 1/16 of the desired baud rate. The flowchart in Figure 17.3.6 shows how the boot program distinguishes between UART and I/O Interface modes. If the length of tAB is equal to or less than the length of tCD, the serial operation mode is determined as UART mode. If the length of tAB is greater than tCD, the serial operation mode is determined as I/O Interface mode. Bear in mind that if the baud rate is too high or the timer operating frequency is too low, the timer resolution will be coarse, relative to the intervals between logic transitions. This becomes a problem due to inherent errors caused by the way in which timer counts are captured by software; consequently the boot program might not be able to determine the serial operation mode correctly. (Serial operation mode settings must be made again in the programming routine.) For example, the serial operation mode may be determined to be I/O Interface mode when the intended mode is UART mode. To avoid such a situation, when UART mode is utilized, the controller should allow for a time-out period within which it expects to receive an echo-back (86H) from the target board. The controller should give up the communication if it fails to get that echo-back within the allotted time. When I/O Interface mode is utilized, once the first
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serial byte has been transmitted, the controller should send the SCLK clock after a certain idle time to get an acknowledge response. If the received acknowledge response is not 30H, the controller should give up further communications. To select I/O Interface mode, the data in the 1st byte need not be 30H so long as tAB > tCD is satisfied. The 1st byte may be 91H, A1H, or B1H; these values generate a falling edge at point A and point C and a rising edge at point B and point D. When tAB > tCD is satisfied and I/O Interface mode is determined, 30H is transmitted as the 2nd byte (even if the first byte is not 30H). (Here it is assumed that 30H is transmitted as the 1st byte to select I/O Interface mode.)
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Start
Initialize TMRB0 Start prescaler (source clock: IMCLK/4)
Point A
High-to-low transition on serial receive pin? YES TMRB0 starts counting up
Point B
Low-to-high transition on serial receive pin? YES Software-capture and save timer value (tAB)
Point C
High-to-low transition on serial receive pin? YES Software-capture and save timer value (tAC)
Point D
Low-to-high transition on serial receive pin? YES Software-capture and save timer value (tAD) TMRB0 stops counting
tAC  tAD?
YES
Make backup copy of tAD value Stop operation (infinite loop until RESET input)
End
Figure 17.3.5
Serial Operation Mode Byte Reception Flow
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Start
tCD  tAD - tAC
tAB > tCD?
YES
UART mode
I/O Interface mode
Figure 17.3.6
Serial Operation Mode Determination Flow
6)
Password
The RAM Transfer command (10H) causes the boot program to perform a password check. Following an echo-back of the command, the boot program checks the contents of the 12-byte password area (0x0000_0474 to 0x0000_047F) within the flash memory. As shown in Figure 17.3.7, if all these address locations contain the same bytes of data other than FFH, a password area error occurs. In this case, the boot program returns an error acknowledge (11H) in response to the checksum byte (the 17th byte) regardless the result of password check. The only exception is when the password area is all 00H and the data at the first flash memory address (0x0000_0000 in Single Boot mode) is 0x0000_0000. In this case, 12 bytes of 00H in the password area do not cause a password area error. The password sequence received from the controller (5th to 16th bytes) is compared to the password stored in the flash memory. Table 17.3.9 shows how they are compared byte by byte. All of the 12 bytes must match to pass the password check. Otherwise, a password error occurs, which causes the boot program to return an error acknowledge in response to the checksum byte (the 17th byte).
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Start
Are all bytes the same?
YES
Are all bytes equal to FFH?
YES
Are all bytes equal to 00H and 0x0000_0000 = 0?
YES
Password area error
Password area is normal.
Figure 17.3.7
Password Area Check Flow
Table 17.3.9 Relationship between Received Bytes and Flash Memory Locations
Received Byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte 11th byte 12th byte 13th byte 14th byte 15th byte 16th byte Compared Flash Memory Data Address 0x0000_0474 Address 0x0000_0475 Address 0x0000_0476 Address 0x0000_0477 Address 0x0000_0478 Address 0x0000_0479 Address 0x0000_047A Address 0x0000_047B Address 0x0000_047C Address 0x0000_047D Address 0x0000_047E Address 0x0000_047F
Note: We recommend setting data other than 0 at address 0x0000_0000 for security reasons.
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7) Calculation of the Show Flash Memory Sum command
The Show Flash Memory Sum command adds all 256 Kbytes of the flash memory together and provides the total sum as a word quantity. The sum is sent to the controller with the upper 8 bits first, followed by the lower 8 bits. Example:
A1H B2H C3H D4H
In the interests of simplicity, assume the depth of the flash memory is four locations. Then the sum of the four bytes is calculated as: A1H + B2H + C3H + D4H = 02EAH Hence, 02H is first sent to the controller, followed by EAH.
8)
Checksum calculation
The checksum byte for a series of bytes of data is calculated by adding the bytes together, dropping the carries, and taking the two's complement of the total sum. The Show Flash Memory Sum command and the Show Product Information command perform the checksum calculation. The controller must perform the same checksum operation in transmitting checksum bytes. Example: Assume the Show Flash Memory Sum command provides the high- and low-order bytes of the sum as E5H and F6H. To calculate the checksum for a series of E5H and F6H: Add the bytes together. E5H + F6H = 1DBH Drop the carry, and then take the two's complement of the sum. The result is the checksum byte. 0 - DBH = 25H
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(7) General boot program flowchart Figure 17.3.8 shows an overall flowchart of the boot program.
Boot Program Start
Initialize
Get SIO operation mode data
SIO operation mode?
UART
Baud rate setting? Can be set
Set UART mode and baud rate ACK data  Received data (Send 86H) Normal response
Cannot be set
I/O Interface
Set I/O Interface mode ACK data  Received data (30H) (Send 30H) Normal response Prepare to get a command
Stop operation (wait for reset input)
Prepare ACK data
Receive routine Get a command
Receive error? No RAM Transfer? Yes
ACK data  Received data (10H) Transmit routine
(Send 0x10:normal response)
Yes
ACK data  ACK data (08H)
Transmit routine (Send x8H: Receive error)
Show Flash Memory Sum? Yes
ACK data  Received data (20H) Transmit routine
(Send 20H: Normal response)
Show Product Information? Yes
ACK data  Received data (30H) Transmit routine
(Send 30H: Normal response)
Command error
ACK data  ACK data (01H) Transmit routine
(Send x1H: Command error)
RAM Transfer processing
Show Flash Memory Sum processing
Show Product Information processing
Processed normally? Yes Jump to RAM
Figure 17.3.8
Overall Boot Program Flow
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(8) Handshake operation in I/O Interface mode  1) After setting SC2MOD0.RXE=1, the TMP19A71 drives the P80 pin high and waits for the SCLK2 signal for receiving data. 2) After receiving one byte and generating a receive-done interrupt request, the TMP19A71 performs the following sequence of operations: * Drives the P80 pin low to notify the controller that new data transfer cannot be performed. * Processes the received data (RAM storage, checksum verification, sum verification, etc.) and then clears the receive-done interrupt request. * Then, drives the P80 pin high to notify the controller that it is ready to receive new data and waits for the SCLK2 signal for the next receive operation. In Figure 17.3.9, the receive wait time is defined as the period between the rising edge of bit 7 of SCLK2 and the next rising edge of the P80 pin. 3) The next transfer operation should be initiated after a low-to-high transition is confirmed on the P80 pin. (The controller must optimize the transmit wait time for each transfer format.)
Note: The receive wait time to be inserted after each receive operation varies depending on the operating frequency and baud rate used and the processing to be performed on received data (checksum verification, RAM storage, password area check, password data check, etc.) .
Controller (Transmit)  TMP19A71 (Receive)
Controller (Receive) TMP19A71 (Transmit)
SCLK
TXD
RXD
IVR [ 8: 0 ]
0
INTR
0
INTR
0
RXE
HS Receive Wait Time
SCLK = SCLK2, TXD = TX2, RXD = RX2, INTT = INTRX2, RXE = SC2MOD0.RXE, HS = P80
Figure 17.3.9 Handshake Waveform and Receive Wait Time
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 1) After setting SC2MOD0.RXE=0 and setting transmit data in the SC2BUF, the TMP19A71 drives the P80 pin high and waits for the SCLK2 signal for transmitting data. 2) After transmitting one byte and generating a transmit-done interrupt request, the TMP19A71 performs the following sequence of operations: * Drives the P80 pin low to notify the controller that new data transfer cannot be performed. * Performs required processing on the transmitted data (checksum verification, sum verification, etc.) and then clears the transmit-done interrupt request. * Then, sets SC2MOD0.RXE to 1 and drives the P80 pin high to notify the controller that it is ready to receive new data. In Figure 17.3.10, the transmit wait time is defined as the period between the rising edge of bit 7 of SCLK2 and the next rising edge of the P80 pin.  The next transfer operation should be initiated after a low-to-high transition is confirmed on the P80 pin. (The controller must optimize the transmit wait time for each transfer format.)
Note: The transmit wait time to be inserted after each transmit operation varies depending on the operating frequency and baud rate used and the processing to be performed on transfer data (SC2MOD0.RXE setting, checksum verification, RAM storage, password verification, etc.).
SCLK = SCLK2, TXD = TX2, RXD = RX2, INTR = INTTX2, INTT = INTRX2, RXE = SC2MOD0.RXE, HS = P80
Figure 17.3.10
Handshake Waveform and Transmit Wait Time
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(9)Supplementary explanation on determination of a serial operation mode (Transmit waveforms and handshaking in I/O Interface mode) As explained in subsection 5) Determination of a serial operation mode, each operation command must send a waveform satisfying tAB>tCD to select I/O Interface mode. At this time, point A and point C should be programmed to be falling edges and point B and point D to be rising edges. If 30H is transmitted as the 1st byte, the boot program must create at least 1 bit of high level after sending 30H so that a rising edge occurs at point D (see Figure 17.3.11 below). This measure is not needed if the data to be sent as the 1st byte includes a rising edge at point D (e.g. 91H, D9H). In either case, the serial receive pin must be driven high before entering the procedure for determining a serial operation mode. (We recommend setting the serial receive pin to high upon reset.) In I/O Interface mode, the serial receive pin functions as a general-purpose input port for receiving the 1st byte. The timing at which I/O Interface mode is determined is after a rising edge at point D, at which point the port pin used for handshaking goes high even if this occurs before bit 7 is transmitted. (If UART mode is determined, no output is made on the handshake pin.) As shown in Figure 17.3.11 below, the position of point D varies with the data transmitted as the 1st byte. After the 1st byte has been transferred, the controller can initiate the transfer of the 2nd byte after the handshake pin goes high, which indicates that the serial operation mode has been determined.
Transmit data in 1st byte = 30H
Point A Point B
bit 1 bit 2 bit 3 bit 4
Point C
bit 5 bit 6
Point D
bit 7 extra bit
RXD
bit 0
HS
Transmit data in 1st byte = 91H
Point A Point B
bit 2 bit 3 bit 4
Point C
bit 5 bit 6
Point D
bit 7
RXD
bit 0
bit 1
HS
Transmit data in 1st byte = D9H
Point A Point B
bit 2 bit 3
Point C
bit 4 bit 5
Point D
bit 6 bit 7
RXD
bit 0
bit 1
HS
Handshake (HS) pin I/O setting = After reset state
RXD = RX2, HS = P80
Figure 17.3.11
Supplementary Explanation on Determination of a Serial Operation Mode
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(10) Recommended baud rates for the boot program Table 17.3.10 Recommended Baud Rates in Single Boot Mode (UART Mode)
PRSC = BR2CR[5:4], N = BR2CR [3:0], K = BR2ADD[3:0]
Note 1: While the serial operation mode is being determined, the baud rate is determined by measuring the waveform with a timer. Capture value errors generated by the prescaler source clock and division errors that occur in the serial mode determination flow may make it impossible to set the baud rate. The above table shows expected combinations of frequency and baud rate settings, and other combinations may be used. Due to the specifications of the boot program, the fastest baud rate setting allowed is BR2CR=02H. The controller must communicate at a baud rate equal to or slower than this setting.
Note 2: Note 3:
Table 17.3.11 Recommended Baud Rate Values in Single Boot Mode (I/O Interface Mode)
Operating Frequency (MHz) 56 40
Note:
Baud Rate in I/O Interface Mode (bps) 3M 2M 2.5M 1.25M 1.25M 1M 1M 500K 500K 250K 250K 125K
When I/O Interface mode is selected, a wait time is generated after transmitting/receiving every single byte.
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(11) Other considerations for using the boot program * The on-chip boot ROM inserts one wait state in executing each instruction. In Single Boot mode, the pipeline operation for executing each instruction takes twice as long as in the case of Single-Chip mode. * No wait states are inserted while the programming routine transferred to the on-chip RAM is executed on the on-chip RAM. * The boot program updates the values of general-purpose registers upon reset. * The boot program executes all instructions in 32-bit ISA mode. The instruction to be placed at the first address of the programming routine (i.e., RAM storage start address) must be a 32-bit ISA instruction. * All special-purpose registers must be set in the programming routine. * The boot program uses the general-purpose register r29 (shadow = 0) as the stack pointer. The r29 is set to 0xFFFF_BFF0 immediately after the RAM Transfer command is executed. * Locations other than those to which the programming routine can be transferred with the RAM Transfer commend (0xFFFF_9800 to 0xFFFF_AFFF) are used in the boot program after reset. * There are no limitations on RAM locations that can be used by the programming routine stored in the on-chip RAM. * While the boot program is being executed, all maskable interrupts are disabled. * If maskable interrupts are enabled during execution of the programming routine, the maskable interrupt vector of the boot program reads the Interrupt Vector Register (IVR) to obtain the vector address corresponding to the interrupt source, and then transfers control to this vector address. The value of the general-purpose register r4/r29 (SP) is updated by executing the routine shown on the following page. The boot program area does not provide vector addresses for interrupt sources and control for clearing interrupt requests. These should be provided in the programming routine including the setting of the IVR value.
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interrupts: addi sw mfc0 nop nop srl andi bne nop lw lw addi jr nop the_other: addi the_other_lp: nop j nop the_other_lp ; Operation stop loop sp, sp, 4 sp, sp, -4 r4, 0( sp ) r4, r13 ; Maskable interrupt vector start address
r4, r4, r4,
r4, r4, r0,
2 0x1F the_other
;
If not a maskable interrupt, operation stops
r4, r4, sp, r4
IVR 0( r4 ) sp, 4
; ;
Read IVR Read maskable interrupt vector address
;
Jump to vector address
Note:
After an interrupt is generated, one wait state is inserted for executing each instruction until control jumps to the vector address.
* Nonmaskable interrupts must not be used as they will cause an endless loop in the boot program. If an endless loop occurs, a reset must be applied. * Once control jumps to the programming routine, it should not be returned to the boot program area except by the above maskable interrupt vector. * Initial settings should be made before the procedure for determining a serial operation mode. After the reset state is released, an interval of approximately 200 instructions should be inserted before the transfer of the 1st byte. Note that the 1st byte is not transferred via a serial channel. To detect a falling edge on the serial receive pin, the serial receive pin must be set to high well in advance of the completion of the above wait interval. (We recommend setting the serial receive pin to high upon reset.)
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17.4
On-Board Programming and Erasure
The TMP19A71 flash memory is controlled by commands. In User Boot mode and Single Boot mode (the RAM Transfer command), the flash memory can be programmed and erased by the TX19A core processor executing software commands. It is the user's responsibility to create a program/erase routine. Because the flash memory cannot be read while it is being programmed or erased, the program/erase routine must be executed from the on-chip RAM.
17.4.1
Key Features
Program and erase operations on the TMP19A71 flash memory are in principle controlled by commands. This feature enables program and erase commands to be executed by accessing particular addresses in the flash memory. The TX19A core processor issues a command sequence to the flash memory by using the 32-bit SW instruction. Once a command sequence is written, the flash memory does not require the TX19A core processor to provide further controls or timings. The flash memory initiates the embedded program or erase algorithm automatically. The entire flash memory or one or two flash blocks can be erased at a time. Table 17.4.1 Feature Description
Programs and verifies the desired addresses word by word automatically. Erases and verifies the entire memory array automatically. Erases and verifies all memory locations in the selected block automatically. Erases and verifies all memory locations in multiple selected blocks automatically. Provides several status bits such as the Data Polling bit and Toggle bit, which can be used to determine whether a program or erase operation is complete or in progress. Prevents intrusive access to the flash memory while in Programmer mode. Protecting both of the two flash blocks turns on the anti-programmer security feature. Unprotecting both the blocks turns off the anti-programmer security feature. This automatically causes the entire flash memory to be erased. Disables program and erase operations in a flash block. Block-protecting both of the two flash blocks automatically turns on the anti-programmer security feature.
Auto Program Auto Chip Erase Auto Block Erase Auto Multi-Block Erase Write Status Flags Anti-Programmer Security Feature
Block Protect
Bear in mind that, due to the on-chip TX19A core processor interface, the TMP19A71 uses addresses different from those of the standard flash command sequences. Programming is done word by word; thus the word (32 bits) load instruction should be used to write to the flash memory. Unless otherwise noted, the addresses in the flash memory are represented as virtual addresses.
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(1) Block architecture
0x0_0000 to 0x1_FFFF 0x2_0000 to 0x3_FFFF 128 Kbytes 128 Kbytes
Address bits [31:18] vary with the operation mode.
Figure 17.4.1 Flash Memory Block Architecture (2) Interface between the TX19A core processor and the flash memory Figure 17.4.2 illustrates the internal interface between the TX19A core processor and the flash memory in on-board programming modes. The diagram does not show the actual logic network; instead it is only a conceptual depiction of the interface between the TX19A core processor and the flash memory.
Single-Chip mode: 0xBFC0_0000 - 0xBFCF_FFFF Single Boot mode: 0x0000_0000 - 0x000F_FFFF Operation Mode Decoder CE (256 KB) A16 - A2 D31- D0 WR RD CPU RESET Register AD14 - AD0 DQ31 - DQ0 WE OE RESET RDY/BSY Flash Memory
TX19A Core Processor A31 - A16
Figure 17.4.2 Internal Interface between TX19A Core Processor and Flash Memory
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(3) Basic operations The TMP19A71 flash memory has the following two modes of operation: * Read mode in which array data is read * Embedded Operation mode in which the flash array is programmed or erased. The flash memory enters Embedded Operation mode when a valid command sequence is executed in Read mode. In Embedded Operation mode, array data cannot be read. 1) Reading Array Data To read array data, the flash memory must be set to Read mode. The flash memory is automatically set to Read mode upon device power-up, upon reset of the TX19A core processor, and after an embedded operation is successfully completed. If an embedded operation terminated abnormally or the flash memory is required to return to Read mode, software reset or hardware reset is used. Writing Commands The TMP19A71 flash memory is controlled by commands. A write to the command sequencer is effected by issuing a command sequence to the flash memory. The flash memory latches the provided address and data in the command sequencer and executes the required instructions (see Table 17.4.4 and Table 17.4.5). The command sequence being written can be canceled by issuing the Read/Reset command or the Reset command (software reset). The Reset command clears the command sequencer and resets the flash memory to Read mode. Invalid command sequences also cause the flash memory to clear the command sequencer and return to Read mode. 3) Reset
2)
* Read/Reset command, Reset command (software reset) The flash memory does not return to Read mode automatically if an embedded operation terminated abnormally. In this case, the Read/Reset or Reset command must be issued to put the flash memory back in Read mode. The Read/Reset or Reset command may also be written between sequence cycles of the command being written to clear the contents of the command sequencer. * Hardware reset As shown in Figure 17.4.2, the flash memory has a reset pin, which is connected to the RESET signal of the TX19A core processor. When the system drives the RESET pin low or when certain events such as a watchdog timer time-out causes a reset of the TX19A core processor, the flash memory immediately terminates any operation in progress and is reset to Read mode. The Read/Reset and Reset commands are also tied to the RESET pin to reset the flash memory to Read mode. The embedded operation that was interrupted should be re-initiated once the flash memory is ready to accept another command sequence because data may be corrupted. For a description of the hardware reset operation, see section 3.1 Reset Operation. When a valid reset is achieved, the TX19A core processor reads the Reset exception vector from the flash memory and services the Reset exception.
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4)
Auto Program command A bit must be programmed to change its state from 1 to 0. A bit cannot be programmed from 0 back to 1. Only an erase operation can change 0 back to 1. In User Boot mode and the RAM Transfer command of Single Boot mode, the Auto Program command programs the desired addresses in units of 32 bits (words). The Auto Program command requires four bus cycles; the program address and data are written in the fourth cycle, upon completion of which the program operation will commence. As programming is performed on a word-by-word basis, the program address must satisfy A1=A0=0. It is not possible to program a 32-bit word if some bits have already been written. (This also applies when 1 is written in some bits. These bits must be erased before new data can be programmed.) The Auto Program command executes a sequence of internally timed events to program the desired bits of the addressed memory word and verify that the desired bits are sufficiently programmed. The system can determine the status of the programming operation by using write status flags (see Table 17.4.3). Any commands written during the programming operation are ignored. A hardware reset immediately terminates the programming operation. The programming operation that was interrupted should be reinitiated once the flash memory is ready to accept another command sequence because data may be corrupted. The block protection feature disables programming operation in any block. If an attempt is made to program a protected block, the Auto Program command does nothing; the flash memory returns to Read mode in approximately 3 s after the completion of the fourth bus cycle of the command sequence. When the embedded Auto Program algorithm is complete, the flash memory returns to Read mode. If any failure occurs during the programming operation, the flash memory remains locked in Embedded Operation mode. The system can determine this status by using write status flags. To put the flash memory back in Read mode, use a software reset to reset the flash memory or a hardware reset to reset the whole chip. In case of a programming failure, it is recommended to replace the chip or to discontinue the use of the failing flash block.
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5) Auto Chip Erase command The Auto Chip Erase command requires six bus cycles. The flash area is partitioned into two blocks, Block 0 and Block 1. The chip erase operation is performed for each individual block. After completion of the sixth bus cycle, the Auto Chip Erase operation will commence immediately. The embedded Auto Erase algorithm automatically preprograms the entire memory for an all-0 data pattern prior to the erase; then it automatically erases and verifies the entire memory for an all-1 data pattern. The system can determine the status of the chip erase operation by using write status flags (see Table 17.4.3). Any commands written during the chip erase operation are ignored. A hardware reset immediately terminates the chip erase operation. The chip erase operation that was interrupted should be re-initiated once the flash memory is ready to accept another command sequence because data may be corrupted. The block protection feature disables erase operations in any block. The Auto Chip Erase algorithm erases the unprotected blocks and ignores the protected blocks. If both blocks are protected, the Auto Chip Erase command does nothing; the flash memory returns to Read mode in approximately 100 s after the completion of the sixth bus cycle of the command sequence. When the embedded Auto Chip Erase algorithm is complete, the flash memory returns to Read mode. If any failure occurs during the erase operation, the flash memory remains locked in Embedded Operation mode. The system can determine this status by using write status flags. To put the flash memory back in Read mode, use a software reset or a hardware reset to reset the flash memory or the device. In case of an erase failure, it is recommended to replace the chip or discontinue the use of the failing flash block. The failing block can be identified by the Block Erase command. 6) Auto Block Erase and Auto Multi-Block Erase Commands The Auto Block Erase command requires six bus cycles. A time-out begins from the completion of the command sequence. After a time-out, the erase operation will commence. The embedded Auto Block Erase algorithm automatically preprograms the selected block for an all-0 data pattern, and then erases and verifies that block for an all-1 data pattern. To erase the next block, the sixth bus cycle must be repeated; the next block address and the Auto Block Erase command must be provided within the time-out period. Any command other than Auto Block Erase during the time-out period resets the flash memory to Read mode. The block erase time-out period is 50 s. The system may read DQ3 to determine whether the time-out period has expired. The block erase timer begins counting upon completion of the sixth bus cycle of the Auto Block Erase command sequence. The system can determine the status of the erase operation by using write status flags (see Table 17.4.3). Any commands written during the block erase operation are ignored. A hardware reset immediately terminates the block erase operation. The block erase operation that was interrupted should be re-initiated once the flash memory is ready to accept another command sequence because data may be corrupted. The block protection feature disables erase operations in any block. The Auto Block Erase algorithm erases the unprotected blocks and ignores the protected blocks. If all the selected blocks are protected, the Auto Block Erase algorithm does nothing; the flash memory returns to Read mode in approximately 100 s after the final bus cycle of the command sequence. If any failure occurs during the erase operation, the flash memory remains locked in Embedded Operation mode. The system can determine this status by using the write status flags. To put the flash memory back in Read mode, use a software or hardware reset to reset the flash memory or the whole chip. In case of an erase failure, it is recommended to replace the chip or discontinue the use of the failing flash block. If any failure occurred during the
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multi-block erase operation, the failing block can be identified by running Auto Block Erase on each of the blocks selected for multi-block erasure. 7) Block Protect command The block protection feature disables both program and erase operations in any block. After completion of the seventh bus write cycle, the RDY/BSY bit in the FLCS register is cleared to 0 during the block protect operation. Once the block protect operation is complete, this bit is set again and the flash memory automatically returns to Read mode. If any failure occurred during the Block Protect operation, the flash memory remains locked in Embedded Operation mode with FLCS.RDY/BSY = 0. To put the flash memory back in Read mode, a software or hardware reset must be executed.
Table 17.4.2
Effects of the Program and Erase Commands on the Protected Blocks
Command Operation No programming operation is performed, and the flash memory automatically returns to Read mode. No erase operation is performed, and the flash memory automatically returns to Read mode. No erase operation is performed, and the flash memory automatically returns to Read mode. Only the unprotected blocks are erased. Upon completion, the flash memory automatically returns to Read mode. Only the unprotected blocks are erased. Upon completion, the flash memory automatically returns to Read mode.
Program command on a protected block Block Erase command on a protected block Chip Erase command when all the blocks are protected Chip Erase command when any blocks are protected Multi-Block Erase command when any blocks are protected
Any commands written during the Block Protect algorithm are ignored. A hardware reset immediately terminates the block protect operation. The Block Protect command that was interrupted should be re-initiated once the flash memory is ready to accept another command sequence. 8) Block Unprotect command The Block Unprotect command requires seven bus cycles. After completion of the seventh bus write cycle, the RDY/BSY bit in the FLCS register is cleared to 0 during the block unprotect operation. Once the block unprotect operation is complete, this bit is set again and the flash memory automatically returns to Read mode. If any failure occurred during the block unprotect operation, the flash memory remains locked in Embedded Operation mode with FLCS.RDY/BSY = 0. To put the flash memory back in Read mode, a software or hardware reset must be executed. Any commands written during the Block Unprotect algorithm are ignored. A hardware reset immeidately terminates the block unprotect operation. In this case, the block unprotect operation must be performed again by starting with protecting all the blocks again. Use the Verify Block Protect command to verify the protect status of a block.
9) Verify Block Protect command The Verify Block Protect command is used to verify the protect status of a block. Verify Block Protect is a four-bus-cycle operation. The address of the block to be verified is given in the fourth cycle. Any address within the block range will suffice, provided A[3:0] = 0, A4 = 1 and A6 = 0. To get correct data, a 32-bit read must be performed at least twice. Use the last read as valid data. If the selected block is protected, a value of 0x0000_0001 is returned. If the selected block is not protected, a value of 0x0000_0000 is returned. Following the fourth bus cycle, an
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additional block address may be read. The Verify Block Protect command does not return the flash memory to Read mode. Either the Read/Reset command or a hardware reset is required to reset the flash memory to Read mode or to write the next command. 10) ID-READ command The ID-READ command reads 0x0098 (fixed) as Toshiba's manufacturer's code. The flash memory address to be read is specified in the fourth bus read cycle. This address must satisfy A[4:0] = 0 and A6 = 0. To get correct data, a 32-bit read must be performed at least twice. Use the last read as valid data. By specifying an address where data other than 0x0098 is stored, the ID-READ command can be used to distinguish between the flash-version device (read value: 0x0098) and the mask-version device (read value: other than 0x0098).
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11) Write Operation Status As shown in Table 17.4.3, the flash memory provides flag bits to determine the status of an embedded operation: DQ7, DQ5 and DQ3. These status bits can be read during an embedded operation in the same timing as for Read mode. The flash memory automatically returns to Read mode when an embedded operation completes. The status of an embedded operation can be checked by reading the DQ7 flag. Once an embedded operation completes, the cell data can be read from the DQ7. The DQ7 must be read after checking that an embedded operation has started (FLCS.RDY/BSY=0). During the embedded program operation, the system must provide the program address (with A[1:0] = 0) to read valid status information. During the embedded erase operation, the system must provide an address (with A[1:0] = 0) within any of the blocks selected for erasure to read valid status information. While an embedded operation is in progress, D[31:16] are read as 0. These bits, therefore, can be used in place of the FLCS.RDY/BSY bit in a system where D[31:16] are not normally 0. Although the FLCS register is read as undefined in the mask-version device, use of D[31:16] allows the same program to be used in the flash-version and mask-version devices.
Table 17.4.3 Write Status Flags
Status Auto Program Auto Erase Embedded operation (during the time-out window) in progress Auto Erase Time-out in Auto Program embedded operation Auto Erase D7 (DQ7) DQ7 inverted 0 0 DQ7 inverted 0 D5 (DQ5) 0 0 0 1 1 D3 (DQ3) 0 0 1 1 1
Note 1: While an embedded operation is in progress, D[31:16]=0, D[15:8]=undefined, and DQ4, DQ2, DQ1, DQ0=undefined. Note 2: While an embedded operation is in progress, DQ7 outputs the inverted value of the programmed cell data. During the auto erase operation, DQ7 outputs 0 (erased state = 1).
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* DQ7 (Data Polling) The Data Polling bit, DQ7, indicates the status of an embedded operation. Data polling is valid after the final bus write cycle of an embedded command sequence. When the embedded Program algorithm is in progress, an attempt to read the flash memory will produce the complement of the data written to DQ7. Upon completion of the Program algorithm, an attempt to read the flash memory will produce the true data written to DQ7. When the embedded Erase algorithm is in progress, an attempt to read the flash memory will produce a 0 at the DQ7 output. Upon completion of the Erase algorithm, the flash memory will produce a 1 at the DQ7 output. If any failure occurs during an embedded operation, DQ7 continues to output the same value. Thus, DQ7 must always be polled in conjunction with the Exceeded Timing Limits (DQ5) flag. (see Table 17.4.3). The flash memory disables address latching when an embedded operation is complete. Data polling must be performed with a valid programmed address or an address within any of the unprotected blocks selected for erasure. * DQ5 (Exceeded Timing Limits) DQ5 produces a 0 while the program or erase operation is in progress normally. DQ5 produces a 1 to indicate that the program or erase time has exceeded the specified internal limit. This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition also appears if the system tries to program a 1 to a location that was previously programmed to a 0. Only an erase operation can change a 0 back to a 1. In this case, the embedded Program algorithm halts the operation. Once the operation has exceeded the timing limits, DQ5 will indicate a 1. Note that this is not a device failure condition since the flash memory was used incorrectly. Under both these conditions, the flash memory remains locked in Embedded Operation mode. A software reset is needed to return the flash memory to Read mode. * DQ3 (Block Erase Timer) After the completion of the sixth bus cycle of the Auto Block Erase command sequence, the block erase time-out window of 50 s begins. The erase operation will begin after the time-out has expired. When the time-out is complete and the erase operation has begun, DQ3 switches from 0 to 1. If DQ3 is 0, the flash memory will accept additional Auto Block Erase commands. Each time an Auto Block Erase command is written, the time-out window is reset. DQ3 produces a 1 if an embedded operation is not successfully completed.
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12)
Flash Control/Status Register This is a 32-bit register for monitoring the status of the flash memory. In Programmer mode, the RDY/BSY output is provided for the host system to monitor the status of an embedded algorithm. The TX19A core processor can poll the RDY/BSY bit in the FLCS register for the same purpose. The RDY/BSY bit is cleared to 0 when the flash memory is performing an embedded operation. The RDY/BSY bit is set to 1 when an embedded operation has completed and the flash memory is ready to accept the next command. If any failure occurs during an embedded operation, this bit remains 0. A hardware reset sets this bit to 1. The RDY/BSY bit is cleared to 0 upon completion of the final bus write cycle of an embedded operation command, with one exception. In the case of the Auto Block Erase command, this bit is cleared after the time-out has expired. Any command is ignored while the RDY/BSY bit is cleared.
7 6  R 0 5  R 0 4  R/W 0 Must be set to 0. 14  R 0 22  R 0 30  R 0 13  R 0 21  R 0 29  R 0 12  R 0 20  R 0 28  R 0 3 MROM R 0 0:Flash 1:Mask 11  R 0 19  R 0 27  R 0 2 RDY/BSY R 1 Ready/Busy 0: Busy 1: Ready 10  R 0 18  R 0 26  R 0 1  W 0 Must be set to 0. 9  R 0 17  R 0 25  R 0 8  R 0 16  R 0 24  R 0 0  R 0
FLCS (0xFFFF_E520)
Bit Symbol Read/Write Reset Value Function
 W 0 Must be set to 0. 15
Bit Symbol Read/Write Reset Value Bit Symbol Read/Write Reset Value Bit Symbol Read/Write Reset Value Note 1: Note 2: Note 3:
 R 0 23  R 0 31  W
This register must be accessed as a 32-bit quantity. This register does not support bit manipulation instructions. In the mask-version device, the MROM bit is set to 1 and any other bits are read-only with the same initial values.
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13) Flash Security The TMP19A71 flash memory supports not only on-board programming but also programming using a general-purpose programmer. Therefore, the TMP19A71 flash memory provides a security feature to prevent intrusive access to the flash memory while in Programmer mode. The TMP19A71 is secured when both of the two blocks are protected, and the contents of the flash memory cannot be read by a programmer. * Turning on the anti-programmer security feature (Disabling read accesses) Turning on the anti-programmer security feature disables a general-purpose programmer from reading the contents of the flash memory. To turn on this feature, once programming is complete, protect both the flash blocks. If either one of the blocks is unprotected, the anti-programmer security feature is off. In on-board programming modes, the TX19A core processor can read the flash memory even if the anti-programmer security feature is on. When the anti-programmer security feature is on, any reads by programming equipment will always return a half-word length value of 0x0098. * Turning off the anti-programmer security feature (Enabling read accesses) The anti-programmer security feature is designed to disable reads of the flash memory by programming equipment. While the TMP19A71 is soldered on a board, the TX19A core processor can always read the flash memory, regardless of whether or not the anti-programmer security feature is on. Since the flash memory is placed under control of a user's application program in on-board operating modes, it is not easy for third parties to perform intrusive access to the flash memory. Therefore, within the confines of a board, the flash memory does not need to be secured. The anti-programmer security feature can be turned off by unprotecting both of the two flash blocks. Prior to turning off the anti-programmer security feature, the flash array is erased unconditionally. After the flash array is erased, the protect bit of each block is erased to turn off the anti-programmer security feature. In Single-Chip mode, block protection is lifted in a user application program. Thus, the flash memory is not erased when the anti-programmer security feature is turned off.
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(4) Command definitions Table 17.4.4 On-Board Programming Mode Command Definitions
Command Sequence Cycles Required 1 3 4 6 6   4 1st Bus Cycle (Write) Addr. Reset Read/Reset Auto Program Auto Chip Erase Auto Block Erase Block Protect Block Unprotect ID Read/ Block Protect Verify 0xXXXX 0x5554 0x5554 0x5554 0x5554 0x5554 0x5554 0x5554 Data 0x0F0 0x0AA 0x0AA 0x0AA 0x0AA 0x0AA 0x0AA 0x0AA 2nd Bus Cycle (Write) Addr. 0xAAA8 0xAAA8 0xAAA8 0xAAA8 0xAAA8 0xAAA8 0xAAA8 Data 0x055 0x055 0x055 0x055 0x055 0x055 0x055 3rd Bus Cycle (Write) Addr. 0x5554 0x5554 0x5554 0x5554 0x5554 0x5554 0x5554 Data 0x0F0 0x0A0 0x080 0x080 0x09A 0x06A 0x090 4th Bus Cycle (Read/Write) Addr. RA PA 0x5554 0x5554 0x5554 0x5554 IA Data RD PD 0xAA 0xAA 0xAA 0xAA ID
(Continued from above)
Command Sequence Reset Read/Reset Auto Program Auto Chip Erase Auto Block Erase Block Protect Block Unprotect ID Read/Block Protect Verify Cycles Required 1 3 4 6 6 7 7 4 5th Bus Cycle (Write) Addr. Data 6th Bus Cycle (Write) Addr. Data 7th Bus Cycle (Write) Addr. Data
0xAAA8 0xAAA8 0xAAA8 0xAAA8
0x055 0x055 0x055 0x055
0x5554 BA 0x5554 0x5554
0x010 0x030 0x09A 0x06A
BA (Note 3) BPA 0x5554
0x030 0x09A 0x06A
Note 1: After every bus write cycle, execute the SYNC and NOP instructions in sequence. Note 2: In each bus write cycle, bits 16 to 19 should be set to the value coresponding to the flash memory address. Note 3: For a multi-block erase operation, add BA in the 7th and subsequent bus write cycles. Note 4: To operate on the flash memory, the watchdog timer must be disabled.
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The addresses to be provided by the TX19A core processor are shown below. Table 17.4.5 Addresses Provided by the TX19A Core Processor
Command Address Addr. 0xXXX0 0x0000 0xAAA8 0x5554 Flash memory block A[23:16] A15 X 0 1 0 A14 A13 X 0 0 1 X 0 1 0 A12 X 0 0 1 A11 X 0 1 0 Address: A[23:0] A10 A9 X 0 0 1 X 0 1 0 A8 X 0 0 1 A7 X 0 1 0 A6 X 0 0 1 A5 X 0 1 0 A4 X 0 0 1 A3 0 0 1 0 A2 0 0 0 1 A1 0 0 0 0 A0 0 0 0 0
(5) Miscellaneous * 0x0F0, 0x0AA, 0x055, 0x0A0, 0x080, 0x09A, 0x06A, 0x090, 0x010, 0x030 Command sequence write data D[8:0]. To write command data, use a 32-bit (word) load (SW) instruction with D[31:9] = 0. * RA: Read Address Any address in the flash memory can be specified. * RD: Read Data The data at the RA (Read Address) can be read by using an 8-bit (byte) 16-bit (half-word) or 32-bit (word) load instruction. * PA: Program Address Any flash memory address (A[1:0]=0) to be programmed can be specified. * PD: Program Data By using a 32-bit (word) SW instruction, the PA (Program Address) can be programmed to the specified data. * IA: ID Address The flash memory address (A[1:0]=0) on which the ID-READ or Verify Block Protect command is to be executed. Table 17.4.6
A17 ID-READ (manufacturer's code) Verify Block 0 Protect Verify Block 1 Protect x 0 0 1 1 0 A6 0
IA (ID Address) Table
A4 0 A3 0 0x0098 (fixed) 0x0000_0001 (Block 0 protected) 0x0000_0000 (Block 0 not protected) 0x0000_0001 (Block 1 protected) 0x0000_0000 (Block 1 not protected) ID
* ID: ID Data The data that indicates the result of ID-READ or Verify Block Protect executed on the IA (ID Address).
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* BA: Block Address The flash memory address (A[1:0]=0) to specify the block to be erased. For example, in User Boot mode, Block 0 can be selected by executing the LW instruction on an address in the range of 0xBFC0_0000 to 0xBFC1_FFFF (0x0000_00000x0001_FFFF). * BPA: Block Protect Address The flash memory address (A[1:0]=0) to specify the block to be protected. For example, in User Boot mode, Block 0 can be selected by executing the LW instruction on an address in the range of 0xBFC0_0000 to 0xBFC1_FFFF (0x0000_00000x0001_FFFF). Table 17.4.7
Block 0 Block 1
BA (Block Address) and BPA (Block Protect Address) Table
User Boot Mode Single Boot Mode 0x0000_0000 to 0x0001_FFFF 0x0002_0000 to 0x0003_FFFF Size 128 Kbytes 128 Kbytes A17 0 1
0xBFC0_0000 to 0xBFC1_FFFF (or 0x0000_0000 to 0x0001_FFFF) 0xBFC2_0000 to 0xBFC3_FFFF (or 0x0002_0000 to 0x0003_FFFF)
(6)
Programming Examples
(a) Programming example for ID-READ lui addiu lui ori ori sw sync nop ori sw sync nop ori sw sync nop ori lw lw lw sync nop r6,r0,0x00aa r7,0(r0) r7,0(r0) r7,0(r0) ; 4th bus read cycle ; 4th 0x0000_0000(IA:A6=A4=A3=A1=A0 =0) --> r7(dummy) ; 4th 0x0000_0000(IA:A6=A4=A3=A1=A0 =0) --> r7(dummy) ; 4th 0x0000_0000(IA:A6=A4=A3=A1=A0 =0) --> r7 r6,r0,0x0090 r6,0(r4) ; 3rd bus write cycle ; 3rd 0x0000_5554 <-- 0x0090 r6,r0,0x0055 r6,0(r5) ; 2nd bus write cycle ; 2nd 0x0000_aaa8 <-- 0x0055 r4,0x0000 r4,r4,0x5554 r5,0x0000 r5,r5,0xaaa8 r6,r0,0x00aa r6,0(r4) ; r4=0x0000_xxxx ; r4=0x0000_5554 ; r5=0x0000_xxxx ; r5=0x0000_aaa8 ; 1st bus write cycle ; 1st 0x0000_5554 <-- 0x00aa
TMP19A71
17-63
TMP19A71
(b) Programming example for polling the FLCS.RDY/BSY bit lui addiu rdybsy_lp: lw andi beq nop r6,0(r7) r6,r6,0x04 r6,r0,rdybsy_lp r7,hi(FLCS) r7,r7,lo(FLCS) ; r7=0xFFFF_xxxx ; r7=0xFFFF_E520 (FLCS address) ; RDY/BSY poiing ; r6 <-- FLCS ; Mask bits other than FLCS.RDY/BSY ; Loop until FLCS.RDY/BSY=1
(c) Programming example for erasing Block 1 and polling the write status flags lui addiu lui ori ori sw sync nop ori sw sync nop ori sw sync nop ori sw sync nop ori sw sync nop ori sw sync nop r6,r0,0x0030 r6,0(r5) ; 6th bus write cycle ; 6th 0x0002_aaa8(A17=1) <-- 0x0030 ; Start erasing Block 1 r6,r0,0x0055 r6,0(r5) ; 5th bus write cycle ; 5th 0x0002_aaa8 <-- 0x0055 r6,r0,0x00aa r6,0(r4) ; 4th bus write cycle ; 4th 0x0002_5554 <-- 0x00aa r6,r0,0x0080 r6,0(r4) ;3rd bus write cycle ; 3rd 0x0002_5554 <-- 0x0080 r6,r0,0x0055 r6,0(r5) ; 2nd bus write cycle ; 2nd 0x0002_aaa8 <-- 0x0055 r4,0x0002 r4,r4,0x5554 r5,0x0002 r5,r5,0xaaa8 r6,r0,0x00aa r6,0(r4) ; r5=0x0002_aaa8 ; 1st bus write cycle ; 1st 0x0002_5554 <-- 0x00aa ; r4=0x0002_5554
dq3_lp: lw r6,0(r5)
; Start polling the write status flags ; Read data at 0x0002_aaa8
TMP19A71
17-64
TMP19A71
andi beq nop dq7_lp: lw andi bne nop andi beq nop lw andi beq nop data_chk: nor lw beq nop erase_err: ori sw sync nop r6,r0,0x00F0 r6,0(r0) ; Software reset ; 1st 0x0000_0000 <-- 0x00F0 ; Return to Read mode r7,r0,r0 r6,0(r5) r7,r6,complete ; r7=0xFFFF_FFFF ; Read data at 0x0002_aaa8 again ; If erased properly, go to end routine r6,0(r5) r7,r6,0x80 r7,r0,erase_err ; Read data at 0x0002_aaa8 again ; Mask flags other than DQ7 ; If DQ7=0, go to error routine r7,r6,0x20 r7,r0,dq7_lp ; Mask flags other than MDQ5 ; If DQ5=0 (busy), go to dq7_lp r6,0(r5) r7,r6,0x80 r7,r0,data_chk ; Read data at 0x0002_aaa8 again ; Mask flags other than DQ7 ; If DQ7=1, go to data_chk r7,r6,0x08 r7,r0,dq3_lp ; Mask flags other than DQ3 ; If during the time-out (DQ3=0), go to dp3_lp
complete:
(Omitted)
; End routine
Note:
These programming examples assume the use of a Toshiba assembler. If a third-party assembler is used, syntax errors may occur. Change the code as necessary according to the assembler to be used.
TMP19A71
17-65
TMP19A71
(7)
Embedded Algorithms
Start
Auto Program Command Sequence (Shown below)
Data Polling Bit (Read as a word quantity)
Address = Address + 4 (Word-by-word)
No
Last Address?
Yes Auto Program Done
Auto Program Command Sequence (Address Command) 0x5554(Addr.)/0xAA(Data)
0xAAA8(Addr.)/55H(Data)
0x5554(Addr.)/A0H(Data)
Program Address (A1, A0 = 0) / Program Data (Word-by-word))
Figure 17.4.3 Auto Program Operation
TMP19A71
17-66
TMP19A71
Start
Auto Erase Command Sequence (Shown below)
Data Polling Bit (Read as a word quantity)
Auto Erase Done
Auto Chip Erase Command Sequence (Address/Command) 0x5554(Addr.)/0xAA(Data)
Auto Block/Multi-Block Erase Command Sequence (Address/Command) 0x5554(Addr.)/0xAA(Data)
0xAAA8(Addr.)/0x55(Data)
0xAAA8(Addr.)0x55(Data)
0x5554(Addr.)/0x80(Data)
0x5554(Addr.)/0x80(Data)
0x5554(Addr.)/0xAA(Data)
0x5554(Addr.)/0xAA(Data)
0xAAA8(Addr.)/0x55(Data)
0xAAA8(Addr.)/0x55(Data)
0x5554(Addr.)/0x10(Data)
Block Address/0x30(Data)
Block Address/0x30(Data)
Additional addresses for Auto Multi-Block Erase (each within 50 s)
Block Address/0x30(Data)
Figure 17.4.4 Auto Erase Operations
TMP19A71
17-67
TMP19A71
Start
Read a word. Addr. = VA
DQ7 = Data? No No DQ5 = 1? Yes Read a word. Addr. = VA
Yes
DQ7 = Data? No
Yes
Read a word. Addr. = virtual address
Compare with 32-bit quantity.
Fail
Pass
Figure 17.4.5 Data Polling (DQ7) Algorithm
TMP19A71
17-68
Under Development
TMP19A71
18. I/O Register Summary
18.1 Register Map
I/O registers occupy 16-Kbyte addresses from FFFFC000H through FFFFFFFFH. (1) Ports (2) Motor control circuit (PMD: Programmable Motor Driver) (3) Encoder input circuit (4) Serial I/O (SIO) (5) 16-bit timer/event counter (TMRB) (6) Watchdog timer (7) AD converter (8) Interrupts (9) Clock/standby control (10) DMA controller (DMAC) (11) Flash memory (12) ROM correction
TMP19A71
18-1
TMP19A71
[1] Ports
Address FFFFC000H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic P0D Address FFFFC010H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Reserved Address FFFFC020H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Reserved Address FFFFC030H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Reserved
P0CR
P0PUCR
Reserved
Reserved
P0IER
Reserved
Reserved
Reserved
P0DSSR
Reserved
Reserved
Reserved
Address FFFFC040H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic P1D
Address FFFFC050H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC060H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC070H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
P1CR
P1PUCR
Reserved
Reserved
P1IER
Reserved
Reserved
Reserved
P1DSSR
Reserved
Reserved
Reserved
Address FFFFC080H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic P2D
Address FFFFC090H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC0A0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC0B0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
P2CR
P2PUCR
Reserved
Reserved
P2IER
Reserved
Reserved
Reserved
P2DSSR
Reserved
Reserved
Reserved
TMP19A71
18-2
Under Development
TMP19A71
Address FFFFC0C0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic P3D
Address FFFFC0D0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC0E0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC0F0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
P3CR
P3PUCR
Reserved
Reserved
P3IER
Reserved
Reserved
Reserved
P3DSSR
Reserved
Reserved
Reserved
Address FFFFC100H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC110H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC120H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC130H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Address FFFFC140H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic P5D
Address FFFFC150H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC160H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC170H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Reserved
P5PUCR
Reserved
Reserved
P5IER
P5FR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TMP19A71
18-3
TMP19A71
Address FFFFC180H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic P6D
Address FFFFC190H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC1A0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC1B0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
P6CR
P6PUCR
Reserved
Reserved
P6IER
P6FR
Reserved
Reserved
P6DSSR
Reserved
Reserved
Reserved
Address FFFFC1C0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic P7D
Address FFFFC1D0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC1E0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC1F0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
P7CR
P7PUCR
Reserved
Reserved
P7IER
P7FR1
Reserved
Reserved
P7DSSR
P7FR2
Reserved
Reserved
Address FFFC200H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic P8D
Address FFFFC210H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic P8ODCR
Address FFFFC220H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC230H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
P8CR
P8PUCR
Reserved
Reserved
P8IER
P8FR
Reserved
Reserved
P8DSSR
Reserved
Reserved
Reserved
TMP19A71
18-4
Under Development
TMP19A71
Address FFFFC240H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic P9D
Address FFFFC250H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC260H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic P9ECR
Address FFFFC270H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
P9CR
P9PUCR
P9ECLR
Reserved
P9IER
P9FR1
Reserved
Reserved
P9DSSR
P9FR2
Reserved
Reserved
Address FFFFC280H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic PAD
Address FFFFC290H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC2A0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic PAECLR
Address FFFFC2B0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
PACR
PAPUCR
Reserved
Reserved
PAIER
PAFR
Reserved
Reserved
PADSSR
PAECR
Reserved
Reserved
Address FFFFC2C0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic PBD
Address FFFFC2D0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFC2E0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic PBECLR
Address FFFFC2F0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
PBCR
PBPUCR
Reserved
Reserved
PBIER
PBFR
Reserved
Reserved
PBDSSR
PBECR
Reserved
Reserved
TMP19A71
18-5
TMP19A71
[2] PMD
Address FFFFC300H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic MDCR0 Address FFFFC310H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic CMPV0 Address FFFFC320H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic EMGCR0 Address FFFFC330 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TRGCMP02
MDCNT0
CMPW0
TRGCR0
Reserved
MDPRD0
MDOUT0
TRGCMP00
CMPU0
EMGREL0
TRGCMP01
Address FFFFC340H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic MDCR1
Address FFFFC350H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic CMPV1
Address FFFFC360H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic EMGCR1
Address FFFFC370 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic TRGCMP12
MDCNT1
CMPW1
TRGCR1
Reserved
MDPRD1
MDOUT1
TRGCMP10
CMPU1
EMGREL1
TRGCMP11
[3] ABZ Encoder
Address FFFFC400H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ENTNCR Address FFFFC410H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Reserved Address FFFFC420H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic
ENRELOAD
ENINT
ENCNT
TMP19A71
18-6
Under Development
[4] SIO
Address FFFFC480H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic SC0MOD0 SC0MOD1 Address FFFFC490H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic SC0BUF Address FFFFC4A0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
TMP19A71
Mnemonic SC1MOD0 SC1MOD1
Address FFFFC4B0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic SC1BUF
SC0CR SC0MOD2
SC0FCNF
SC1CR SC1MOD2
SC1FCNF
BR0CR BR0ADD
SC0FTC SC0FRC
BR1CR BR1ADD
SC1FTC SC1FRC
SC0FTS SC0FRS
SC1FTS SC1FRS
Address FFFFC4C0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic SC2MOD0 SC2MOD1
Address FFFFC4D0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic SC2BUF
Address FFFFC4E0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic SC3MOD0 SC3MOD1
Address FFFFC4F0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic SC3BUF
SC2CR SC2MOD2
SC2FCNF
SC3CR SC3MOD2
SC3FCNF
BR2CR BR2ADD
SC2FTC SC2FRC
BR3CR BR3ADD
SC3FTC SC3FRC
SC2FTS SC2FRS
SC3FTS SC3FRS
[5] TMRB
Address FFFFC700H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TB0RUN Address FFFFC710H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TB0REG1 Address FFFFC720H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TB1RUN Address FFFFC730H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic TB1REG1
TB0MOD(L) (TB0MODH)
TB0CP0
TB1MOD(L) (TB1MODH)
TB1CP0
TB0FF
TB0CP1
TB1FF
Reserved
TB0REG0
TB0CNT
TB1REG0
TB1CNT
TMP19A71
18-7
TMP19A71
Address FFFFC740H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic TB2RUN
Address FFFFC750H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic TB2REG1
Address FFFFC760H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic TB3RUN
Address FFFFC770H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic TB3REG1
TB2MOD(L) (TB2MODH)
TB2CP0
TB3MOD(L) (TB3MODH)
TB3CP0
TB2FF
Reserved
TB3FF
Reserved
TB2REG0
TB2CNT
TB3REG0
TB3CNT
[6] WDT
Address FFFFC830H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic WDMOD(L) (WDMODH)
WDCR
WDCNT
[7-1] ADC (Normal Mode)
Address FFFFC900H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADNRES0 Address FFFFC910H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADNRES4 Address FFFFC920H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADCHPR0 Address FFFFC930H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADCHPC0
ADNRES1
ADNRES5
ADNMOD0(L) (ADNMOD0H)
ADCMP00
ADNRES2
ADNRES6
ADNCLK0
ADCMP01
ADNRES3
ADNRES7
CMPCTL0(L) (CMPCTL0H)
ADCBASN0
TMP19A71
18-8
Under Development
TMP19A71
Address FFFFC940H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic ADCSTART0
Address FFFFC980H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic ADNRES8
Address FFFFC990H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic ADNRES12
Address FFFFC9A0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic ADCHPR1
Address FFFFC9B0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic ADCHPC1
ADNRES9
ADNRES13
ADNMOD1(L) (ADNMOD1H)
ADCMP10
ADNRES10
ADNRES14
ADNCLK1
ADCMP11
ADNRES11
ADNRES15
CMPCTL1(L) (CMPCTL1H)
ADCBASN1
Address FFFFC9C0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic ADCSTART1
TMP19A71
18-9
TMP19A71
[7-2] ADC (PMD Mode)
Address FFFFCD00H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADPRES0 Address FFFFCD10H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADPRES4 Address FFFFCD20H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Reserved Address FFFFCD30H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Reserved
ADPRES1
ADPRES5
Reserved
Reserved
ADPRES2
ADPRES6
Reserved
Reserved
ADPRES3
ADPRES7
Reserved
Reserved
Address FFFFCD40H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic ADCSETT00(L) (ADCSETT00H)
Address FFFFCD50H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
Address FFFFCD60H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic ADPMOD01(L) (ADPMOD01H)
Address FFFFCD70H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic ADMODSEL0
Reserved
Reserved
ADCNE0(L) (ADCNE0H)
ADCSET00(L) (ADCSET00H)
ADPCLK0
ADCNT0
ADCSET01(L) (ADCSET01H)
ADPMOD00
ADCBASP0
Address FFFFCD80H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic ADPRES8
Address FFFFCD90H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic ADPRES12
Address FFFFCDA0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic ADPRES16
Address FFFFCDB0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic Reserved
ADPRES9
ADPRES13
ADPRES17
Reserved
ADPRES10
ADPRES14
ADPRES18
Reserved
ADPRES11
ADPRES15
Reserved
Reserved
TMP19A71
18-10
Under Development
TMP19A71
Address FFFFCDC0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH [8] IRC Address FFFFD000H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic ADCSETT10(L) (ADCSETT10H)
Address FFFFCDD0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic ADCSET12(L) (ADCSET12H)
Address FFFFCDE0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic ADPMOD11(L) (ADPMOD11H)
Address FFFFCDF0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic ADMODSEL1
ADCSETT11
Reserved
ADCNE1(L) (ADCNE1H)
ADCSET10(L) (ADCSET10H)
ADPCLK1
ADCNT1
ADCSET11(L) (ADCSET11H)
ADPMOD10
ADCBASP1
Mnemonic IMR00 (IMR01) (IMR02) (IMR03) IMR04 (IMR05) (IMR06) (IMR07) IMR08 (IMR09) (IMR10) (IMR11) IMR12 (IMR13) (IMR14) (IMR15)
Address FFFFD010H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic IMR16 (IMR17) (IMR18) (IMR19) IMR20 (IMR21) (IMR22) (IMR23) IMR24 (IMR25) (IMR26) (IMR27) IMR28 (IMR29) (IMR30) (IMR31)
Address FFFFD020H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic IMR32 (IMR33) (IMR34) (IMR35) IMR36 (IMR37) (IMR38) (IMR39) IMR40 (IMR41) (IMR42) (IMR43) IMR44 (IMR45) (IMR46) (IMR47)
Address FFFFD030H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic IMR48 (IMR49) (IMR50) (IMR51) IMR52 (IMR53) (IMR54) (IMR55) IMR56 (IMR57) (IMR58) (IMR59) IMR60 (IMR61) (IMR62) (IMR63)
Address FFFFD040H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic IMR64 (IMR65) (IMR66) (IMR67) IMR68 (IMR69) (IMR70) (IMR71) IMR72 (IMR73) (IMR74) (IMR75) IMR76 (IMR77) (IMR78) (IMR79)
Address FFFFD050H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic IMR80 (IMR81) (IMR82) (IMR83) IMR84 (IMR85) (IMR86) (IMR87) IMR88 (IMR89) (IMR90) (IMR91) IMR92 (IMR93) (IMR94) (IMR95)
Address FFFFD080H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic IVR
Address FFFFD070H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic
ICLR
ILEV
TMP19A71
18-11
TMP19A71
[9] Clock Generator
Address FFFFD300H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic CLKACT Address FFFFD310H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic CLKNMI Reserved CLKW0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved CLKINT0 CLKINT1 CLKINT2 CLKINT3 Reserved Reserved Address FFFFD320H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Reserved Reserved Address Mnemonic FFFFD330H Reserved 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
CLKOSC CLKWUT CLKSPD CLKPRSC Reserved Reserved Reserved Reserved CLKMISC
[10] MODEC
Address FFFFD400H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic MODECR Address FFFFD410H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFD420H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Address FFFFD430H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic
[11] DMAC
Address FFFFD600H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic CCR0(LL) (CCR0LH) (CCR0HL) (CCR0HH) CSR0(LL) (CSR0LH) (CSR0HL) (CSR0HH) SAR0(LL) (SAR0LH) (SAR0HL) (SAR0HH) DAR0(LL) (DAR0LH) (DAR0HL) (DAR0HH) Address FFFFD610H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH DTCR0(LL) (DTCR0LH) (DTCR0HL) (DTCR0HH) Mnemonic BCR0(LL) (BCR0LH) (BCR0HL) (BCR0HH) Address FFFFD620H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic CCR1(LL) (CCR1LH) (CCR1HL) (CCR1HH) CSR1(LL) (CSR1LH) (CSR1HL) (CSR1HH) SAR1(LL) (SAR1LH) (SAR1HL) (SAR1HH) DAR1(LL) (DAR1LH) (DAR1HL) (DAR1HH) Address FFFFD630H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH DTCR1(LL) (DTCR1LH) (DTCR1HL) (DTCR1HH) Mnemonic BCR1(LL) (BCR1LH) (BCR1HL) (BCR1HH)
TMP19A71
18-12
Under Development
Address FFFFD640H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic CCR2(LL) (CCR2LH) (CCR2HL) (CCR2HH) CSR2(LL) (CSR2LH) (CSR2HL) (CSR2HH) SAR2(LL) (SAR2LH) (SAR2HL) (SAR2HH) DAR2(LL) (DAR2LH) (DAR2HL) (DAR2HH) Address FFFFD650H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH DTCR2(LL) (DTCR2LH) (DTCR2HL) (DTCR2HH) Mnemonic BCR2(LL) (BCR2LH) (BCR2HL) (BCR2HH) Address FFFFD660H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
TMP19A71
Mnemonic CCR3(LL) (CCR3LH) (CCR3HL) (CCR3HH) CSR3(LL) (CSR3LH) (CSR3HL) (CSR3HH) SAR3(LL) (SAR3LH) (SAR3HL) (SAR3HH) DAR3(LL) (DAR3LH) (DAR3HL) (DAR3HH) Address FFFFD670H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH DTCR3(LL) (DTCR3LH) (DTCR3HL) (DTCR3HH) Mnemonic BCR3(LL) (BCR3LH) (BCR3HL) (BCR3HH)
Address FFFFD680H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic CCR4(LL) (CCR4LH) (CCR4HL) (CCR4HH) CSR4(LL) (CSR4LH) (CSR4HL) (CSR4HH) SAR4(LL) (SAR4LH) (SAR4HL) (SAR4HH) DAR4(LL) (DAR4LH) (DAR4HL) (DAR4HH)
Address FFFFD690H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic BCR4(LL) (BCR4LH) (BCR4HL) (BCR4HH)
Address FFFFD6A0H 1H 2H 3H 4H 5H 6H 7H
Mnemonic CCR5(LL) (CCR5LH) (CCR5HL) (CCR5HH) CSR5(LL) (CSR5LH) (CSR5HL) (CSR5HH) SAR5(LL) (SAR5LH) (SAR5HL) (SAR5HH) DAR5(LL) (DAR5LH) (DAR5HL) (DAR5HH)
Address FFFFD6B0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic BCR5(LL) (BCR5LH) (BCR5HL) (BCR5HH)
DTCR4(LL) (DTCR4LH) (DTCR4HL) (DTCR4HH)
8H 9H AH BH CH DH EH FH
DTCR5(LL) (DTCR5LH) (DTCR5HL) (DTCR5HH)
Address FFFFD6C0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic CCR6(LL) (CCR6LH) (CCR6HL) (CCR6HH) CSR6(LL) (CSR6LH) (CSR6HL) (CSR6HH) SAR6(LL) (SAR6LH) (SAR6HL) (SAR6HH) DAR6(LL) (DAR6LH) (DAR6HL) (DAR6HH)
Address FFFFD6D0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic BCR6(LL) (BCR6LH) (BCR6HL) (BCR6HH)
Address FFFFD6E0H 1H 2H 3H 4H 5H 6H 7H
Mnemonic CCR7(LL) (CCR7LH) (CCR7HL) (CCR7HH) CSR7(LL) (CSR7LH) (CSR7HL) (CSR7HH) SAR7(LL) (SAR7LH) (SAR7HL) (SAR7HH) DAR7(LL) (DAR7LH) (DAR7HL) (DAR7HH)
Address FFFFD6F0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic BCR7(LL) (BCR7LH) (BCR7HL) (BCR7HH)
DTCR6(LL) (DTCR6LH) (DTCR6HL) (DTCR6HH)
8H 9H AH BH CH DH EH FH
DTCR7(LL) (DTCR7LH) (DTCR7HL) (DTCR7HH)
TMP19A71
18-13
TMP19A71
Address FFFFD700H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic DCR(LL) (DCRLH) (DCRHL) (DCRHH) Reserved Reserved Reserved Reserved
Address FFFFD710H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH
Mnemonic
Address FFFFD720H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic
Address FFFFD730H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic
DHR(LL) (DHRLH) (DHRHL) (DHRHH)
CH DH EH FH
Address FFFFD740H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic
Address FFFFD750H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic
Address FFFFD760H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic
Address FFFFD770H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Mnemonic
TMP19A71
18-14
Under Development
TMP19A71
[12] Flash Memory (Flash version only; DMA not supported)
Address FFFFE510H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic SEQMOD Address FFFFE520H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic FLCS Address FFFFE530H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic B0DCR
SEQCNT
B0DLR
Reserved
B1DCR
Reserved
B1DLR
[13] ROM Correction (DMA not supported)
Address FFFFE540H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADDREG0 Address FFFFE550H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic ADDREG4 Address FFFFE560H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Reserved Address FFFFE570H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Mnemonic Reserved
ADDREG1
ADDREG5
Reserved
Reserved
ADDREG2
ADDREG6
Reserved
Reserved
ADDREG3
ADDREG7
Reserved
Reserved
TMP19A71
18-15
TMP19A71
18.2
FFFF_C000
Bus Error Area
FFFF_D000 Ports 0 to 3 IRC FFFF_D0FF FFFF_D080 (Note 1) (Note 1) FFFF_D2FF FFFF_D300 Ports 5 to B CG FFFF_D33F FFFF_D340 PMD (Note 1) FFFF_D3FF FFFF_D400 (Note 1) MODEC FFFF_D4FF FFFF_D500 ENC (Note 1) FFFF_D5FF FFFF_D600 (Note 1) DMAC FFFF_D61B FFFF_D61C SIO (Note 2) FFFF_D61F FFFF_D620 (Note 1) DMAC FFFF_D63B FFFF_D63C TMRB (Note 2) FFFF_D63F FFFF_D640 (Note 1) DMAC FFFF_D65B FFFF_D65C WDT (Note 2) FFFF_D65F FFFF_D660 (Note 1) DMAC FFFF_D67B ADC (Normal) FFFF_D67C (Note 2) FFFF_D67F FFFF_D680 (Note 1) DMAC FFFF_D69B ADC (PMD) FFFF_D69C (Note 2) FFFF_D69F FFFF_D6A0 (Note 1) DMAC FFFF_D6BB Bus error area. A store access does not cause a bus error exception, but a NMI occurs.(MODECR=0) Bus error area, but a store access does not cause a NMI. FFFF_FFFF FFFF_E6FF FFFF_E700 (Note 1) FFFF_E4FF FFFF_E500 Flash /ROM FFFF_E48B FFFF_E48C (Note 2) FFFF_E47F FFFF_E480 Reserved FFFF_E40F FFFF_E410 (Note 1) FFFF_E3FF FFFF_E400 Reserved FFFF_D7FF FFFF_D800 (Note 1) FFFF_D70F FFFF_D710 (Note 2) FFFF_D70B FFFF_D70C DMAC FFFF_D707 FFFF_D708 (Note 2) FFFF_D6FF FFFF_D700 DMAC FFFF_D6FB FFFF_D6FC (Note 2) FFFF_D6DF FFFF_D6E0 DMAC FFFF_D6DB FFFF_D6DC (Note 2) FFFF_D6BF FFFF_D6C0 DMAC FFFF_D6BC (Note 2)
FFFF_C0FF FFFF_C100 FFFF_C13F FFFF_C140 FFFF_C2FF FFFF_C300 FFFF_C37F FFFF_C380 FFFF_C3FF FFFF_C400 FFFF_C43F FFFF_C440 FFFF_C47F FFFF_C480 FFFF_C4DF FFFF_C4E0 FFFF_C6FF FFFF_C700 FFFF_C77F FFFF_C780 FFFF_C82F FFFF_C830 FFFF_C83F FFFF_C840 FFFF_C8FF FFFF_C900 FFFF_C9FF FFFF_CA00 FFFF_CCFF FFFF_CD00 FFFF_CDFF FFFF_CE00 FFFF_CFFF Note 1: Note 2:
TMP19A71
18-16
TMP19A71
19. Electrical Characteristics
19.1 Maximum Ratings Mask-Version Product
Parameter Symbol VCC15 (Core) Supply voltage VCC3 (I/O) AVCC (AD) Input voltage Low-level output current High-level output current Per pin Total Per pin Total VIN IOL IOL IOH IOH PD TSOLDER TSOLDER Ta ave TSTG TOPR Rating -0.3 to 3.0 -0.3 to 3.9 -0.3 to 3.6 -0.3 to VCC3 + 0.3 (Note 2) -0.3 to AVCC + 0.3 15 80 -15 -50 600 260 350 -20 to 65 -65 to 150 -40 to 85 mW      mA
(Note 1)
The letter X in equations presented in this chapter represents the fsys or IMCLK period selected by the CLKPRSC.PRS1 or PRS2 field.
Unit
V
V
Power dissipation (Ta = 85C) Soldering temperature 10 seconds 3 seconds
Average temperature Storage temperature Operating temperature
VCC15DVCC15CVCC15, VCC3DVCC3, AVCCAVCCn (n0, 1), VSSDVSSAVSSCVSS Note 1: Note 2: The absolute maximum rating of VCC3 (-0.3 to 3.9 V) must not be exceeded. Since Ports 5 to 7 use AVCC as the power supply for each port function, the maximum rating for AVCC (-0.3 to 3.6 V) should be applied to these ports. Note 3: Maximum ratings are limiting values of operating and environmental conditions which should not be exceeded under the worst possible conditions. The equipment manumacturer should design so that no maximum rating value is exceeded with respect to current, voltage, power dissipation, temperature, etc. Exposure to conditions beyond those listed above may cause permanent damage to the device or affect device reliability, which could increase potential risks of personal injury due to IC blowup and/or burning.
TMP19A71
19-1
TMP19A71
Flash-Version Product
Parameter Supply voltage Symbol VCC2 (Core) VCC3 (I/O) AVCC (A/D) Input voltage VIN Low-level output current High-level output current Per pin Total Per pin Total IOL IOL IOH IOH PD TSOLDER TSOLDER Ta ave TSTG Rating -0.3 to 3.6 -0.3 to 3.9 -0.3 to3.6 -0.3 to VCC3 + 0.3 (Note 2) -0.3 to AVCC + 0.3 15 80 -15 -50 1000 260 350 -20 to 65 -65 to 150 -40 to 85 TOPR -0 to 60 NWE 100 cycle  mW     mA
(Note 1)
Unit
V
V
Power dissipation (Ta = 85C) Soldering temperature 10 seconds 3 seconds
Average temperature Storage temperature Operating temperature Other than Flash program/erase Flash program/erase
Flash reprogram times
VCC2DVCC2CVCC2FVCC2, VCC3FVCC3DVCC3, AVCCAVCCn (n0, 1), VSSDVSSAVSSCVSSFVSS
Note 1: Note 2:
The absolute maximum rating of VCC3 (-0.3 to 3.9V) must not be exceeded. Since Ports 5 to 7 use AVCC as the power supply for each port function, the maximum rating for AVCC (-0.3 to 3.6 V) should be applied to these ports.
Note 3:
Maximum ratings are limiting values of operating and environmental conditions which should not be exceeded under the worst possible conditions. The equipment manufacturer should design so that no maximum rating value is exceeded with respect to current, voltage, power dissipation, temperature, etc. Exposure to conditions beyond those listed above may cause permanent damage to the device or affect device reliability, which could increase potential risks of personal injury due to IC blowup and/or burning.
Note 4:
The number of times the flash memory can be reprogrammed includes programming of nonvolatile bits in the flash ROM. Note that programming nonvolatile bits to the same value is also counted in the reprogram times.
TMP19A71
19-2
TMP19A71
19.2 Recommended Operating Conditions Mask-Version Product
Ta  -40 to 85  Parameter Supply voltage DVCC15CVCC15 DVCC3 CVSSDVSSAVSS0V P0, P1, P23, P3, P80-P83, P85, P86, P94, PA0-PA5, PB0-PB5 P5-P63 (Used as a port) P20-P22, P24, P64-P67, P70-P72, P84, P87, P90-P93, P95, PA6, PA7, PB6, PB7, P95/NMI, RESET X1 P0, P1, P23, P3, P80-P83, P85-P86, P94, PA0-PA5, PB0-PB5 P5-P63 (Used as a port) P20-P22, P24, P64-P67, P70-P72, P84, P87, P90-P93, P95, PA6, PA7, PB6, PB7, P95/NMI, RESET X1 Symbol Conditions Min. Typ.
(Note 1)
Max.
Unit
DVCC15 DVCC3 Input clock = 4 to 7 MHz fsys = 32 to 56 MHz
1.35 3.0 3.0
1.65 3.6 3.6 V
AVCCn VIL
3.0 V  DVCC3  3.6 V
0.3 DVCC3
Low-level input voltage
VIL1
3.0 V  AVCCn (n=0, 1)  3.6 V -0.3 3.0 V  DVCC3  3.6 V 3.0 V  AVCCn (n=0, 1)  3.6 V
0.3 AVCCn V 0.2 DVCC3 (0.2 AVCCn)
VIL2 VIL3 VIH
1.35 V  CVCC15  1.65 V 3.0 V  DVCC3  3.6 V 0.7 DVCC3
0.1 CVCC15 DVCC3
High-level input voltage
VIH1
3.0 V  AVCCn (n=0, 1)  3.6 V
0.7 AVCCn
AVCCn V
VIH2
3.0 V  DVCC3  3.6 V 3.0 V  AVCCn (n=0, 1)  3.6 V
0.8 DVCC3 (0.8 AVCCn)
DVCC3 (AVCCn)
VIH3
1.35 V  CVCC15  1.65 V
0.9 CVCC15
CVCC15
Note 1:
Recommended operating conditions are usage conditions recommended for proper operation of the device maintaining an expected level of quality. The equipment manufacturer should design so that no recommended operating condition is exceeded with respect to supply voltage, operating temperature range, AC/DC specifications, etc. Using the device under conditions beyond those listed above may cause the device to malfunction. No maximum absolute rating as well as recommended operating condition must ever be exceeded. Since AVCCn is also used as the power supply for Ports 5 to 7, it should be connected to a power source even if the AD converter is not used. Unless otherwise specified, the values specified for ports also apply to functions assigned to each port.
Note 2: Note 3:
Note 4:
TMP19A71
19-3
TMP19A71
Flash-Version Product
Ta  -40 to 85  Parameter Supply voltage DVCC2FVCC2CVCC2 DVCC3FVCC3 CVSSDVSSFVSS AVSS0V P0, P1, P23, P3, P80-P83, P85, P86, P94, PA0-PA5, PB0-PB5 P5-P63 (Used as a port) P20-P22, P24, P64-P67, P70-P72, P84, P87, P90-P93, P95, PA6, PA7, PB6, PB7, P95/NMI, RESET X1 P0, P1, P23, P3, P80-P83, P85, P86, P94, PA0-PA5, PB0-PB5 P5-P63 (Used as a port) P20-P22, P24, P64-P67, P70-P72, P84, P87, P90-P93, P95, PA6, PA7, PB6, PB7, P95/NMI, RESET X1 Symbol Conditions Min. Typ.
(Note 1)
Max.
Unit
DVCC2 DVCC3 Input clock = 4 to 7 MHz fsys = 32 to 56 MHz
2.3
2.7 V
3.0
3.6
AVCCn VIL
3.0
3.6
3.0 V  DVCC3  3.6 V
0.3 DVCC3
Low-level input voltage
VIL1
3.0 V  AVCCn (n=0, 1)  3.6 V -0.3 3.0V  DVCC3  3.6 V 3.0 V  AVCCn (n=0, 1)  3.6 V
0.3 AVCCn V 0.2 DVCC3 (0.2 AVCCn)
VIL2 VIL3 VIH
2.3 V  CVCC2  2.7 V
0.1 CVCC2
3.0 V  DVCC3  3.6 V
0.7 DVCC3
DVCC3
High-level input voltage
VIH1
3.0 V  AVCCn (n=0, 1)  3.6 V
0.7 AVCCn
AVCCn V
VIH2
3.0 V  DVCC3  3.6 V 3.0 V  AVCCn (n=0, 1)  3.6 V
0.8 DVCC3 (0.8 AVCCn)
DVCC3 (AVCCn)
VIH3
2.3 V  CVCC2  2.7 V
0.9 CVCC2
CVCC2
Note 1:
Recommended operating conditions are usage conditions recommended for proper operation of the device maintaining an expected level of quality. The equipment manufacturer should design so that no recommended operating condition is exceeded with respect to supply voltage, operating temperature range, AC/DC specifications, etc. Using the device under conditions beyond those listed above may cause the device to malfunction. No maximum absolute rating as well as recommended operating condition must ever be exceeded. Since AVCCn is also used as the power supply for Ports 5 to 7, it should be connected to a power source even if the AD converter is not used. Unless otherwise specified, the values specified for ports also apply to functions assigned to each port.
Note 2: Note 3:
Note 4:
TMP19A71
19-4
TMP19A71
19.3 DC Electrical Characteristics (1/2) Mask-Version Product
Parameter Low drive capability High drive capability Low drive capability High drive capability Ta  -40 to 85  Symbol Conditions Min. Typ.
(Note1)
Max.
Unit
Low-level output (Note 2) voltage
IOL = 0.5 mA VOL IOL = 2 mA IOL =10 mA VOH ILI ILO IOH = -0.5 mA IOH = -2 mA
DVCC3  3.0 V DVCC3  3.0 V DVCC3  3.0 V DVCC3  3.0 V 2.4 DVCC3  3.0 V 0.02 0.05
0.4 1.0
V
High-level output (Note 2) voltage Input leakage current
0.0  VIN  DVCC3 0.0  VIN  AVCCn (n=0, 1) 0.2  VIN  DVCC3-0.2 0.2  VIN  AVCCn-0.2 (N=0, 1)
 
5 A 10
Output leakage current Hysteresis (Schmitt width) P20-P22, P24, P64-P67, P70-P72, P84, P87, P90-P93, P95, PA6, A7, PB6, PB7, P95/NMI, RESET Pull-up resistor Pin capacitance (excluding power supply pins) Note 1: Note 2:
VIN
3.0VDVCC33.6V 3.0 V  AVCCn (n=0, 1)  3.6 V
0.4
0.9
1.6
V
PUP CIO
DVCC3 = 3.0 V to 3.6 V fc = 1 MHz
40
100
185 10
k pF
Ta = 25, DVCC3 = 3.3 V, DVCC15 = 1.5V and AVCCn = 3.3 V, unless otherwise noted. The drive capability can be set to low or high in the PnDSSR register for each port. Ta -40 to 85  Symbol Conditions Min. Typ.
(Note 1)
Flash-Version Product
Parameter
Low drive
Max.
Unit
Low-level output (Note 2) voltage
capability High drive capability Low drive
IOL = 0.5mA VOL IOL = 2mA IOL = 10mA VOH ILI ILO IOH = -0.5mA IOH = -2mA
DVCC3  3.0V DVCC3  3.0V DVCC3  3.0V DVCC3  3.0V 2.4 DVCC3  3.0V 0.02 0.05
0.4 1.0
V
High-level output (Note 2) voltage Input leakage current
capability High drive capability
0.0  VIN DVCC3 0.0  VIN AVCCn (n=0, 1) 0.2VINDVCC3-0.2 0.2  VIN AVCCn-0.2 (n=0, 1)
5 A  10
Output leakage current Hysteresis (Schmitt width) P20-P22, P24, P64-P67, P70-P72, P84, P87, P90-P93, P95, PA6, PA7, PB6, PB7, P95/NMI, RESET Pull-up resistor Pin capacitance (excluding power supply pins) Note 1: Note 2:
VIN
3.0V  DVCC3  3.6 V 3.0 V  AVCCn (n=0, 1)  3.6 V
0.4
0.9
1.6
V
PUP CIO
DVCC3 = 3.0 V to 3.6 V fc = 1 MHz
40
100
185 10
k pF
Ta=25, DVCC3=3.3V, DVCC2=2.5V and AVCCn=3.3V, unless otherwise noted. The drive capability can be set to low or high in the PnDSSR register for each port.
TMP19A71
19-5
TMP19A71
19.4 DC Electrical Characteristics (2/2) Mask-Version Product
DVCC15  CVCC151.35 V to 1.65 V, DVCC3  3.0 V to 3.6 V, AVCCn  3.0 V to 3.6 V, Ta  -40 to 85 (n0, 1) Parameter Symbol ICCN15 ICCD ICCH ICCSt fsys=56 MHz (Input clock = 7 MHz, PLL x16, gear ratio = 1/2) DVCC15=CVCC15=1.35 to 1.65V DVCC3= 3.0 to 3.6V AVCCn=3.0 to 3.6V Conditions Min. Typ.
(Note 1)
Max.
(Note 2)
Unit
NORMAL 1.5V IDLE (Doze) IDLE (Halt) STOP
(Note 3)
70 45 45 3
90 60 60 5 mA mA
Note 1: Note 2: Note 3:
Ta=25, DVCC3=3.3V, DVCC15=1.5V and AVCCn=3.3V, unless otherwise noted. Max. values are theoretical maximum values that should not be exceeded under the worst possible conditions. ICCN (Typ) measurement conditions: Run an arithemetic program provided by Toshiba with all internal peripheral active.
Flash-Version Product
DVCC2  CVCC2  2.3 V to 2.7 V, DVCC3  3.0 V to 3.6 V, AVCCn  3.0 V to 3.6 V, Ta  -40 to 85 (n  0, 1)
Parameter
Symbol ICCN2 ICCD2 ICCH2 ICCSt fsys = 56 MHz
Conditions
Min.
Typ.
(Note 1)
Max.
(Note 2)
Unit
NORMAL 2.5V IDLE (Doze) IDLE (Halt) STOP
(Note 3)
212 130 120 11
285 200 190 1000 A mA
(Input clock = 7 MHz, PLL x16, gear ratio = 1/2) DVCC2 = CVCC2 = 2.3 to 2.7 V DVCC3 = 3.0 to 3.6 V AVCCn = 3.0 to 3.6 V
Note 1: Note 2: Note 3:
Ta=25, DVCC3=3.3V, DVCC2=2.5V and AVCCn=3.3V, unless otherwise noted. Max. values are theoretical maximum values that should not be exceeded under the worst possible conditions. ICCN (Typ) measurement conditions: Run an arithmetic program provided by Toshiba with all internal peripherals acitve.
TMP19A71
19-6
TMP19A71
19.5 10-Bit AD Conversion Characteristics Mask-Version Product
DVCC15 = CVCC15 = 1.35 to 1.65 V, DVCC3 = 3.0 to 3.6 V, AVCCn = VREFH = 3.0 to 3.6 V, AVSS = DVSS = VREFL = 0 V, Ta  -40 to 85 
Parameter Analog reference voltage (+) Analog input voltage Integral nonlinearity error
(Note 6) (Note 3)
Symbol VREFH VAIN
Conditions
Min 3.0 AVSS
Typ
Max 3.6 AVCCn
Unit V V LSB
   
Differential nonlinearity error
AVCCn = VREFH = 3.0 to 3.6 V DVSS = AVSS AVCCn load capacitance  10 F VREFH load capacitance  10 F Conversion time  2.36 s
 1.5
3
1
2
LSB
Offset error
4
7
LSB
Gain error
2
4
LSB
Relative error
(Note 5)
 
4
8
LSB
Total error
4
7
LSB
Note 1: 1 LSB = (VREFH-VREFL)/1024 [V] Note 2: The supply current flowing through the AVCCn pin is included in the digital supply current parameter (ICC). Note 3: The VREFHn pin is shared with the AVCCn pin. Note 4: The above characteristics apply when the ADC input pins are not used for other functions. Note 5: Indicates the difference between the minimum and maximum conversion errors. Note 6: Indicates a value after offset and gain errors have been adjusted.
TMP19A71
19-7
TMP19A71
Flash-Version Product
DVCC2 = FVCC2 = CVCC2 = 2.5 0.2 V, DVCC3 = 3.3 0.3 V, AVCCn = VREFH = 3.0 to 3.6 V, AVSS = DVSS = VREFL = 0 V, Ta  -40 to 85 
Parameter Analog reference voltage (+) Analog input voltage Integral nonlinearity error
(Note 6) (Note 3)
Symbol VREFH VAIN
Condition
Min 3.0 AVSS
Typ
Max 3.6 AVCCn
Unit V V LSB
   
Differential nonlinearity error
AVCCn = VREFH = 3.0 to 3.6V DVSS = AVSS AVCCn load capacitance 10F VREFH load capacitance 10F Conversion time2.36s
 1.5
3
1
2
LSB
Offset error
4
7
LSB
Gain error
2
4
LSB
Relative error
(Note 6)
 
4
8
LSB
Total error
4
7
LSB
Note 1: 1 LSB = (VREFH-VREFL)/1024 [V] Note 2: The supply current flowing through the AVCCn pin is included in the digital supply current parameter (ICC). Note 3: The VREFHn pin is shared with the AVCCn pin. Note 4: The above characteristics apply when the ADC input pins are not used for other functions. Note 5: Indicates the difference between the minimum and maximum conversion errors. Note 6: Indicates a value after offset and gain errors have been adjusted.
TMP19A71
19-8
TMP19A71
19.6 SIO Timings Mask-Version Product
(1) I/O Interface Mode (DVCC3 = 3.3 0.3 V, DVCC15 = 1.5 0.15 V, Ta = -40 to 85 C) The letter x in the tables below represents the system clock fsys period which depends on the clock gear setting. * SCLK Input mode (SIO2)
Parameter SCLK period TxD data to SCLK rise or fall * TxD data hold after SCLK rise or fall* RxD data valid to SCLK rise or fall* RxD data hold after SCLK rise or fall* Symbol tSCY tOSS tOHS tSRD tHSR Equation Min 16x (tSCY/2) - 4x - 23 (tSCY/2) + 2x 2x + 8 0 Max 56 MHz Min 286 50 179 44 0 Max ns ns ns ns ns Unit
*) SCLK rise or fall: Measured relative to the programmed active edge of SCLK.
* SCLK Output mode (SIO2)
Parameter SCLK period (programmable) TxD data to SCLK rise TxD data hold after SCLK rise RxD data valid to SCLK rise RxD data hold after SCLK rise Symbol tSCY tOSS tOHS tSRD tHSR Equation Min 16x (tSCY/2) - 15 (tSCY/2) - 15 2X + 23 0 Max 56 MHz Min 286 128 128 59 0 Max ns ns ns ns ns Unit
SCLK Output Mode Active-High SCLK Input Mode Active-Low Output Data TxD
tSCY
tOSS 0 tSRD 1
tOHS 2 tHSR 1 Valid 2 Valid 3 Valid 3
Input Data RxD
0 Valid
Note 1: Output level measurement conditions: High 0.8DVCC3 [V] / Low 0.2DVCC3 [V], CL=30 pF Note 2: Input level measurement conditions: High 0.7DVCC3 [V] / Low 0.2DVCC3 [V]
TMP19A71
19-9
TMP19A71
Flash-Version Product
(1) I/O Interface mode (DVCC3 = 3.3 0.3 V, DVCC2 = 2.5 0.2 V, Ta = -40 to 85 C) The letter x in the tables below represents the system clock fsys period which depends on the clock gear setting. * SCLK Input mode (SIO2)
Parameter SCLK period TxD data to SCLK rise or fall* TxD data hold after SCLK rise or fall* RxD data valid to SCLK rise or fall* RxD data hold after SCLK rise or fall* Symbol tSCY tOSS tOHS tSRD tHSR Equation Min 16x (tSCY/2) - 4x - 23 (tSCY/2) + 2x 2x + 8 0 Max 56 MHz Min 286 50 179 44 0 Max ns ns ns ns ns Unit
*) SCLK rise or fall: Measured relative to the programmed active edge of SCLK
* SCLK Output mode (SIO2)
Parameter SCLK period (programmable) TxD data to SCLK rise TxD data hold after SCLK rise RxD data valid to SCLK rise RxD data hold after SCLK rise Symbol tSCY tOSS tOHS tSRD tHSR Equation Min 16x (tSCY/2) - 15 (tSCY/2) - 15 2X + 23 0 Max 56 MHz Min 286 128 128 59 0 Max ns ns ns ns ns Unit
SCLK Output Mode Active-High SCLK Input Mode Active-Low Output Data TxD
tSCY
tOSS 0 tSRD 1
tOHS 2 tHSR 1 Valid 2 Valid 3 Valid 3
Input Data RxD
0 Valid
Note 1: Output level measurement conditions: High 0.8DVCC3 [V] / Low 0.2DVCC3 [V], CL=30 pF Note 2: Input level measurement conditions: High 0.7DVCC3 [V] / Low 0.2DVCC3 [V]
TMP19A71
19-10
TMP19A71
19.7 Event Counter Mask-Version and Flash-Version Products
The letter x in the table below represents the IMCLK period.
Parameter Clock low-level pulse width Clock high-level pulse width Symbol Min tVCKL tVCKH X + 100 X + 100 Equation Max IMCLK = 28 MHz Min 136 136 Max ns ns Unit
19.8 Capture Mask-Version and Flash-Version Products
The letter x in the table below represents the IMCLK period.
Parameter Low-level pulse width High-level pulse width Symbol Min tCPL tCPH X + 100 X + 100 Equation Max IMCLK = 28 MHz Min 136 136 Max ns ns Unit
19.9 Interrupts (INTC) Mask-Version and Flash-Version Products
The letter x in the table below represents the system clock fsys period.
Parameter INT0 to A low-level pulse width INT0 to A high-level pulse width Symbol Min tINTAL tINTAH X + 100 X + 100 Equation Max fsys = 56 MHz Min 118 118 Max ns ns Unit
19.10 Interrupts (NMI, STOP wakeup interrupt) Mask-Version and Flash-Version Products
Parameter NMI, INT0 to 4 low-level pulse width INT0 to 4 high-level pulse width Symbol tINTBL tINTBH Equation Min 100 100 Max fsys = 56 MHz Min 100 100 Max ns ns Unit
TMP19A71
19-11
TMP19A71
19.11 ADTRG Input Mask-Version and Flash-Version Products
The letter x in the table below represents the IMCLK period.
Parameter ADTRG low-level pulse width ADTRG high-level pulse width Symbol Min tadL tadh X + 100 X + 100 Equation Max IMCLK = 28 MHz Min 136 136 Max ns ns Unit
TMP19A71
19-12
TMP19A71
20. Package Dimensions
20.1 P-LQFP-1414-0.50F
TMP19A71
20-1
TMP19A71
20.2
P-QFP-1420-0.65A
TMP19A71
20-2