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High Performance Current Mode PWM Controller with Complementary Output, Programmable Delay
POWER MANAGEMENT Description
The SC4810B/E is a 16 pin BICMOS primary side PWM controller for use in Isolated DC-DC and off-line switching power supplies. It is a highly integrated solution, requiring few external components. It features a high frequency of operation, accurately programmable maximum duty cycle, current mode control, line voltage monitoring, supply UVLO, low start-up current, and programmable soft start with user accessible reference. It operates in a fixed frequency, highly desirable for Telecom applications. The output for switch is complementary to each other with programmable delay between each transition. The active technique allows single ended converters beyond 50% duty cycle and greater flux swing for the power transformer while reducing voltage stresses on the switches. The separate sync pin simplifies synchronization to an external clock. Feeding the oscillator of one device to the sync of another forces biphase operation which reduces input ripple and filter size. The SC4810B/E has a turn-on voltage threshold of 7V. In the SC4810B, OUT2 is inverted to drive the N-MOSFET. In the SC4810E, OUT2 is non-inverted to drive the P-MOSFET. These devices are available in a TSSOP-16 or MLPQ-16 lead package.
SC4810B/E
Features
Operation to 1MHz Accurate programmable maximum duty cycle Line voltage monitoring External frequency synchronization Bi-phase mode of operation for low ripple Independent programmable delays Hiccup mode current limit Under 250A start-up current Programmable maximum volt-second clamp Accessible reference voltage VDD undervoltage lockout -40C to 105C operating temperature 16 lead TSSOP or MLPQ lead free packages. Both fully WEEE and RoHS compliant
Applications
Telecom equipment and power supplies Networking power supplies Power over LAN applications Industrial power supplies Isolated power supplies VoIP phones
Typical Application Circuit
R1 C1 Q1 D4 C3 R2 C4 C2 D1 T1 D3 L1
D2
Vout
+48V
C5
R3
U1 SC1302A C8 6 1 R7 2 7
C7 T2
C6
Q2 R4 D5
R5
C9
R6 U2 2 LUVLO VDD 1
C10
6 3
RAMP SY NC RCT DMAX
OUT2 OUT1 CS FB VREF SS
13 15 10 11 16 9
4
5
R9
Q3
R10
4 5 R12 7
R11
8
SC4810
3
C11 R13 6 C12 5
U3 1 2 7 R8
DELAY 1 DELAY 2
PGND
C13 Q4 R17
R14 8 R18 R19
R15 C14 U4 SC431L R16
12
GND
C15
R20 R22 R21
R23
C16
Revision: July 27, 2006
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SC4810B/E
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability.
Parameter Supply Voltage Supply Current LUVLO SS, DMAX, RCT, FB, CS, RAMP, SYNC Current VREF Current LUVLO Storage Temperature Range Junction Temperature Range Lead Temperature (Soldering) 10 Sec. Peak IR Reflow Temperature 20 - 40 Sec.
Symbol V DD IDD VLUVLO
Maximum 19 25 10 -0.3V to VREF + 0.3V
Units V mA V V mA mA C C C C
IREF ILUVLO TSTG TJ TLEAD TPKG
15 -1 -65 to +150 -40 to +150 300 260
Electrical Characteristics
Unless specified: VDD = 12V, CSS = 1nF, FOSC = 420kHz, RT = 10k, CT = 220pF, DMAX = 2V, RDELAY = 75k, TA = TJ = -40C to 105C
Parameter Supply Section Supply Voltage IDD IDD Shutdown Ramp Section Ramp Clamp Threshold Voltage UVLO Section (B/E version) Start Threshold Hysteresis
Test Conditions
Min
Typ
Max
Unit
15 VDD = 15V, NO LOAD S S = 0V 3.5 100 4.5 250
V mA A
3
V
8
8.4 2
8.8
V V
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SC4810B/E
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: VDD = 12V, CSS = 1nF, FOSC = 420kHz, RT = 10k, CT = 220pF, DMAX = 2V, RDELAY = 75k, TA = TJ = -40C to 105C
Parameter VREF Section VREF (B/E version) Line Under Voltage Lockout Start Threshold Hysteresis Input Bias Current(1) Comparator Section CS Input Current(1) PWM to OUT Propagation Delay (No Load)(1) Current Limit Section Current Limit Threshold ILIM to OUT Propagation Delay(1) Soft Start Section ISS Shutdown Threshold Oscillator Section Frequency Range
(2)
Test Conditions
Min
Typ
Max
Unit
0 - 5mA
4.85
5
5.15
V
2.91
3 150
3.09
V mV nA
LUVLO = 3.2V
-100
-200 75
nA ns
590
625 75
660
mV ns
V S S = 0V
-2.5 500
-5
-7.5
A mV
50 3.00 0.05 DMAX = 2.8V, OUT1 DMAX = 1.25V, OUT1 380 85 29 420
1100
kHz V V % %
RCT Peak Voltage RCT Valley Voltage Maximum Duty Cycle Maximum Duty Cycle Frequency Sync/CLOCK Clock SYNC Threshold Minimum Sync Input Pulse Width(1) Positive Edge Triggered FSYNC > Fosc 2
460
kHz
V 50 ns
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SC4810B/E
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: VDD = 12V, CSS = 1nF, FOSC = 420kHz, RT = 10k, CT = 220pF, DMAX = 2V, RDELAY = 75k, TA = TJ = -40C to 105C
Parameter Output Section (OUT1 and OUT2) Output VSAT Low Output VSAT High Rise Time(1) Fall Time(1) Program Delay Section OUT1 Fall to OUT2 Rise (SC4810B) OUT2 Fall to OUT1 Rise (SC4810B) OUT1 Fall to OUT2 Fall (SC4810E) OUT2 Rise to OUT1 Rise (SC4810E)
Test Conditions
Min
Typ
Max
Unit
IOUT = 5mA sinking IOUT = 5mA sourcing COUT = 20pF COUT = 20pF VREF - 0.6 10 10
500
mV V ns ns
120 140 120 140
ns ns ns ns
Notes: (1) Guaranteed by design. (2) Guaranteed by characterization. (3) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC4810B/E
POWER MANAGEMENT Pin Configurations
TOP VIEW
VDD LUVLO SYNC RCT DMAX RAMP DELAY 1 DELAY 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VREF OUT1 PGND OUT2 GND FB CS SS
Ordering Information
Part Number(2) SC4810BITSTRT SC4810EITSTRT SC4810BIMLTRT SC4810EIMLTRT Package(1) TSSOP-16 -40C to 105C MLPQ-16 Temp. Range (TJ)
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices for TSSOP and 3000 parts for MLP package. (2) Lead free product. This product is fully WEEE and RoHS compliant.
(16 Pin TSSOP )
TOP VIEW
(16 Pin MLPQ)
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SC4810B/E
POWER MANAGEMENT Pin Descriptions
Pin # TSSOP 1 Pin # MLPQ 15 Pin Name VD D Pin Function The power input connection for this device. This pin is shunt regulated at 17.5V which is sufficiently below the voltage rating of the DMOS output driver stage. VDD should be bypassed with a 1F ceramic capacitor. Line undervoltage lock out pin. An external resistive divider will program the undervoltage lock out level. During the LUVLO, the Driver OUT1 is disabled and the softstart is reset. OUT2 continues with a fixed on time of DELAY 1 + DELAY2 approximately. SYNC is a positive edge triggered input with a threshold set to 2.1V. In the Bi-Phase operation mode the SYNC pin should be connected to the CT (Timing Capacitor) of the second controller. This will force a out of phase operation. In a single controller operation, SYNC could be grounded or connected to an external synchronization clock with a frequency higher than the on-board oscillator frequency. The external OSC frequency should be 30% greater for guaranteed SYNC operation. The oscillator frequency is configured by connecting resistor RT from VREF to RCT and capacitor CT from RCT to ground. Using the equation below values for RT and CT can be selected to provide the desired OUT frequency.
F= 1 V - (RT + 1k ) * CT * ln 1 - P-K VREF
2
16
LUVLO
3
1
SYNC
4
2
RCT
where VP-K = RCT peak voltage 5 3 DMAX
Duty cycle up to 95% can be programmed via R18 and R12 (the resistor divider from Vref in the Application Circuit). When DMAX pin is taken above 3V, 100% duty cycle is achieved. A resistor from the RAMP to the input voltage and a capacitor from the RAMP to GND forms the ramp signal of maximum allowable volt-second product. The RAMP is discharged to GND when OUT1 is low and allowed to charge when OUT1 is high. A volt-second comparator compares the ramp signal to 3V to limit the maximum allowable volt-second product: Volt-second product clamp = 3 * Rramp * Cramp. A resistor from these pins to GND programs the non-overlap delay time between OUT1 and OUT2. A resistor from these pins to GND programs the non-overlap delay time between OUT2 and OUT1.
6
4
RAMP
7 8
5 6
DELAY 1 DELAY 2
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SC4810B/E
POWER MANAGEMENT Pin Descriptions (Cont.)
Pin # TSSOP 9 Pin # MLPQ 7 Pin Name SS Pin Function This pin serves two functions. The soft start timing capacitor connects to SS and is charged by an internal 5A current source. Under normal soft start SS is discharged to less than 0.65V and then ramps positive to 1V during which time the OUT1 is held low. As SS charges from 1V to 2.5V, soft start is implemented by an increasing output duty cycle. If SS is taken below 0.5V, the output driver is inhibited and held low. The user accessible 4V (A and D) or 5V (B, C and E) voltage reference also goes low and IDD = 100A. Current sense input is provided via the CS pin. The current sense input from a sense resistor provides current feedback to the PWM comparator and current limit signal to terminate the PWM pulse. When a pulse peak voltage provided at this pin exceeds 600mV, a soft-restart sequence will follow. Slope compensation is derived from the rising voltage at the timing capacitor and can be buffered with an external small signal PNP transistor. This pin is used to generate a reset signal when compared to CS for the PWM comparator with an offset voltage of 600mV and 1/2 attenuation. The feedback analog signal from the output of an error amplifier or an opto-coupler will be connected to this pin to provide regulation. Signal ground for all functions. This pin is the logic level drive output to the external MOSFET driver circuit (similar to SC1302) for the complementary switch. Ground connection for the gate drivers. Connect PGND and GND at a single point. This pin is the logic level drive output to the external MOSFET driver circuit (similar to SC1302) for the main switch. The 5V reference output. This reference is buffered and is available on the VREF pin. VREF should be bypassed with a 0.47 - 1.0F ceramic capacitor.
10
8
CS
11
9
FB
12 13 14 15 16 N/A
10 11 12 13 14
GND OUT2 PGND OUT1 VREF
THERMAL Pad for heatsinking purposes only. Connect to ground plane using multiple vias. Not PAD connected internally.
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SC4810B/E
POWER MANAGEMENT Block Diagram
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SC4810B/E
POWER MANAGEMENT Application Information
Introduction Circuit Description The SC4810B/E is a 16 pin BICMOS peak current mode The schematic of the active clamp forward converter is controlled PWM controller for isolated DC-DC and off- illustrated in Figure. 1 below. T4 is the power transformer. line switching power supplies. It features a high switching M17 is the N-channel main switching MOSFET and M15 frequency of operation, programmable limits for both is the auxiliary N-channel MOSFET. C35 is the reset power transformer voltage-second product and maximum capacitor for resetting the power transformer's core. M14 PWM duty cycle, line under-voltage lockout, auxiliary switch and M16 construct the synchronous rectification circuit. activation complementary to main power switch drive, L2 and C32 and C33 construct the low-pass output programmable leading-edge delay time between filtering circuit. T6 is the current sensing transformer. R62 activation of each switch, multiple protection features is the reset resistor for resetting the magnetic core of with programmable cycle -by-cycle current limit and hiccup the current sensing transformer. D18 is the rectifying mode over-current protection plus soft-restart. It diode. R63 is the current sensing resistor. R60 and C41 operates in a fixed frequency programmed by external construct the low-pass filtering circuit for the sensed components. The separate sync pin simplifies current signal. The primary bias circuit consists of R55, synchronization to an external clock. Feeding the oscillator R58, D17, Q8, C40, C31, D14 and R51. R55 and R58 of one device to the sync of another forces biphase construct a voltage divider, which limits the bias voltage operation which reduces input ripple and input and output to 6.9V until the line voltage reach 36V. D17 is a zener filter size. diode that limits the bias voltage to under 8V. R51, D14 The SC4810 can be applied in an active clamp forward and C31 construct the peak charge circuit. The peak topology with the input voltage ranging from 36V to 72V. charge circuit will provide bias to the PWM IC U9 (SC4810) This topology allows the converter to achieve an efficiency and the driver U8 (SC1302A) after the converter starts of 92.4% at normal input voltage of 48V. Figure 1: Active Clamp Forward Converter
T4 D14 1N4148WS C31 0.1uF R50 10 M 14 1 11 7 6 8 9 5.11 Si4842DY 1N4148WS D13
3.3V/30A
R51 5.11
5 6 7 8
48V
2 C35 C34 1u,100V 3300pF 8 7 6 5 1 M15 2 Si4488DY 3 4 R53 D15 1N4148WS R54 R55 30K Q8 FZT458 C37 0.1uF D17 open C40 10uF R61 1.1M 20K C36 0.1uF 10K
1.3uH L2
100uF C32 C33 680uF
4
10K R52
T 5 PE68386
8 7 6 5
M 16 Si4842DY 1 2 3 4
4 3 2 1
Q7 FZT 458 R56 10K R57
6
4
1
3
R58 8K
0.1uF C38 1K 1N4148WS D18
5.11K D16 open
C39 0.1uF
R59 10 D19 1N5819HW
P8208T 8 T6 1 R62 10K
R60
7
3
R63 6.8
330pF C41 C42 open
M17 SC1302A U8 Si4488DY
6 1
R64 165k
C43 100pF
R65 100K U9
5 6 7 8
R66
R67 R68 1K 50
2
LUVLO
VDD
1
2
7
open
C44 220pF
6
RAMP
OUT2
13 4 15 D20 1N5819HW 5 R69 10K
3 R71
SYNC
OUT1
4 3 2 1
C45 open R73 R72 5.11K C47 0.01uF
8
RCT
SC4810
CS
3
10K
4
10
R70 open
5 R74 4.3K
DM AX
FB
11 3.01K 16 U10 U11 MOC207 0.1uF C48 6 5 2 1 SC431
C46 open
100K R75
7
DELAY1
VREF
Q9 FM MT718 R77 18K R78 5.6K R79 100K
PGND
GND
C49 180pF
8
DELAY2
SS
9
R76 3.01K
R80 1.47K R81 4.7K R82 5.11K C51 0.01uF
14
12
1000pF C50
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SC4810B/E
POWER MANAGEMENT Application Information (Cont.)
up so that the total power loss is less. D19, R59, C37, T5, C36, D15 and R53 construct the driving circuit for the auxiliary reset switch M15. The secondary side bias circuit composed of R50, D13 and C38 is regulated to about 7.5V via a linear regulator composed of R57, Q7 D16 and C39. The feedback of the converter is composed of U10 (SC431), U11, R73, C47, C45, R72, R76, R70 and C46. SC4810 is the PWM controller which processes the voltage feedback plus current signal and generates driving signals to drive the main switch and auxiliary reset switch. SC1302A is a dual driver IC which is capable of sourcing 3A peak current. To obtain the best performance, SC1302A is adopted to drive M17 and M15 in the Semtech application circuits. SC4810 features dual complementary driving signals. And SC4810 also provides adjustable leading-edge delay time for the driving signals, which helps to achieve zero-voltage switching in active clamp forward converter. R75 and R79 are the two resistors available to adjust the delay for the complementary driving. C50 is the soft-start capacitor. R61 and R65 construct the voltage divider for the line under voltage lock out protection. R64 and C44 construct the circuit for the programmable power transformer voltage-second production protection limits. This special protection function provide the voltage-second balance for the power transformer under different input line conditions. R78 and R74 also provide an extra maximum duty cycle protection for the power converter. The clock signal is generated by C49 and R77. When VDD of SC4810 hits the threshold voltage, VREF jumps up to 5.0V. VREF charges C49 via R77. C49 will be discharged via an internal FET whenever the voltage on C49 reaches 3.0V. The selection of C49 and R77 is described in the "Set Clock Frequency" section on the following page. Q9 works as a buffer between the clock signal and the slope compensation signal to minimize the interference on the system clock signal. R80 is a pull-up resistor tied to VREF. Since SYNC function is not utilized, SYNC pin is grounded via R71. Power Transformer Design A power transformer with the turns ratio of 6 to 1 was designed for this application. With the turns ratio of 6:1, the duty ratio under different input line and load conditions were calculated to verify feasibility.
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A self-driven configuration was adopted on the secondary side for driving the synchronous rectification FETs. One extra winding (Pin8~Pin9) was added at the bottom side of the power transformer's secondary side to drive the freewheeling FET. The forward FET was driven directly from the top of the power winding. Primary side auxiliary winding was used to generate primary side bias to improve the converter's efficiency. The final configuration of the power transformer is illustrated as Fig. 2.
2 6T(PRI) 4 1 2T(PRI AUX) 6
11 1T(SEC) 10 9 1T(SEC AUX) 8 1T(SEC) 7
Fig.2 Illustration of the power transformer PA0944G (PUSLE ENGINEERING)
Power MOSFET Selection The selection of the switching power MOSFET is based on the peak & RMS current rating, the total gate charge, Rds and drain to source voltage rating. In this application, SI4842 was chosen for the secondary side synchronous rectification MOSFET. And SI4488 was chosen for the primary side main switching and reset MOSFET. Output Filter Design The output filtering circuit consists of the output inductor and output capacitors. The design of the output capacitor usually depends on the specification of the requirement of the output ripple. Given the worst case output ripple requirement and peak to peak output current ripple plus the duty ratio under the different line and load condition, output capacitance is calculated to meet the output ripple requirement. After all, ESR and ESL of the output capacitor under certain switching frequency should also be considered during the calculation. The value of the output inductance would affect the peak to peak value of the output current, which would also influence the
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SC4810B/E
POWER MANAGEMENT Application Information (Cont.)
output voltage ripple. The designer needs to take the output inductance and output capacitance and the ESL and ESR of the output capacitor into consideration during the design. For this application, one Panasonic power choke output inductor was selected and three 6.3V, 100uF TDK ceramic capacitors were adopted in the design. Selection of the Current Sensing Resistor The selection of the current sensing resistor is based on the over-current protection triggering point. SC4810 employs a Hiccup mode over-current protection with an overcurrent threshold of 600mV. A voltage signal above 600mV on the CS pin will trigger hiccup mode overcurrent protection. Suppose the over-current protection setpoint is set to be Iov. The threshold voltage of SC4810 is Vthreshold. The turns ratio of the power transformer is Ns/Np. The turns ratio of the current sensing transformer is Ncs:1. Then the Rsense would be calculated as:
VRCT 3V 0V
Fig.4 Voltage Waveform on RCT Pin
VPK
t
As illustrated, the capacitor C is charged via the resistor R from VREF. Whenever the voltage on the RCT pin reaches 3V, the capacitor C will be discharged through an internal FET shorted to ground. When the clock signal circuit is connected as in Fig.3, the frequency of the clock signal is defined, as in equation 2.
F= 1 V - (RT + 1k ) * CT * ln 1 - P-K VREF ........( 2)

R sense =
VThreshold x NP x NCS ......(1) IOV x NS
V REF is the reference voltage of the SC4810, 4V for SC4810A/D and 5V for SC4810B/C/E. In this application, to get 600kHz, C = 180pF, (R + 1k) = 10k ohms and VP-K = 3V. Maximum Duty Ratio Limit SC4810 features maximum duty ratio limitation for extra protection. The maximum duty ratio is determined by the voltage on DMAX pin. As illustrated as in Fig. 5, VDMAX will be compared with VRCT and DMAX is determined by the comparison of the two signals.
Set Clock Frequency The SC4810 uses a pair of resistors and capacitors to generate a triangle signal as the clock signal, as illustrated in Fig. 3.
VRCT RCT VREF
R
C
Fig. 3 Configuration for Clock Signal
The voltage waveform on the RCT pin is illustrated as in Fig. 4.
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SC4810B/E
POWER MANAGEMENT Application Information (Cont.)
Voltage waveform on RAMP pin Clock Signal of SC4810
VRAMP 3V
VRCT 3V VDMAX
0V 0V t t OUT1
Maximum OUT1 of SC4810 DMAX
0V 0V
Fig. 5 Illustration for DMAX
t t
Fig. 6 Illustration of the programmable limits for power transformer voltage-second product
In this application, VDMAX was designed to be 2.8V. So the DMAX = 90%. Limit for Power Transformer Voltage Second Product The SC4810 also features programmable limits for power transformer voltage-second product. As illustrated in Fig. 6 and Fig. 7 RAMP pin is charged up via a resistor R from the input line voltage. The capacitor C will be discharged via an internal FET shorted to ground and the output OUT1 will be pulled low whenever the voltage on RAMP pin hits 3V. By adjusting the values of the resistor R and the value of the capacitor C, the maximum voltage-second product imposed on the power transformer is preset. The maximum voltage-second product limitation helps prevent saturation of the power transformer.
VIN
R
RAMP
C
Fig. 7 Illustration for Maximum voltagesecond product on the power transformer
The selection of the R and C should consider the maximum voltage rating of the main switching FET. In this application, the voltage rating of SI4488 is 150V. Since Vin*D/(1-D) = 150V, D = 0.8 for low line 36V. So to get 80% at low line, R = 165kOhms and C = 220pF were selected using volt-second product equation: 3 * Ramp * Cramp.
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SC4810B/E
POWER MANAGEMENT Application Information (Cont.)
VDD and LUVLO SC4810 features three different input turn-on voltage thresholds, as specified in the Electrical Characteristics on page 2. V starts to regulate when the supply voltage on the VDD pin is above the turn-on voltage threshold. V drops to ground when VDD is lower than the turn-on threshold minus the hysteresis value. The soft start cap remains grounded as long as LUVLO is below the threshold voltage 3V. The soft start cap will be charged up through an internal 5uA current source when LUVLO is above the threshold voltage.
REF REF
Soft Start The soft-start function is implemented by charging the soft-start cap through an internal 5uA current source. Under normal soft-start, the SS pin is discharged below 0.65V and ramps up to 1V, during which time the output driving signals OUT1 and OUT2 are held low. During the time when the SS pin is charged from 1V to 2.5V, softstart is implemented by an increasing output duty ratio. The duty ratio is completely under the control of the feedback after the SS pin is above 2.5V. When the SS pin is pulled down below 0.5V, OUT1 and OUT2 will be held low and the VREF pin will be grounded via an internal FET. Complementary Driving with Programmable Delays The SC4810 features dual driving signals to drive two power switches complementarily. This feature makes the SC4810 suitable for a variety of applications in which dual complimentary driving signals are needed. The SC4810 even provides programmable driving delay as an extra feature for applications such as active-clamp forward topology. The users can program the driving delay by adjusting the resistors tied to pin DELAY1 and pin DELAY2 respectively to achieve the optimum delay for each output. The delay of OUT1 is controlled by the resistor tied to pin DELAY1 and the delay of OUT2 is controlled by the resistor tied to pin DELAY2. For illustration, see Fig. 8.
Over Current Protection The SC4810 provides Hiccup mode over-current protection when the sensed current signals are beyond 0.6V. When the hiccup mode over-current protection is triggered, the soft-start cap will be discharged immediately by an internal grounded FET. When the softstart pin SS is pulled down below 1V, OUT1 and OUT2 will be disabled, and a soft re-start sequence will follow. SC4810 can also be configured to implement cycle-bycycle over-current limit. As illustrated in Fig. 9, cycle-bycycle over-current limitation can be achieved by adjusting the values of R1 and R2 to limit the voltage of FB pin to less than the threshold voltage (0.6Volt) of the hiccup over-current protection, using equations (3) and (4).
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SC4810B/E
POWER MANAGEMENT Application Information (Cont.)
guaranteed synchronization. SYNC pin should be grounded if synchronization is unused. (The patent for the synchronization scheme is pending). The synchronous function is illustrated as in Fig. 10.
R3 Vout FB R4 R2 R5 SC431 GND
0V
Fig.9 Cycle-by-cycle over-current limitation
VREF VBias
R1
Clock Signal of the Master SC4810
VRCT 3V 2.1V
t
OUT1 of the Master SC4810
VFB = 2 * VCS + 1.3 V........( 3) VFB = VREF * R2 ........( 4) R1 + R 2
0V t
Synchronization SC4810 features a special synchronization function which is leading-edge triggered with a threshold set to 2.1V. Applications like multi-phase interleaving can be achieved using the SYNC pin. When the SYNC pin is connected to the RCT pin of the master SC4810, the outputs of the two SC4810's will be out of phase. The frequency of the master SC4810 clock signal should be at least 30% faster than that of the slave SC4810 for the
OUT1 of the Slave SC4810
0V t
Fig. 10 Illustration for Synchronization
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SC4810B/E
POWER MANAGEMENT Applications Information (Cont.)
PCB Layout Guidelines PCB layout is very critical, and the following should be used to insure proper operation of the SC4810. High switching currents are present in applications and their effect on ground plane must be understood and minimized. 1) The high power parts of the circuit should be placed on a board first. A ground plane should be used. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and the main switch FET ground. 2) The loop formed by the Input Capacitor(s) (Cin), the main transformer and the main switch FET must be kept as small as possible. This loop contains all the high fast transient switching current. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically "cleaner" grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3) The connection between FETs and the main transformer should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. 4) The output capacitor(s) (Cout) should be located as close to the load as possible. Fast transient load currents are supplied by Cout only. Connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) A 0.1uF to 1uF ceramic capacitor should be directly connected between VDD and PGND and a 1uF to 4.7uF ceramic capacitor between VREF and PGND. The SC4810 is best placed over a quiet ground plane area. Avoid pulse currents in the Cin and the main switch FET loop flowing in this area. GND should be returned to the ground plane close to the package and close to the ground side of (one of) the VDD supply capacitor(s). Under no circumstances should GND be returned to a ground inside the Cin and the main switch FET loop. This can be achieved by making a star connection between the quiet GND planes that the SC4810 will be connected to and the noisy high current GND planes connected to the FETs. 6) The feed back connection between the error amplifier and the FB pin should be kept as short as possible, and the GND connections should be to the quiet GND used for the SC4810. 7) If an opto-coupler is used for isolation, quiet primary and secondary ground planes should be used. The same precautions should be followed for the primary GND plane as mentioned in item 5. For the secondary GND plane, the GND plane method mentioned in item 4 should be followed. 8) All the noise sensitive components such as VDD bypass capacitor, RCT oscillator resistor/capacitor network, DMAX resistive divider, VREF by pass capacitor, delay setting resistors, current sensing circuitry and feedback circuitry should be connected as close as possible to the SC4810. The GND return should be connected to the quiet SC4810 GND plane. 9) The connection from the OUT of the SC4810 should be minimized to avoid any stray inductance. If the layout can not be optimized due to constraints, a small Schottky diode may be connected from the OUT pin to the ground directly at the IC. This will clamp excessive negative voltages at the IC. 10) If the SYNC function is not used, the SYNC pin should be grounded at the SC4810 GND to avoid noise pick up.
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D1 Q1 FMMT618 R54 5.1 R3 5.11K D3 MMSZ4702(15V) TP5 M2 Open 5 6 7 8 5 6 7 8 5 6 7 8 L1 M3 Si4842DY M4 Si4842DY 1.3uH D4 MMSZ4698(11V) C2 0.1uF C1 2.2nF/630V R2 5.1K C52 0.1uF 1N4148WS 1N4148WS
D2
10Vbias
Vout=3.3V/20A
D8 MMSZ4698(11V) C5 0.1uF 6 2 4 3 2 1 4 3 2 1 4 3 2 1 C13 22nF/100V 4 R9 10K M7 SI2308 TP3 10K TP2 Q2 FMMT718 M9 SI2308 TP6 TP14 8 7 6 5 M8 Si4842DY 1 2 3 4 R8 10K R10 8 7 6 5 1 M5 2 Si4488DY 3 4 8 7 6 5 1 2 3 4 4 3 2 1 M6 Open 8 9 C6 680uF C7 100uF C8 100uF C9 100uF 5 6 7 8 TP7 8 7 6 5 M10 Si4842DY 1 2 3 4 11 7
6
POWER MANAGEMENT SC4810B Evaluation Board - Schematic
1N4148WS R57 5.1 1 3 R56 5.1 C18 0.1uF R22 TP9 M11 Open 5 6 7 8 D9 1N5819HW M12 Open 5 6 7 8 M13 Si4488DY 5 6 7 8 M14 SI2308 7 3 10 6 1 C19 1uF 2 1 TP10 4 3 2 1 13 4 15 D11 1N5819HW Q5 FMMT718 8 3 R28 10K 10 11 16 TP8 9 C24 1uF 8 R60 open 7 5 D10 1N4148WS 4 3 2 1 SC1302A 4 3 2 1 U3 2 7 C20 1uF U2 R19 10K R20 8.2(16//16) C53 1uF T2 PE68386 P8208T 8 T3 1 R18 1K C17 180pF
C16 47uF/16V 4
RAMP SY NC RCT SC4810 FB VREF SS DMAX DELAY 1 DELAY 2 GND PGND CS OUT1
LUVLO
6 OUT2
3
VDD
12
14
2006 Semtech Corp.
R1 5.11 T1 PA0944G 10 C4 0.1uF M1 Open D5 1N4148WS 1 TP4 C3 0.1uF Q3 FZT853 R13 open D7 1N4148WS R15 open C15 0.1uF D6 1N4148WS R52 51
R12 5.1K
Vin=48V
C10 1u,100V
C11 1u,100V
C12 1u,100V
R61 200K
Q10 FMMT493
D20 MMSZ4697(10V)
D21
16
U1 MOCD207 1 2 R17 1K 6 R42 2.4K 5 3 4 R63 10K 0.1uF C50 C27 0(short) R44 1.5K U4 SC431 TP13
R21 1.1M
R23 160K
C21 100pF
R24 100K
C22 220pF
R30 10K
4
10Vbias
R16 1K R62 4.75K C23 open R34 1K C14 open R14 open U6 SC431 R40 R25 5.1K 15.8K C26 47nF R32 5.1K R50 open
5
R31 7.5K
7
C25 220pF Q6 FMMT718
R37 100K
8
C51 open
R35 10K
R36 7.5K
R33 100K
R38 1.47K
R43
10K
R29 6.34K
SC4810B/E
TP11
TP12
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SC4810B/E
POWER MANAGEMENT SC4810B Evaluation Board - BOM
Item 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Quantity 1 11 1 3 3 1 1 1 1 2 1 1 1 7 1 2 2 1 1 4 2 3 1 3 1 1 1 4 1 9 1 1 3 Reference C1 C2,C3,C4,C5, C15,C18,C19, C20,C50,C52,C53 C6 C7,C8,C9 C10,C11,C12 C13 C16 C17 C21 C25,C22 C24 C26 C27 D1,D2,D5, D6,D7,D10,D21 D3 D4,D8 D9,D11 D20 L1 M3,M4,M8,M10 M5,M13 M7,M9,M14 Q1 Q2,Q5,Q6 Q3 Q10 R1 R2,R12,R25,R32 R3 R8,R9,R10,R19, R28,R30,R35,R43,R63 R13 R16 R17,R18,R34 Part 2.2nF/630V 0.1uF 680uF 100uF 1u,100V 22nF/100V 47uF/16V 180pF 100pF 220pF 1uF 47nF 0(short) 1N4148WS MMSZ4702(15V) MMSZ4698(11V) SL04 MMSZ4697(10V) 1.3uH Si4842DY Si4488DY SI2308 FMMT618 FMMT718 FZT853 FMMT493 5.11 5.1K 5.11K 10K open 1K 1K Package SM0805 SM0805 SM/CT_7343_12 SM/C_1812 SM/C_1210 SM1206 SM/CT_7343 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SOD123 SOD123 SOD123 SOD123 SOD123 PCC-S1 SO-8 SO-8 SOT-23 SOT-23 SOT-23 SM/SOT223_BCEC SOT-23 SM0805 SM0805 SM0805 SM0805 SM1206 RC0805 SM0805 Vishay On Semi On Semi Vishay On Semi Panasonic Vishay Vishay Vishay Zetex Zetex Zetex Zetex 1N4148WS MMSZ4702T1 MMSZ4698T1 SL04 MMSZ4697T1 ETQPAF1R3EFA Si4842DY Si4488DY SI2308 FMMT618 FMMT718 FZT853 FMMT493 Sanyo TDK TDK TDK Sanyo 4TPB680M C4532X5ROJ107MT C3225X7R2A105K C3216X7R2J223M 16TQC47M Manufacturer TDK P/N C3216X7R2J222K
2006 Semtech Corp.
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SC4810B/E
POWER MANAGEMENT SC4810B Evaluation Board - BOM (Cont.) 1 36 R20
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 53 54 55 56 57 58 59 1 1 1 1 1 2 2 1 1 1 1 1 3 1 1 1 1 1 1 1 1 2 R21 R22 R23 R24 R29 R31,R36 R33,R37 R38 R40 R42 R44 R52 R54,R56,R57 R61 R62 T1 T2 T3 U1 U2 U3 U4,U6
8.2 1.1M 10 160K 100K 6.34K 7.5K 100K 1.47K 15.8K 2.4K 1.5K 51 5.1 200K 4.75K PA0944G PE68386 P8208T MOCD207 SC1302A SC4810 SC431
SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 PA0646 PE68386 P8208 SO-8 MSOP-8 TSSOP16 SOT-23 Pulse Pulse Pulse Fairchild Semtech Semtech Semtech PA0944G PE68386 P8208T MOCD207 SC1302A SC4810 SC431
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5 6 7 8
5 6 7 8
5 6 7 8
D8 MMSZ4698(11V) C5 0.1uF 6 2 4 3 2 1 4 3 2 1 4 3 2 1 M5 IRF6216 C13 22nF/100V 4 R9 10K M7 SI2308 TP3 R8 10K R10 10K TP2 8 7 6 5 M9 SI2308 TP6 D6 M8 Si4842DY 1 2 3 4 TP14 1 2 3 4 8 7 6 5 8 7 6 5 1 2 3 4 4 3 2 1 M6 Open 8 9 C6 680uF C7 100uF C8 100uF 5 6 7 8 11 7
6 1
5 6 7 8
2
1
R23 160K U3 TP10 4 3 2 1 OUT2 4 15 D11 1N5819HW Q5 FMMT718 8 3 R28 10K 10 11 16 TP8 9 1uF C24 8 R60 open 7 5 OUT1 CS FB VREF SS 13 D10 1N4148WS 4 3 2 1 SC1302A 2 7
C21 100pF
R24 100K
C19 1uF 5 6 7 8
RAMP SYNC RCT SC4810 DMAX DELAY1 DELAY2 GND PGND
3
LUVLO
6
VDD
12
14
2006 Semtech Corp.
D1 Q1 FMMT618 R54 5.1 R3 5.11K D3 MMSZ4702(15V) TP5 M2 Open L1 M3 Si4842DY M4 Si4842DY 1.3uH D4 MMSZ4698(11V) C2 0.1uF C1 2.2nF/630V R2 5.1K C52 0.1uF 1N4148WS 1N4148WS D2
10Vbias
Vout=3.3V/20A
R1 5.11 T1 PA0944G 10 C4 0.1uF M1 Open TP4 1 C3 0.1uF
R12 5.1K Q3 FZT853 D5 1N4148WS
Vin=48V
C9 100uF
C10 1u,100V
C11 1u,100V
C12 1u,100V
POWER MANAGEMENT SC4810E Evaluation Board - Schematic
R61 200K R13 open C18 0.1uF TP7 R15 open C16 47uF/16V R57 5.1 R56 5.1 TP9 C53 1uF C20 1uF U2 D9 1N5819HW M12 Open M13 Si4488DY M14SI2308 7 3 R19 10K R20 8.2(16//16) R22 2 P8208T 8 T3 1 R18 1K C17 180pF 1N5819HW
Q10 FMMT493
D20 MMSZ4697(10V)
D21
8 7 6 5
M10 Si4842DY 1 2 3 4
1N4148WS
19
U1 MOCD207 1 2 R17 1K 6 R42 2.4K 5 3 4 R63 10K R33 80.6K 0.1uF C50 C27 0(short) R44 1.5K U4 SC431 TP13
R21 1.1M
C22 220pF
R52 51
R30 10K
4
10Vbias
R16 1K R62 4.75K C23 open R34 1K C14 open R14 open U6 SC431 R25 5.1K C26 47nF R32 5.1K R50 open
5
R31 7.5K
7
C25 220pF Q6 FMMT718
R37 80.6K
8
C51 open
R35 10K
R36 7.5K
R38 1.47K
R40 15.8K
R43
10K
R29 6.34K
SC4810B/E
TP11
TP12
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SC4810B/E
POWER MANAGEMENT SC4810E Evaluation Board - BOM
Item 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 31 32 33 35 Quantity 1 10 1 3 3 1 1 1 1 2 1 1 1 5 1 2 3 1 1 4 1 3 1 1 1 2 1 1 4 1 9 1 Reference C1 C2,C3,C4,C5,C18, C19,C20,C50,C52,C53 C6 C7,C8,C9 C10,C11,C12 C13 C16 C17 C21 C25,C22 C24 C26 C27 D1,D2,D5,D10,D21 D3 D4,D8 D6,D9,D11 D20 L1 M3,M4,M8,M10 M5 M7,M9,M14 M13 Q1 Q3 Q5,Q6 Q10 R1 R2,R12,R25,R32 R3 R8,R9,R10,R19, R28,R30,R35,R43,R63 R16 Part 2.2nF/630V 0.1uF Package SM0805 SM0805 Sanyo TDK TDK TDK Sanyo 4TPB680M C4532X5ROJ107MT C3225X7R2A105K C3216X7R2J223M 16TQC47M Manufacturer TDK P/N C3216X7R2J222K
680uF SM/CT_7343 100uF SM/C_1812 1u,100V SM/C_1210 22nF/100V SM1206 47uF/16V SM/CT_7343 180pF SM0805 100pF SM0805 220pF SM0805 1uF SM0805 47nF SM0805 0(short) SM0805 1N4148WS SOD123 MMSZ4702(15V) SOD123 MMSZ4698(11V) SOD123 SL04 SOD123 MMSZ4697(10V) SOD123 1.3uH PCC-S1 Si4842DY SO-8 IRF6216 SO-8 SI2308 SOT-23 Si4488DY SO-8 FMMT618 SOT-23 FZT853 SM/SOT223 FMMT718 SOT-23 FMMT493 SOT-23 5.11 SM0805 5.1K SM0805 5.11K SM0805 10K 1K SM0805 SM0805
Vishay On Semi On Semi Vishay On Semi Panasonic Vishay I. R. Vishay Vishay Zetex Zetex Zetex Zetex
1N4148WS MMSZ4702T1 MMSZ4698T1 SL04 MMSZ4697T1 ETQPAF1R3EFA Si4842DY IRF6216 SI2308 Si4488DY FMMT618 FZT853 FMMT718 FMMT493
2006 Semtech Corp.
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SC4810B/E
POWER MANAGEMENT SC4810E Evaluation Board - BOM
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 54 55 56 57 58 59 3 1 1 1 1 1 1 2 2 1 1 1 1 1 3 1 1 1 1 1 1 1 2 R17,R18,R34 R20 R21 R22 R23 R24 R29 R31,R36 R33,R37 R38 R40 R42 R44 R52 R54,R56,57 R61 R62 T1 T3 U1 U2 U3 U4,U6 1K 8.2 1.1M 2 160K 100K 6.34K 7.5K 80.6K 1.47K 15.8K 2.4K 1.5K 51 5.1 200K 4.75K PA0944G P8208T MOCD207 SC1302A SC4810 SC431 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 SM0805 PA0646 P8208 SO-8 MSOP-8 TSSOP16 SOT-23
Pulse Pulse Fairchild Semtech Semtech Semtech
PA0944G P8208T MOCD207 SC1302A SC4810 SC431
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SC4810B/E
POWER MANAGEMENT Outline Drawing - TSSOP-16
A e N 2X E/2 E1 PIN 1 INDICATOR ccc C 2X N/2 TIPS 123 E
D
DIM
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.047 .002 .006 .031 .042 .007 .012 .003 .007 .192 .196 .201 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 16 0 8 .004 .004 .008 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.00 5.10 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 16 0 8 0.10 0.10 0.20
e/2 B D A2 A
aaa C SEATING PLANE
C bxN
A1 bbb C A-B D GAGE PLANE 0.25
H c L (L1) DETAIL
01
SIDE VIEW
SEE DETAIL
A
A
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -BTO BE DETERMINED AT DATUM PLANE -H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AB.
Land Pattern - TSSOP-16
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20
Y P
NOTES: 1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
2006 Semtech Corp.
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SC4810B/E
POWER MANAGEMENT Outline Drawing - MLPQ-16, 4 x 4
DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX
B
A A1 A2 b D D1 E E1 e L N aaa bbb .040 .031 .002 .000 (.008) .010 .012 .014 .153 .157 .161 .100 .106 .110 .153 .157 .161 .100 .106 .110 .026 BSC .012 .016 .020 16 .003 .004 1.00 0.80 0.05 0.00 (0.20) 0.25 0.30 0.35 3.90 4.00 4.10 2.55 2.70 2.80 3.90 4.00 4.10 2.55 2.70 2.80 0.65 BSC 0.30 0.40 0.50 16 0.08 0.10
A
D
PIN 1 INDICATOR (LASER MARK)
E
A2 A aaa C A1
D1
C e/2
LxN E/2
SEATING PLANE
E1
2 1 N e D/2 bxN bbb CAB
NOTES: 1. 2. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
2006 Semtech Corp.
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SC4810B/E
POWER MANAGEMENT Land Pattern - MLPQ-16, 4 x 4
K
DIM
2x (C) H 2x G 2x Z C G H K P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.156) .122 .106 .106 .026 .016 .033 .189 (3.95) 3.10 2.70 2.70 0.65 0.40 0.85 4.80
Y X P
NOTES: 1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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