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Preliminary
RT9248A
Multi-Phase PWM Controller for CPU Core Power Supply
General Description
The RT9248A is a cost-effective multi-phase buck DC/DC controller integrated with all control functions for GHz CPU VRM. The RT9248A controls 2 or 3 buck switching stages operating in interleaved phase set automatically. The multiphase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. The high equivalent operating frequency also reduces the component dimension and the output voltage ripple in load transient. RT9248A controls both voltage and current loops to achieve good regulation, response & power stage thermal balance. Precise current loop using RDS(ON) as sense component builds precise load line for strict VRM DC & transient specification and also ensures thermal balance of different power stages. The settings of current sense, droop tuning, VCORE initial offset and over current protection are independent to compensation circuit of voltage loop. The feature greatly facilitates the flexibility of CPU power supply design and tuning. The DAC output of RT9248A supports VRM9 & VRD10 by VID125 multi-level input, precise initial value & smooth VCORE transient at VID jump. The IC monitors the VCORE voltage for PGOOD and over-voltage protection. Soft-start, over-current protection and programmable under-voltage lockout are also provided to assure the safety of microprocessor and power system.
Features
Multi-Phase Power Conversion with Automatic Phase Selection VRM9 & VRD10 DAC Output with Active Droop Compensation for Fast Load Transient Smooth VCORE Transition at VID Jump Multi-Level VID125 Input for VRM9 & VRD10 Selection Power Stage Thermal Balance by RDS(ON) Current Sense Hiccup Mode Over-Current Protection Programmable Switching Frequency (50kHz to 400kHz per Phase), Under-Voltage Lockout and Soft-Start High Ripple Frequency Times Channel Number RoHS Compliant and 100% Lead (Pb)-Free
Applications
Intel(R) Processors Voltage Regulator: VRM9 and VRD10 Low Output Voltage, High Current DC-DC Converters Voltage Regulator Modules
Pin Configurations
(TOP VIEW)
VID4 VID3 VID2 VID1 VID0 VID125 SGND FB COMP PGOOD DVD SS RT VOSS
2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
Ordering Information
RT9248A Package Type C : TSSOP-28 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard)
VCC PWM1 PWM2 PWM3 NC ISP1 ISP2 ISP3 ISN GND ADJ VDIF VSEN IMAX
Note : RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating. DS9248A-06 March 2006
TSSOP-28
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+12V
C6 1uF C7 Q1 IPD09N03LA Q2 L1 1uH 4.7uF C8 2200uF R12 10 D1 1N4148 1 SW 7
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+12V RT9603 8 DRVH BST +5V
4
RT9248A
VCC
5 DRVL
C4 1uF
C5 1uF 2
VIN PGND
IPD06N03LA 6 C9 0.01uF
R13 1
RT9248A VCC PWM1 +12V
+12V C11 1uF C12 4.7uF Q3 IPD09N03LA Q4 IPD06N03LA L2 1uH 1 R14 10 D2 1N4148 C13 2200uF 27 26 25 24 23 22 21 20 R10 1k C10 1uF 2 R9 3k 4 R8 3k R7 3k 28
VID4 >
1
VID4
Typical Application Circuit
VID3 >
2
VID3 PWM2 PWM3 NC ISP1 ISP2 ISP3 VIN DRVL PGND
19 6 18 17 16 5
VID2 >
3
VID2
VCORE
C20 to C24 2200uF x 5
VID1 >
4
VID1
VID0 >
5
VID0 RT9603 8 BST DRVH SW VCC
7
VID125 >
6
VID125
7
SGND
8
R1 15k
FB ISN GND ADJ VDIF VSEN +12V IMAX
R11 12k R16 10 D3 1N4148 15
C1 22nF
R15 4.7 C14 0.01uF
C25 to C28 2200uF x 4
9
COMP
Preliminary
C2
33pF
PG_VCORE <
10
PGOOD
11
DVD
R2 2.4k
+12V
C3 0.1uF
12
SS
R3 9k
13
+12V
C16 1uF C17 4.7uF Q5 1 C18 2200uF
RT
14
VOSS
R4 1k
R5 12k
R6 100k
RT9603 8 BST DRVH
4
SW VCC
C15 1uF 2
7
IPD09N03LA Q6 R17 4.7
L3 1uH
VIN
6
DRVL PGND
5
DS9248A-06 March 2006
IPD06N03LA
C19 0.01uF
Preliminary Functional Pin Description
VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4), VID0 (Pin 5) & VID125 (Pin 6) DAC voltage identification inputs. Tie VID125 to GND for VRM9 or to VCC for VRD10. These pins are internally pulled to 3.3V if left open. SGND (Pin 7) Connect this pin to the return pin of VCORE . FB (Pin 8) Inverting input of the internal error amplifier. VDIF (Pin 17) COMP (Pin 9) Output of the error amplifier and input of the PWM comparator. PGOOD (Pin 10) Power good open-drain output. GND (Pin 19) DVD (Pin 11) Programmable power UVLO detection or converter enable input. SS (Pin 12) Connect this SS pin to GND with a capacitor to set the soft-start time interval. RT (Pin 13) Switching frequency setting. Connect this pin to GND with a resistor to set the frequency.
450 400 350 300
RT9248A
VOSS (Pin 14) VCORE initial value offset. Connect this pin to GND with a resistor to set the offset value. IMAX (Pin 15) Over-Current protection set. VSEN (Pin 16) Power good and over-voltage monitor input. Connect this to the sense pin of VCORE.
This pin is being tied to VSEN pin internally. ADJ (Pin 18) Current sense output for active droop adjust. Connect a resistor from this pin to GND to set the load droop.
IC ground. ISN (Pin 20) RDS(ON) current sense input from anyone of channel sense components' GND node. ISP1 (Pin 23), ISP2 (Pin 22), ISP3 (Pin 21) RDS(ON) current sense inputs for individual converter channels. Tie this pin to the component's sense node. NC (Pin 24) No internal connection.
Frequency vs. RRT
PWM1 (Pin 27), PWM2 (Pin 26), PWM3 (Pin 25) PWM outputs for each driven channel. Connect these pins to the PWM input of the MOSFET driver. For systems which use 2 channels, connect PWM3 high. VCC (Pin 28) IC power supply. Connect this pin to a 5V supply.
f OSC(kHz)
250 200 150 100 50 0 0 10 20 30 40 50 60 70
RRT (k )
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OCP Setting Power On Reset ++ PWMCP
INH
Function Block Diagram
++ PWMCP
INH
SGND OVP Trip Point ++ + + PWMCP +
DAC + Droop
PG Trip Point
Offset Currrent Source/Sink Current Correction + + + ISP1 + ISN ISP2 +
Preliminary
VOSS ERROR AMP GAP AMP
SUM/M
DS9248A-06 March 2006
FB COMP SS
VSEN
VDIF
ADJ
GND
-
SS Control -
-
+
VID0 VID1 VID2 VID3 VID4 VID125
INH
DAC
PWM Logic & Driver
Oscillator & Sawtooth -
+
+
+
+
-
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IMAX PGOOD VCC DVD RT
INH
RT9248A
PWM Logic & Driver
PWM1
PWM2
PWM Logic & Driver
PWM3
ISP3
Preliminary
Table 1. Output Voltage Program
Pin Name VID4 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
(2) 1: Open (3) For VID125, H: VCC, L: GND DS9248A-06 March 2006
RT9248A
Nominal Output Voltage DACOUT
VID3 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1
VID2 1 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
VID1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
VID0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VID125 = H No CPU 0.850V 0.875V 0.900V 0.925V 0.950V 0.975V 1.000V 1.025V 1.050V 1.075V 1.100V 1.125V 1.150V 1.175V 1.200V 1.225V 1.250V 1.275V 1.300V 1.325V 1.350V 1.375V 1.400V 1.425V 1.450V 1.475V 1.500V 1.525V 1.550V 1.575V 1.600V
VID125 = L No CPU 1.625V 1.650V 1.675V 1.700V 1.725V 1.750V 1.775V 1.800V 1.825V 1.850V 1.100V 1.125V 1.150V 1.175V 1.200V 1.225V 1.250V 1.275V 1.300V 1.325V 1.350V 1.375V 1.400V 1.425V 1.450V 1.475V 1.500V 1.525V 1.550V 1.575V 1.600V
Note: (1) 0: Connected to GND
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RT9248A
Absolute Maximum Ratings
Preliminary
(Note 1) 7V GND-0.3V to VCC+0.3V 45C/W 150C 260C -65C to 150C 2kV 200V
Supply Voltage, VCC ------------------------------------------------------------------------------------------Input, Output or I/O Voltage ---------------------------------------------------------------------------------Package Thermal Resistance TSSOP-28, JA -------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------ESD Susceptibility (Note 2) HBM (Human Body Mode) ----------------------------------------------------------------------------------MM (Machine Mode) -------------------------------------------------------------------------------------------
Recommended Operating Conditions
(Note 3)
Supply Voltage, VCC ------------------------------------------------------------------------------------------- 5V 10% Ambient Temperature Range --------------------------------------------------------------------------------- 0C to 70C Junction Temperature Range --------------------------------------------------------------------------------- 0C to 125C
Electrical Characteristics
(VCC = 5V, TA = 25C, unless otherwise specified)
Parameter VCC Supply Current Nominal Supply Current Power-On Reset POR Threshold Hysteresis VDVD Threshold Oscillator Free Running Frequency Frequency Adjustable Range Ramp Amplitude Ramp Valley Maximum On-Time of Each Channel RT Pin Voltage Reference and DAC DACOUT Voltage Accuracy DACOUT Voltage Accuracy VDAC_10 VDAC_9 VRD10, VDAC 1V VRD10, VDAC < 1V VRM9 -1 -10 -1 ---+1 +10 +1 % mV % VRT RRT = 12k fOSC fOSC_ADJ VOSC VRV RRT = 12k RRT = 12k 170 50 --62 0.94 200 -1.9 1.0 66 1.0 230 400 --75 1.06 kHz kHz V V % V Trip (Low to High) Hysteresis VCCRTH VCCHYS VDVDTP VDVDHYS Enable VCC Rising 4.0 0.2 0.9 -4.2 0.5 1.0 70 4.5 -1.1 -V V V mV ICC PWM 1,2,3 Open -12 -mA Symbol Test Conditions Min Typ Max Units
To be continued
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DS9248A-06 March 2006
Preliminary
Parameter DAC (VID0-VID4) Input Low DAC (VID0-VID4) Input High VID125 Input for VRM9 VID125 Input for VRD10 DAC (VID0-VID125) Bias Current VOSS Pin Voltage Error Amplifier DC Gain Gain-Bandwidth Product Slew Rate Current Sense GM Amplifier ISP 1,2,3 Full Scale Source Current ISP 1,2,3 Current for OCP Protection IMAX Voltage SS Current Over-Voltage Trip (VSEN/DACOUT) Power Good Lower Threshold (VSEN/DACOUT) Output Low Voltage VPG- VPGL VSEN Rising IPG = 4mA --VIMAX ISS OVT RIMAX = 10k VSS = 1V 0.94 --IISPFSS IISPOCP 60 90 GBW SR COMP = 10pF ---Symbol VILDAC VIHDAC VVID125_9 VVID125_10 IBIAS_DAC VVOSS RVOSS = 100k Test Conditions Min -0.8 -0.8 35 0.95
RT9248A
Typ ----50 1.0 Max 0.4 -0.4 -65 1.15 Units V V V V A V
85 10 3
----
dB MHz V/s
---
---
A A
1.0 13 140
1.06 ---
V A %
92 --
-0.2
% V
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions.
DS9248A-06 March 2006
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RT9248A
Application Information
Preliminary
RT9248A is a multi-phase DC/DC controller that precisely regulates CPU core voltage and balances the current of different power channels. The converter consisting of RT9248A and its companion MOSFET driver provides high quality CPU power and all protection functions to meet the requirement of modern VRM. Voltage Control RT9248A senses the CPU V CORE by an precise instrumental amplifier to minimize the voltage drop on PCB trace at heavy load. VSEN & SGND are the differential inputs. VDIF is the output node of the differential voltage & the input for PGOOD & OVP sense. The internal high accuracy VID DAC allows selection of either VRM9 or VRD10 compliance via VID125 pin setting. Control loop consists of error amplifier, multi-phase pulse width modulator, driver and power components. Like conventional voltage mode PWM controller, the output voltage is locked at the VREF of error amplifier and the error signal is used as the control signal VC of pulse width modulator. The PWM signals of different channels are generated by comparison of EA output and split-phase sawtooth wave. Power stage transforms VIN to output by PWM signal on-time ratio. Current Balance RT9248A senses the current of low side MOSFET in each synchronous rectifier when it is conducting for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the RDS(ON) of the low side MOSFET) to current signal into internal balance circuit. The current balance circuit sums and averages the current signals then produces the balancing signals injected to pulse width modulator. If the current of some power channel is greater than average, the balancing signal reduces the output pulse width to keep the balance. Load Droop The sensed power channel current signals regulate the reference of DAC to form a output voltage droop proportional to the load current. The droop or so-called "active voltage positioning" can reduce the output voltage ripple at load transient and the LC filter size.
Fault Detection The chip detects VCORE for over voltage and power good detection. The "hiccup mode" operation of over-current protection is adopted to reduce the short circuit current. The inrush current at the start up is suppressed by the soft start circuit through clamping the pulse width and output voltage. Phase Setting and Converter Start Up RT9248A interfaces with companion MOSFET drivers (like RT9600, RT9602 or RT9603 series) for correct converter initialization. The tri-state PWM output (high, low and high impedance) pins sense the interface voltage at IC POR period (both VCC and DVD trip). The channel is enabled if the pin voltage is 1.2V less than VCC. Please tie the PWM output to VCC and the current sense pins to GND or left floating if the channel is unused. For 2-Channel application, connect PWM3 high. Current Sensing Setting RT9248A senses the current of low side MOSFET in each synchronous rectifier when it is conducting for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the RDS(ON) of the low side MOSFET) to current signal into internal circuit (see Figure 1). Be careful to choose GND sense input, ISN, of the GM amplifier for effective channel current balance.
IX 1
< < <
C u rre n t B a la n c e D ro o p T u n e O v e r-C u rre n t D e te c tio n
IX 2 IX IX S a m p le & H o ld GM +
IB P
IS P 1
R SP1 RS IL
IB N
IX 2
< < <
C u rre n t B a la n c e D ro o p T u n e O v e r-C u rre n t D e te c tio n
IX 2 IX IX S a m p le & H o ld GM +
IB P
IS P 2
R SP2 RSN RS IL
IB N
IS N
G N D R e tu rn
IX 3
< < <
C u rre n t B a la n c e D ro o p T u n e O v e r-C u rre n t D e te c tio n
IX 2 IX IX S a m p le & H o ld GM +
IB P
IS P 3
R SP3 RS IL
IB N
Figure 1. Current Sense Circuit
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Preliminary
I L x RS by local feedback. RSP RSP = 3 x RSN (at 3 phase operation) to cancel the voltage drop caused by GM amplifier input bias current. IX is sampled and held just before low side MOSFET turns off (See Figure 2). Therefore, The sensing circuit gets IX = Protection and SS Function
RT9248A
V O T OFF I L (S/H) x R S x , , I L (S/H) = I L (AVG) - L 2 R SP V IN - V O T OFF = x 5uS for fosc = 200kHz V IN V IN - V O VO - x 5uS RS V IN x I X (S/H) = I L(AVG) - 2L R SP Falling Slope = Vo/L IL I X (S/H) =
IL(AVG)
Inductor Current
For OVP, the RT9248A detects the VCORE by VDIF pin voltage of the differential amplifier output. Eliminate the delay due to compensation network (compared to sensing FB voltage) for fast and accurate detection. The trip point of OVP is 140% of normal output level. The PWM outputs are pulled low to turn on the low side MOSFET and turn off the high side MOSFET of the synchronous rectifier at OVP. The OVP latch can only be reset by VCC or DVD restart power on reset sequence. The PGOOD detection trip point of VCORE is 92% lower than the normal level. The PGOOD open drain output pulls low when VCORE is lower than the trip point. For VID jumping issue, only power fail conditions (VCC & DVD are lower than trip point or OVP) reset the output low. Soft-start circuit generates a ramp voltage by charging external capacitor with 13A current after IC POR acts. The PWM pulse width and VCORE are clamped by the rising ramp to reduce the inrush current and protect the power devices. Over-current protection trip point is set by the resistor RIMAX connected to IMAX pin. OCP is triggered if one channel S/H current signal IX >
IL(S/H)
PWM Signal & High Side MOSFET Gate Signal
Low Side MOSFET Gate Signal
Figure 2. Inductor Current and PWM Signal DAC Offset Voltage & Droop Tuning The DAC offset voltage is set by compensation network 1V R f 1 & VOSS pin external resistors by R VOSS x 4 . The S/H current signals from power channels are injected to ADJ pin to create droop voltage. VADJ = RADJx 2 IX
PWM output latched at high impedance to turn off both high and low side MOSFETs in the power stage and initial the hiccup mode protection. The SS pin voltage is pulled low with a 13A current after it is less than 90% VCC. The converter restarts after SS pin voltage < 0.2V. Three times of OCP disable the converter and only release the latch by POR acts (see Figure 4).
S.S VCORE 0V
0 .6 V x 1 .4 . Controller forces R IMAX
COUNT= 1 COUNT= 2 COUNT==33 Count = 1 Count = 2 Count
The DAC output voltage decreases by VADJ to form the VCORE load droop (see Figure 3).
VDAC VADJ FB RF1 VCORE + -
COMP Current Source IVOSS = 1V RVOSS
+ EA 1 IVOSS 4
2IX1 2IX2 2IX3
Overload Applied
>
VOSS RVOSS
Figure 3. DAC Offset Voltage & Droop Tune Circuit
DS9248A-06 March 2006 www.richtek.com 9
+
ILOAD
0A
>
ADJ RADJ
T0,T1
T2 TIME
T3,T4
Figure 4.
>
RT9248A
Preliminary
3-Phase Converter and Components Function Grouping
12V
VCC
BST DRVH SW
RT9603
IN SGND VSEN VDIF PWM1 VID ISP1 PGOOD VCC BST DRVH SW COMP FB ADJ Droop Setting 12V Driver Power UVLO DAC Offset Voltage Setting IMAX OCP Setting DVD VOSS SS ISP3 VCC PWM3 GND IN BST DRVH SW ISP2 ISN 12V PWM2 IN VCORE 12V DRVL PGND
RT9248A
Compensation & Offset
RT9603
DRVL PGND
RT9603
DRVL PGND Current Sense Components
Design Procedure Suggestion
Voltage Loop Setting a. Output filter pole and zero (Inductor, output capacitor value & ESR). b. Error amplifier compensation & sawtooth wave amplitude (compensation network). c. Kelvin sense for VCORE. Current Loop Setting a. GM amplifier S/H current (current sense component RDS(ON), ISPx & ISN pin external resistor value, keep ISPx current < 60A at full load condition for better load line linearity). b. Over-current protection trip point (IMAX pin resistor, keep ISPx current < 90A at OCP condition for precision issue).
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VRM Load Line Setting a. Droop amplitude (ADJ pin resistor). b. No load offset (additional resistor in compensation network). c. DAC offset voltage setting (VOSS pin & compensation network resistor). Power Sequence & SS DVD pin external resistor and SS pin capacitor. PCB Layout a. Kelvin sense for current sense GM amplifier input. b. Refer to layout guide for other item.
DS9248A-06 March 2006
Preliminary Design Example
Given:
Apply for three phase converter VIN = 12V ILOAD (max) = 60A VDROOP = 120mV at full load OCP trip point set at 30A for each channel (S/H) RDS(ON) = 6m of low side MOSFET at 27C L = 2H COUT = 9,000F with 2m ESR. 1. Compensation Setting a. Modulator Gain, Pole and Zero: From the following formula: V IN 12V Modulator Gain = = = 4.2 (12.46dB) V RAMP 1.9V x 3 where VRAMP : ramp amplitude of sawtooth wave
1
2
Gain (dB)
RT9248A
Asymptotic Bode Plot of PWM Loop Gain
100 80 60 40 20 0 -20 -40 -60 10 10 100 100 1K 1000 10K 10000 100K 100000 1M 10M 1000000 10000000
Compensated EA Gain PWM Loop Gain Modulator Gain Uncompensated EA Gain
VCORE = 1.5V
Frequency (Hz)
Figure 6. 2. Droop & DAC Offset Setting For each channel the load current is 60A / 3 = 20A and the ripple current, IL, is given as:
5us x
LC Filter Pole = 2 x LC = 1.2kHz and ESR Zero =
1 2 x ESR x COUT
= 8.8kHz
b. EA Compensation Network: Select R1 = 2.4k, R2 = 24k, C1 = 6.6nF, C2 = 33pF and use the type 2 compensation scheme shown in Figure 5.
R2
C1
R3 R1
C3
C2 COMP + DACOUT FB
> VDIF
R3,C3 are used in type 3 compensation scheme (left NC in type 2)
IL = 18.36 A . 2 Using the following formula to select the appropriate IX (MAX) for the S/H of GM amplifier: R DS(ON) x 18.36A I X (MAX) = R SP The suggested IX is in the order of 40 to 50A, select RSP = 2.4k then IX (MAX) will be 45.9A. VDROOP = 120mV = 45.9A x 2 x 3 (phase no.) x RADJ, therefore RADJ will be 435. The RDS(ON) of MOSFET varies with temperature rise. When the low side MOSFET working at 70C and 5000ppm/C temperature coefficient of RDS(ON), the RDS(ON) at 70C is given as: 6m x {1+ (70C - 27C) x 5000ppm/C} = 7.3m. RADJ at 70C is given as: RADJ_27C x (RDS(ON)_27C / RDS(ON)_70C) = 358 The load current, IL, at S/H is 20 A - 3. Over-Current Protection Setting OCP trip point set at 30A for each channel,
1.5V 1.5V x 1 - = 3.28A 2uH 12V
Figure 5. From the following formulas: 1 1 FZ = , FP = 2 x R 2 x C 1 C1 x C 2 2 x R 2 x R2 C1 + C 2 Middle Band Gain =
R1
IX =
RDS(ON) x 30A 0.6V = 1.4 x , RIMAX = 11.2k RSP RIMAX
By calculation, the FZ = 1kHz, FP = 200kHz and Middle Band Gain is 10 (i.e 20dB). The asymptotic bode plot of EA compensation and PWM loop gain is shown as Figure 6.
DS9248A-06 March 2006
Take the temperature rise into account, the RIMAX at 70C will be: RIMAX_27C x (RDS(ON)_27C / RDS(ON)_70C) = 9.2k 4. Soft-Start Capacitor Selection CSS = 0.1F is the suitable value for most application.
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RT9248A
Layout Guide
Preliminary
Place the high-power switching components first, and separate them from sensitive nodes. 1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense resistors tied to ISP1,2,3 and ISN should be located not more than 0.5 inch from the IC and away from the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible. Kelvin connection of the sense component (additional sense resistor or MOSFET RDS(ON)) ensures the accurate stable current sensing.
Keep well Kelvin sense to ensure the stable operation!
2. Switching ripple current path: a. Input capacitor to high side MOSFET. b. Low side MOSFET to output capacitor. c. The return path of input and output capacitor. d. Separate the power and signal GND. e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points. Keep them away from sensitive small-signal node. f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via. 3. MOSFET driver should be closed to MOSFET. 4. The compensation, bypass and other function setting components should be near the IC and away from the noisy power path.
SW1
L1
VIN RIN
VOUT
COUT CIN
RL
V
L2 SW2
Figure 7. Power Stage Ripple Current Path
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DS9248A-06 March 2006
Preliminary
+12V CBP Next to IC +12V or +5V PWM CBOOT LO1 CIN
Kelvin Sense
RT9248A
+5VIN CBP Next to IC COMP CC
VCC
IMAX VOSS VCORE
VCC IN
BST DRVH SW
RT9603
DRVL PGND
COUT RSP
RT9248A
FB ISPx ISN RSN ADJ GND VSEN
RC Locate next to FB Pin RFB
Locate near MOSFETs
For Thermal Couple
Figure 8. Layout Consideration
DS9248A-06 March 2006
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RT9248A
Outline Dimension
Preliminary
D L
E
E1
e
A A1 b
A2
Symbol A A1 A2 b D e E E1 L
Dimensions In Millimeters Min 0.850 0.050 0.800 0.178 9.601 0.650 6.300 4.293 0.450 6.500 4.496 0.762 Max 1.200 0.152 1.050 0.305 9.804
Dimensions In Inches Min 0.033 0.002 0.031 0.007 0.378 0.026 0.248 0.169 0.018 0.256 0.177 0.030 Max 0.047 0.006 0.041 0.012 0.386
28-Lead TSSOP Plastic Package
Richtek Technology Corporation
Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
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DS9248A-06 March 2006

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