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RT9173B
2A Bus Termination Regulator
General Description
The RT9173B regulator is designed to convert voltage supplies ranging from 1.7V to 6V into a desired output voltage of which adjusted by two external voltage divider resistors. The regulator is capable of sourcing or sinking up to 2A of current while regulating an output voltage to within 40mV. The RT9173B, used in conjunction with series termination resistors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed backplane designs. The voltage output of the regulator can be used as a termination voltage for DDR SDRAM. Current limits in both sourcing and sinking mode, plus onchip thermal shutdown make the circuit tolerant of the output fault conditions. The RT9173B are available in the popular 5-lead TO-252 and fused SOP-8 (the multiple VCNTL pins on the SOP-8 package are internally connected but lowest thermal resistance) surface mount packages.
Features
Support Both DDR I (1.25VTT) and DDR II (0.9VTT) Requirements SOP-8 and TO-252-5 Packages Capable of Sourcing and Sinking Current Current-limiting Protection Thermal Protection Integrated Power MOSFETs Generates Termination Voltages for SSTL-2 High Accuracy Output Voltage at Full-Load Adjustable VOUT by External Resistors Minimum External Components Shutdown for Standby or Suspend Mode Operation with High-impedance Output RoHS Compliant and 100% Lead (Pb)-Free
Applications
DDR Memory Termination Supply Active Termination Buses Desktop PC/AGP Graphics Set Top Box/IPC Supply Splitter
Ordering Information
RT9173B Package Type S : SOP-8 L5 : TO-252-5 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard)
Pin Configurations
(TOP VIEW)
VIN GND REFEN VOUT 2 3 4 8 7 6 5 VCNTL VCNTL VCNTL VCNTL
Note : RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100%matte tin (Sn) plating.
SOP-8
5 4 3 2 1 VOUT REFEN VCNTL (TAB) GND VIN
TO-252-5
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RT9173B
Typical Application Circuit
VCNTL = 3.3V CCNTL R1 VCNTL VIN CIN RT9173B REFEN VOUT R2 GND COUT RDUMMY VIN = 2.5V RTT
2N7002 EN
R1 = R2 = 100k, RTT = 50 / 33 / 25 COUT(MIN) = 10F (Ceramic) + 1000F under the worst case testing condition RDUMMY = 1k as for VOUT discharge when VIN is not present but VCNTL is present CIN = 470F (Low ESR), CCNTL = 47F
Test Circuit
3.3V 2.5V
1.25V
VCNTL VIN RT9173B REFEN VOUT GND IL
VOUT COUT
V
Figure 1. Output Voltage Tolerance, VOUT
3.3V
A
2.5V
1.25V 0.2V
VCNTL VIN RT9173B VOUT REFEN GND RL
VOUT COUT
1.25V 0V
V
RL and COUT Time deleay
Figure 2. Current in Shutdown Mode, SHDN
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RT9173B
3.3V 2.5V
VCNTL 1.25V
VIN VOUT
RT9173B VOUT REFEN GND
A
IL
COUT
V
Figure 3. Current Limit for High Side, CLHIGH
3.3V
Power Supply with Current Limit 2.5V
VCNTL 1.25V
VIN
A
RT9173B REFEN VOUT GND
IL
VOUT COUT
V
Figure 4. Current Limit for Low Side, CLLOW
3.3V
2.5V
VCNTL 1.25V VREFEN 0.2V
VIN VOUT COUT
RT9173B VOUT REFEN GND RL
V
1.25V VOUT 0V
VOUT would be low if VREFEN < 0.2V VOUT would be high if VREFEN > 0.6V RL and COUT Time deleay
Figure 5. REFEN Pin Shutdown Threshold, VTRIGGER
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RT9173B
Functional Pin Description
Pin Name VIN GND VCNTL REFEN VOUT Power Input Ground Gate Drive Voltage Reference Voltage Input and Chip Enable Output Voltage Pin Function
Function Block Diagram
VCNTL VIN
Current Limiting Sensor REFEN Thermal GND CNTL VOUT
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RT9173B
Absolute Maximum Ratings
(Note 1) Input Voltage ------------------------------------------------------------------------------------------------------------ 7V Power Dissipation, PD @ TA = 25C SOP-8 -------------------------------------------------------------------------------------------------------------------- 0.625W TO-252 ------------------------------------------------------------------------------------------------------------------- 1.471W Package Thermal Resistance (Note 5) SOP-8, JA -------------------------------------------------------------------------------------------------------------- 160C/W SOP-8, JC -------------------------------------------------------------------------------------------------------------- 23C/W TO-252, JA ------------------------------------------------------------------------------------------------------------- 68C/W TO-252, JC ------------------------------------------------------------------------------------------------------------- 8C/W Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260C Junction Temperature ------------------------------------------------------------------------------------------------ 150C Storage Temperature Range ---------------------------------------------------------------------------------------- -65C to 150C ESD Susceptibility (Note 2) HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions Electrical Characteristics
(Note 3)
Junction Temperature Range ---------------------------------------------------------------------------------------- -40C to 125C
(VIN = 2.5V, VCNTL = 3.3V, VREFEN = 1.25V, COUT = 10F (Ceramic), TA = 25C unless otherwise specified)
Parameter Output Offset Voltage Load Regulation Input Voltage Range (DDR I/II) Operating Current of VCNTL Current In Shutdown Mode Short Circuit Protection Current limit Over Temperature Protection
Symbol VOS VLOAD VIN VCNTL ICNTL ISHDN ILIM
Test Conditions IOUT = 0A, Figure 1 (Note 4) IL : 0A 2A, Figure 1 IL : 0A -2A Keep VCNTL VIN on operation power on and power off sequences No Load VREFEN < 0.2V, RL = 180, Figure 2 Figure 3,4 3.3V VCNTL 5V 3.3V VCNTL 5V Output = High, Figure 5 Output = Low, Figure 5
Min -20 -20 1.7 3 --2.2 125 -0.6 --
Typ 0 0 2.5/1.8 3.3/5 1 50 2.6 170 35 ---
Max Units 20 20 -6 2.5 90 ----0.2 mV mV V mA A A C C
Thermal Shutdown Temperature TSD Thermal Shutdown Hysteresis Shutdown Function Shutdown Threshold Trigger TSD
V
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RT9173B
Note 1. Stresses beyond those listed under
"Absolute Maximum Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. The human body model is a 100pF capacitor discharged through a 1.5k resistor into each pin. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN. Note 5. JA is measured in the natural convection at T A = 25C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. The case point of JC is on the center of VCTRL pins (Lead 6 & 7) for SOP-8 packages.
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RT9173B
Typical Operating Characteristics
Source Current Limit vs. Temperature
3.8
3.8
Source Current Limit vs. Temperature
3.4
VIN = 1.8V, VCNTL = 5V
3.4
Source current (A)
Source current (A)
VIN = 1.8V, VCNTL = 3.3V
3
3
2.6
VIN = 2.5V, VCNTL = 5V
2.6
VIN = 2.5V, VCNTL = 3.3V
2.2
2.2
1.8 -40 -25 -10 5 20 35 50 65 80 95 110 125
1.8 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (C)
Temperature (C)
Sink Current Limit vs. Temperature
3.8
3.8
Sink Current Limit vs. Temperature
VIN = 1.8V, VCNTL = 5V
3.4
3.4
Sink current (A)
Sink current (A)
3
3
VIN = 2.5V, VCNTL = 5V
2.6
VIN = 1.8V, VCNTL = 3.3V
2.6
VIN = 2.5V, VCNTL = 3.3V
2.2
2.2
1.8 -40 -25 -10 5 20 35 50 65 80 95 110 125
1.8 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (C)
Temperature (C)
Turn-On Threshold vs. Temperature
0.5
Turn-Off Threshold vs. Temperature
0.5
Threshold Voltage (V)
0.45
Threshold Voltage (V)
VIN = 2.5V, VCNTL = 5V
0.45
0.4
VIN = 2.5V, VCNTL = 3.3V
0.4
VIN = 2.5V, VCNTL = 5V
0.35
0.35
VIN = 2.5V, VCNTL = 3.3V
0.3 -40 -25 -10 5 20 35 50 65 80 95 110 125
0.3 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (C)
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Temperature (C)
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RT9173B
Output Voltage vs. Temperature
0.91
Output Voltage vs. Temperature
1.26
VIN = 1.8V VCNTL = 3.3V
VIN = 2.5V VCNTL = 3.3V
Output Voltage (V)
Output Voltage (V)
0.905
1.255
0.9
1.25
0.895
1.245
0.89 -40 -25 -10 5 20 35 50 65 80 95 110 125
1.24 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (C)
Temperature (C)
0.9VTT @ 2A Transient Response
Output Transient Voltage (mV) Output Transient Voltage (mV)
VREFEN = 0.9V
0.9VTT @ 2A Transient Response
VREFEN = 0.9V
100 Swing Frequency : 1kHz 0 -100
VIN = 1.8V VCNTL = 3.3V
100 Swing Frequency : 1kHz 0 -100
VIN = 1.8V VCNTL = 5V
Output Current (A)
Output Current (A)
2 0 -2
2 0 -2
Time (250us/Div)
Time (250us/Div)
1.25VTT @ 2A Transient Response
Output Transient Voltage (mV) Output Transient Voltage (mV)
VREFEN = 1.25V
1.25VTT @ 2A Transient Response
VREFEN= 1.25V
100 Swing Frequency : 1kHz 0 -100
VIN = 2.5V VCNTL = 3.3V
100 Swing Frequency : 1kHz 0 -100
VIN = 2.5V VCNTL = 5V
Output Current (A)
Output Current (A)
2 0 -2
2 0 -2
Time (250us/Div)
Time (250us/Div)
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RT9173B
Output Short-Circuit Protection
Source
Output Short-Circuit Protection
Sink
6
Output Short Circuit (A)
VIN = 2.5V VCNTL = 3.3V
12
Output Short Circuit (A)
VIN = 2.5V VCNTL = 3.3V
5 4 3 2 1 0
Force the output shorted to ground
10 8 6 4 2 0
Force the output shorted to VDDQ
Time (1ms/DIV)
Time (1ms/DIV)
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RT9173B
Application Information
Internal parasitic diode Avoid forward-bias internal parasitic diode, VOUT to VCNTL, and VOUT to VIN, the VOUT should not be forced some voltage respect to ground on this pin while the VCNTL or VIN is disappeared. Consideration while designs the resistance of voltage divider Make sure the sinking current capability of pull-down NMOS if the lower resistance was chosen so that the voltage on VREFEN is below 0.2V. In addition, the capacitor and voltage divider form the lowpass filter. There are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. How to reduce power dissipation on Notebook PC or the dual channel DDR SDRAM application? In notebook application, using RichTek' s Patent
R DS(ON) ()
VREFEN VCNTL VIN R1
RT9173B VOUT REFEN GND
R2
Figure 6 Make sure that VCNTL >= VIN in all conditions including power on and off. As other linear regulator, dropout voltage and thermal issue should be specially considered. Figure 6 and 7 show the RDS(ON) over temperature of RT9173B in SOP-8 and TO-252 packages respectively. The minimum dropout voltage could be obtained by the product of RDS(ON) and output current. For thermal consideration, please refer to the relative sections.
RDS(ON) vs. Temperature
0.45 0.43 0.41 0.39 0.37 0.35 0.33 0.31 0.29 0.27 0.25 0.23 -50 -25 0 25 50 75 100 125
SOP-8 VCNTL = 3.3V
Bus Terminator Topology" with choosing RichTek' s product is encouraged.
"Distributed Distributed Bus Terminating Topology
Terminator Resistor R0 R1 BUS(1) RT9173B VOUT R2 R3 R4 REFEN R5 R6 BUS(6) RT9173B VOUT R7 R8 R9 BUS(7) BUS(8) BUS(9) BUS(2) BUS(3) BUS(4) BUS(5) BUS(0)
Temperature (C)
RDS(ON) vs. Temperature
0.48 0.45 0.42
TO-252 VCNTL = 3.3V
R DS(ON) ()
RN R(N+1)
0.39 0.36 0.33 0.30 0.27 0.24 -50 -25 0 25 50 75 100 125
BUS(N) BUS(N+1)
General Regulator The RT9173B could also serves as a general linear regulator. The RT9173B accepts an external reference voltage at REFEN pin and provides output voltage regulated to this reference voltage as shown in Figure 6, where VOUT = VREF x R1/(R1+R2)
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Temperature (C)
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RT9173B
Input Capacitor and Layout Consideration Place the input bypass capacitor as close as possible to the RT9173B. A low ESR capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to minimize parasitic resistance and inductance. Inappropriate layout may result in large parasitic inductance and cause undesired oscillation between RT9173B and the preceding power converter. Thermal Consideration An internal thermal limiting circuitry shuts down the RT9173B when junction temperature is over 170C. This protects the device during overload conditions. It is noted that the thermal limiting circuitry is not intended for normal operation. For maximum reliability, the junction temperature should not exceed absolute maximum operation temperature 125C during normal operation. The power dissipation should be well considered to keep the junction temperature within the specification. The power dissipation in RT9173B is calculated as: PD = (VIN - VOUT) x IOUT + VIN x IQ The maximum power dissipation can be calculated by following formula: PD(MAX) = ( TJ(MAX) -TA ) /JA Where T J(MAX) is the maximum operation junction temperature 125C, TA is the ambient temperature and the JA is the junction to ambient thermal resistance. The junction to ambient thermal resistance JA highly depends on IC package, PCB layout , the rate of surroundings airflow. JA for SOP-8 package is 160C/W and TO-252 package is 68C/W on standard JEDEC 51-3 (single layer, 1S) thermal test board. The maximum power dissipation at TA = 25C can be calculated by following formula: PD(MAX) = (125 - 25C) / 160 = 0.625W (SOP-8) PD(MAX) = (125 - 25C) / 68 = 1.471W (TO-252)
100 90
Since the multiple VCTRL pins of the SOP-8 package are internally shorted and connected to lead frame, it is efficient to dissipate the heat by adding cooper area on VCTRL footprint. Figure 7 shows the relation about thermal resistance JA vs. copper area on a standard JEDEC 51-7 (4 layer, 2S2P) thermal test board at TA = 25C. The corresponding maximum power dissipation is shown in Figure 8. For example, with 10mm x 10mm cooper area, we can obtain the lower thermal resistance about 45C/W. The power maximum dissipation can be calculated as: PD(MAX) = (125 - 25C) / 45 = 2.22W (SOP-8)
JA vs. Copper Area
100 90 80
JA (C/W)
70 60 50 40 30 0 10 20 30 40 50 60 70
2
SOP-8
80 90 100
Copper Area (mm )
Figure 7
Power Dissipation vs. Copper Area
TJ = 125C
Copper Area (mm 2 ))
80 70 60 50 40 30 20 10 0 0 0.5 1 1.5 2
2
TA = 65C TA = 55C TA = 25C
SOP-8
2.5 3
Power Dissipation (W)
Figure 8
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RT9173B
Outline Information
E b3 L3 T V D H S C2 R
L b P L2
A
Symbol A b b3 C2 D E H L L2 L3 P V R S T
Dimensions In Millimeters Min 2.184 0.381 4.953 0.457 5.334 6.350 9.000 0.508 0.889 Max 2.388 0.889 5.461 0.889 6.223 6.731 10.414 1.780 2.032
Dimensions In Inches Min 0.086 0.015 0.195 0.018 0.210 0.250 0.354 0.020 Max 0.094 0.035 0.215 0.035 0.245 0.265 0.410 0.070
0.508 Ref. 1.270 Ref. 5.200 Ref. 0.200 2.500 0.500 1.500 3.400 0.850
0.020 Ref. 0.035 0.080
0.050 Ref. 0.205 Ref. 0.008 0.098 0.020 0.059 0.134 0.033
5-Lead TO-252 Surface Mount Package
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RT9173B
A
H M
J
B
F
C I D
Symbol A B C D F H I J M
Dimensions In Millimeters Min 4.801 3.810 1.346 0.330 1.194 0.170 0.050 5.791 0.400 Max 5.004 3.988 1.753 0.508 1.346 0.254 0.254 6.200 1.270
Dimensions In Inches Min 0.189 0.150 0.053 0.013 0.047 0.007 0.002 0.228 0.016 Max 0.197 0.157 0.069 0.020 0.053 0.010 0.010 0.244 0.050
8-Lead SOP Plastic Package
Richtek Technology Corporation
Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
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