Part Number Hot Search : 
C5750X7R 2SD90 07K460 13156 CMF85A E001700 1006F TZJ18
Product Description
Full Text Search
 

To Download PJSDA6V1W5 Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
 PJSDA6V1W5
QUAD TVS/ZENER FOR ESD AND LATCH-UP PROTECTION
This Quad TVS/Zener Array has been designed to Protect Sensitive Equipment against ESD and to prevent Latch-Up events in CMOS circuitry operating at 5Vdc and below. This TVS array offers an integrated solution to protect up to 4 data lines where the board space is a premium.
PRELIMINARY
SPECIFICATION FEATURES
6
4
150W Power Dissipation (8/20s Waveform) Very Low Leakage Current, Maximum of 5A @ 5Vdc Very low Clamping voltage (Max of 10V @ 14A 8/20s) IEC61000-4-2 ESD 15kV air, 8kV Contact Compliance Industry standard SOT353 (Also known as SC70-5L)
1 2 3 SC70-5L
3 2 1
6
APPLICATIONS
Personal Digital Assistant (PDA) SIM Card Port Protection (Mobile Phone) Portable Instrumentation Mobile Phones and Accessories Computer Data Ports
4
MAXIMUM RATINGS
Rating Peak Pulse Power (8/20s Waveform) Peak Pulse Current (8/20s Waveform) ESD Voltage (HBM) Operating Temperature Range Storage Temperature Range Symbol P pp I pp V ESD TJ Tstg Value 150 14 >25 -55 to +150 -55 to +150 Units W A kV C C
ELECTRICAL CHARACTERISTICS
Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8/20s) Clamping Voltage (8/20s) Off State Junction Capacitance Off State Junction Capacitance Symbol VWRM VBR IR Vc Vc Cj Cj
Tj = 25C
Conditions Min Typical Max 5 I BR = 1 mA VR = 5V I pp = 5 Amps I pp = 10 Amps
0 Vdc Bias f = 1MHz Between I/O pins and pin 7 5 Vdc Bias f = 1MHz Between I/O pins and pin 7
Units v V A V V pF pF
6.2
7.2 5 8.6 9.1 180 90
10/1/2005
Page
1
www.panjit.com
PJSDA6V1W5
TYPICAL CHARACTERISTICS
Percent of Ipp
Capacitance, pF
PRELIMINARY
10/1/2005
Clamping Voltage vs Ipp 8x20sec Surge
16 14 12 Ipp, Amps 10 8 6 4 2 0 6 7 8 9 10 11 12 Clam ping Voltage, V
Pulse Waveform 110 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 time, sec 20 25 30 Rise time 10-90% - 8s 50% of Ipp @ 20s
Capacitance vs. Biasing Voltage @1MHz
200 150 100 50 0 0 1 2 3 4 5 Bias Voltage , Vdc
Page 2
www.panjit.com
PJSDA6V1W5
TYPICAL APPLICATION EXAMPLE AND PACKAGE LAYOUT DIMENSIONS
Data Line 1 Data Line 2 Data Line 3 Data Line 4
PRELIMINARY
SIM Card Port or Phone Port
PJSDA6V1W5
10/1/2005
Page 3
www.panjit.com


▲Up To Search▲   

 
Price & Availability of PJSDA6V1W5

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X