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W55VG580 TV ENCODER
W55VG580
The information described in this document is the exclusive intellectual property of Winbond Electronics Corporation and shall not be reproduced without permission from Winbond. Winbond is providing this document only for reference concerning the W55VG580 design. Winbond assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. Copyright 1997 (All rights reserved) Winbond Electronics Corporation
Document History
DATE REVISION COMMENTS
Aug 2002 Feb 2004 May 2006
A1 A2 A5
--Remove "H" from W55VG580H Add W55VG580 bonding pad diagram and application circuit Add package, QFN-32, and proof edit.
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Publication Release Date: May, 2006 Revision A5
W55VG580
Table of Contents1. 2. GENERAL DESCRIPTION ......................................................................................................... 1 FEATURES AND APPLICATIONS ............................................................................................. 2 2.1 2.2 3. 4. 5. FEATURES..................................................................................................................... 2 APPLICATIONS.............................................................................................................. 2
PINOUT AND DESCRIPTION .................................................................................................... 3 BLOCK DIAGRAM ...................................................................................................................... 5 FUNCTIONAL DESCRIPTION.................................................................................................... 6 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Input formatting ............................................................................................................... 6 Mode selection................................................................................................................ 6 Color space conversion .................................................................................................. 8 Low-pass filter................................................................................................................. 8 Modulator ........................................................................................................................ 8 Video timing .................................................................................................................... 9 Video and Burst Blanking ............................................................................................... 9 Power Down.................................................................................................................... 9 Analog outputs ................................................................................................................ 9 Recommended Operating Conditions .......................................................................... 13 Absolute Maximum Ratings .......................................................................................... 13 DC Characteristics ........................................................................................................ 14 AC Characteristics ........................................................................................................ 15
6.
ELECTRICAL CHARACTERISTICS......................................................................................... 13 6.1 6.2 6.3 6.4
7. 8.
PACKAGE INFORMATION....................................................................................................... 25 APPLICATION CIRCUIT........................................................................................................... 30
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W55VG580
1. GENERAL DESCRIPTION
The W55VG580 is a digital video encoder designed for digital video applications such as VCD players, DVD players, and video games. It digital video encoder converts 8-bit YCrCb (4:2:2) 8-bit data into analog composite video or Y/C video (S-video) signals. The W55VG580 supports video format is 525-line (M) NTSC/PAL orand 625-line (B, D, G, H, I, M, Nc) PAL video formats; CCIR 601 . and square pixel input data; and interlaced and non-interlaced frames. The W55VG580 can operates at in either master or slave mode. The data rate can be CCIR601 or square pixel. At In slave mode, the W55VG580 can auto auto-detect the input video format from the HSYNCN and VSYNCN pins and generates the corresponding video signals. At In master mode, it generates the required video timing, based on internally according to the various pin and internal settings In addition to slave and master modes, configuration. The input YCrCb data are converted into YUV signals. The chroma data are then low passed by a 1.3 MHz filter and modulated by a color subcarrier. The W55VG580 operates with a 2X pixel rate input. The W55VG580 has two DAC outputs which can output two composite video or Y/C S-video signal. The W55VG580 can operate at has a power-down mode that is controlled by by selecting the SLEEP pin. The W55VG580 is designed for digital video applications such as VCD, DVD, and video games. The W55VG580 operates at twice the input data rate. The input YCrCb data are first converted into YUV signals. Then, the chroma data are passed through a 1.3-MHz low-pass filter and modulated by a color subcarrier. The result is available on the two DAC outputs, which can output two composite video or one Y/C S-video signal.
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Publication Release Date: May, 2006 Revision A5
W55VG580
2. FEATURES AND APPLICATIONS
2.1 FEATURES
* Monolithic CMOS process * Master clock rate 2X 2x pixel rate * Two composite outputs or Y/C video output (S video) * Power-down mode * CCIR601 or square pixel input data rates * Master/slave sync signal switchable (controlled by pin) * Interlaced and non-interlaced operation
* Optional internal voltage reference
2.2 APPLICATIONS
P[7:0] CLK CVBS/ C
W55VG081 HSYNCN
VSYNCN
W55VG580
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W55VG580
3. PINOUT AND DESCRIPTION
W55VG580P
W55VG580YG
PLCC
(All digital pins are TTL compatible)
PLCC PIN NO. PIN NAME I/O
QFN-32
DESCRIPTION
21-28 29 32 1 16 15 14 13
P[0:7] CLK VSYNCN HSYNCN MASTER CBSWAP SVIDEO SLEEP
I I I/O I/O I I I I
YCrCb pixel inputs. They are latched on the falling edge of CLK. YCrCb input data conform to CCIR 601. 2XPixel clock input for 8-bit YCrCb data. Vertical sync input/output. VSYNCN is latched/output following the rising edge of CLK. Horizontal sync input/output. HSYNCN latched/output following the rising edge of CLK. is
Master/slave mode select. A logical -high 1 for master mode operation. A logical 0 for slave mode operation. Cr and Cb pixel sequence set up pin. Logic high swap the Cr and Cb sequence. SVIDEO select input pin. A logic high selects Y/C output; A logical low selects composite video output. Power save mode. Logic high 1 on this pin puts the chip into power-down mode.
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W55VG580
Continued.
PLCC PIN NO.
PIN NAME
I/O
DESCRIPTION
17-20 2
Mode[3:0] TEST
I I
Mode configuration pin. Test pin. This pin must be connected to DGND. Voltage reference input. An external reference voltage reference must supply typical 1.235 V to this pin. In either case, A 0.1-uF ceramic capacitor must be used to decouple this input to GND. The decoupling capacitor must be as close as possible to minimize the length of the load. This pin may be connected directly to VREF_OUT. Voltage reference output. It generates a typical 1.2V voltage reference and may be used to drive VREF_IN pin directly. Full-Scale adjust control pin. The full-Scale scale current of the D/A converters can be adjusted by connecting a resistor (RSET) between this pin and ground. The relationship is
RSET () = 2015 * VREF _ IN (V ) / Iout (mA).
9
VREF_IN
I
8
VREF_OUT
O
5
FSADJ
---
6
COMP
---
Compensation pin. A 0.1-uF ceramic capacitor must should be used to bypass this pin to VAA. The lead length must should be kept as short as possible to avoid noise. Composite/Luminance output. This is a high-impedance current source output, and it can drive a 37.5-W load. The output format can be is selected by the PAL pin. The pin can drive a 37.5 W load. If unused , this pin must should be connected directly to GND. Composite/Chroma output. This is a high high-impedance current source Outputoutput, and it can drive a 37.5-W load. The output format can be is selected by the PAL pin. The pin can drive a 37.5 W load. If unused, this pin must should be connected directly to GND. No connection Digital power pin Digital ground pin Analog power pin Analog ground pin
4
CVBS_Y
O
11
CVBS_C
O
10 31 30 7 3,12
NC VDD DGND VAA AGND
-----------
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W55VG580
4. BLOCK DIAGRAM
Sync/ Blank/ Pedestal P[7:0]
FSADJ
CBSWAP
Color Space Converter
+
1.3 MHz Low Pass Filter
+
Modu lator Mux Mux
VREF_IN
Up Sampl8 ing
8
COMP DAC DAC Y C
CLK MASTER SLEEP MODE[3:0]
Video Timing Generator
DTO
Bandgap Voltage Reference
VREF _OUT
VSYNCN HSYNCN TEST
SVIDEO
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W55VG580
5. FUNCTIONAL DESCRIPTION
5.1 Input formatting
The input circuitry accepts 8-bit CCIR601 4:2:2 YCrCb data . The data are input via the P[7:0] inputs and latched on the falling edge of CLK. The input YCrCb pixel sequence can be arranged by setting the CBSWAP pin and the YCSWAP mode register. If the CBSWAP pin and the YCSWAP mode register are all zero, the first pixel data latched by the CLK pin after the falling edge of HSYNCN is Cb. The sequence appears as Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 .... This can be swap by setting the CBSWAP pin and the YCSWAP mode register. The input clock rate can be CCIR601 2X13.5MHz or square pixel rate . Color burst frequency is derived from the CLOCK input. Any jitter on the CLOCK pin may induce a color burst frequency error. A stable clock source is recommended. The Y of the 16-bit YCrCb data has nominal range from 16-235 and Cr/Cb has a nominal range from 16-240, with 128 equal to zero. When the Y value is between 1-15, the internal circuit will clamp these values to 16. When the Y value is 0 and 255, the internal circuit will set the Y value as 38. When the Cr/Cb is between 1-15, the internal circuit will clamp these values to 16. When the Cr value is 0 and 255, the internal circuit will set the Cr value as 112. When Cb value is 0 and 255, the internal circuit will set the Cb value as 225. Thus when the external video source is reset to 0 or 255, the color at video output will appear blue.
5.2
Mode selection
There are 7Seven mode registers which can be are programmed by setting the four MODE [3:0] pins and the MASTER pin. The following table illustrates the arrangement of the 7 mode these registers.
PIN DESCRIPTION
The MASTER pin 0 (slave) 1 (master)
MODE[3] YCSWAP EFIELD
MODE[2] SETUP PAL625
MODE[1] PALSA INTERLACED
MODE[0] -SQUARE
In slave mode, the MODE [3:1] pins control the YCSWAP, SETUP, and PALSA registers. The W55VG580 automatically detects the input video timing, so the EFIELD, PAL625, INTERLACE, and SQUARE registers are not necessary. In master mode, however, the MODE [3:0] pins control the EFIELD, PAL625, INTERLACED and SQUARE registers. The YCSWAP, SETUP, and PALSA registers can be programmed by switching the W55VG580 to slave mode, setting the desired value(s) on the appropriate pin(s), and then switching back to master mode. Note that, at power-on, the YCSWAP, SETUP, and PALSA are set to zero.Each register is described in the following table.
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W55VG580
MODE REGISTER NAME
SET TO 0
SET TO 1
COMMENTS
EFIELD
The VSYNCN pin will outputs the field signal. Low at VSYNCN pin for even fields, high for odd fields. 525-line operation will be select Non-interlaced operation will be select CCIR-601 timing is selected. Do not swap Y and Cr/Cb Disable the 7.5 IRE setup When the PAL625 register is set to high, PAL-BDGHI mode is selected. When the PAL625 register is set to low, NTSC mode is selected.
The VSYNCN pin will output the normal vertical synchronization signal. The 625-line operation will be select The interlace operation will be select The square pixel timing is selected. Swap Y and Cr/Cb sequence Enable the 7.5 IRE setup When the PAL625 register is set to high, PAL-Nc mode is selected. When the PAL625 register is set to low, PAL-M mode is selected.
This is only used at in master mode. This is only used at in master mode This is only used at in master mode This is only used at in master mode -------
PAL625 INTERLACED SQUARE YCSWAP SETUP
PALSA
----
At slave mode, the W55VG580 will automatically detect the input video timing. The EFIELD, PAL625, INTERLACE, and SQUARE register will not be necessary. At master mode, the MODE[3:0] pins will set EFIELD, PAL625, INTERLACED and SQUARE registers. The YCSWAP, SETUP, and PALSA registers can be programmed by switching the W55VG580 to slave mode, then back to the master mode. At power-on, the YCSWAP, SETUP, and PALSA are set to zero.
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W55VG580
The Relationship between TV System and Bit allocation
BITS[4:0]={ PALSA, PAL625, SQUARE, INTERLACE } FL: Line Rate FP: Pixel Rate FSC: Sub-carrier Frequency
BITS[4:0] FORMAT PIXEL X LINE FL FP FSC
0 1 2 3 4 5 6 7 8 9 A B C D E F
M/NTSC, 601, NI M/NTSC, 601, I M/NTSC, S, NI M/NTSC, S, I BDGHIN/PAL, 601, NI BDGHIN/PAL, 601, I BDGHIN/PAL, S, NI BDGHIN/PAL, S, I M/PAL, 601, NI M/PAL, 601, I M/PAL, S, NI M/PAL, S, I Nc/PAL, 601, NI Nc/PAL, 601, I Nc/PAL, S, NI Nc/PAL, S, I
858x262 858x525 780x262 780x525 864x312 864x625 944x312 944x625 858x262 858x525 780x262 780x525 864x312 864x625 944x312 944x625
15734.264 15734.264 15734.264 15734.264 15625.000 15625.000 15625.000 15625.000 15734.264 15734.264 15734.264 15734.264 15625.000 15625.000 15625.000 15625.000
13500000 13500000 12272727 12272727 13500000 13500000 14750000 14750000 13500000 13500000 12272727 12272727 13500000 13500000 14750000 14750000
3579545.00 3579545.00 3579545.00 3579545.00 4433618.75 4433618.75 4433618.75 4433618.75 3575611.49 3575611.49 3575611.49 3575611.49 3582056.25 3582056.25 3582056.25 3582056.25
5.3
Color space conversion
The 8-bit 4:2:2 YCrCb data input are linearly interpolated to 4:4:4 format and then converted to YUV format.
5.4
Low-pass filter
The U/V signal is low-passed by a digital filter specified by CCIR 624.
5.5
Modulator
The U and V color color-difference signals are modulated by a sub-carrier frequency generated by an internal DTO. After modulation, they are summed together to produce the luminance signal.
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W55VG580
5.6 Video timing
The W55VG580 can operates in master mode and or slave mode. This is done by setting controlled by the MASTER pin. When the MASTER pin is set to logical low, the W55VG580 operates at in slave mode. When The the MASTER pin is set to logical high, the W55VG580 operates at in master mode. At In master mode, the W55VG580 automatically generates the required timing from the CLK input. The HSYNCN and VSYNCN pins are output following the rising edge of CLK. Coincident falling edges of on HSYNCN and VSYNCN indicates the beginning of an odd field. A falling edge of on VSYNC without a coincident falling edge of on HSYNCN indicates the beginning of an even field. At In slave mode, the W55VG580 accepts external horizontal and vertical synchronization signals via the HSYNCN and VSYNCN pins and automatically detects the input video format. The W55VG580 then generates the detected video timing. The W55VG580 automatically calculates the width of the horizontal sync pulse and the start and end of the color burst. The color burst is automatically disabled, and serration and equalization pulses automatically inserted, on the appropriate lines. Serration and equalization pulses are automatically inserted into appropriate lines.
5.7
Video and Burst Blanking
Video and burst information is automatically disabled according to the Rec. CCIR 624.
5.8
Power Down
When the SLEEP pin is logical high, the W55VG580 enters sleep mode. The clock input and DAC outputs are disabled.
5.9
Analog outputs
There are two 8-bit D/A converter outputs: CVBS_Y and CVBS_C. These two outputs are specified to drive a 37.5 5- load. When the SVIDEO pin is connected to high, the CVBS_Y will output luminance signal, and CVBS_C will outputs a signal which that can be interfaced to the an S-Video machine. When the SVIDEO pin is connected to low, both the CVBS_Y and CVBS_C will output composite videos.
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W55VG580
field 1
START of VSYNC
523
524
525
1
2
3
4
5
6
7
8
9
10
21
22
field 2
burst phase
261
262
263
264
265
266
267
268
269
270
271
272
273
284
285
field 3
burst phase
523
524
525
1 field 4
2
3
4
5
6
7
8
9
10
21
22
burst phase
261
262
263
264
265
266
267
268
269
270
271
272
273
284
285
Burst begins with positive half cycle Burst phase=180 relative to B-Y Burst begins with negative-half cycle Burst phase=180 relative to B-Y
Figure 1.
NTSC Interlace Video Timing
( SMPTE line conversion rather than CCIR-624 is used)
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W55VG580
START of VSYNC
620
621
622
623
624
625
1
2
3
4
5
6
7
22
23
24
+U phase
field 1 field 5
308
309
310 311
312
313
314
315
316
317
318
319
320
335
336
field 2,6
620
621
622 623
624
625
1
2
3
4
5
6
7
22
23
24
field 3,7
308
309
310
311
312
313
314
315
316
317
318
319
320
335 336
field 4,8
Burst Blanking Interval
field 1,5 field 2,6 field 3,7 field 4,8
Burst phase=135 relative to U +V component Burst phase=225 relative to U -V component
Figure 2.
B,D,G,H,I/PAL Interlace Video Timing
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W55VG580
START of VSYNC
257 258
259
260
261
262
1
2
3
4
5
6
7
8
17
18
257 258
259
260
261
262
1
2
3
4
5
6
7
8
17
18
Burst begins with positive half cycle Burst phase=180 relative to B-Y Burst begins with negative-half cycle Burst phase=180 relative to B-Y
Figure 3.
NTSC Non-interlace Video Timing
START of VSYNC
307
308 309
310
311
312
1
2
3
4
5
6
7
22
23
307
308
309
310
311
312
1
2
3
4
5
6
7
22
23
Burst phase=135 relative to U +V component Burst phase=225 relative to U -V component
Figure 4.
PAL Non-interlace Video Timing
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W55VG580
6. ELECTRICAL CHARACTERISTICS
6.1 Recommended Operating Conditions
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Power Supply Ambient Operating Temperature DAC Output Load External Voltage Reference
VAA TA RL VREF_IN
4.75 0 50 1.14
5.00 --1.235
5.25 70 -1.26
V C V
6.2
Absolute Maximum Ratings
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Power Supply ( Measured to ground) Ambient Operating Temperature Voltage on Any Signal Pin Storage Temperature Junction Temperature
VAA TA -TS TJ
--55 GND-0.5 -65 --
------
7 125 VAA+0.5 +150 +150
V C V C C
Note: This device employs high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any pin that exceeds the power supply voltage by more than +0.5V can cause destructive latch up.
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W55VG580
6.3 DC Characteristics
(Recommended operating conditions using external voltage reference with RSET= 67 , VREFIN= 1.235V, NTSC CCIR 601 operation and clock frequency= 27 MHz at 25C, +5V)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
VAA Supply Current Video D/A Resolution Integral Nonlinearity Differential Nonlinearity Maximum Output Current Output Compliance Video level Error Using External Reference Using Internal Reference Full-Scale DAC Output Digital Inputs Input High Voltage Input Low Voltage Input High current (Vin=2.4V) Input Low current (Vin=0.4V) Digital Outputs Output High Voltage (IOH=-400uA) Output Low Voltage (IOL=3.2mA) Three-State Current VREF_IN Input Current VREF_OUT Output Voltage VREF_OUT current
IAA@ 70C IAA@ 0C INL DNL VOC VIH VIL IIH IIL
8 0 2.0 GND-0.5 -
100 100 8 182.5 -
tbd tbd 8 +/- 1 +/- 1 26.04 1.5 5 10 VAA+0.5 0.8 1 -1
mA mA Bits LSB LSB mA V % % IRE V V uA uA
VOH VOL IOZ IREF_IN VREF_OUT IREF_OUT
2.4 1.064 -
10 1.18 10 0.4 50 1.298 -
V V uA uA V uA
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W55VG580
6.4 AC Characteristics
(Recommended operating conditions using external voltage reference with RSET=67 , VREFIN=1.235V, NTSC CCIR 601 operation and clock frequency=27 MHz at 25 C, +5V)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Luminance Bandwidth Chrominance Bandwidth Differential Gain Differential Phase SNR Hue Accuracy Color Saturation Accuracy Analog Output Delay Analog Output Rise Time Analog Output Settling Time Pixel/Control Setup Time Pixel/Control Hold Time Control Output Delay Time CLOCK Frequency CLOCK Pulse Width Low Time CLOCK Pulse Width High Time Pipeline Delay
5 1 2 3 Fin 4
0 6 24.54 10 10 -
Fin/4 1.3 1 1 60 1.5 1.5 30 3 30 15 27 28
3 3 29.5 -
MHz MHz % dB % ns ns ns ns ns ns MHz ns ns Clocks
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W55VG580
Level White Yellow Cyan Green Magenta Red Blue Black Blank
HSYNC BLANK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
mA 20.42 18.81 16.34 14.91 12.56 11.13 8.58 7.20 6.13
V 1.021 0.944 0.817 0.745 0.628 0.556 0.429 0.360 0.306
IRE 100 white yellow Cyan Green Magenta Red Blue 7.5 0 Black Blank
Sync
0
0
0.41
0.02
-40
Hsync
Note: 37.5 load is used. VREF_IN=1.235V, RSET=67 . 100% amplitude, 100% saturation are shown. RS170A levels and tolerance are assumed.
Figure 5.
NTSC Y (Luminance) Output Waveform
Level White Yellow Cyan Green Magenta Red Blue Black/ Blank Sync
HSYNC BLANK mA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 20.82 19.19 16.54 14.91 12.06 10.72 8.17 6.53
V 1.041 0.960 0.827 0.745 0.623 0.536 0.408 0.327
IRE 100 white yellow Cyan Green Magenta Red Blue 0 Black/Blank
0
0
0.41
0.020
-43
Hsync
Note: 37.5 load is used. VREF_IN=1.235V, RSET=67 . 100% amplitude, 100% saturation are shown. CCIRCCIR 624 levels and tolerance are assumed.
Figure 6.
PAL-BDGHI Y (Luminance) Output Waveform
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W55VG580
Color Cyan/Red Green/magenta Yellow/Blue Peak Burst Blank Peak Burst Yellow Blue Green/Magenta Cyan/Red
mA 21.44 20.93 28.99 15.92 13.07 10.21 7.15 5.21 4.7
V 1.071 1.047 0.950 0.794 0.653 0.510 0.357 0.260 0.235 Note: 37.5 load is used. VREF_IN=1.235V, RSET=67 . 100% amplitude, 100% saturation are shown. RS170A levels and tolerance are assumed. 20 IRE 20 IRE 3.58MHz ( 9 cycles)
Figure 7. NTSC C (Chroma) Output Waveform
Color Cyan/Red Green/magenta Yellow/Blue Peak Burst Blank Peak Burst Yellow Blue Green/Magenta Cyan/Red mA 22.15 21.54 19.50 16.13 13.07 10.00 6.64 4.59 3.98 V 1.107 1.077 0.975 0.806 0.653 0.500 0.332 0.230 0.199 21.5 IRE 21.5 IRE 4.43MHz (10 cycles)
Note: 37.5 load is used. VREF_IN=1.235V RSET=67 . 100% amplitude, 100% saturation are shown. CCIR 624 levels and tolerance are assumed.
Figure 8. PAL-BDGHI C (Chroma) Output Waveform
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W55VG580
Color/Level Peak Chroma White
HSYNC 1 1
BLANK 1 1
mA 24.80 20.42
V 1.240 1.021
IRE 134 100
Peak Burst Black Blank Peak Burst
1 1 1 1
1 1 0 0
8.99 7.20 6.13 3.27
0.449 0.360 0.306 0.164
20 7.5 0 -20
SYNC
0
0
0.41
0.020
-40
Note: 37.5 load is used. VREF_IN=1.235V, RSET=67 . 100% amplitude, 100% saturation are shown. RS170A levels and tolerance are assumed.
Figure 9. NTSC Composite Output Waveform
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W55VG580
Color/Level Peak Chroma White
HSYNC BLANK mA 1 1 25.61 1 1 20.82
V 1.281 1.041
IRE 133 100
Peak Burst Black/Blank Peak Burst
1 1 1
1 0 0
9.59 6.53 3.47
0.480 0.327 0.174
21.5 0 -21.5
SYNC
0
0
0.41
0.02
-43
Note: 37.5 load is used. VREF_IN=1.235V, RSET=67 . 100% amplitude, 100% saturation are shown. CCIR 624 levels and tolerance are assumed.
Figure 10. PAL-BDGHI Composite Output Waveform
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W55VG580
Analog Power Plane VAA COM
VREF_OUT
+5V (VDD) c4 c1-c3 c5 RSET 75 75 L1 R1 c7 Z1 c6 To Power Supply Ground
VREF_IN AGND FSADJ CVBS_Y CVBS_C
To Video Connectors (75 load)
VAA
=
LOW PASS FILTER
To Connector GND
PART NUMBER
VALUE
VENDOR NUMBER
c1-c6 c7 L1 R1 RSET Z1
0.1uF (Ceramic) 47uF Ferrite bead 1KW (5% ) 1% Metal Film 1.2V Zener Diode
Erie RPE112Z5U104M50V Mallory CSR13F476KM Fair-Rite 2743001111 Dale CMF-55C LM358BZ-1.2
Note: 1. The vendor number is are only for reference. 2. RSET is determined by (Iout=full scale output current)
RSET () = 2015 * VREF _ IN (V ) / Iout (mA)
Figure 11. Typical connection diagram and part list(using external voltage reference)
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W55VG580
Analog Power Plane VAA COM VREF_OU VREF_IN RSET 75 75 c4 c1-c3 c5 Z1 L1 c7 c6 To Power Supply Ground +5V (VDD)
FSADJ AGND CVBS_Y CVBS_C
To Video Connectors (75 load)
VAA LOW PASS
=
FILTER
To Connector GND
PART NUMBER
VALUE
VENDOR NUMBER
c1-c6 c7 L1 RSET
0.1uF (Ceramic) 47uF Ferrite bead 1% Metal Film
Erie RPE112Z5U104M50V Mallory CSR13F476KM Fair-Rite 2743001111 Dale CMF-55C
Note: 1. The vendor number is are only for reference. 2. RSET is determined by (Iout=full scale output current)
RSET () = 2015 * VREF _ IN (V ) / Iout (mA)
Figure 12. Typical connection diagram and part lis (using internal voltage reference)
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W55VG580
CLOCK
pixel P[7:0] HSYNCN,VSYNCN (slave mode) 1 2
Pixel 1
4 pixel 1 pixel 0 3 5
Analog output
Figure 13. Video Input and Output Timing
CLOCK
P[7:0]
Cb0
Y0
Cr0
Y1
HSYNCN,VSYNCN
Figure 14. pixel sequence at power on reset (The pixel sequence can be swap changed by setting the CBSWAP pin and the MODE[3] pin at in slave mode)
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W55VG580
OPERATING MODE
ACTIVE PIXELS
TOTAL PIXELS
CLK FREQUENCY (MHZ)
NTSC/PAL-M CCIR601CCIR 601 PAL-B,D,G,H,I,Nc NTSC/PAL-M Square pixel PAL-B,D,G,H,I,Nc Square pixel
720 x 240 720 x 288 640 x 240 768 x 288
858 x 262 864 x 313 780 x 262 944 x 312
27 27 24.545454 29.5
Table1. Field Resolution and clock Rates for Various Modes of Operation
a
b d c e
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Publication Release Date: May, 2006 Revision A5
W55VG580
OPERATION MODE
FRONT PORCH (E)
HORIZONTAL SYNC WIDTH (B)
START OF BURST (C)
DURATION OF BURST (D)
BACK PORCH (E)
NTSC CCIR601CCIR 601 PAL-M CCIRCCIR 610 PAL-B CCIR601CCIR 601 PAL-Nc CCIR601CCIR 601 NTSC SQUARE PAL-M SQUARE PAL-B SQUARE PAL-Nc SQUARE
20 20 20 20 18 18 22 22
63 63 63 63 58 58 69 69
72 78 76 76 65 71 83 83
34 34 30 34 31 31 33 37
127 127 142 142 115 115 155 155
Notes: (1) The unit is the number of luminance pixels.
Table 2. Various Video Timing
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W55VG580
7. PACKAGE INFORMATION
PART NO. PACKAGE AMBIENT TEMPERATURE RANGE
W55VG580P W55VG580YG W55VG580H W44VG580W
PLCC-32 QFN-32 Chip form Wafer form
0 C ~70 C 0 C ~70 C 0 C ~70 C 0 C ~70 C
plcc
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Publication Release Date: May, 2006 Revision A5
W55VG580
SYMBOL
INCHES MIN TYP MAX MIN
MM TYP MAX
A A1 B B1 D D1 D2 E E1 E2 e N Nd Ne
0.1 0.06 0.013 0.026 0.485 0.447 0.39 0.585 0.547 0.49 0.05
0.14 0.095 0.021 0.032 0.495 0.455 0.43 0.595 0.555 0.53
2.54 1.52 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.54 1.27 32 7 9
3.56 2.41 0.53 0.81 12.57 11.56 10.92 15.11 14.1 13.46
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W55VG580
QFN-32
L
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Publication Release Date: May, 2006 Revision A5
W55VG580
W55VG580H Bonding Pad Diagram
Window: (xl = -1435.00, yl = -1485.00), (xh = 1435.00, yh = 1485.00). Windows size: width = 2870.00, length = 2970.00
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W55VG580
PAD NO.
PAD NAME
X(M)
Y(M)
PAD NO.
PAD NAME
X(M)
Y(M)
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
FSADJ
COMP VAA VAA VREF_OUT VREF_IN NC CVBS_C AGND AGND SLEEP SVIDEO CBSWAP MASTER MODE <3> MODE <2> MODE <1>
-1338.56
-1338.56 -1338.56 -1338.56 -1338.56 -1338.56 -1338.56 -1338.56 -1338.56 -1338.56 -1293.56 -1135.86 -807.66 -481.06 -152.86 173.74 501.94
855.24
538.31 297.44 212.44 -6.37 -212.14 -451.27 -711.12 -898.11 -983.11 -1211.20 -1342.30 -1342.30 -1342.30 -1342.30 -1342.30 -1342.30
18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
MODE <0>
P<0> P<1> P<2> P<3> P<4> P<5> P<6> P<7> CLK DGND VDD VSYNCN HSYNCN TEST AGND CVBS_Y
828.54
1156.74 1287.84 1287.84 1287.84 1287.84 1287.84 1287.84 1287.84 1155.92 883.02 636.54 288.47 -76.41 -442.89 -882.55 -1192.35
-1342.30
-1342.30 -1063.60 -713.23 -364.45 -14.08 334.70 685.08 1033.85 1313.03 1313.03 1313.03 1313.03 1313.03 1313.03 1313.03 1313.03
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Publication Release Date: May, 2006 Revision A5
W55VG580
8. APPLICATION CIRCUIT
J1
2
Video Out
1
C1
Opction
470uF
R1 75
C? Vdd 0.1U
PAL
NTSC
14
29
13 28 12 11 32 18 17
15
J2
2
S?
SW SPDT Master
16
VDD
Mode2
Mode1 Mode3 DGNDSLEEP Mode0 SVIDEO TEST(TP) CBSWAP
CVBSC Vref_In Vref_Out
Audio Out
8
1 4.7U
C? .1U 0
6 5
C? 180
34 9 10 39
CVBS_Y AGND2 AGND1 AGND
R?
R? W55VG580
4 3 2 VAA4 VAA5 COMP FSADJ(RSET)
68
1
Vaa
C? 0.1U
/Hsync /Vsync Clk NC(VB) 31 30 27 7
P0 19
P1 20
P2 21
P3 22
P4 23
P5 24
P6 25
P7 26
Vdd
PAL
Vdd JP?
JP? R? R?
NTSC
JP?
JP? R? R? R? RESISTOR 100K 100K 100K 100K
W567R
R? JP?
S?
JP? 100K
0.1U C? 37 29 28 27
Reset 36 26 P0 25 P1 24 P2 23 P3 22 P4 21 P5 20 P6 19 P7 DAC
CD0 39
34
Clk VSS2
38
VCC
JP2
Vsync VDD2Hsync
/RESET
Vdd
33 VSS1 CD1
JP1
40
C?
0.1U
32
VDD1 Xout 30
C?
9
VSS
R14 C? Vdd
41
0.1U
10
VDD /TSM
W55VG080 Chip Form
Y?
27MHz
C?
Xin
31
JP4 VCC IP0.0 1 IP0.1 2 IP0.2 3 IP0.3 4 IP0.4 5 IP0.5 6 IP0.6 7 IP0.7 8 BP0.0 BP0.2 BP0.4 BP0.6TEST_0 BP0.1 BP0.3 BP0.5 BP0.7 RDY 11 12 13 14 15 16 17 18 42 35 R? Default
4.7K
Vdd
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W55VG580
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
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Publication Release Date: May, 2006 Revision A5

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