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| TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L Series TMP93CW46A Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = (NMI , INT0), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2/RUN are not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP93CW46A Low Voltage/Low Power CMOS 16-Bit Microcontroller TMP93CW46AF 1. Outline and Device Characteristics The TMP93CW46AF is high-speed advanced 16-bit microcontroller to enable low voltage and low power consumption operation. The TMP93CW46AF is housed in 100-pin mini flat package. The device characteristics are as follows: (1) Original 16-bit CPU (900/L CPU) * * * * * TLCS-90 instruction mnemonic upward compatible 16-Mbyte linear address space General-purpose registers and register bank system 16-bit multiplication/division and bit transfer/arithmetic instructions Micro DMA: 4 channels (1.6 s/2 bytes at 20 MHz) (2) Minimum instruction execution time: 200 ns at 20 MHz (3) Internal RAM: 4 Kbytes Internal ROM: 128 Kbytes (4) External memory expansion * * Can be expanded up to 16 Mbytes (for both programs and data). Can mix 8- and 16-bit external data buses. ...Dynamic data bus sizing (5) 8-bit timer: 2 channels (6) 8-bit PWM timer: 2 channels (7) 16-bit timer: 2 channels (8) Serial interface: 5 channels * * UART/synchronous modes: 4 channels UART mode: 1 channel 030619EBP1 (9) 10-bit AD converter: 8 channels * The information contained herein is subject to change without notice. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 93CW46A-1 2004-02-10 TMP93CW46A (10) Watchdog timer (11) Chip select/wait controller: 3 blocks (12) Interrupt functions: 35 * * * * 9 CPU interrupts ... SWI instruction, and Illegal instruction 20 internal interrupts 6 external interrupts 7-level priority can be set. (13) I/O ports: 79 Large current output: 6 pins, LED direct drive 4 HALT modes (RUN, IDLE2, IDLE1, STOP) (15) Clock gear function * * * High-frequency clock can be changed fc to fc/16. Dual clock operation VCC = 2.7 to 5.5 V (14) Standby function (16) Operating voltage (17) Package: P-LQFP100-1414-0.50F Note: Note that TMP93CW46A is different from OTP type TMP93PW46A in the electrical characteristics as follows. See the respective electrical characteristics for details. * Power supply current ICC * Large current port IOLA 93CW46A-2 2004-02-10 TMP93CW46A PA0 to PA6 PA7 (SCOUT) Port A CPU VCC [3] VSS [3] Highfrequency OSC X1 X2 CLK Lowfrequency OSC XT1 XT2 AM8/ AM16 EA RESET P50 to P57 (AN0 to AN7) AVCC AVSS VREFH VREFL 10-bit 8-ch AD converter (TXD0) P90 (RXD0) P91 (SCLK0/ CTS0 ) P92 (TXD1) P93 (RXD1) P94 (SCLK1) P95 XWA XBC XDE XHL XIX XIY XIZ XSP Serial I/O (Channel 0) Serial I/O (Channel 1) WA BC DE HL IX IY IZ SP 32 bits SR PC F ALE TEST2, TEST1 Interrupt controller P87 (INT0) NMI (TXD2) P60 (RXD2) P61 (SCLK2/ CTS2 ) P62 (TXD3) P63 (RXD3) P64 (SCLK3/ CTS3 ) P65 (TXD4) P66 (RXD4) P67 Serial I/O (Channel 2) Serial I/O (Channel 3) Serial I/O (Channel 4) Watchdog timer WDTOUT 4-Kbyte RAM Port 0 P00 to P07 (AD0 to AD7) (TI0) P70 8-bit timer (Timer 0) 8-bit timer (Timer 1) Port 1 (TO1) P71 P10 to P17 (AD8 to AD15/ A8 to A15) P20 to P27 (A0 to A7/A16 to A23) Port 2 (TO2) P72 8-bit PWM (Timer 2) 8-bit PWM (Timer 3) P30 ( RD ) P31 ( WR ) P32 ( HWR ) P33 ( WAIT ) P34 ( BUSRQ P36 (R/ W ) P37 ( RAS ) CS/WAIT controller (3 blocks) P40 ( CS0 / CAS0 ) P41 ( CS1 / CAS1 ) P42 ( CS2 / CAS2 ) (TO3) P73 128-Kbyte ROM Port 3 ) (INT4/TI4) P80 (INT5/TI5) P81 (TO4) P82 (TO5) P83 (INT6/TI6) P84 (INT7/TI7) P85 (TO6) P86 P35 ( BUSAK ) 16-bit timer (Timer 4) 16-bit timer (Timer 5) Figure 1.1 TMP93CW46A Block Diagram 93CW46A-3 2004-02-10 TMP93CW46A 2. Pin Assignment and Functions The assignment of input/output pins for the TMP93CW46AF, their names and outline functions are described below. Programmable Pull Pull down up Programmable Pull Pull up down TMP93CW46A P66/TXD4 P67/RXD4 VSS P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 VREFH VREFL AVSS AVCC NMI Pin no. 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Pin no. TMP93CW46A 88 P65/ CTS3 /SCLK3 87 P64/RXD3 86 P63/TXD3 85 P62/ CTS2 /SCLK2 84 P61/RXD2 83 P60/TXD2 82 P42/ CS2 / CAS2 81 P41/ CS1 / CAS1 80 P40/ CS 0 / CAS 0 79 P37/ RAS 78 P36/ R / W 77 P35/ BUSAK 76 P34/ BUSRQ 75 P33/ WAIT 74 P32/ HWR 73 P31/ WR 72 71 70 69 68 67 66 65 64 63 62 60 59 58 57 56 55 54 53 52 51 P30/ RD P27/A7/A23 P26/A6/A22 P25/A5/A21 P24/A4/A20 P23/A3/A19 P22/A2/A18 P21/A1/A17 P20/A0/A16 VCC VSS P17/AD15/A15 P16/AD14/A14 P15/AD13/A13 P14/AD12/A12 P13/AD11/A11 P12/AD10/A10 P11/AD9/A9 P10/AD8/A8 P07/AD7 P06/AD6 SIO ADC SIO P70/TI0 P71/TO1 P72/TO2 P73/TO3 P80/INT4/TI4 P81/INT5/TI5 P82/TO4 P83/TO5 P84/INT6/TI6 P85/INT7/TI7 P86/TO6 P87/INT0 P90/TXD0 P91/RXD0 P93/TXD1 P94/RXD1 P95/SCLK1 AM8/ AM16 CLK VCC VSS Timer Top view LQFP100 61 WDTOUT P92/ CTS 0 /SCLK0 19 50 P05/AD5 49 P04/AD4 48 P03/AD3 47 P02/AD2 46 P01/AD1 45 P00/AD0 44 VCC 43 ALE 42 PA7/SCOUT 41 PA6 40 PA5 39 PA4 38 PA3 Clock, Mode X1 X2 EA RESET P96/XT1 P97/XT2 TEST1 TEST2 PA0 PA1 PA2 2.1 Pin Assignment Figure 2.1.1 shows pin assignment of the TMP93CW46AF. Figure 2.1.1 Pin Assignment (100-Pin LQFP) 93CW46A-4 2004-02-10 Memory interface TMP93CW46A 2.2 Pin Names and Functions The names of input/output pins and their functions are described below. Table 2.2.1 to Table 2.2.4 show pin names and functions. Table 2.2.1 Pin Names and Functions (1/4) Pin Names P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30 RD Number of Pins 8 8 I/O I/O 3 states I/O 3 states Output I/O Output Output Functions Port 0: I/O port that allows selection of I/O on a bit basis Address/Data (Lower): Bits 0 to 7 of address/data bus Port 1: I/O port that allows selection of I/O on a bit basis Address data (Upper): Bits 8 to 15 of address/data bus Address: 8 to 15 of address bus Port 2: I/O port that allows selection of I/O on a bit basis (with pull-down resistor) Address: Bits 0 to 7 of address bus Address: Bits 16 to 23 of address bus Port 30: Output port Read: Strobe signal for reading external memory Port 31: Output port Write: Strobe signal for writing data on pins AD0 to AD7 Port 32: I/O port (with pull-up resistor) High write: Strobe signal for writing data on pins AD8 to AD15 Port 33: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait Port34: I/O port (with pull-up resistor) Bus request: Signal used to request high impedance for AD0 to AD15, A0 to A23, RD , WR , HWR , R/ W , RAS , CS0 , CS1 , and CS2 pins. (For external DMAC) Port 35: I/O port (with pull-up resistor) Bus acknowledge: Signal indicating that AD0 to AD15, A0 to A23, RD , WR , HWR , R/ W , RAS , CS0 , CS1 , and CS2 pins are at high impedance after receiving BUSRQ. (For external DMAC) Port 36: I/O port (with pull-up resistor) Read/Write: 1 represents read or dummy cycle. 0 represents write cycle. Port 37: I/O port (with pull-up resistor) Row address strobe: Outputs RAS strobe for DRAM. Port 40: I/O port (with pull-up resistor) Chip select 0: Outputs 0 when address is within specified address area. Column address strobe 0: Outputs CAS strobe for DRAM when address is within specified address area. 8 1 1 1 1 1 Output Output Output Output I/O Output I/O Input I/O Input P31 WR P32 HWR P33 WAIT P34 BUSRQ P35 BUSAK 1 I/O Output P36 R/ W P37 RAS 1 I/O Output I/O Output I/O Output Output 1 1 P40 CS0 CAS0 Note: This device's built-in memory or built-in I/O cannot be accessed with the external DMA controller, using the BUSRQ and BUSAK signals. 93CW46A-5 2004-02-10 TMP93CW46A Table 2.2.2 Pin Names and Functions (2/4) Pin Names P41 CS1 CAS1 Number of Pins 1 I/O I/O Output Output I/O Output Output Input Input Input Input I/O Output I/O Input I/O Input I/O I/O Output I/O Input I/O Input I/O I/O Output I/O Input I/O Input I/O Output I/O Output I/O Output Functions Port 41: I/O port (with pull-up resistor) Chip select 1: Outputs 0 if address is within specified address area. Column address strobe 1: Outputs CAS strobe for DRAM if address is within specified address area. Port 42: I/O port (with pull-down resistor) Chip select 2: Outputs 0 if address is within specified address area. Column address strobe 2: Outputs CAS strobe for DRAM if address is within specified address area. Port 5: Input port Analog input: Analog signal input for AD converter Pin for high level reference voltage input to AD converter Pin for low level reference voltage input to AD converter Port 60: I/O port (with pull-up resistor) Serial send data 2 Port 61: I/O port (with pull-up resistor) Serial receive data 2 Port 62: I/O port (with pull-up resistor) Serial data send enable 2 (Clear to send) Serial Clock I/O 2 Port 63: I/O port (with pull-up resistor) Serial receive data 3 Port 64: I/O port (with pull-up resistor) Serial receive data 3 Port 65: I/O port (with pull-up resistor) Serial data send enable 3 (Clear to send) Serial Clock I/O 3 Port 66: I/O port (with pull-up resistor) Serial send data 4 Port 67: I/O port (with pull-up resistor) Serial receive data 4 Port 70: I/O port (with pull-up resistor) Timer input 0: Timer 0 input Port 71: I/O port (with pull-up resistor) Timer output 1: Timer 0 or 1 output Port 72: I/O port (with pull-up resistor) PWM output 2: 8-bit PWM timer 2 output Port 73: I/O port (with pull-up resistor) PWM output 3: 8-bit PWM timer 3 output P42 CS2 CAS2 1 P50 to P57 AN0 to AN7 VREFH VREFL P60 TXD2 P61 RXD2 P62 CTS2 8 1 1 1 1 1 SCLK2 P63 TXD3 P64 RXD3 P65 CTS3 1 1 1 SCLK3 P66 TXD4 P67 RXD4 P70 TI0 P71 TO1 P72 TO2 P73 TO3 1 1 1 1 1 1 93CW46A-6 2004-02-10 TMP93CW46A Table 2.2.3 Pin Names and Functions (3/4) Pin Names P80 TI4 INT4 P81 TI5 INT5 P82 TO4 P83 TO5 P84 TI6 INT6 P85 TI7 INT7 P86 TO6 P87 INT0 P90 TXD0 P91 RXD0 P92 CTS0 Number of Pins 1 I/O I/O Input Input I/O Input Input I/O Output I/O Output I/O Input Input I/O Input Input I/O Output I/O Input I/O Output I/O Input I/O Input I/O I/O Output I/O Input I/O I/O I/O I/O Functions Port 80: I/O port (with pull-up resistor) Timer input 4: Timer 4 count/capture trigger signal input Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge Port 81: I/O port (with pull-up resistor) Timer input 5: Timer 4 count/capture trigger signal input Interrupt request pin 5: Interrupt request pin with rising edge Port 82: I/O port (with pull-up resistor) Timer output 4: Timer 4 output pin Port 83: I/O port (with pull-up resistor) Timer output 5: Timer 4 output pin Port 84: I/O port (with pull-up resistor) Timer input 6: Timer 5 count/capture trigger signal input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge Port 85: I/O port (with pull-up resistor) Timer input 7: Timer 5 count/capture trigger signal input Interrupt request pin 7: Interrupt request pin with rising edge Port 86: I/O port (with pull-up resistor) Timer output 6: Timer 5 output pin Port 87: I/O port (with pull-up resistor) Interrupt request pin 0: Interrupt request pin with programmable level/rising edge Port 90: I/O port (with pull-up resistor) Serial send data 0 Port 91: I/O port (with pull-up resistor) Serial receive data 0 Port 92: I/O port (with pull-up resistor) Serial data send enable 0 (Clear to send) Serial Clock I/O 0 Port 93: I/O port (with pull-up resistor) Serial send data 1 Port 94: I/O port (with pull-up resistor) Serial receive data 1 Port 95: I/O port (with pull-up resistor) Serial clock I/O 1 Port A0 to A5: I/O ports (large current output) Port A6: I/O port 1 1 1 1 1 1 1 1 1 1 SCLK0 P93 TXD1 P94 RXD1 P95 SCLK1 PA0 to PA5 PA6 1 1 1 6 1 93CW46A-7 2004-02-10 TMP93CW46A Table 2.2.4 Pin Names and Functions (4/4) Pin Names PA7 SCOUT WDTOUT Number of Pins 1 I/O I/O Output Output Input Output Functions Port A7: I/O port System clock output: Outputs system clock or 2 times oscillation clock for synchronizing to external circuit. Watchdog timer output pin Non-maskable interrupt request pin: Interrupt request pin with falling edge. Can also be operated at rising edge by program. Clock output: Outputs "System clock / 2" clock. Pulled-up during reset. Can be disabled for reducing noise. 1 1 1 NMI CLK EA 1 1 1 1 2 1 1 2 3 3 1 1 Input Input Output Input I/O Input I/O Output I/O Output/Input Fixed to "1". Fixed to "1". Address latch enable (Can be disabled for reducing noise.) Reset: Initializes LSI (with pull-up resistor). High-frequency oscillator connecting pin Low-frequency oscillator connecting pin Port 96: I/O port (Open-drain output) Low-frequency oscillator connecting pin Port 97: I/O port (Open-drain output) TEST1 should be connected with TEST2 pin. Do not connect to any other pins. Power supply pin (All VCC pins are connected to the power supply source.) GND pin (All VSS pins are connected to the GND (0 V).) Power supply pin for AD converter GND pin for AD converter (0 V) AM8/ AM16 ALE RESET X1/X2 XT1 P96 XT2 P97 TEST1/TEST2 VCC VSS AVCC AVSS Note: Built-in pull-up/pull-down resistors can be released from the pins other than the RESET pin by software. 93CW46A-8 2004-02-10 TMP93CW46A 3. Operation This section describes the functions and basic operational blocks of the TMP93CW46A devices. See the 7. "Points of Note and Restrictions" for the using notice and restrictions for each block. 3.1 CPU The TMP93CW46A device has a built-in high-performance 16-bit CPU (900/L CPU). (For CPU operation, see TLCS-900/L CPU in the previous chapter.) This section describes CPU functions unique to the TMP93CW46A that are not described in the previous chapter. 3.1.1 Reset When resetting the TMP93CW46A microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then set the RESET input to low level at least for 10 system clocks (16 s at 20 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by reset operation. It means that the system clock mode fSYS is set to fc/32 (= fc/16 x 1/2). When reset is accepted, the CPU sets as follows: * Program counter (PC) according to reset vector that is stored 8000H to 8002H. PC<7:0> Data located at 8000H PC<15:8> Data located at 8001H PC<23:16> Data located at 8002H Note: The address in which the reset vector is stored depends on the respective derivative products. Stack pointer (XSP) for system mode to 100H. * * * * Status register When reset is released, instruction execution starts from PC (Reset vector). CPU internal registers other than the above are not changed. When reset is accepted, processing for built-in I/Os, ports, and other pins are as follows. * * * * * Initializes built-in I/O registers as per specifications. Sets port pins (including pins also used as built-in I/Os) to general-purpose input/output port mode. Sets WDTOUT pin to "0". (Resetting enables the watchdog timer.) Pulls up the CLK pin to 1. Sets the ALE pin to high impedance (High-Z). Note 1: By resetting, register in the CPU except program counter (PC), status register (SR) and stack pointer (XSP) and the data in internal RAM are not changed. Note 2: The CLK pin is pulled up during reset. When the voltage is put down externally, there is possible to cause malfunctions. Figure 3.1.1 shows the reset timing chart of TMP93CW46A. 93CW46A-9 2004-02-10 Omitted 45 times of X1 Omitted 220 times of X1 X1 CLK Sampling (P20 to P27 input mode) (P40 to P41 input mode) (P42 input mode) (P36 input mode) Sampling RESET A16 to A23 CS0 to CS1 CS2 R/W ALE Address Address AD0 to AD15 RD Address Data output Address Read (Starts read cycle of 0 waits after reset release) Write AD0 to AD15 WR HWR RAS (P37 input mode) (P40 to P41 input mode) (P42 input mode) (Input mode) (Input mode) (Input mode) (Output mode: open drain output) (P32 input mode) Figure 3.1.1 TMP93CW46A Reset Timing Chart 93CW46A-10 CAS2 Internal pull up or pull down High impedance CAS0 to CAS1 P20 to P27, P42 P32 to P37, P40 to P41 P60 to P67, P70 to P73 P80 to P87, P90 to P95 P50 to P57, A0 to A7 P96 to P97 TMP93CW46A 2004-02-10 TMP93CW46A 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP93CW46A. 000000H Internal I/O (128 bytes) 256-byte direct area (n) 000080H 000100H Internal RAM (4 Kbytes) 001080H 64-Kbyte area (nn) External memory 008000H 008100H 010000H Interrupt vector table area (64 entries x 4 bytes) 128-Kbyte internal ROM 028000H External memory 16-MByte area (R) (-R) (R +) (R + R8/16) (R + d8/16) (nnn) FFFF00H FFFFFFH Reserved (256 bytes) ( = Internal area) Note: The 256-byte area from FFFF00H to FFFFFFH can not be used. Figure 3.2.1 Memory Map 93CW46A-11 2004-02-10 TMP93CW46A 3.3 Standby Function Standby control circuits consist of (1) System clock controller, (2) Prescaler clock controller, and (3) Standby controller. The Oscillator operating mode is classified to (a) Single clock mode (Only X1, X2 pin), and (b) Dual clock mode (X1, X2, XT1, XT2 pin). Figure 3.3.1 shows a transition figure. Figure 3.3.2 shows the block diagram. Reset RUN mode (Stops only CPU) IDLE2 mode (Stops CPU and AD) Instruction Interrupt Instruction Interrupt Instruction Release reset Instruction Interrupt NORMAL mode (fc/gear_value/2) STOP mode (Stops all circuits) Interrupt IDLE1 mode (Operates only oscillator) (a) Signal Clock Mode Transition Figure Reset RUN mode (Stops only CPU) IDLE2 mode (Stops CPU and AD) IDLE1 mode (Operates only oscillator) RUN mode (Stops only CPU) IDLE2 mode (Stops CPU and AD) IDLE1 mode (Operates only oscillator) Instruction Interrupt Instruction Interrupt Instruction Interrupt Interrupt Instruction Instruction Interrupt Instruction Interrupt Instruction Interrupt Instruction Release reset NORMAL mode (fc/gear_value/2) Instruction STOP mode (Stops all circuits) SLOW mode (fs/2) (b) Dual Clock Mode Transition Figure Figure 3.3.1 Transition Figure The clock frequency input from X1, X2 pin is called fc, and the clock frequency selected by SYSCR1 93CW46A-12 2004-02-10 TMP93CW46A Table 3.3.1 Internal Operation and System Clock Operating Mode RESET Single clock NORMAL RUN IDLE2 IDLE1 STOP RESET NORMAL Dual clock SLOW RUN IDLE2 IDLE1 STOP Oscillation Programmable Stop Stop Programmable Oscillation Reset Operate Oscillation Stop Stop Oscillator High Frequency (fc) Low Frequency (fs) CPU Reset Operate Internal I/O Reset Operate Stop only AD Stop Reset System Clock fSYS fc/32 Programmable (fc/2, fc/4, fc/8, fc/16, fc/32) Stop fc/32 Programmable (fc/2, fc/4, fc/8, fc/16, fc/32) Operate fs/2 Programmable (fc/2, fc/4, fc/8, fc/16, fc/32, fs/2) Stop Oscillator using as system clock: Oscillation Other oscillator: Programmable Stop Stop Stop only AD Stop 93CW46A-13 2004-02-10 * Warm up (Changing clocks) .................... fc or fs. * Warm up (Releasing STOP mode) .......... fFPH * Watchdog timer ....................................... fSYS fc fs Watchdog timer/ Warm-up timer SYSCR0 8-bit PWMs 0 and 1 5-bit prescaler Run & stop TRUN fs fc/16 Selector 9-bit prescaler /2 /4 8-bit timers 0 and 1 16-bit timers 4 and 5 Serial interfaces 0 to 4 Figure 3.3.2 Block Diagram of Dual Clock, Standby Circuits SYSCR0 93CW46A-14 SYSCR0 Low-frequency oscillator Selector Internal I/O ROM, RAM System clock fSYS fFPH XT2 XT1 CPU /2 /2 Selector CLK SYSCR1 WDMOD fc/2 fc/4 fc/8 fc/16 SYSCR0 High-frequency oscillator SCOUT/PA7 SYSCR1 TMP93CW46A 2004-02-10 /2 /4 /8 /16 CKOCR TMP93CW46A SYSCR0 (006EH) 7 Bit symbol XEN Read/Write After reset 1 Function Highfrequency oscillator (fc) 0: Stop 1: Oscillation 6 XTEN 0 Lowfrequency oscillator (fs) 0: Stop 1: Oscillation 5 RXEN 1 Highfrequency oscillator (fc) after released STOP mode 0: Stop 1: Oscillation 4 RXTEN R/W 0 Lowfrequency oscillator (fs) after released STOP mode 0: Stop 1: Oscillation 3 RSYSCK 0 Slect clock after released STOP mode 0: fc 1: fs 2 WUEF 0 Warm-up timer (Write) 0: Don't care 1: Start timer (Read) 0: End warm-up 1: Not end warm-up 1 PRCK1 0 PRCK0 0 0 Select prescaler clock 00: fFPH 01: fs 10: fc/16 11: (Reserved) 7 SYSCR1 (006FH) Bit symbol Read/Write After reset Function 6 5 4 3 SYSCK 0 Select system clock 0: fc 1: fs 2 GEAR2 1 GEAR1 0 GEAR0 R/W 1 0 0 Select gear value of high frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 2 HALTM0 0 1 RESCR 0 0 DRVE 0 WDMOD (005CH) 7 6 5 Bit symbol WDTE WDTP1 WDTP0 Read/Write After reset 1 0 0 Function WDT control WDT detection time 1: Enable 00: 215/fSYS 01: 217/fSYS 10: 219/fSYS 11: 221/fSYS 4 WARM R/W 0 Warm-up timer 0: 214/ inputted frequency 1: 216/ inputted frequency 3 HALTM0 0 Standby mode 00: 01: 10: 11: RUN mode STOP mode IDLE1 mode IDLE2 mode 1: Connects 1: Drives WDT pin even output to in STOP mode RESET pin internally. 1 ALEEN 0 CLKEN 0/1(Note 2) CLK pin output control 0: High-Z output 1: CLK output 7 CKOCR (006DH) Bit symbol Read/Write After reset Function 6 5 4 3 SCOSEL 0 SCOUT select 0: fFPH 1: fSYS 2 SCOEN R/W 1 0/1(Note 2) ALE pin SCOUT output output control control 0: I/O ports 0: High-Z output 1: SCOUT 1: ALE output output Note 1: Note 2: Note 3: SYSCR1 Figure 3.3.3 I/O Register about Dual Clock and Standby 93CW46A-15 2004-02-10 TMP93CW46A 3.3.1 System Clock Controller The system clock controller generates system clock (fSYS) for CPU core and internal I/O. It contains two oscillation circuits and clock gear circuit for high frequency (fc). The register SYSCR1 High-frequency Clock X1 X2 X1 X2 XT1 Low-frequency Clock XT2 XT1 XT2 (Open) 74HCU04 * See application circuit in chapter 5 (a) Crystal/ceramic resonator (b) External oscillator (c) Crystal resonator (d) External oscillator Figure 3.3.4 Examples of Resonator Connection Note 1: Note on using low-frequency oscillation circuit To connect the low-frequency resonator to port 96, 97, it is necessary to set the following to reduce the power consumption. (Connecting with resonators) P9CR 93CW46A-16 2004-02-10 TMP93CW46A (1) Switching NORMAL to SLOW mode When the resonator is connected to X1, X2, or XT1, XT2 pin, the warm-up timer is used to change the operation frequency after getting stabilized oscillation. The warm-up time can be selected by WDMOD 0 (214/frequency) 1 (2 /frequency) 16 Change to NORMAL 0.8192 (ms) 3.2768 (ms) Change to SLOW 500 (ms) 2000 (ms) at fc = 20 MHz, fs = 32.768 kHz 93CW46A-17 2004-02-10 TMP93CW46A Setting example 1 The case of changing from high frequency (fc) to low frequency (fs). SYSCR0 SYSCR1 WDCR WDMOD EQU EQU EQU EQU RES LD SET SET SET BIT JR SET RES SET 006EH 006FH 005DH 005CH 7, (WDMOD) (WDCR), B1H 4, (WDMOD) 6, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 7, (SYSCR0) 7, (WDMOD) WUP: ; Disables watchdog timer. ; ; Sets warm-up time to 216/fs. ; Enables low-frequency oscillation ; Clears and starts warm-up timer. ; Detects end of warm-up timer. ; ; Changes fSYS from fc to fs. ; Disables high-frequency oscillation. ; Enables watchdog timer. Enables Clears and starts low frequency warm-up timer Changes fSYS Disables high frequency from fc to fs End of warm-up timer 93CW46A-18 2004-02-10 TMP93CW46A Setting example 2 The case of changing from low frequency (fs) to high frequency (fc). SYSCR0 SYSCR1 WDCR WDMOD EQU EQU EQU EQU RES LD RES SET SET BIT JR RES RES SET 006EH 006FH 005DH 005CH 7, (WDMOD) (WDCR), B1H 4, (WDMOD) 7, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 6, (SYSCR0) 7, (WDMOD) WUP: ; ; Disables watchdog timer. ; Sets warm-up time to 214/fc. ; Enables high frequency (fc). ; Clears and starts warm-up timer. ; Detects end of warm-up timer. ; ; Changes fSYS from fs to fc. ; Disables low-frequency oscillation. ; Enable watchdog timer Enables high frequency Clears and starts warm-up timer 93CW46A-19 2004-02-10 TMP93CW46A (2) Clock gear controller When the high-frequency clock fc is selected at SYSCR1 SYSCR1 EQU LD LD X: Don't care 006FH (SYSCR1), XXXX0000B (SYSCR1), XXXX0100B ; Changes fSYS to fc/2 ; Changes fSYS to fc/32 (High-speed clock gear changing) To change the clock gear, write the register value to SYSCR1 SYSCR1 EQU LD 006FH (SYSCR1), XXXX0001B ; Changes fSYS to fc/4. LD (DUMMY), 00H ; Dummy instruction Instruction to be executed by the clock gear after changing 3.3.2 Prescaler Clock Controller The 9-bit prescaler provides a clock to 8-bit timers 0 and 1, 16-bit timers 4 and 5, and serial interfaces 0 to 4. And the 5-bit prescaler provides a clock to 8-bit PWMs 0 and 1. The clock input to the 5-bit prescaler is a clock divided by 2 which is selected by fFPH, fc/16 or fs by SYSCR0 93CW46A-20 2004-02-10 TMP93CW46A 3.3.3 Internal Clock Pin Output Function (1) PA7/SCOUT pin PA7/SCOUT pin outputs the internal clocks fFPH or fSYS. The port A control register PACR Operation Mode Output Clock fFPH fSYS NORMAL, SLOW HALT Mode RUN, IDLE2, IDLE1 Outputs fFPH clock. Outputs fSYS clock. STOP Fixed to "0" or "1". (2) CLK pin CLK pin outputs fSYS divided by 2 internal clock. Outputs are specified by the clock output control register CKOCR TMP93CW46A CKOCR 0 CLK Pin Operation High impedance Note: To set 93CW46A-21 2004-02-10 TMP93CW46A 3.3.4 Standby Controller (1) HALT mode When the HALT instruction is executed, the operating mode changes RUN, IDLE2, IDLE1 or STOP mode depending on the contents of the HALT mode setting register WDMOD WDMOD Bit symbol (005CH) Read/Write After reset Function WDTE 1 Watchdog timer control 0: Disable 1: Enable 6 WDTP1 0 5 WDTP0 0 4 WARM 0 Warm-up timer 0: 214/ select clock frequency 1: 216/ select clock frequency 3 HALTM1 R/W 2 HALTM0 1 RESCR 0 Runaway detect internal reset control 1: Executes internal reset by runaway detect 0 DRVE 0 STOP mode pin control 1: Drive pins in STOP mode Watchdog timer detect time selection 00: 215/fSYS 01: 217/fSYS 10: 219/fSYS 11: 221/fSYS 0 0 HALT mode selection 00: RUN mode 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode Pin state control in STOP mode 0 1 I/O off Retains the state before halt HALT mode setting 00 RUN mode (Only CPU stop) 01 STOP mode (All circuits stop) 10 IDLE1 mode (Only oscillator operating) 11 IDLE2 mode (A part I/O operating) Warm-up time selection at returning from the stop mode (see Table 3.3.7) 0 1 214/select clock frequency 216/select clock frequency Figure 3.3.5 Watchdog Timer Mode Register The futures of RUN, IDLE2, IDLE1 and STOP modes are as follows. 1. RUN: Only the CPU halts 2. IDLE2: The built-in oscillator and the specified I/O operates. 3. IDLE1: Only the built-in oscillator operates, while all other built-in circuits stop. 4. STOP: All internal circuits including the built-in oscillator stop. This greatly reduces power consumption. The operations in the halt state is described in Table 3.3.5. 93CW46A-22 2004-02-10 TMP93CW46A Table 3.3.5 I/O Operation during HALT Mode HALT Mode WDMOD CPU I/O port 8-bit timer Block 8-bit PWM timer 16-bit timer Serial channel AD converter Watchdog timer Interrupt controller Operate Stop RUN 00 IDLE2 11 Stop IDLE1 10 STOP 01 See Table 3.3.8 Keep the state when the "HALT" instruction was executed. (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combinations between the states of interrupt mask register * 93CW46A-23 2004-02-10 TMP93CW46A Table 3.3.6 Halt Releasing Source and Halt Releasing Operation Interrupt Receiving Status HALT mode NMI Halt releasing source INTWDT Interrupt INT0 INT4 to 7 INTT0 to 3 INTTR4 to 7 INTRX0 to 4, TX0 to 4 INTAD RESET Interrupt Enable (Interrupt level) (Interrupt mask) RUN Interrupt Disable (Interrupt level) < (Interrupt mask) RUN - - *1 IDLE2 x IDLE1 x STOP x *1 IDLE2 - - IDLE1 - - STOP - - x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x *1 : After releasing the HALT mode, CPU starts interrupt processing. (RESET initializes LSI.) After releasing the HALT mode, CPU starts executing an instruction that follows the HALT instruction. It can not be used to release the HALT mode. The priority level (Interrupt request level) of non-maskable interrupts is fixed to highest priority level "7". There is not this combination type. Releasing the HALT mode is executed after passing the warm-up time. When releasing the HALT mode is executed by INT0 interrupt of the level mode in the interrupt enabled status, hold level "H" until starting interrupt processing. If level "L" is set before holding level "L", interrupt processing is correctly started. (Example releasing "RUN" mode) INT0 interrupt releases halt state when the RUN mode is on. Address 8203H 8206H 8209H 820BH 820EH INT0 : x: -: *1: Note: LD LD EI LD HALT (IIMC), 00H (INTE0AD), 06H 5 (WDMOD), 00H ; Selects INT0 interrupt rising edge. ; Sets interrupt level to "6" for INT0. ; Sets interrupt level to "5" for CPU. ; Sets HALT mode to "RUN". ; Halts CPU. INT0 Interrupt routine 820FH LD XX, XX RETI 93CW46A-24 2004-02-10 TMP93CW46A (3) Operation 1. RUN mode In the RUN mode, the system clock continues to operate even after a HALT instruction is executed. Only the CPU stops executing the instruction. In the halt state, an interrupt request is sampled with the falling edge of the "CLK" signal. Releasing the RUN mode is executed by the external/internal interrupts. (See Table 3.3.6 "Halt Releasing Source and Halt Releasing Operation".) Figure 3.3.6 shows the interrupt timing for releasing the halt state by interrupts in the RUN/IDLE2 mode. X1 CLK A0 to A23 ALE AD0 to AD15 RD WR NMI Address Data Address Address Data Address Address + 2 INT0 (Level) INT4 to INT7 (Rising edge) INT4, INT6 (Falling edge) Internal INT RUN/IDLE2 mode Figure 3.3.6 Timing Chart for Releasing the Halt State by Interrupt in RUN/IDLE2 Modes 2. IDLE2 mode In the IDLE2 mode, the system clock is supplied to only specific internal I/O devices, and the CPU stops executing the current instruction. In the IDLE2 mode, the halt state is released by an interrupt with the same timing as in the RUN mode. The IDLE2 mode is released by external/internal interrupt, except INTWDT/INTAD interrupts. (See Table 3.3.6 "Halt Releasing Source and Halt Releasing Operation".) In the IDLE2 mode, the watchdog timer should be disabled before entering the halt status to prevent the watchdog timer interrupt occurring just after releasing the HALT mode. 93CW46A-25 2004-02-10 TMP93CW46A 3. IDLE1 mode In the IDLE1 mode, only the internal oscillator operates. The system clock in the MCU stops, the CLK pin is fixed at the level "H" in the output enable (CKOCR X1 CLK A0 to A23 ALE AD0 to AD15 RD WR NMI Address Data Address Data Address Address + 2 INT0 (Level) INT0 (Rising edge) IDEL1 mode Figure 3.3.7 Timing Chart of Halt Released by Interrupts in IDLE1 Mode 93CW46A-26 2004-02-10 TMP93CW46A 4. STOP mode The STOP mode is selected to stop all internal circuits including the internal oscillator. The pin status in the STOP mode is depended on setting the watchdog timer mode register WDMOD Warm-up time X1 CLK A0 to A23 ALE AD0 to AD15 RD WR NMI Address Data Address Data Address Address + 2 INT0 (Level) INT0 (Rising edge) STOP mode Figure 3.3.8 Timing Chart of Halt Released by Interrupt in STOP Mode 93CW46A-27 2004-02-10 TMP93CW46A Table 3.3.7 The Example of Warm-up Time after Releasing the STOP Mode Operation Clock after the STOP Mode fc fc/2 fc/4 fc/8 fc/16 fs Warm-up Time [ms] WDMOD 0.8192 1.6384 3.2768 6.5536 13.1072 500 3.2768 6.5536 13.1072 26.2144 52.4288 2000 Clock fc = 20 MHz fs = 32.768 kHz How to calculate the warm-up time WDMOD Address SYSCR0 SYSCR1 WDMOD 8FFDH 9000H 9002H EQU EQU EQU LD RES LD HALT 9005H NMI 006EH 006FH 005CH (SYSCR1), 08H 4, (WDMOD) (SYSCR0), -11000 - - B ; fSYS = fs/2 ; Sets warm-up time to 214/fc ; Operates high frequency after released. Clears and starts warm-up timer (High-frequency clock) End NMI interrupt routine 9006H LD -: No change XX, XX RETI Note: When different modes are used before and after STOP mode as the above mentioned, there is possible to release the HALT mode without changing the operation mode by acceptance of the halt release interrupt request during execution of "HALT" instruction (during 8 states). In the system which accepts the interrupts during execution "HALT" instruction, set the same operation mode before and after the STOP mode. 93CW46A-28 2004-02-10 TMP93CW46A Table 3.3.8 Pin States in STOP Mode Pin Name P00 to P07 I/O Input mode Output mode AD8 to AD15 Input mode Output mode AD0 to AD7 Input mode Output mode A0 to A7/A16 to A23 Output pin Input mode Output mode Input mode Output mode Input mode Output mode Input mode Input mode Output mode Input mode Output mode Input mode Output mode Input mode Output mode Input mode (INT0) Input mode Output mode Input mode Output mode Input mode Output mode, SCOUT Input pin Output pin Output ( TMP93CW46A - - Output - P10 to P17 - - Output - P20 to P27 - PU* PU* PU* PU* PD* PD* Output Output Input Output Input Output Input Output P30 ( RD ), P31 ( WR ) P32 to P37 P40, P41 P42 ( CS2 / CAS2 ) P5 P6 P7 P80 to P86 P87 (INT0) PU* PU* PU* PU* PU* PU* PU PU Input PU* PU* - - - - Input Output "L" level output - Input Input Input - "H" level output - - - - - - Input Output Input Output Input Output Input Output Input Input Output Input Output Input Output Input Output "L" level output "H" level output Input Input Input - "H" level output Input Output* - Input Output* - P90 to P95 PA0 to PA6 PA7 NMI WDTOUT ALE CLK RESET EA AM8/ AM16 X1 X2 P96 P97 -: Input: Output: Output*: PU: PU*: PD*: : x: Note: Input for input mode/input pin is invalid; output mode/output pin is at high impedance. Input gate in operation. Fix input voltage to "L" or "H" so that input pin stays constant. Output state Open-drain output state. Input gate in operation. Set output to "L" or attach pull-up pin so that the input gate stays constant. Programmable pull-up pin. Fix the pin to avoid through current since the input gate operates when a pull-up pin resistor is not set Programmable pull-up pin. Input gate disable state. No through current even if the pin is set t high impedance. Programmable pull-down pin. Input gate disable state. No through current even if the pin is set t high impedance. When HALT instruction is executed and CPU stops at the address of the port register, input gate in operation. Fix the pin to avoid through current and change the program. In the other cases, input for input mode is invalid, output mode is at high impedance. Cannot set. Port registers are used for controlling programmable pull up/pull down. If a pin is also used for an output function (e.g., TO1) and the output function is specified, whether pull up or pull down is selected depends on the output function data. If a pin is also used for an input function, whether pull up or pull down is selected depends on the port register setting value only. 93CW46A-29 2004-02-10 TMP93CW46A 3.4 Interrupts Interrupts are controlled by the CPU interrupt mask register SR A fixed individual interrupt vector number is assigned to each interrupt source; six levels of priority (Variable) can also be assigned to each maskable interrupt. Non-maskable interrupts have a fixed priority of 7. When an interrupt is generated, the interrupt controller sends the value of the priority of the interrupt source to the CPU. When more than one interrupt is generated simultaneously, the interrupt controller sends the value of the highest priority (7 for non-maskable interrupts is the highest) to the CPU. The CPU compares the value of the priority sent with the value in the CPU interrupt mask register 93CW46A-30 2004-02-10 TMP93CW46A Interrupt processing Read interrupt vector V. Clear interrupt request F/F. Vector V and high-speed micro DMA start vector match No Yes Data transfer by high-speed micro DMA COUNT COUNT - 1 General-purpose interrupt processing PUSH PC PUSH SR SR Micro DMA processing (Note) Yes COUNT = 0 No PC (8000H + V) Interrupt processing program Note: In read-only mode, always branches to NO without conditional branch. RETI instruction POP SR POP PC INTNEST INTNEST - 1 End Figure 3.4.1 Interrupt Processing Flowchart 93CW46A-31 2004-02-10 TMP93CW46A 3.4.1 General-purpose Interrupt Processing When accepting an interrupt, the CPU operates as follows. In the software interrupts or the illegal instruction execution interrupts from CPU, the following (1) and (3) are not executed. (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same level is generated simultaneously, the interrupt controller generates interrupt vectors in accordance with the default priority, then clears the interrupt request. The default priority is fixed as follows: The smaller the vector value, the higher the priority. (2) The CPU pushes the program counter and the status register to the system stack area (Area indicated by the system mode stack pointer (XSP)). (3) The CPU sets a value in the CPU interrupt mask register 8-bit 16-bit Bus Width of Interrupt Vector Area 8 bits 16 bits 8 bits 16 bits Interrupt Processing State Number MAX Mode 35 31 29 25 MIN Mode 31 27 27 23 To complete the interrupt processing, the RETI instruction is usually used. Executing this instruction restores the contents of the program counter and the status registers and decrements INTNEST (Interrupt nesting counter). Though acceptance of non-maskable interrupts cannot be disabled by program, acceptance of maskable interrupts can. A priority can be set for each source of maskable interrupts. The CPU accepts an interrupt request with a priority higher than the value in the CPU mask register 93CW46A-32 2004-02-10 TMP93CW46A (1) Maskable interrupt (INTT0 interrupt routine) (main) EI 1 [1] INTT0 (Level 1) [5] [4] IFF1 RETI IFF2 [2] (main) DI [1] IFF7 [2] (2) Non-maskable interrupt (NMI interrupt routine) [3] NMI (Level 7) [5] [4] IFF7 [3] RETI During execution of the main program, the CPU accepts an interrupt request. The CPU increments the IFF so that the interrupts of level 1 are not accepted during processing the interrupt routine. DI instruction is executed in the main program, so that the interrupts of only level 7 are accepted. The CPU does not increment the IFF even if the CPU accepts an interrupt request of level 7. (3) Interrupt nesting (INTT0 interrupt routine) (main) EI 3 [1] INTT0 (Level 3) [9] [8] IFF3 RETI IFF4 [2] [3] INTT1 (Level 4) [7] [6] IFF4 RETI IFF5 [4] (4) Software interrupt (INTT1 interrupt routine) (main) DI [1] [2] (SWI3 routine) [5] SWI 3 [5] [4] [3] RETI During processing the interrupts of level 3, the IFF is set to 4. When an interrupt with a level higher than level 4 is generated, the CPU accepts the interrupt with the higher level, causing interrupt processing to nest. The CPU accepts the software interrupt request during DI status (IFF = 7) because of the level 7. The IFF is not changed by the software interrupts. (5) Interrupt sampling timing (INTT0 interrupt routine) [3] INTT1 (Level 4) [2] XXX (main) EI 3 [1] INTT0 (Level 3) [8] [7] [5] [6] RETI [4] Example: RETI (Underline): Instruction [1], [2] ... : Execution flow If an interrupt with a level higher than the interrupt being processed is generated, the CPU accepts the interrupt with the higher level. The program counter which returns at [5] is the start address of INTT0 interrupt routine. 93CW46A-33 2004-02-10 TMP93CW46A The addresses 008000H to 0080FFH (256 bytes) of the TMP93CW46A are assigned for interrupt vector area. Table 3.4.1 TMP93CW46A Interrupt Table Default Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 - to - Type Interrupt Source Reset, or SW10 instruction SWI 1 instruction Illegal instruction, or SWI2 SWI 3 instruction SWI 4 instruction SWI 5 instruction SWI 6 instruction SWI 7 instruction NMI: NMI pin INTWD: Watchdog timer INT0: INT0 pin INT4: INT4 pin INT5: INT5 pin INT6: INT6 pin INT7: INT7 pin (Reserved) INTT0: 8-bit timer0 INTT1: 8-bit timer1 INTT2: 8-bit timer2/PWM0 INTT3: 8-bit timer3/PWM1 INTTR4: 16-bit timer4 (TREG4) INTTR5: 16-bit timer4 (TREG5) INTTR6: 16-bit timer5 (TREG6) INTTR7: 16-bit timer5 (TREG7) INTRX0: Serial receive (Channel 0) INTTX0: Serial send (Channel 0) INTRX1: Serial receive (Channel 1) INTTX1: Serial send (Channel 1) INTAD: AD conversion completion INTRX2: Serial receive (Channel 2) INTTX2: Serial send (Channel 2) INTRX3: Serial receive (Channel 3) INTTX3: Serial send (Channel 3) INTRX4: Serial receive (Channel 4) INTTX4: Serial send (Channel 4) (Reserved) to (Reserved) Vector Value "V" 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 to F 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C C H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H Address Refer to Vector 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 to F 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C C H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H Micro DMA Start Vector - - - - - - - - 08H 09H 0AH 0BH 0CH 0DH 0EH - 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H - to - Nonmaskable Maskable 93CW46A-34 2004-02-10 TMP93CW46A Setting to reset/interrupt vector 1. Reset vector 8000H 8001H 8002H 8003H PC<7:0> PC<15:8> PC<23:16> XX 2. Interrupt vector (except reset vector) +0 +1 +2 +3 PC<7:0> PC<15:8> PC<23:16> XX Address refer to vector XX: Don't care (Setting example) Reset vector: 8100H, NMI Vector: 9ABCH, INTAD Vector: 123456H. ORG DL ORG DL ORG DL ORG LD ORG LD ORG LD 8000H 008100H 8020H 009ABCH 8070H 123456H 8100H A, B 9ABCH B, C 123456H C, A ; Reset = 8100H ; NMI = 9ABCH ; INTAD = 123456H (cf) ORG, DL are the assembler directive. ORG: Control location counter DL: Define the long word (32 bits) data 93CW46A-35 2004-02-10 TMP93CW46A 3.4.2 Micro DMA In addition to the conventional interrupt processing, the TMP93CW46A also has a micro DMA function. When an interrupt is accepted, in addition to an interrupt vector, the CPU receives data indicating whether processing is micro DMA mode or general-purpose interrupt. If micro DMA mode is requested, the CPU performs micro DMA processing. The micro DMA can process at very high speed compared with the TLCS-90 micro DMA because it has transfer parameters in dedicated registers in the CPU. Since those dedicated registers are assigned as CPU control registers, they can only be accessed by the LDC instruction. (1) Micro DMA operation Micro DMA operation starts when the accepted interrupt vector value matches the micro DMA start vector value set in the interrupt controller. The micro DMA has four channels so that it can be set for up to four types of interrupt source. When a micro DMA interrupt is accepted, data is automatically transferred from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decremented. If the value in the counter after decrementing is other than 0, micro DMA processing is completed; if the value in the counter after decrementing is 0, general-purpose interrupt processing is performed. In read-only mode, which is provided for DRAM refresh, the value in the counter is ignored and dummy read is repeated. 32-bit control registers are used for setting transfer source/destination addresses. However, the TMP93CW46A has only 24 address pins for output. A 16-Mbyte space is available for the micro DMA. There are two data transfer modes: One-byte mode and one-word mode. Incrementing, decrementing, and fixing the transfer source/destination address after transfer can be done in both modes. Therefore data can easily be transferred between I/O and memory and between I/Os. For details of transfer modes, see the description of transfer mode registers. The transfer counter has 16 bits, so up to 65536 transfers (The maximum when the initial value of the transfer counter is 0000H.) can be performed for one interrupt source by micro DMA processing. When the transfer counter is decremented to "0" after data is transferred with micro DMA, general-purpose interrupt processing is performed. After processing the general-purpose interrupt, starting the interrupts of the same channel restarts the transfer counter from 65536. If necessary, reset the transfer counter. Interrupt sources processed by micro DMA processing are 26 sources with the micro DMA start vectors listed in Table 3.4.1. 93CW46A-36 2004-02-10 1 state DM2 DM5 DM6 DM11 DM12 DM3 DM4 DM7 DM8 DM9 DM10 (Note 1) (Note 2) (Note 3) (Note 3) DM13 DM14 (Note 3) DM15 DM16 DM1 X1 ALE A0 to A15 D0 to D15 A0 to A15 AD0 to AD15 D0 to D15 A0 to A15 D0 to D15 A0 to A15 D0 to D15 A0 to A15 D0 to D15 A16 to A23 Dummy Source address Destination address Dummy Dummy Address Address + 2 Address + 4 Figure 3.4.2 Micro DMA Cycle (COUNT 0) High-speed micro DMA cycle (COUNT 0) 93CW46A-37 RD WR, HWR Note 1: This is added 2 states the case of the bus width of source address area is 8 bits. Note 2: This added 2 states the case of the bus width of destination address area is 8 bits. Note 3: This may be a dummy cycle with instruction queue buffer. Note 4: In the case of the word transfer mode. TMP93CW46A 2004-02-10 (Note 1) DM3 DM4 DM5 DM7 DM8 DM9 DM10 DM13 DM14 DM6 DM11 DM12 DM15 (Note 2) (Note 3) (Note 3) DM16 DM1 DM2 X1 ALE A0 to A15 D0 to D15 A0 to A15 AD0 to AD15 D0 to D15 A0 to A15 D0 to D15 A0 to A15 D0 to D15 A16 to A23 Dummy Destination address Source address Dummy Address Dummy Address + 2 Dummy RD WR, HWR (Note 4) DM19 DM20 DM21 DM22 DM23 DM25 DM26 DM24 DM27 (Note 4) (Note 4) DM28 DM29 DM30 DM31 DM32 DM17 DM18 X1 ALE XSP - 6 XSP - 4 XSP - 2 Dummy 8000H + V 8002H + V Dummy AD0 to AD15 Dummy Figure 3.4.3 Micro DMA Cycle (COUNT=0) DM35 DM36 DM37 Address Address + 2 93CW46A-38 RD WR, HWR DM33 DM34 X1 ALE AD0 to AD15 Dummy RD WR, HWR TMP93CW46A 2004-02-10 Note 1: Note 2: Note 3: Note 4: This is added 2 states the case of the bus width of source address area is 8 bits. This added 2 states the case of the bus width of destination address area is 8 bits. This be a dummy cycle with instruction queue buffer. This is added 2 states the case of the bus width of stack address area is 8 bits. TMP93CW46A Timing chart in the previous page is a micro DMA cycle of the transfer address increment mode. (The other mode except the read-only mode is the same as this.) (Condition: MAX mode, 16-bit bus width for 16 Mbytes, 0 waits) (2) Register configuration (CPU control register) Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 Channel 1 DMAS1 DMAD1 DMAC1 DMAM1 Channel 2 DMAS2 DMAD2 DMAC2 DMAM2 Channel 3 DMAS3 DMAD3 DMAC3 DMAM3 8 bits 16 bits Transfer source address register 3 Transfer destination address register 3 Transfer counter register 3 Transfer mode register 3 Transfer source address register 2 Transfer destination address register 2 Transfer counter register 2 Transfer mode register 2 Transfer source address register 1 Transfer destination address register 1 Transfer counter register 1 Transfer mode register 1 Transfer source address register 0 Transfer destination address register 0 Transfer counter register 0 Transfer mode register 0 (1 to 65536) (Use only lower 24 bits.) 32 bits These control registers can be set only with "LDC cr, r" instruction. (e.g.) LD LDC LD LDC LD LDC LD LDC XWA, 100H DMAS0, XWA XWA, 50H DMAD0, XWA WA, 40H DMAC0, WA A, 05H DMAM0, A 93CW46A-39 2004-02-10 TMP93CW46A (3) Transfer mode register: DMAM0 to DMAM3 (DMAM0 to DMAM3) 0 0 0 0 Mode Note: When setting values for this register, set the upper 4 bits to 0. Execution time (Min) at 20 MHz 16 states (1.6 s) 16 states (1.6 s) 16 states (1.6 s) 16 states (1.6 s) 16 states (1.6 s) 14 states (1.4 s) 11 states (1.1 s) Z: 0 = Byte transfer, 1 = Word transfer 0 0 0 Z Transfer destination address INC mode ........................ I/O to memory (DMADn+) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INT. Transfer destination address DEC mode .......................... I/O to memory (DMADn-) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INT. Transfer source address INC mode ................................. memory to I/O (DMADn) (DMASn+) DMACn DMACn - 1 if DMACn = 0 then INT. Transfer source address DEC mode ................................ memory to I/O (DMADn) (DMASn-) DMACn DMACn - 1 if DMACn = 0 then INT. Fixed address mode .................................................................... I/O to I/O (DMADn) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INT. Read-only mode ............................................................. for DRAM refresh Dummy (DMASn); Reads 4 bytes. DMASn DMASn + 4; Increments lower word only. DMACn DMACn - 1 Counter mode ............................................................. for interrupt counter DMASn DMASn + 1 DMACn DMACn - 1 if DMACn = 0 then INT. 0 0 1 Z 0 1 0 Z 0 1 1 Z 1 0 0 Z 1 0 1 0 1 0 1 1 Note 1: n: Corresponds to micro DMA channels 0 to 3. DMADn+/DMASn+: Post-increment (Increments register value after transfer.) DMADn-/DMASn-: Post-decrement (Decrement register value after transfer.) Note 2: Execution time: When setting source address/destination address area to 16-bit bus, 0 waits. Clock condition: fc = 20 MHz, Clock gear: 1 (fc) Note 3: Do not use the codes other than the above mentioned codes for transfer mode register. 93CW46A-40 2004-02-10 TMP93CW46A When the hardware configuration is as follows: DRAM mapping size: 1 Mbyte DRAM data bus size: 8 bits DRAM mapping address range: 100000H to 1FFFFFH Set the following registers first; refresh is performed automatically. 1. Register initial value setting LD LDC LD LDC 2. 3. XIX, A, 100000H ... Mapping start address ... Read only mode (for DRAM refresh) 00001010B DMAS0, XIX DMAM0, A Timer setting Set the timers so that interrupts are generated at intervals of 62.5 s or less. Interrupt controller setting Set the timer interrupt mask higher than the other interrupts mask. Write the above timer interrupt vector value in the micro DMA start vector register, DMA0V. (Operation description) The DRAM data bus is an 8-bit bus and the micro DMA is in read-only mode (4 bytes), so refresh is performed for four times per interrupt. When a 512 refresh/8 ms DRAM is connected, DRAM refresh is performed sufficiently if the micro DMA is started every 15.625 s x 4 = 62.5 s or less, since the timing is 15.625 s/refresh. (Overhead) Each processing time by the micro DMA is 1.8 s (18 states) at 20 MHz with an 8-bit data bus. In the above example, the high-speed micro DMA is started every 62.5 s, 1.8 s/62.5 s = 0.0288; thus, the overhead is 2.88%. (Note) When the bus is released which must wait to accept the interrupt, DRAM refresh is not performed because of the micro DMA is generated by an interrupt. 93CW46A-41 2004-02-10 TMP93CW46A 3.4.3 Interrupt Controller Figure 3.4.4 is a block diagram of the interrupt circuits. The left half of the diagram shows the interrupt controller; the right half includes the CPU interrupt request signal circuit and the halt release signal circuit. Each interrupt channel (Total of 26 channels) in the interrupt controller has an interrupt request flag, interrupt priority setting register, and a register for storing the micro DMA start vector. The interrupt request flag is used to latch interrupt requests from peripheral devices. The flag is cleared to 0 at the following conditions. * * * At reset When the CPU reads the interrupt vector after acceptance of interrupt When the CPU executes an instruction that clears the interrupt of that channel (Writes 0 in For example, to clear the INT0 interrupt request, set the register after the DI instruction as follows. INTE0AD - - - -0- - - Zero-clears the INT0 flip-flop. The status of the interrupt request flag is detected by reading the clear bit. Detects whether there is an interrupt request for an interrupt channel. The interrupt priority can be set by writing the priority in the interrupt priority setting register (e.g., INTE0AD, INTE45, etc.) provided for each interrupt source. Interrupt levels to be set are from 1 to 6. Writing 0 or 7 as the interrupt priority disables the corresponding interrupt request. The priority of the non-maskable interrupt ( NMI pin, watchdog timer, etc.) is fixed to 7. If interrupt requests with the same interrupt level are generated simultaneously, interrupts are accepted in accordance with the default priority. The interrupt controller sends the interrupt request with the highest priority among the simultaneous interrupts and its vector address to the CPU. The CPU compares the priority value 93CW46A-42 2004-02-10 Interrupt controller 1 CPU NMI RESET Interrupt vecror V read Interrupt request flip flop S Q R Interrupt enable flag on CPU side RESET Priority encoder IFF2 to 0 3 3 INTRQ2 to 0 Interrupt vector read 3 Interrupt level detect 1 7 6 Interrupt request signal to CPU INTWD Priority setting register Dn A D Q CLR B C 6 Interrupt request F/F V = 20H V = 24H Decoder EI1 to EI7 DI Interrupt request signal Dn + 1 Dn + 2 Y1 Y2 Y3 Y4 Y5 Y6 INT0 Q Interrupt request flip flop read Interrupt request clear Dn + 3 Interrupt request V read V = 28H (Highest priority = 7) S Dn + 3 RESET R 26 Interrupt vector generation 1 2 Highest A priority 3 B interrupt 4 level select C 5 6 7 D0 D1 if INTRQ2 to 0 IFF2 to 0 then 1. D2 D3 D4 D5 D6 D7 Figure 3.4.4 Block Diagram of Interrupt Controller 93CW46A-43 6 Micro DMA start vector setting register During IDLE1 During STOP Halt release RESET INT0 NMI INT4 INT5 INT6 INT7 INTT0 INTT1 INTT2 INTT3 INTTR4 INTTR5 INTTR6 INTTR7 INTRX0 INTTX0 INTRX1 INTTX1 INTAD INTRX2 INTTX2 INTRX3 INTTX3 INTRX4 INTTX4 4 input OR V = 2CH V = 30H V = 34H V = 38H V = 40H V = 44H V = 48H V = 4CH V = 50H V = 54H V = 58H V = 5CH V = 60H V = 64H V = 68H V = 6CH V = 70H V = 74H V = 78H V = 7CH V = 80H V = 84H V = 88H D CLR 6 Q 6 Match detect DMA0V DMA1V DMA2V DMA3V 4 Micro DMA request A B Micro DMA channel priority encoder 2 2 Micro DMA channel specification D5 D4 D3 D2 D1 D0 RESET TMP93CW46A 0 1 2 3 2004-02-10 TMP93CW46A (1) Interrupt priority setting register Symbol Address 7 IADC INTE0AD 0070H R/W 0 I5C INTE45 0071H R/W 0 I7C INTE67 0072H R/W 0 IT1C INTET10 0073H R/W 0 IPW1C INTEPW10 0074H R/W 0 IT5C INTET54 0075H R/W 0 IT7C INTET76 0076H R/W 0 ITX0C INTES0 0077H R/W 0 ITX1C INTES1 0078H R/W 0 ITX2C INTES2 0059H R/W 0 ITX3C INTES3 005AH R/W 0 ITX4C INTES4 005BH R/W 0 0 INTTX4 0 INTTX3 ITX4M2 ITX4M1 W 0 0 ITX4M0 IRX4C R/W 0 0 INTRX4 0 INTTX2 ITX3M2 ITX3M1 W 0 0 ITX3M0 IRX3C R/W 0 0 INTRX3 IRX4M2 IRX4M1 W 0 0 IRX4M0 0 INTTX1 ITX2M2 ITX2M1 W 0 0 ITX2M0 IRX2C R/W 0 0 INTRX2 IRX3M2 IRX3M1 W 0 0 IRX3M0 0 INTTX0 ITX1M2 ITX1M1 W 0 0 ITX1M0 IRX1C R/W 0 0 INTRX1 IRX2M2 IRX2M1 W 0 0 IRX2M0 0 ITX0M2 0 IT7M2 0 IT5M2 0 IPW1M2 0 INT7 IT1M2 IT1M1 W 0 IPW1M1 W 0 IT5M1 W 0 IT7M1 W 0 ITX0M1 W 0 0 0 ITX0M0 INTTR7 (TREG7) IRX0C R/W 0 0 INTRX0 IRX1M2 IRX1M1 W 0 0 IRX1M0 0 IT7M0 INTTR5 (TREG5) IT6C R/W 0 0 IRX0M2 0 IT5M0 INTT3 (Timer 3/PWM1) IT4C R/W 0 0 IT6M2 0 IPW1M0 INTT1 (Timer 1) IPW0C R/W 0 0 IT4M2 IT1M0 IT0C R/W 0 0 IPW0M2 IT0M2 0 INT5 I7M2 I7M1 W 0 0 I7M0 I6C R/W 0 0 INT6 IT0M1 W 0 IPW0M1 W 0 IT4M1 W 0 IT6M1 W 0 IRX0M1 W 0 0 0 IRX0M0 INTTR6 (TREG6) 0 IT6M0 INTTR4 (TREG4) 0 IT4M0 INTT2 (Timer 2/PWM0) 0 IPW0M0 INTT0 (Timer 0) IT0M0 I6M2 0 INTAD I5M2 I5M1 W 0 0 I5M0 I4C R/W 0 0 INT4 I6M1 W 0 0 I6M0 I4M2 6 IADM2 5 IADM1 W 0 4 IADM0 0 3 I0C R/W 0 2 I0M2 0 INT0 1 I0M1 W 0 I4M1 W 0 0 I0M0 0 I4M0 0 Bit symbol Read/Write After reset Interrupt source IxxM2 0 0 0 0 1 1 1 1 IxxC 0 1 IxxM1 0 0 1 1 0 0 1 1 IxxM0 0 1 0 1 0 1 0 1 Function (Write) Prohibits interrupt request. Sets interrupt request level to "1". Sets interrupt request level to "2". Sets interrupt request level to "3". Sets interrupt request level to "4". Sets interrupt request level to "5". Sets interrupt request level to "6". Prohibits interrupt request. Function (Write) Clears interrupt request flag. - - - - - Don't care - - - - - Function (Read) Indicates no interrupt request. Indicates interrupt request. Note 1: Read-modify-write is prohibited. Note 2: Note about clearing interrupt request flag The interrupt request flag of INTAD, INTRX0 to INTRX4 are not cleared by writing "0" to IxxC because of they are level interrupts. They can be cleared only by resetting or reading the conversion value or the receive buffer. 93CW46A-44 2004-02-10 TMP93CW46A (2) External interrupt control Interrupt Input Mode Control Register 7 IIMC (007BH) Bit symbol Read/Write After reset Function 6 5 4 3 2 I0IE W 0 1: INT0 input enable 1 I0LE W 0 0: INT0 edge mode 1: INT0 level mode 0 NMIREE W 0 1: Can be accepted in NMI rising edge. INT0 input enable (Note 1) 0 1 INT0 disable (P87 function only) Input enable 1 0 NMI rising edge enable Interrupt request generation at falling edge Interrupt request generation at rising/falling edge INT0 level enable (Note 2) 0 1 Rising edge detect interrupt High level interrupt Note 1: The INT0 pin can also be used for standby release as described later. Even if the pin is not used for standby release, setting this register to "0" maintains the port function during standby mode. Note 2: Case of changing from level to edge for INT0 pin mode execution example: LD (INTE0AD), XXXX0000B ; INT0 disable, clean the request flag LD (IIMC), XXXXX10XB ; Change from level to edge LD (INTE0AD), XXXX0nnnB ; Set interrupt level "n" for INT0, clear the request flag Note 3: Read-modify-write is prohibited. Note 4: IIMC Figure 3.4.5 Interrupt Input Mode Control Register Table 3.4.2 Setting of External Interrupt Pin Functions Interrupt NMI Pin Name - Mode Falling edge Falling and rising edges Rising edge Setting Method IIMC INT0 P87 High level Rising edge INT4 P80 Falling edge INT5 P81 Rising edge Rising edge INT6 P84 Falling edge INT7 P85 Rising edge 93CW46A-45 2004-02-10 TMP93CW46A (3) Micro DMA start vector When the CPU reads the interrupt vector after accepting an interrupt, it simultaneously compares the bits 2 to 7 of the interrupt vector with each channel's micro DMA start vector. When both match, the interrupt is processed in micro DMA mode for the channel whose value matched. If the interrupt vector matches more than two channel, the channel with the lower channel number has a higher priority. Micro DMA 0 Start Vector 7 DMA0V (007CH) Bit symbol Read/Write After reset Function 0 0 0 6 5 DMA0V5 4 DMA0V4 3 DMA0V3 W 2 DMA0V2 0 1 DMA0V1 0 0 DMA0V0 0 Micro DMA channel 0 processed by matching bits 2 to 7 of the interrupt vector. Micro DMA 1 Start Vector 7 DMA1V (007DH) Bit symbol Read/Write After reset Function 0 0 0 6 5 DMA1V5 4 DMA1V4 3 DMA1V3 W 2 DMA1V2 0 1 DMA1V1 0 0 DMA1V0 0 Micro DMA channel 1 processed by matching bits 2 to 7 of the interrupt vector. Micro DMA 2 Start Vector 7 DMA2V (007EH) Bit symbol Read/Write After reset Function 0 0 0 6 5 DMA2V5 4 DMA2V4 3 DMA2V3 W 2 DMA2V2 0 1 DMA2V1 0 0 DMA2V0 0 Micro DMA channel 2 processed by matching bits 2 to 7 of the interrupt vector. Micro DMA 3 Start Vector 7 DMA3V (007FH) Bit symbol Read/Write After reset Function Note: 0 0 0 6 5 DMA3V5 4 DMA3V4 3 DMA3V3 W 2 DMA3V2 0 1 DMA3V1 0 0 DMA3V0 0 Micro DMA channel 3 processed by matching bits 2 to 7 of the interrupt vector. Read-modify-write is not possible for DMA0V to DMA3V. Figure 3.4.6 Micro DMA Start Vector Register 93CW46A-46 2004-02-10 TMP93CW46A (4) Notes The instruction execution unit and the bus interface unit of this CPU operate independently of each other. Therefore, if the instruction used to clear an interrupt request flag of an interrupt is fetched before the interrupt is generated, it is possible that the CPU might execute the fetched instruction to clear the interrupt request flag while reading the interrupt vector after accepting the interrupt. To avoid the above occurring, clear the interrupt request flag by entering the instruction to clear the flag after the DI instruction. In the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing instruction and following more than one instruction are executed. When EI instruction is placed immediately after clearing instruction, an interrupt becomes enable before interrupt request flags are cleared. In the case of changing the value of the interrupt mask register 93CW46A-47 2004-02-10 TMP93CW46A 3.5 Functions of Ports The TMP93CW46A has 79 bits for I/O ports. These port pins have I/O functions for the built-in CPU and internal I/Os as well as general-purpose I/O port functions. Table 3.5.1 lists the function of each port pin. Table 3.5.2 lists I/O registers and specification. Table 3.5.1 Functions of Ports (R: = with programmable pull-up resistor = with programmable pull-down resistor) Port Name Port 0 Port 1 Port 2 Port 3 Pin Name P00 to P07 P10 to P17 P20 to P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P50 to P57 P60 P61 P62 P63 P64 P65 P66 P67 Number of Pins 8 8 8 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7 1 Direction I/O I/O I/O Output Output I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O R - - - - - - - - - Direction Setting Unit Bit Bit Bit (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Pin Name for Built-in Function AD0 to AD7 AD8 to AD15/A8 to A15 A0 to A7/A16 to A23 RD WR HWR WAIT BUSRQ BUSAK R/ W RAS CS0 / CAS0 CS1 / CAS1 CS2 / CAS2 Port 4 Port 5 Port 6 AN0 to AN7 TXD2 RXD2 CTS2 /SCLK2 TXD3 RXD3 CTS3 /SCLK3 TXD4 RXD4 TI0 TO1 TO2 TO3 TI4/INT4 TI5/INT5 TO4 TO5 TI6/INT6 TI7/INT7 TO6 INT0 TXD0 RXD0 CTS0 /SCLK0 Port 7 P70 P71 P72 P73 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 PA0 to PA6 PA7 Port 8 Port 9 TXD1 RXD1 SCLK1 XT1 XT2 SCOUT Port A 93CW46A-48 2004-02-10 TMP93CW46A Table 3.5.2 I/O Registers and Specification (1/2) Port Port 0 Name P00 to P07 Specification Input port Output port AD0 to AD7 bus Input port Output port AD8 to AD15 bus A8 to A15 output Input port (without PD) Input port (with PD) Output port A0 to A7 output A16 to A23 output Output port Outputs RD only when accessing external space Always outputs RD Output port Outputs WR only when accessing external space Input port (without PU) Input port (with PU) Output port HWR output WAIT input (without PU) WAIT input (with PU) BUSRQ input (without PU) BUSRQ input (with PU) BUSAK output I/O Register Pn x x x x x x x 1 0 x 1 1 x 1 0 x x 0 1 x x 0 1 0 1 x x x 0 1 x 1 0 x x x x x x 0 1 x x x x 0 1 0 1 PnCR 0 1 x 0 1 0 1 0 0 1 0 1 None PnFC None 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 0 0 1 None 1 1 1 1 1 0 0 0 0 0 0 1 1 1 None Port 1 P10 to P17 Port 2 P20 to P27 Port 3 P30 P31 P32 to P37 None 0 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 1 1 1 1 P32 P33 P34 P35 P36 P37 Port 4 P40 to P41 R/ W output RAS output Input port (without PU) Input port (with PU) Output port Input port (without PD) Input port (with PD) Output port (Note 1) CS0 output CS1 output CS2 output P42 P40 P41 P42 Port 5 Port 6 P50 to P57 P60 to P67 (Note 1) (Note 1) P60 P63 P66 P61 P64 Input port AN0 to AN7 input (Note 2) Input port (without PU) Input port (with PU) Output port TXD2 output TXD3 output TXD4 output RXD2 input (without PU) RXD2 input (with PU) RXD3 input (without PU) RXD3 input (with PU) 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 None None X: Don't care Note 1: CS/WAIT control registers BnCH 93CW46A-49 2004-02-10 TMP93CW46A Table 3.5.3 I/O Registers and Specification (2/2) Port Port 6 Name P67 P62 Specification RXD4 input (without PU) RXD4 input (with PU) SCLK2 output CTS2 /SCLK2 input (without PU) CTS2 /SCLK2 input (with PU) SCLK3 output CTS3 /SCLK3 input (without PU) CTS3 /SCLK3 input (with PU) Input port (without PU) Input port (with PU) Output port TI0 input (without PU) TI0 input (with PU) TO1 output port TO2 output port TO3 output port Input port (without PU) Input port (with PU) Output port TI4/INT4 input (without PU) TI4/INT4 input (with PU) TI5/INT5 input (without PU) TI5/INT5 input (with PU) TI6/INT6 input (without PU) TI6/INT6 input (with PU) TI7/INT7 input (without PU) TI7/INT7 input (with PU) TO4 output TO5 output TO6 output INT0 input (without PU) INT0 input (with PU) Input port (without PU) Input port (with PU) Output port TXD0 output TXD1 output RXD0 input (without PU) RXD0 input (with PU) RXD1 input (without PU) RXD1 input (with PU) SCLK0 output CTS0 /SCLK0 input (without PU) CTS0 /SCLK0 input (with PU) SCLK1 output SCLK1 input (without PU) SCLK1 input (with PU) Input port Output port (Note 4) XT1/2 (Note 5) Input port Output port SCOUT output port (Note 6) I/O Register Pn 0 1 x 0 1 x 0 1 0 1 x 0 1 x x x 0 1 x 0 1 0 1 0 1 0 1 x x x 0 1 0 1 x x x 0 1 0 1 x 0 1 x 0 1 x x x x x x PnCR 0 0 1 0 0 1 0 0 0 0 1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 1 PnFC None 1 0 0 1 0 0 0 0 0 None 1 1 1 0 0 0 None None None None 1 1 1 None 0 0 0 1 1 None None 1 0 0 1 0 0 None P65 Port 7 P70 to P73 P70 P71 P72 P73 P80 to P87 Port 8 P80 P81 P84 P85 P82 P83 P86 P87 (Note 3) P90 to P95 Port 9 P90 P93 P91 P94 P92 P95 P96 to P97 Port A PA0 to PA7 PA7 None Note 3: Using P87 pin as INT0, IIMC register has to be set enable interrupt. Note 4: Using P96/P97 as output port, output is through the open-drain buffer. Note 5: Using P96/P97 as XT1 to XT2, SYSCR0 register has to be set enable oscillation. Note 6: Using PA7 as SCOUT, PAFC register has to be written suitable value. 93CW46A-50 2004-02-10 TMP93CW46A Resetting makes the port pins listed below function as general-purpose I/O ports. I/O pins programmable for input or output are set to input ports except P96/XT1, P97/XT2. To set port pins for built-in functions, a program is required. Note about the Bus Release and programmable pull-up/pull-down I/O ports. When the bus is released ( BUSAK = "0"), the output buffer of AD0 to AD15, A0 to A23, control signal ( RD , WR , HWR , R/ W , RAS , CS0 / CAS0 to CS2 / CAS2 ) is off and their state become high impedance. However, the output of built-in programmable pull-up/pull-down resistors are kept before the bus is released. These programmable pull-up/pull-down resistors can be selected ON/OFF by programmable when they are used as the input ports. The case of they are used as the output ports, they can not be selected ON/OFF by programmable. Table 3.5.4 shows the pin state when the bus is released. Table 3.5.4 The Pin State (when the Bus is Released) The Pin State (when the Bus is Released) Pin Name Used as the Port P00 to P07 (AD0 to AD7) P10 to P17 (AD8 to AD15/A8 to A15) P30 ( RD ) P31 ( WR ) P32 ( HWR ) P37 ( RAS ) The state is not changed. (Do not become to high impedance (High-Z).) Becomes high impedance (High-Z). The output buffer is OFF. The programmable pull-up resistor is ON the case of only the output latch is equal to "1". The output buffer is OFF. The programmable pull-up resistor is ON the case of only the output latch is equal to "1". The output buffer is OFF. The programmable pull-down resistor is ON the case of only the output latch is equal to "0". The state is not changed. (Do not become to high impedance (High-Z).) Used as the Function Become high impedance (High-Z). Becomes high impedance (High-Z). The output buffer is OFF. The programmable pull-up resistor is ON irrespective of the output latch. The output buffer is OFF. There is a possibility that the programmable pull-up resistor is ON or OFF due to the bus releasing timing irrespective of the output latch. The output buffer is OFF. There is a possibility that the programmable pull-down resistor is ON or OFF due to the bus releasing timing irrespective of the output latch. The output buffer is OFF. The programmable pull-down resistor is ON the case of only the output latch is equal to "0". P36 (R/ W ) P40 ( CS0 / CAS0 ) P41 ( CS1 / CAS1 ) P42 ( CS2 / CAS2 ) P20 to P27 (A16 to A23) 93CW46A-51 2004-02-10 TMP93CW46A Figure 3.5.1 shows the example of the external interface circuit the case of the bus releasing function is used. When the bus is released, both internal memory and internal I/O can not be accessed. But the internal I/O continues to operate. So, the watchdog timer also continues to run. Therefore, be careful about bus releasing time and setting the detection time of the WDT. P35 ( BUSAK ) About 3 to 5 k P42 ( CS2 ) P30 ( RD ) P31 ( WR ) P32 ( HWR ) P36 ( R / W ) P37 ( RAS ) P40 ( CS0 ) P41 ( CS1 ) System control bus P20 (A16) to P27 (A23) Address bus (A23 to A16) Figure 3.5.1 Example of the Interface Circuit (The case of using bus releasing function) The above circuit is necessary to fix the signal level in the case of the bus is released. Resetting sets P30 ( RD ), P31 ( WR ) to output, P40 ( CS0 ), P41 ( CS1 ), P32 ( HWR ), P36 ( R / W ), P37 ( RAS ), and P35 ( BUSAK ) to input with pull-up resistor, P42 ( CS2 ) and P20 to P27 (A16 to A23) to input with pull-down resistor. The above circuit is necessary to fix the signal level after reset because of the external pull-up resistor collisions with the internal pull-down resistor. The value of this external pull-up resistor must be 3 to 5 k. (The value of the internal pull-down resistor is about 50 to 150 k.) P20 to P27 (A16 to A23) also needs circuit like P42 ( CS2 ) to fix the signal level. But for the P20 to P27 (A16 to A23) which does not have means "L" is active, add pull-down directly like above circuit. 93CW46A-52 2004-02-10 TMP93CW46A 3.5.1 Port 0 (P00 to P07) Port 0 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis using the control register P0CR. Resetting resets all bits of P0CR to 0 and sets port 0 to input mode. In addition to functioning as a general-purpose I/O port, port 0 also functions as an address data bus (AD0 to AD7). To access external memory, port 0 functions as an address data bus (AD0 to AD7) and all bits of the control register P0CR are cleared to 0. Reset Direction control (on bit basis) P0CR write Internal data bus Output latch Output buffer Port 0 P00 to P07 (AD0 to AD7) S P0 write S B Selector A P0 read A B Selector Figure 3.5.2 Port 0 93CW46A-53 2004-02-10 TMP93CW46A 3.5.2 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis using control register P1CR and function register P1FC. Reset all bits of output latch P1, control register P1CR, and function register P1FC to 0 and sets port 1 to input mode. In addition to functioning as a general-purpose I/O port, port 1 also functions as an address data bus (AD8 to AD15) or an address bus (A8 to A15). Reset Direction control (on bit basis) P1CR write Function control (on bit basis) Internal data bus P1FC write Output latch P1 write S B Port 1 Output buffer P10 to P17 (AD8 to AD15/A8 to A15) Selector A P1 read Figure 3.5.3 Port 1 93CW46A-54 2004-02-10 TMP93CW46A 7 P0 (0000H) Bit symbol Read/Write After reset P07 6 P06 5 Port 0 Register 4 P04 R/W 3 P03 2 P02 1 P01 0 P00 P05 Input mode (Output latch register becomes undefined.) 7 P0CR (0002H) Bit symbol Read/Write After reset Function 0 P07C 6 P06C 0 Port 0 Control Register 5 4 3 P05C 0 P04C R/W 0 0 P03C 2 P02C 0 1 P01C 0 0 P00C 0 0: Input 1: Output (At external access, Port 0 becomes AD7 to AD0 and P0CR is cleared to 0.) Port 0 I/O setting 0 1 Input Output 7 P1 (0001H) Bit symbol Read/Write After reset P17 6 P16 5 Port 1 Register 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 P15 Input mode (Output latch register is cleared to "0".) 7 P1CR (0004H) Bit symbol Read/Write After reset Function 0 P17C 6 P16C 0 Port 1 Control Register 5 4 3 P15C 0 P14C R/W 0 0 P13C 2 P12C 0 1 P11C 0 0 P10C 0 < 7 P1FC (0005H) Bit symbol Read/Write After reset Function 0 P17F 6 P16F 0 Port 1 Function Register 5 4 3 P15F 0 P14F R/W 0 0 P13F 2 P12F 0 1 P11F 0 0 P10F 0 P1FC/P1CR = 00: Input 01: Output 10: AD15 to AD8 11: A15 to A8 Read-modify-write is prohibited for registers P0CR, P1CR, and P1FC. P1CR Port 1 function setting P1FC 0 1 Address data bus (AD15 to AD8) Address bus (A15 to A8) 0 Input port 1 Output port Note: Figure 3.5.4 Registers for Ports 0 and 1 93CW46A-55 2004-02-10 TMP93CW46A 3.5.3 Port 2 (P20 to P27) Port 2 is an 8-bit general-purpose I/O port. I/O can be set on bit basis using the control register P2CR and function register P2FC. Resetting resets all bits of output latch P2, control register P2CR and function register P2FC to 0. It also sets port 2 to input mode and connects a pull-down resistor. In addition to functioning as a general-purpose I/O port, port 2 also functions as an address data bus (A0 to A7) and an address bus (A16 to A23). Using port 2 as address bus (A0 to A7 or A16 to A23), write "1" to output latches and be off the programmable pull-down resistors. A16 to A23 B Selector A0 to A7 Reset Direction control (on bit basis) P2CR write A S Function control (on bit basis) Internal data bus P2FC write S B Selector Output latch P2 write A Output buffer N-ch Port 2 P20 to P27 (A0 to A7/ A16 to A23) S Selector Programmable B pull down A P2 read Figure 3.5.5 Port 2 93CW46A-56 2004-02-10 TMP93CW46A 7 P2 (0006H) Bit symbol Read/Write After reset P27 6 P26 5 Port 2 Register 4 P24 R/W 3 P23 2 P22 1 P21 0 P20 P25 Input mode (Output latch register is cleared to "0".) 7 P2CR (0008H) Bit symbol Read/Write After reset Function 0 P27C 6 P26C 0 Port 2 Control Register 5 4 3 P25C 0 P24C W 0 0 P23C 2 P22C 0 1 P21C 0 0 P20C 0 < 7 P2FC (0009H) Bit symbol Read/Write After reset Function 0 P27F 6 P26F 0 Port 2 Function Register 5 4 3 P25F 0 P24F W 0 0 P23F 2 P22F 0 1 P21F 0 0 P20F 0 P2FC/P2CR = 00: Input 01: Output 10: A7 to A0 11: A23 to A16 Port 2 function setting P2FC 0 1 Address data bus (A7 to A0) Address bus (A23 to A16) 0 Input port 1 Output port Note: Figure 3.5.6 Registers for Port 2 93CW46A-57 2004-02-10 TMP93CW46A 3.5.4 Port 3 (P30 to P37) Port 3 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis, but note that P30 and P31 are used for output only. I/O is set using control register P3CR and function register P3FC. Resetting resets all bits of output latch P3, control register P3CR (Bits 0 and 1 are unused), and function register P3FC to 0. Resetting also outputs 1 from P30 and P31, sets P32 to P37 to input mode, and connects a pull-up resistor. In addition to functioning as a general-purpose I/O port, port 3 also functions as an I/O for the CPU's control/status signal. When P30 pin is defined as RD signal output mode ( 93CW46A-58 2004-02-10 TMP93CW46A Reset Function control (on bit basis) P3FC write Internal data bus S Output latch P3 write S A Output buffer Selector B P30 ( RD ) P31 ( WR ) RD , WR P3 read Reset Direction control (on bit basis) P3CR write Function control (on bit basis) P-ch P3FC write Programmable pull up Internal data bus S Output latch P3 write A S Selector Output buffer P32 ( HWR ) P35 ( BUSAK ) P36 (R/ W ) P37 ( RAS ) B HWR , BUSAK , R/ W , RAS S Selector B A P3 read Figure 3.5.7 Port 3 (P30, P31, P32, P35, P36, P37) 93CW46A-59 2004-02-10 TMP93CW46A Reset Direction control (on bit basis) P3CR write S Output latch P3 write S B Selector A Internal WAIT P-ch Programmable pull up P33 ( WAIT ) Output buffer Internal data bus P3 read Reset Direction control (on bit basis) P3CR write Function control (on bit basis) P-ch P3FC write Programmable pull up Internal data bus S Output latch P3 write P34 ( BUSRQ ) S Selector B A P3 read Internal BUSRQ Figure 3.5.8 Port3 (P33, P34) 93CW46A-60 2004-02-10 TMP93CW46A 7 P3 (0007H) Bit symbol Read/Write After reset 1 P37 6 P36 1 5 Port 3 Register 4 P34 R/W 1 3 P33 1 2 P32 1 1 P31 1 0 P30 1 P35 1 Input mode (pulled up) Output mode 7 P3CR (000AH) Bit symbol Read/Write After reset 0 P37C 6 P36C 0 Port 3 Control Register 5 4 3 P35C W 0 0 0 P34C P33C 2 P32C 0 1 0 0: Input 1: Output I/O setting Output mode 0 Input 1 Output 7 P3FC (000BH) Bit symbol Read/Write After reset Function 0 0: Port 1: RAS P37F 6 P36F 0 0: Port 1: R/ W Port 3 Function Register 5 4 3 P35F 0 0: Port 1: BUSAK P34F W 0 0: Port 1: BUSRQ 2 P32F 0 0: Port 1: HWR 1 P31F 0 0: Port 1: WR 0 P30F 0 0: Port 1: RD P30 ( RD ) function setting BUSRQ setting 0 "0" output Always RD output (for pseudo SRAM) 1 "1" output RD output only for external access P3FC BUSAK setting 1 0 0 1 P3FC RAS setting 1 1 P31 ( WR ) function setting 0 1 0 1 1 1 "0" output "1" output WR output only for external access HWR setting P3FC 1 1 P3FC 1 1 Note 1: Read-modify-write is prohibited for registers P3CR and P3FC. Note 2: When port P3 is used in the input mode, P3 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Note 3: When P33/ WAIT pin is used as a WAIT pin, set P3CR Figure 3.5.9 Registers for Port 3 93CW46A-61 2004-02-10 TMP93CW46A 3.5.5 Port 4 (P40 to P42) Port 4 is a 3-bit general-purpose I/O port. I/O can be set on a bit basis using control register P4CR and function register P4FC. Resetting does the following: * * * * Sets the P40 and P42 output latch registers to 1. Resets all bits of the P42 output latch register, the control register P4CR, and the function register P4FC to 0. Sets P40 and P41 to input mode and connects a pull-up resistor. Sets P42 to input mode and connects a pull-down resistor. In addition to functioning as a general-purpose I/O port, port 4 also functions as a chip select output signal ( CS0 to CS2 or CAS0 to CAS2 ). 93CW46A-62 2004-02-10 TMP93CW46A Reset Direction control (on bit basis) P4CR write Function control (on bit basis) P4FC write P-ch Programmable pull up Internal data bus S Output latch P4 write A S Output buffer Selector P40 ( CS0 / CAS0 ), P41 ( CS1 / CAS1 ) B CS0 / CAS0 , CS1 / CAS1 S Selector B A P4 read Reset Direction control (on bit basis) P4CR write Function control (on bit basis) P4FC write Internal data bus R Output latch P4 write A S Output buffer Selector N-ch P42 ( CS2 / CAS2 ) B CS2 / CAS2 Programmable pull down S Selector B A P4 read Figure 3.5.10 Port 4 93CW46A-63 2004-02-10 TMP93CW46A 7 P4 (000CH) Bit symbol Read/Write After reset Function 6 5 Port 4 Register 4 3 2 P42 0 (Pull down) 1 P41 R/W 1 (Pull up) 0 P40 1 (Pull up) Input mode 7 P4CR (000EH) Bit symbol Read/Write After reset Function 6 Port 4 Control Register 5 4 3 2 P42C 0 1 P41C W 0 0: Input 1: Output I/O setting 0 1 Input Output 0 P40C 0 7 P4FC (0010H) Bit symbol Read/Write After reset Function 6 Port 4 Function Register 5 4 3 2 P42F 0 0: Port 1 P41F W 0 1: CS / CAS 0 P40F 0 0 1 0 1 0 1 Port (P40) CS0 / CAS0 Port (P41) CS1 / CAS1 Port (P42) CS2 / CAS2 Note 1: Read-modify-write is prohibited for registers P4CR and P4FC. Note 2: When port P4 is used in the input mode, P4 register controls the built-in pull-up/pull-down resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up/pull-down resistor may be depended on the states of the input pin. Note 3: To output chip select signal ( CS0 / CAS0 to CS2 / CAS2 ), set the corresponding bits of the control register P4CR and the function register P4FC to "1". Chip select/wait controller (B0CS, B1CS, B2CS) registers select the function of CS / CAS . Note 4: P4 Figure 3.5.11 Registers for Port 4 93CW46A-64 2004-02-10 TMP93CW46A 3.5.6 Port 5 (P50 to P57) Port 5 is an 8-bit input port, also used as an analog input pin for the internal AD Converter. Port 5 Internal data bus Port 5 read P50 to P57 (AN0 to AN7) Conversion result register AD read AD converter Channel selector Figure 3.5.12 Port 5 7 P5 (000DH) Bit symbol Read/Write After reset Note: P57 6 P56 5 Port 5 Register 4 P54 R 3 P53 2 P52 1 P51 0 P50 P55 Input mode The input channel selection of AD converter is set by AD converter mode register ADMOD2. Figure 3.5.13 Register for Port 5 93CW46A-65 2004-02-10 TMP93CW46A 3.5.7 Port 6 (P60 to P67) Port 60 to 67 are 8-bit general-purpose I/O ports. I/O can be set on bit basis. Resetting sets port 6 as an input port and connects a pull-up resistor. It also sets all bits of the output latch to 1. In addition to functioning as a general-purpose I/O port, port 60 to 67 also function as serial channels 2, 3, 4 I/O functions. Writing 1 in the corresponding bit of the port 6 function register (P6FC) enables the respective functions. Resetting resets the function register P6FC to 0, and sets all bits to ports. (1) Port 60, 63, 66 (TXD2, TXD3, TXD4) In addition to functioning as a general-purpose I/O port, port 60, 63, 66 also function as serial channel TXD output pins. Reset Direction control (on bit basis) P6CR write Function control (on bit basis) P6FC write P-ch Programmable pull up A S Selector P60 (TXD2) P63 (TXD3) P66 (TXD4) Internal data bus S Output latch P6 write TXD2, TXD3, TXD4 B S Selector B A P6 read Figure 3.5.14 Port 60, 63, 66 93CW46A-66 2004-02-10 TMP93CW46A (2) Port 61, 64, 67 (RXD2, RXD3, RXD4) In addition to functioning as a general-purpose I/O port, port 61, 64, 67 also function as serial channel RXD input pins. Reset Direction control (on bit basis) P6CR write P-ch Programmable pull up P61 (RXD2) P64 (RXD3) P67 (RXD4) S Selector P6 read RXD2, RXD3, RXD4 A B Internal data bus S Output latch P6 write Figure 3.5.15 Port 61, 64, 67 (3) Port 62, 65 ( CTS2 /SCLK2, CTS3 /SCLK3) In addition to functioning as a general-purpose I/O port, port 62, 65 also function as serial channel 2, 3 CTS input pins or SCLK input/output pins. Reset Direction control (on bit basis) P6CR write Function control (on bit basis) Internal data bus P6FC write S Output latch P6 write SCLK2, SCLK3 S Selector B A P-ch Programmable pull up P62 (SCLK2/ CTS2 ) P65 (SCLK3/ CTS3 ) S Selector P6 read B A CTS2 , CTS3 SCLK2, SCLK3 Figure 3.5.16 Port 62, 65 93CW46A-67 2004-02-10 TMP93CW46A 7 P6 (0012H) Bit symbol Read/Write After reset 1 P67 6 P66 1 5 Port 6 Register 4 P64 R/W 3 P63 2 P62 1 1 P61 1 0 P60 1 P65 1 1 1 Input mode (Pull up) 7 P6CR (0014H) Bit symbol Read/Write After reset Function 0 P67C 6 P66C 0 Port 6 Control Register 5 4 3 P65C 0 P64C W 0 0 0: Input 1: Output P63C 2 P62C 0 1 P61C 0 0 P60C 0 Port 6 I/O setting 0 1 Input Output 7 P6FC (0016H) Bit symbol Read/Write After reset Function 6 P66F W 0 0: Port 1: TXD4 Port 6 Function Register 5 4 3 P65F 0 0: Port 1: SCLK3 P63F W 0 0: Port 1: TXD3 2 P62F 0 0: Port 1: SCLK2 1 0 P60F W 0 0: Port 1: TXD2 P60 TXD2 output setting P6FC P62 SCLK2 output setting P6FC P63 TXD3 output setting P6FC P65 SCLK2 output setting P6FC P66 TXD4 output setting P6FC Figure 3.5.17 Registers for Port 6 93CW46A-68 2004-02-10 TMP93CW46A 3.5.8 Port 7 (P70 to P73) Port 7 is a 4-bit general-purpose I/O port. I/O can be set on bit basis. Resetting sets port 7 as an input port and connects a pull-up resistor. In addition to functioning as a general-purpose I/O port, port 70 also functions as an input clock pin TI0 of an 8-bit timer 0, port 71 as an 8-bit timer output (TO1), port 72 as a PWM0 output (TO2), and port 73 as a PWM1 output (TO3) pin. Writing 1 in the corresponding bit of the port 7 function register (P7FC) enables output of the timer. Resetting resets the function register P7CR, P7FC to 0, and sets all bits to ports. Reset Direction control (on bit basis) P7CR write S Output latch P7 write S B P-ch Programmable pull up P70 (TI0) Selector P7 read TI0 Reset A Internal data bus Direction control (on bit basis) P7CR write Function control (on bit basis) P7FC write S Output latch P7 write Timer F/F OUT TO1: Timer 1 TO2: Timer 2 TO3: Timer 3 B Selector P7 read A B S Selector P71 to P73 (TO1 to TO3) Programmable pull up P-ch A S Figure 3.5.18 Port 7 93CW46A-69 2004-02-10 TMP93CW46A 7 P7 (0013H) Bit symbol Read/Write After reset Function 6 5 Port 7 Register 4 3 P73 1 2 P72 R/W 1 1 P71 1 0 P70 1 Input mode (Pull up) 7 P7CR (0015H) Bit symbol Read/Write After reset Function 6 Port 7 Control Register 5 4 3 P73C 0 2 P72C W 0 0: Input 1 P71C 0 1: Output 0 P70C 0 Port 7 I/O setting 0 1 Input Output 7 P7FC (0017H) Bit symbol Read/Write After reset Function 6 Port 7 Function Register 5 4 3 P73F 0 0: Port 1: TO3 2 P72F W 0 0: Port 1: TO2 1 P71F 0 0: Port 1: TO1 0 Setting P71 as TO1 P7FC Setting P72 as TO2 P7FC Setting P73 as TO3 P7FC Note 1: Read-modify-write is prohibited for registers P7CR and P7FC. Note 2: When port P7 is used in the input mode, P7 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Note 3: P70/TI0 pin does not have a register changing port/function. For example, when it is used as an input port, the input signal is inputted to 8-bit timer 0 as a timer input 0 (T10). Note 4: P4 Figure 3.5.19 Registers for Port 7 93CW46A-70 2004-02-10 TMP93CW46A 3.5.9 Port 8 (P80 to P87) Port 8 is an 8-bit general-purpose I/O port. I/O can be set on a bit basis. Resetting sets port 8 as an input port and connects a pull-up resistor. It also sets all bits of the output latch register P8 to 1. In addition to functioning as a general-purpose I/O port, port 8 also functions as an input for 16-bit timer 4 and 5 clocks, an output for 16-bit timer F/F 4, 5, and 6 output, and an input for INT0. Writing "1" in the corresponding bit of the port 8 function register (P8FC) enables those functions. Resetting resets the function register P8CR, P8FC to "0" and sets all bits to ports. (1) P80 to P86 Reset Direction control (on bit basis) P8CR write S Output latch P8 write S B P-ch Programmable pull up P80 (TI4/INT4) P81 (TI5/INT5) P84 (TI6/INT6) P85 (TI7/INT7) Selector TI4, TI5 TI6, TI7 P8 read Reset Direction control (on bit basis) P8CR write Function control (on bit basis) P8FC write S Output latch P8 write A S A Internal data bus P-ch Programmable pull up Selector Timer F/F OUT TO4: Timer 4 TO5: Timer 4 TO6: Timer 5 P8 read B B Selector S A P82 (TO4) P83 (TO5) P86 (TO6) Figure 3.5.20 Port 8 (P80 to P86) 93CW46A-71 2004-02-10 TMP93CW46A (2) P87 (INT0) Port 87 is a general-purpose I/O port, and also used as an INT0 pin for external interrupt request input. Reset Direction control (on bit basis) Internal data bus P8CR write S Output latch P8 write S Selector P8 read A B P-ch Programmable pull up P87 (INT0) INT0 interrupt Level/edge detect IIMC IIMC Figure 3.5.21 Port 87 93CW46A-72 2004-02-10 TMP93CW46A 7 P8 (0018H) Bit symbol Read/Write After reset 1 P87 6 P86 1 5 Port 8 Register 4 P84 R/W 1 3 P83 1 2 P82 1 1 P81 1 0 P80 1 P85 1 Input mode (Pull up) 7 P8CR (001AH) Bit symbol Read/Write After reset Function 0 P87C 6 P86C 0 Port 8 Control Register 5 4 3 P85C 0 P84C W 0 0: Input 0 1: Output P83C 2 P82C 0 1 P81C 0 0 P80C 0 Port 8 I/O setting 0 1 Input Output 7 P8FC (001CH) Bit symbol Read/Write After reset Function 6 P86F W 0 0: Port 1: TO6 Port 8 Function Register 5 4 3 P83F W 0 0: Port 1: TO5 2 P82F W 0 0: Port 1: TO4 1 0 Setting P82 as TO4 P8FC Setting P83 as TO5 P8FC Setting P84 as TO6 P8FC Note 1: Read-modify-write is prohibited for registers P8CR and P8FC. Note 2: When port P8 is used in the input mode, P8 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Note 3: P80/T14, P81/T15, P84/T16, P85/T17 pins do not have a register changing port/function. For example, when it is used as an input port, the input signal is inputted to 16-bit timer as a time input. When P87/INT0 pin is used as an INT0 pin, set P8CR Figure 3.5.22 Registers for Port 8 93CW46A-73 2004-02-10 TMP93CW46A 3.5.10 Port 9 (P90 to P97) * Port 90 to 95 Port 90 to 95 is a 6-bit general-purpose I/O port. I/Os can be set on a bit basis. Resetting sets P90 to P95 to an input port and connects a pull-up resistor. It also sets all bits of the output latch register to 1. In addition to functioning as a general-purpose I/O port, P90 to P95 can also function as an I/O for serial channels 0 and 1. Writing "1" in the corresponding bit of the port 9 function register (P9FC) enables those functions. Resetting resets the function register P9CR, P9FC to "0" and sets all bits to ports. * Port 96 to 97 Port 96 to 97 is a 2-bit general-purpose I/O port. I/Os can be set on a bit basis. The output buffer for P96 to P97 is an open drain type buffer. Resetting sets output latch and control registers to "1" and outputs high-impedance (High-Z). In addition to functioning as a general-purpose I/O port, P96 to P97 can also function as a low-frequency oscillator connecting pin (XT1, XT2) for dual clock mode. The dual clock function can be set by programming system clock control register SYSCR0, 1. (1) Port 90, 93 (TXD0/TXD1) Ports 90 and 93 also function as serial channel TXD output pins in addition to I/O ports. They have a programmable open-drain function. Reset Direction control (on bit basis) P9CR write Internal data bus Function control (on bit basis) P9FC write S Output latch P9 write P-ch Programmable pull up P90 (TXD0) P93 (TXD1) Open drain possible S Selector P9 read A B ODE A S Selector TXD0, TXD1 B Figure 3.5.23 Ports 90 and 93 93CW46A-74 2004-02-10 TMP93CW46A (2) Port 91, 94 (RXD0, RXD1) Port 91and 94 are I/O ports, and also used as RXD input pins for serial channels. Reset Direction control (on bit basis) P-ch Internal data bus P9CR write S Output latch S P9 write Selector P9 read A B Programmable pull up P91 (RXD0) P94 (RXD1) RXD0, RXD1 Figure 3.5.24 Ports 91 and 94 (3) Port 92 ( CTS0 /SCLK0) Port 92 is an I/O port, and also used as a CTS0 input pin and as a SCLK0 I/O pin for serial channel 0. Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write S Output latch P9 write P-ch Programmable pull up A S P92 (SCLK0/ CTS0 ) Selector SCLK0 OUT B Internal data bus S Selector P9 read CTS0 B A SCLK0 Figure 3.5.25 Ports 92 93CW46A-75 2004-02-10 TMP93CW46A (4) Port 95 (SCLK1) Port 95 is a general-purpose I/O port. It is also used as a SCLK1 I/O pin for serial channel 1. Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write S Output latch P9 write P-ch Programmable pull up A S P95 (SCLK1) Selector SCLK1 OUT B Internal data bus S Selector P9 read B A SCLK1 Figure 3.5.26 Port 95 93CW46A-76 2004-02-10 TMP93CW46A (5) Port 96 (XT1), 97(XT2) Port 96, 97 is general purpose I/O ports. It is also used as a low-frequency oscillator connecting pin. Reset Bus6 S Direction control (on bit basis) P9CR write Low-frequency oscillation enable Bus6 S Output latch P9 write P96 (XT1) Output buffer (Open-drain output) S Internal data bus Bus6 B Selector A P9 read (ON at "1") S Direction control (on bit basis) P9CR write Bus7 Bus7 S Output latch P9 write P97 (XT2) Output buffer (Open-drain output) Low-frequency clock (fs) S Bus7 Selector B A P9 read Figure 3.5.27 Port 96 to 97 93CW46A-77 2004-02-10 TMP93CW46A 7 P9 (0019H) Bit symbol Read/Write After reset 1 P97 6 P96 1 5 Port 9 Register 4 P94 R/W 1 3 P93 1 2 P92 1 Input mode 1 P91 1 0 P90 1 P95 1 Output mode 7 P9CR (001BH) Bit symbol Read/Write After reset Function 1 P97C 6 P96C 1 Port 9 Control Register 5 4 3 P95C 0 P94C W 0 0: Input 0 1: Output P93C 2 P92C 0 1 P91C 0 0 P90C 0 Port 9 I/O setting Note: Port 96, 97's output buffer is an open drain output type. 0 1 Input Output 7 P9FC (001DH) Bit symbol Read/Write After reset Function 6 Port 9 Function Register 5 4 3 P95F W 0 0: Port 1: SCLK1 P93F W 0 0: Port 1: TXD1 2 P92F W 0 0: Port 1: SCLK0 1 0 P90F W 0 0: Port 1: TXD0 P90 TXD0 output setting (Note) P9FC P92 SCLK0 output setting P9CR Figure 3.5.28 Register for Port 9 93CW46A-78 2004-02-10 TMP93CW46A 3.5.11 Port A (PA0 to PA7) Port A is an 8-bit general-purpose I/O port. Port A0 to A5 is possible to output large current and drive LED directly. I/Os can be set on a bit basis by control register PACR. After reset, PACR is reset to "0" and port A is set to an input port. In addition to functioning as a general-purpose I/O port (only PA7), PA7 can also functions as a clock output pin. The output clock is fFPH or fSYS that is selected by the CKOCR Reset R Direction Control (on bit basis) PACR write Internal data bus S Output latch PA write PA0 to PA6 S Selector B A PA read Figure 3.5.29 Port A0 to A6 93CW46A-79 2004-02-10 TMP93CW46A Reset Bus 7 R Direction control (on bit basis) PACR write Bus 2 R Function control (on bit basis) Internal data bus CKOCR write Bus 7 S Output latch S A Selector B PA7 (SCOUT) PA write S B Bus 7 PA read fFPH fSYS Selector A A Selector B S CKOCR Figure 3.5.30 Port A7 93CW46A-80 2004-02-10 TMP93CW46A 7 PA (001EH) Bit symbol Read/Write After reset 1 PA7 6 PA6 5 Port A Register 4 PA4 R/W 3 PA3 2 PA2 1 PA1 0 PA0 PA5 Input mode 1 1 1 1 1 1 1 7 PACR (001FH) Bit symbol Read/Write After reset Function 0 PA7C 6 PA6C 0 Port A Control Register 5 4 3 PA5C 0 PA4C W 0 0: Input 0 1: Output PA3C 2 PA2C 0 1 PA1C 0 0 PA0C 0 7 CKOCR (006DH) Bit symbol Read/Write After reset Function 6 Clock Output Control Register 5 4 3 SCOSEL 0 2 SCOEN R/W 0 1 ALEEN 0/1 ALE enable 0 CLKEN 0/1 CLK enable Clock select Clock enable CLK pin output control (Note 2) 0 1 "High-Z" output CLK output ALE pin output control (Note 2) 0 1 "High-Z" output ALE output SCOUT/PA7 pin control PACR 0 0 1 Output mode 0 1 0 1 Input Port 1 fFPH clock output fSYS clock output (Note 3) Note 1: Read-modify-write is prohibited for registers PACR. Note 2: The value after reset of e.g.) The case of connected 20 MHz oscillator to X1, X2 pin. Figure 3.5.31 Registers for Port A 93CW46A-81 2004-02-10 TMP93CW46A 3.6 Chip Select/Wait Controller, AM8/ AM16 Pin TMP93CW46A has a built-in chip select/wait controller used to control chip select ( CS0 to CS2 pins), wait ( WAIT pin), and data bus size (8 or 16 bits) for any of the three block address areas. And AM8/ AM16 pin selects external data bus width for TMP93CW46A. 3.6.1 AM8/ AM16 Pin Set this pin to "1". After reset, the CPU accesses the internal ROM with 16-bit bus width. The bus width when the CPU accesses an external area is set by chip select/wait control register (Described at 3.6.3.) and the registers of port 1. 3.6.2 Address/Data Bus Pins Port 0/AD0 to AD7, Port 1/AD8 to AD15 and Port 2/AD16 to AD23/A0 to A7 function as address/data bus for connecting the external memories. a. b. Max 24 (to 16 Mbytes) 16 16 AD0 to AD7 AD8 to AD15 A16 to A23 A23 to 16 A23 to 16 A15 to 0 D15 to 0 c. Max 16 (to 64 Kbytes) 8 0 AD0 to AD7 A8 to A15 A0 to A7 A15 to 0 A15 to 0 (Note 1) A7 D7 to 0 to 0 d. Max 8 (to 256 bytes) 16 0 AD0 to AD7 AD8 to AD15 A0 to A7 A7 to 0 A7 to 0 (Note 1) A15 D15 to 0 to 0 Number of address bus pins Number of data bus pins Number of multiplexed pins Port 0 Port function Port 1 Port 2 Max 24 (to 16 Mbytes) 8 8 AD0 to AD7 A8 to A15 A16 to A23 A23 to 8 A23 to 8 A7 to 0 D7 to 0 AD7 to 0 AD15 to 0 ALE AD7 to 0 ALE AD15 to 0 ALE Timing chart ALE RD RD RD RD Note 1: In case of c. and d., the data bus signals output the addresses since the signals are also used as the address bus. Writing "0" to bit CKOCR 93CW46A-82 2004-02-10 TMP93CW46A 3.6.3 Chip Select/Wait Control Registers Table 3.6.1 shows control registers. One block address areas are controlled by 1-byte CS/WAIT control registers (B0CS, B1CS, and B2CS). (1) Enable Control register bit7 (B0E, B1E, and B2E) is a master bit used to specify enabling ("1")/disabling ("0") of the setting. Resetting sets B0E and B1E to disable ("0") and B2E to enable ("1"). (2) CS/CAS Waveform select Control register bit5 (B0CAS, B1CAS, and B2CAS) is used to specify waveform mode output from the chip select pin ( CS0 / CAS0 to CS2 / CAS2 ). Setting this bit to 0 specifies CS0 to CS2 waveforms; setting it to 1 specifies CAS0 to CAS2 waveforms. Resetting clears bit5 to 0. (3) Data bus size select Bit4 (B0BUS, B1BUS, and B2BUS) of the control register is used to specify data bus size. Setting this bit to 0 accesses the memory in 16-bit data bus mode; setting it to 1 accesses the memory in 8-bit data bus mode. Changing data bus size depending on the access address is called dynamic bus sizing. Table 3.6.2 shows the details of the bus operation. (4) Wait control Control register bits 3 and 2 (B0W1 to B0W0, B1W1 to B1W0, B2W1 to B2W0) are used to specify the number of waits. Setting these bits to 00 inserts a 2 states wait regardless of the WAIT pin status. Setting them to 01 inserts a 1-state wait regardless of the WAIT status. Setting them to 10 inserts a 1-state wait and samples the WAIT pin status. If the pin is low, inserting the wait maintains the bus cycle until the pin goes high. Setting them to 11 completes the bus cycle without a wait regardless of the WAIT pin status. Resetting sets these bits to 00 (2-state wait mode). (5) Address area specification Control register bits 1 and 0 (B0C1 to B0C0, B1C1 to B1C0, B2C1 to B2C0) are used to specify the target address area. Setting these bits to 00 enables settings (CS output, Wait state, Bus size, etc.) as follows: * CS0 setting enabled when 7F00H to 7FFFH is accessed. * CS1 setting enabled when 1080H to 7FFFH is accessed. * CS2 setting enabled when 28000H to 3FFFFH is accessed. Setting bits to 01 enables setting for all CS's blocks and outputs a low strobe signal ( CS0 / CAS0 to CS2 / CAS2 ) from chip select pins when 400000H to 7FFFFFH is accessed. Setting bits to 10 enables them 800000H to BFFFFFH is accessed. Setting bits to 11 enables them when C00000H to FFFFFFH is accessed. 93CW46A-83 2004-02-10 TMP93CW46A Table 3.6.1 Chip Select/Wait Control Register Code Name Address 7 B0E Block0 CS/WAIT control register W 0068H 0 1: Master bit of bit 0 to 6 6 5 B0CAS W 0 0: CS0 1: CAS0 4 B0BUS W 0 0: 16-bit bus 1: 8-bit bus B1BUS W 0 0: 16-bit bus 1: 8-bit bus B2BUS W 0 0: 16-bit bus 1: 8-bit bus 3 B0W1 W 0 2 B0W0 W 0 1 B0C1 W 0 0 B0C0 W 0 B0CS 00: 2 waits 01: 1 wait 10: (1 + N) waits 11: 0 waits B1W1 W 0 B1W0 W 0 00: 7F00H to 7FFFH 01: 400000H to 10: 800000H to 11: C00000H to B1C1 W 0 B1C0 W 0 B1E Block1 CS/WAIT control register W 0069H 0 1: Master bit of bit 0 to 6 B1CAS W 0 0: CS1 1: CAS1 B1CS 00: 2 waits 01: 1 wait 10: (1 + N) waits 11: 0 waits B2W1 W 0 B2W0 W 0 00: 1080H to 7FFFH 01: 400000H to 10: 800000H to 11: C00000H to B2C1 W 0 00: 28000H to 01: 400000H to 10: 800000H to 11: C00000H to B2C0 W 0 B2E Block2 CS/WAIT control register W 006AH 1 1: Master bit of bit 0 to 6 B2CAS W 0 0: CS2 1: CAS2 B2CS 00: 2 waits 01: 1 wait 10: (1 + N) waits 11: 0 waits Table 3.6.2 Dynamic Bus Sizing Operand Data Size 8 bits Operand Start Memory Data Address Size 2n + 0 (Even number) 2n + 1 (Odd number) 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 2n + 1 (Odd number) 16 bits 8 bits CPU Address 2n + 0 2n + 0 2n + 1 2n + 1 2n + 0 2n + 1 2n + 0 2n + 1 2n + 2 2n + 1 2n + 2 2n + 0 2n + 1 2n + 2 2n + 3 2n + 0 2n + 2 2n + 1 2n + 2 2n + 3 2n + 4 2n + 1 2n + 2 2n + 4 CPU Data D15 to D8 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx D7 to D0 b7 to b0 b7 to b0 b7 to b0 xxxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 16 bits 2n + 0 (Even number) 32 bits 2n + 0 (Even number) 8 bits 16 bits 2n + 1 (Odd number) 8 bits 16 bits xxxxx: During a read, data input to the bus is ignored. At write, the bus is at high impedance and the wirte strobe signal remains non active. 93CW46A-84 2004-02-10 TMP93CW46A 3.6.4 Chip Select Image An image of the actual chip select is shown below. Out of the whole memory area, address areas that can be specified are divided into four parts. Addresses from 000000H to 3FFFFFH are divided differently: 7F00H to 7FFFH is specified for CS0; 1080H to 7FFFH, for CS1; and 28000H to 3FFFFFH, for CS2. The reason is that a device other than ROM (e.g., RAM or I/O) might be connected externally. 7F00H to 7FFFH (256 bytes) for CS0 are mapped mainly for possible expansions to external I/O. 1080H to 7FFFH (Approx. 31 Kbytes) for CS1 are mapped there mainly for possible extensions to external RAM. 28000H to 3FFFFFH (Approx. 4 Mbytes) for CS2 are mapped mainly for possible extensions to external ROM. With the TMP93CW46A which has a built-in ROM, addresses from 8000H to 27FFFH are used as the internal ROM area. After reset, the CPU reads the program from the built-in ROM in 16-bit bus, 0-wait mode. CS0 CS1 CS2 000000H 7F00H 8000H 28000H 400000H B0C1, 0 = "01" 800000H B0C1, 0 = "10" C00000H B0C1, 0 = "11" FFFFFFH (Mainly for I/O) (Mainly for RAM) (Mainly for ROM) B1C1, 0 = "11" B2C1, 0 = "11" B1C1, 0 = "10" B2C1, 0 = "10" B1C1, 0 = "01" B2C1, 0 = "00" B2C1, 0 = "01" B0C1, 0 = "00" B1C1, 0 = "00" Note 1: Access priority is highest for built-in I/O, then built-in memory, and lowest for the chip select/wait controller. Note 2: External areas other than CS0 to CS2 are accessed in 16-bit data bus (0 waits) mode. When using the chip select/wait controller, do not specify the same address area more than once. (However, when addresses 7F00H to 7FFFH for CS0 and 1080H to 7FFFH for CS1 are specified, in other words, specifications overlap, only the CS0 setting/pin is active.) Note 3: When the bus is released ( BUSAK = "0"), CS0 to CS2 pins are also released (the output buffer is OFF). Refer to note about the bus release in 3.5 "Functions of Ports" about the state of pins. 93CW46A-85 2004-02-10 TMP93CW46A 3.6.5 Example of Usage Figure 3.6.1 is an example in which an external memory is connected to the TMP93CW46A. In this example, a ROM 128 Kbytes is connected using 16-bit bus, and RAM 256 Kbytes using 16-bit bus. TMP93CW46A A16 to A17 AD8 to AD15 Latch x 16 D Q LE A16 A1 to A15 ROM (128 Kbits x 16) A15 A0 to A14 OE CE D8 to D15 D0 to D7 AD0 to AD7 ALE CS2 RAM (128 Kbits x 8) A16 to A17 A1 to A15 A15 to A16 A0 to A14 OE R/ W CE1 I/O1 to I/O8 RD HWR Upper byte CS1 WR A1 to A15 RAM (128 Kbits x 8) A16 to A17 A15 to A16 A0 to A14 OE R/ W CE1 I/O1 to I/O8 AM8/ AM16 EA Lower byte Figure 3.6.1 Example of External Memory Connection (ROM and RAM = 16 bits) TMP93CW46A has built-in ROM and RAM. When ROM and RAM have insufficient capacity, it is possible to connect an external memory as the example of the external memory connection. In this example, the memory configuration is as follows. Memory ROM SRAM Internal External Internal External Memory Size 128 Kbytes 128 Kbytes 4 Kbytes 256 Kbytes Address 008000H to 027FFFH 400000H to 41FFFFH 000080H to 00107FH 800000H to 83FFFFH CS Pin - CS2 Data Bus 16 bits 16 bits 16 bits 16 bits - CS1 93CW46A-86 2004-02-10 TMP93CW46A 3.7 8-Bit Timers The TMP93CW46A contains two 8-bit timers (Timers 0 and 1), each of which can be operated independently. The cascade connection allows these timers to be used as 16-bit timer. The following four operating modes are provided for the 8-bit timers. * * * * 8-bit interval timer mode (2 timers) 16-bit interval timer mode (1 timer) 8-bit programmable square wave pulse generation (PPG: Variable duty with variable cycle) output mode (1 timer) 8-bit pulse width modulation (PWM: variable duty with constant cycle) output mode (1 timer) Figure 3.7.1 shows the block diagram of 8-bit timer (Timer 0 and timer 1). Each timer consists of an 8-bit up counter, 8-bit comparator, and 8-bit timer register. Besides, one timer flip-flop (TFF1) is provided for pair of timer 0 and timer 1. Among the input clock sources for the timers, the internal clocks of T1, T4, T16, and T256 are obtained from the 9-bit prescaler shown in Figure 3.7.2. The operation modes and timer flip-flops of the 8-bit timer are controlled by three control registers TMOD, TFFCR, and TRUN. 93CW46A-87 2004-02-10 TRUN TRUN Timer F/F control RUN Clear RUN Clear TFFCR, TMOD TFF1 TO1 (P71) Selector 2n - 1 Over flow T1 T16 T256 Selector TMOD TI0 pin T1 T4 T16 TMOD 8-bit up counter (UC0) 8-bit up counter (UC1) Figure 3.7.1 Block Diagram of 8-Bit Timers (Timers 0 and 1) 93CW46A-88 8-bit comparator (CP0) Select Register buffer TFFCR 8-bit comparator (CP1) Match detect Selector TMOD PPGTRG PWMTRG TREG0-WR INTT1 TMP93CW46A 2004-02-10 TMP93CW46A 1. Prescaler, Prescaler clock select There are 9 bit prescaler and prescaler clock selection register to generate input clock for 8-bit timers 0 and 1, 16-bit timers 4 and 5 and serial interfaces 0 to 4. Figure 3.7.2 shows the block diagram. Table 3.7.1 shows prescaler clock resolution into 8, 16-bit timer. To CPU System clock (fSYS) To 8-bit PWM prescaler 9-bit prescaler Selector 2 4 8 16 32 64 128 256 512 2 4 T1 T4 T16 T256 T1 T4 T16 2 fFPH To 8-bit timers 0 and 1 XT1 fs Selector SYSCR0 To 16-bit timers 4 and 5 SYSCR1 2 1 T0 T2 T8 T32 Selector To serial interfaces 0 to 4 fc fc/2 fc/4 fc/8 fc/16 SYSCR1 X1 /2 /4 /8 /16 Figure 3.7.2 The Block Diagram of Prescaler Table 3.7.1 Prescaler Clock Resolution to 8-/16-Bit Timer at fc = 20 MHz, fs = 32.768 kHz Select System Clock 1 (fs) Select Prescaler Clock Gear Value XXX 000 (fc) Prescaler Clock Resolution T1 fs/23 (244 s) fc/23 (0.4 s) fc/2 fc/2 fc/2 fc/2 4 5 6 7 T4 fs/25 (977 s) fc/25 (1.6 s) fc/2 fc/2 fc/2 fc/2 6 7 8 9 T16 fs/27 (3.9 ms) fc/27 (6.4 s) fc/2 fc/2 fc/2 fc/2 8 9 10 11 T256 fs/211 (62.5 ms) fc/211 (102.4 s) fc/212 (204.8 s) fc/213 (409.6 s) fc/214 (819.2 s) fc/215 (1.638 ms) fs/211 (62.5 ms) fc/215 (1.638 ms) 00 0 (fc) (fFPH) 001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16) (0.8 s) (1.6 s) (3.2 s) (6.4 s) (3.2 s) (6.4 s) (12.8 s) (25.6 s) (12.8 s) (25.6 s) (51.2 s) (102.4 s) XXX XXX 01 (Low-frequency clock) 10 (Note) (fc/16 clock) XXX XXX fs/23 (244 s) fc/27 (6.4 s) fs/25 (977 ms) fc/29 (25.6 s) 16-bit timer 8-bit timer fs/27 (3.9 ms) fc/211 (102.4 s) XXX: Don't care Note: The fc/16 clock as a prescaler clock can not be used when the fs is used as a system clock. 93CW46A-89 2004-02-10 TMP93CW46A The clock selected among fFPH clock, fc/16 clock and fs is divided by 4 and input to this prescaler. This is selected by prescaler clock selection register SYSCR0 When TMOD 93CW46A-90 2004-02-10 TMP93CW46A 3. Timer register This is an 8-bit register for setting an interval time. When the set value of timer registers TREG0, TREG1, matches the value of up counter, the comparator match detect signal becomes active. If the set value is 00H, this signal becomes active when the up counter overflows. Timer register TREG0 is a double buffer structure, each of which makes a pair with register buffer. The timer flip-flop control register TFFCR Up counter Comparator (CP0) Timer registers 0 (TREG0) Matching detection of PPG cycle 2n - 1 overflow of PWM TREG0 WR Shift trigger Register buffers 0 Write Internal data bus Selector TFFCR Figure 3.7.3 Configuration of Timer Register 0 Note: Timer register and the register buffer are allocated to the same memory address. When The memory address of each timer register is as follows. TREG0: 000022H TREG1: 000023H All the registers are write-only and cannot be read. 93CW46A-91 2004-02-10 TMP93CW46A 4. Comparator A comparator compares the value in the up counter with the values to which the timer register is set. When they match, the up counter is cleared to zero and an interrupt signal (INTT0, INTT1) is generated. If the timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. 5. Timer flip-flop The timer flip-flop (TFF1) is a flip-flop inverted by the match detect signal (8-bit comparator output). Inverting is disabled or enabled by the timer flip-flop control register TFFCR 93CW46A-92 2004-02-10 TMP93CW46A 7 TRUN (0020H) Bit symbol Read/Write After reset Function PRRUN R/W 0 6 5 T5RUN 0 4 T4RUN 0 3 P1RUN R/W 0 2 P0RUN 0 1 T1RUN 0 0 T0RUN 0 Prescaler and timer run/stop control 0: Stop and clear 1: Run (Count up) Count operation 0 1 PRRUN: Operation of prescaler T5RUN: Operation of 16-bit timer (Timer 5) T4RUN: Operation of 16-bit timer (Timer 4) P1RUN: Operation of PWM timer (PWM1/Timer 3) P0RUN: Operation of PWM timer (PWM0/Timer 2) T1RUN: Operation of 8-bit timer (Timer 1) T0RUN: Operation of 8-bit timer (Timer 0) Stop and clear Count 7 SYSCR0 Bit symbol (006EH) Read/Write After reset Function XEN 1 Highfrequency oscillator (fc) 6 XTEN 0 Lowfrequency oscillator (fs) 5 RXEN 1 4 RXTEN 0 Lowfrequency oscillator (fs) after released STOP mode 0: Stop 1: Oscillator 3 RSYSCK R/W 0 Select clock after released STOP mode 0: fc 1: fs 2 WUEF 0 Warm-up timer (Write) 1 PRCK1 0 00: fFPH 0 PRCK0 0 Highfrequency oscillator (fc) after released 0: Stop 0: Stop 1: Oscillator 1: Oscillator STOP mode 0: Stop 1: Oscillator Select prescaler clock 01: fs 0: Don't care 10: fc/16 1: Start 11: (Reserved) timer (Read) 0: End warm up 1: Not end warm up Figure 3.7.4 Timer Operation Control Register/System Clock Control Register 93CW46A-93 2004-02-10 TMP93CW46A 7 TMOD (0024H) Bit symbol Read/Write After reset Function 0 Operation mode 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM T10M1 6 T10M0 0 5 PWMM1 0 PWM cycle 00: - 01: 26 - 1 10: 27 - 1 11: 28 - 1 4 PWMM0 W 0 3 T1CLK1 0 2 T1CLK0 0 1 T0CLK1 0 0 T0CLK0 0 Source clock of timer 1 00: TO0TRG 01: T1 10: T16 11: T256 Source clock of timer 0 00: TI0 01: T1 10: T4 11: T16 Input clock of timer 0 00 01 10 11 External input (TI0) T1 (Prescaler) T4 (Prescaler) T16 (Prescaler) Input clock of timer 1 TMOD 00 01 10 11 Comparator output of timer 0 Internal clock T1 Internal clock T16 Internal clock T256 Select PWM cycle 00 01 10 11 - 26 - 1 27 - 1 28 - 1 Set the operation mode of timers 0 and 1 00 01 10 11 Note: Prohibit read-modify-write Two 8-bit timers (Timer 0 and timer 1) 16-bit timer 8-bit PPG output 8-bit PWM output (Timer 0) 8-bit timer (Timer 1) Figure 3.7.5 Timer Mode Control Register (TMOD) 93CW46A-94 2004-02-10 TMP93CW46A 7 TFFCR (0025H) Bit symbol Read/Write After reset Function 6 5 4 DBEN R/W 0 Double buffer 0: Disable 1: Enable 3 TFF1C1 W 1 2 TFF1C0 1 1 TFF1IE R/W 0 TFF1 Inversion trigger 0: Disable 1: Enable 0 TFF1IS 0 TFF1 Inversion source 0: Timer 0 1: Timer 1 00: Invert TFF1 01: Set TFF1 10: Clear TFF1 11: Don't care * Always read as "11" Select inverse signal of timer F/F1 ("Don't care" except in 8-bit timer mode) TMOD 01 10 11 PWM mode Inversion by match and 0 1 Inversion by timer 0 match signal Inversion by timer 1 match signal 16-bit timer mode PPG mode Inversion by match signal Inversion by match signal of each timer 0 and overflow signal timer 1 of timer 0 Inversion of timer F/F1 (TFF1) 0 1 Disable invert Enable invert Control of timer F/F1 (TFF1) 00 01 10 11 Invert the value of TFF1 (software inversion) Set TFF1 to "1". Clear TFF1 to "0". Don't care Double buffer control of TREG0 0 1 Disable double buffer Enable double buffer Note: TFFCR Figure 3.7.6 Timer Flip-Flop Control Register (TFFCR) 93CW46A-95 2004-02-10 TMP93CW46A The operation of 8-bit timers will be described below: (1) 8-bit timer mode Two interval timers 0, 1, can be used independently as 8-bit interval timer. All interval timers operate in the same manner, and thus only the operation of timer 1 will be explained below. 1. Generating interrupts in a fixed cycle To generate timer 1 interrupt at constant intervals using timer 1 (INTT1), first stop timer 1 then set the operation mode, input clock, and a cycle to TMOD and TREG1 register, respectively. Then, enable interrupt INTT1 and start the counting of timer 1. Example: To generate timer 1 interrupt every 1 s at fs = 32.768 MHz, set each register in the following manner. System clock: Clock gear: Prescaler clock: Low frequency (fs) xxx Low frequency (fs) * Clock condition MSB TRUN TMOD TREG1 INTET10 TRUN 7 - 0 0 1 1 6 X 0 0 1 X 5 - X 0 0 - 4 - X 0 1 - 3 - 1 0 - - 2 - 0 0 - - 1 0 - 0 - 1 LSB 0 - - 0 - - Stop timer 1, and clear it to "0". Set the 8-bit timer mode, and select T16 (3.9 ms at fs = 32.768 kHz) as the input clock. Set the timer register 1 s / T16 = 256 (00H). Enable INTT1, and set it to level 5. Start timer 1 counting. X: Don't care, -: No change Use the Table 3.7.1 for selecting the input clock. Note: The input clock of timer 0 and timer 1 are different from as follows. Timer 0: TI0 input, T1, T4, T16 Timer 1: Match output of timer 0, T1, T16, T256 93CW46A-96 2004-02-10 TMP93CW46A 2. Generating a 50% duty square wave pulse The timer flip-flop (TFF1) is inverted at constant intervals, and its status is output to timer output pin (TO1). Example: To output a 4.0 s square wave pulse from TO1 pin at fc = 20 MHz, set each register in the following procedures. Either timer 0 or timer 1 may be used, but this example uses timer 1. System clock: Clock gear: Prescaler clock: High frequency (fc) 1 (fc) fFPH * Clock condition TRUN TMOD TREG1 TFFCR P7CR P7FC TRUN 7 - 0 0 - X X 1 6 - 0 0 - X X X 5 - X 0 - X X - 4 - X 0 - X X - 3 - 0 0 1 - - - 2 - 1 1 0 - - - 1 1 - 0 1 1 1 1 0 - - 1 1 - X - Stop timer 1, and clear it to "0". Set the 8-bit timer mode, and select T1 (0.4 s at fc = 20 MHz) as the input clock. Set the timer register 4.0 s / T1 / 2 = 5. Clear TFF1 to "0", and set to invert by the match detect signal from timer 1. Select P71 as TO1 pin. Start timer 1 counting. X: Don't care, -: No change T1 TRUN TFF1 TO1 2.0 s at fc = 20 MHz Figure 3.7.7 Square Wave (50% Duty) Output Timing Chart 93CW46A-97 2004-02-10 TMP93CW46A 3. Making timer 1 count up by match signal from timer 0 comparator Set the 8-bit timer mode, and set the comparator output of timer 0 as the input clock to timer 1. Comparator output (Timer 0 match) Timer 0 up counter (when TREG0 = 5) Timer 1 up counter (when TREG1 = 2) Timer 1 match output 1 2 3 1 4 5 1 2 3 2 4 5 1 2 1 3 Figure 3.7.8 Timer 1 Count Up by Timer 0 (2) 16-bit timer mode A 16-bit interval timer is configured by using the pair of timer 0 and timer 1. To make a 16-bit timer mode, set timer 0/timer 1 mode register TMOD System clock: High frequency (fc) High frequency clock gear: 1 (fc) Prescaler clock: fFPH * Clock condition When counting with input clock of T16 (6.4 s at 20 MHz) 0.4 s / 6.4 s = 62500 = F424H Therefore, set TREG1 = F4H and TREG0 = 24H, respectively. 93CW46A-98 2004-02-10 TMP93CW46A The comparator match signal is output from timer 0 each time the up counter UC0 matches TREG0, where the up counter UC0 is not be cleared. With the timer 1 comparator, the match detect signal is output at each comparator timing when up counter UC1 and TREG1 values match. When the match detect signal is output simultaneously from both comparators of timer 0 and timer 1, the up counters UC0 and UC1 are cleared to "0", and the interrupt INTT1 is generated. If inversion is enabled, the value of the timer flip-flop TFF1 is inverted. Example: When TREG1 = 04H and TREG0 = 80H Value of up counter (UC1, UC0) Timer 0 comparator match detect signal 0000H 0080H 0180H 0280H 0380H 0480H Interrupt INTT1 Timer output TO1 Inversion Figure 3.7.9 Timer Output by 16-Bit Timer Mode (3) 8-bit PPG (Programmable pulse generation) output mode Square wave pulse can be generated at any frequency and duty by timer 0. The output pulse may be either low-active or high-active. In this mode, timer 1 cannot be used. Timer 0 outputs pulse to TO1 pin (Also used as P71). tH tL t TREG0 and UC0 match (Interrupt INTT0) TREG1 and UC0 match (Interrupt INTT1) TO1 TREG0 TREG1 Figure 3.7.10 8-Bit PPG Output Waveforms 93CW46A-99 2004-02-10 TMP93CW46A In this mode, a programmable square wave is generated by inverting timer output each time the 8-bit up counter (UC0) matches the timer registers TREG0 and TREG1. However, it is required that the set value of TREG0 is smaller than that of TREG1. Though the up counter (UC1) of timer 1 is not used in this mode, UC1 should be set for counting by setting TRUN TO1 TI0 pin T1 T4 T16 TRUN Inversion TMOD Comparator INTT1 TREG 0 TREG0-WR Selector Shift trigger Register buffer TFFCR Figure 3.7.11 Block Diagram of 8-Bit PPG Output Mode When the double buffer of TREG0 is enabled in this mode, the value of register buffer will be shifted in TREG0 each time TREG1 matches UC0. Use of the double buffer makes the handling of low duty waves easily (when duty is varied). Match with TREG0 and up counter (Up counter = Q1) Match with TREG 1 TREG 0 (Value to be compared) Register buffer Q1 Q2 Shift from register buffer Q2 Q3 TREG 0 (Register buffer) write (Up counter = Q2) Figure 3.7.12 Operation of Register Buffer 93CW46A-100 2004-02-10 TMP93CW46A Example: Generating 1/5 duty 50 kHz pulse (at fc = 20 MHz) 20 s System clock: Clock gear: Prescaler clock: High frequency (fc) 1 (fc) fFPH * Clock condition Calculate the value to be set for timer register. To obtain the frequency 50 kHz, the pulse cycle t should be: t = 1/50 kHz = 20 s. Given T1 = 0.4 s (at 20 MHz), 20 s / 0.4 s = 50 Consequently, to set the timer register 1 (TREG1) to TREG1 = 50 = 32H and then duty to 1/5, t x 1/5 = 20 s x 1/5 = 4 s 4 s / 0.4 s = 10 Therefore, set timer register 0 to TREG0 = 10 = 0AH. 7 - 1 0 0 - 6 X 0 0 0 - 5 - X 0 1 - 4 - X 0 1 1 3 - X 1 0 0 2 - X 0 0 1 1 0 0 1 1 1 0 0 1 0 0 X TRUN TMOD TREG0 TREG1 TFFCR Stop timer 0, and clear it to "0". Set the 8-bit PPG mode, and select T1 as input clock. Write "0AH". Write "32H". Sets TFF1 and enable the inversion and double buffer enable. Writing "10" provides negative logic pulse. Set P71 as the TO1 pin. Start timer 0 and timer 1 counting. P7CR P7FC TRUN X X 1 X X X X X - X X - - - - - - - 1 1 1 - X 1 X: Don't care, -: No change 93CW46A-101 2004-02-10 TMP93CW46A (4) 8-bit PWM output mode This mode is valid only for timer 0. In this mode, maximum 8-bit resolution of PWM pulse can be output. PWM pulse is output to TO1 pin (also used as P71) when using timer 0. Timer 1 can also be used as 8-bit timer. Timer output is inverted when up counter (UC0) matches the set value of timer register TREG0 or when 2n - 1 (n = 6, 7, or 8; specified by TMOD TREG0 and UC0 match 2n - 1 overflow (interrupt INTT0) TO1 tPWM (PWM cycle) Figure 3.7.13 8-Bit PWM Waveforms Figure 3.7.14 shows the block diagram of this mode. TRUN Selector Clear TMOD TFF1 2n - 1 TMOD Invert INTT 0 TREG0 Selector TREG0-WR TFFCR Figure 3.7.14 Block Diagram of 8-Bit PWM Mode 93CW46A-102 2004-02-10 TMP93CW46A In this mode, the value of register buffer will be shifted in TREG0 if 2n - 1 overflow is detected when the double buffer of TREG0 is enabled. Use of the double buffer makes easy the handling of small duty waves. Match with TREG0 Up counter = Q1 2n - 1 overflow TREG 0 (Value to be compared) Register buffer Shift into TREG0 Q1 Q2 Q2 Q3 TREG0 (Register buffer) write Up counter = Q2 Figure 3.7.15 Operation of Register Buffer Example: To output the following PWM waves to TO1 pin at fc = 20 MHz. 68 s 102 s System clock: Clock gear: Prescaler clock: High frequency (fc) 1 (fc) fFPH * Clock condition To realize 102 s of PWM cycle by T1 = 0.4 s (at fc = 20 MHz), 102 s / 0.4 s = 255 = 2n - 1 Consequently, n should be set to 8. As the period of low level is 68 s, for T1 = 0.4 s, set the following value for TREG0. 68 s / 0.4 s = 170 = AAH MSB 7 - 1 1 X X X 1 LSB 0 0 1 0 X - X 1 TRUN TMOD TREG0 TFFCR P7CR P7FC TRUN 6 X 1 0 X X X X 5 - 1 1 X X X - 4 - 0 0 X X X - 3 - - 1 1 - - - 2 - - 0 0 - - - 1 - 0 1 1 1 1 - Stop timer 0, and clear it to "0". Set 8-bit PWM mode (cycle: 28 - 1) and select T1 as the input clock. Writes "AAH". Clears TFF1, enable the inversion and double buffer. Set P71 as the TO1 pin. Start timer 0 counting. X: Don't care, -: No change 93CW46A-103 2004-02-10 TMP93CW46A Table 3.7.2 PWM Cycle at fc = 20 MHz, fs = 32.768 kHz Select Prescaler Clock 1 (fs) Select Gear Value System |