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High Speed Synchronous Power MOS.ET Driver
POWER MANAGEMENT Description
The SC1205H is a cost effective, High Drive Voltage, Dual MOS.ET Driver designed for switching High and Low side Power MOS.ETs. Each driver is capable of Ultrafast rise/fall times as well as a 20ns max propagation delay from input transition to the gate of the power .ETs. An internal Overlap Protection circuit prevents shootthrough from Vin to GND in the main and synchronous MOS.ETs. The Adaptive Overlap Protection circuit ensures the Bottom .ET does not turn on until the Top .ET source has reached a voltage low enough to prevent cross-conduction. Higher gate voltage drive capability of 8V (top and bottom) optimally reduces Rds_on of power MOS.ETs without excessive driver and .ET switching losses. The high current drive capability (5A peak) allows fast switching, thus reducing switching losses at high (up to 1MHz) frequencies without causing thermal stress on the driver. The high voltage CMOS process allows operation from 518 Volts at top MOS.ET drain, thus making SC1205H suitable for battery powered applications. Connecting Enable pin (EN) to logic low shuts down both drives and reduces operating current to less than 10A. An under-voltage-lock-out and overtemperature shutdown feature is included to guarantee proper and safe operation. The SC1205H is offered in a standard SO-8 package.
SC1205H
PRELIMINARY .eatures
K Higher efficiency (>90%) K .ast rise and fall times (15ns typical with 3000pf KHigher gate drive voltage (8V) for optimum
load) MOS.ET RDS_ON at minimum switching loss
K Ultra-low (<20ns) propagation delay (BG going low) K 5 Amp peak drive current K Adaptive non-overlapping gate drives provide K K K K K K K K K K
shoot-through protection .loating top drive switches up to 18V Under-voltage lock-out Over-temperature shutdown Less than 10A supply current when EN is low Low cost
Applications
Intel PentiumTM power supplies AMD AthlonTM and K8TM power supplies High efficiency portable and notebook computers Battery powered applications High frequency (to 1.0 MHz) operation allows use of small inductors and low cost caps in place of electrolytics
Typical Application Circuit
Vin 5-12V
2200uf 10u,CER 10nf 10 2.5m
+8V
70N03
1 2 3 4 5 6 7 Rf 8
VID4 VID3 VID2 VID1 VID0 ERROUT FB RREF
VCC BGOUT OC+ OUT1 OUT2 OCUVLO GND
16 15 14 13 12 11
BST TG
+8V
VS EN
DRN 70N03 BG
CO SC1205H GND
1.5V,40A
70N03 10 9 BST TG VS EN DRN 70N03 Rref
+8V
SC2422B
CO Ri SC1205H
BG
GND
Revision 2, June 2002
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SC1205H
POWER MANAGEMENT Absolute Maximum Ratings
Parameter VCC Supply Voltage BST to PGND BST to DRN DRN to PGND DRN to PGND Pulse Symbol VIMAXSW VMAXBST-PGND VMAXBST-DRN VMAXDRN-PGN VMAXPULSE tPULSE < 100ns tPULSE < 20ns EN to PGND Input Pin Continuous Power Dissipation Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec. VMAXOVP S-PGND CO PD J C J A TJ TSTG TLEAD Tamb = 25C, TJ = 125C Tcase = 25C, TJ =125C Conditions Maximum 11 30 11 -2 to 25 -5 to 25 -10 to 25 12 -0.3 to 12 0.66 2.56 40 150 0 to +125 -65 to +150 300 V V W C/W C/W C C C
PRELIMINARY
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Units V V V V V
Note: (1) Specification refers to application circuit in Figure 1.
Electrical Characteristics
Unless specified: -0 < J < 125C; VCC = 5V; 4V < VBST < 26V
Parameter Pow er Supply Supply Voltage Quiescent Current, Operating Quiescent Current Under Voltage Lockout Start Threshold Hysteresis
Symbol
Conditions
Min
Typ
Max
Units
V CC Iq_op Iq_stby
V CC VCC = 5V, CO = OV EN = OV
4.2
5 1
9.0
V mA
10
A
VSTART VhysUVLO
4.2
4.4 0.05
4.75
V V
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SC1205H
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: -0 < J < 125C; VCC = 5V; 4V < VBST < 26V
PRELIMINARY
Parameter CO High Level Input Voltage High Level Input Voltage Low Level Input Voltage EN High Level Input Voltage High Level Input Voltage Low Level Input Voltage Thermal Shutdow n Over Temperature Trip Point Hysteresis High Side Driver Peak Output Current Output Resistance
Symbol
Conditions
Min
Typ
Max
Units
VIH VIH VIL V C C = 9V
2.0 2.65 0.8
V V V
VIH VIH VIL V C C = 9V
2.0 2.2 0.8
V V V
TOTP THYST
165 10
C C
IPKH RsrcTG RsinkTG duty cycle < 2%, tpw < 100 s, TJ = 125C, VBST - VDRN = 4.5V, VTG = 4.0V (src) +VDRN or VTG = 0.05V (sink) +VDRN
3 1
A
.7
Low -Side Driver Peak Output Current Output Resistance IPKL RsrcBG RsinkBG duty cycle < 2%, tpw < 100 s, TA = 25C, VV S = 4.6V, VBG = 4V (src), or VLOWDR = 0.5V (sink) 3 1.2 A
1.0
AC Operating Specifications
Parameter High Side Driver Rise Time Fall Time Propagation Delay Time, TG Going High Propagation Delay Time, TG Going Low
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Symbol
Conditions
Min
Typ
Max
Units
trTG1 tfTG tpdhTG tpdlTG
CI = 3nF, VBST - VDRN = 8V CI = 3nF, VBST - VDRN = 8V CI = 3nF, VBST - VDRN = 8V CI = 3nF, VBST - VDRN = 8V
3
14 12 20 15
ns ns ns ns
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SC1205H
POWER MANAGEMENT AC Operating Specifications (Cont.)
Parameter Low -Side Driver Rise Time Fall Time Propagation Delay Time BG Going High Propagation Delay Time BG Going Low Under-Voltage Lockout V_5 ramping up V_5 ramping down tpdhUVLO tpdLUVLO EN is High EN is High 10 10 s s trBG trBG tpdhBGHI tpdlBGHI CI = 3nF, V CI = 3nF, V CI = 3nF, V CI = 3nF, V
VS
PRELIMINARY
Conditions Min Typ Max Units
Symbol
= 8V = 8V = 8V = 8V
15 13 12 7
ns ns ns ns
VS
VS
VS
Note: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required.
Timing Diagrams
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SC1205H
POWER MANAGEMENT Pin Configuration
Top View
PRELIMINARY Ordering Information
Device
(1)
P ackag e SO-8
Temp Range (TJ) 0 to 125C
SC1205HSTR
Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices.
(SO-8)
Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 Pin Name DRN TG BST CO EN VS BG PGND Pin Function This pin connects to the junction of the switching and synchronous MOSFETs . This pin can be subjected to a -2V minimum relative to PGND without effecting operation. Output gate drive for the switching (high-side) MOSFET. Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1F and 1F (ceramic). TTL-level input signal to the MOSFET drivers. When high, this pin enables the internal circuitry of the device. When low, TG and BG are forced low and the supply current (5V) is less than 10A. 5V-9.0V supply. A .22-1F ceramic capacitor should be connected from 5V to PGND very close to this pin. Output drive for the synchronous (bottom) MOSFET. Ground. Keep this pin close to the synchronous MOSFETs source.
Note: (1) All logic level inputs and outputs are open collector TTL compatible.
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SC1205H
POWER MANAGEMENT Block Diagram PRELIMINARY
Applications Information
Theory of Operation SC1205H is the higher gate drive voltage version of it predecessor, the SC1205. It is designed for optimum enhancement of Low Rds_On power MOS.ETs with ultra-low rise/fall times and propagation delays. Higher MOS.ET enhancement has been made possible by optimally increasing the gate drive voltage while maintaining low switching losses at minimum RDS_ON. The SC1205H is designed for a gate drive voltage of 8V, without compromising features that allow fast switching and low propagation delays. .ast Switching Drives As the switching frequency of PWM controllers is increased to reduce power supply volume and cost, fast rise and fall times are necessary to minimize switching losses (TOP MOS.ET) and reduce dead-time (BOTTOM MOS.ET) losses. While low Rds_On MOS.ETs present a power saving in I2R losses, the MOS.ETs die area is larger and the effective input capacitance of the MOS.ET is increased. Often a 50% decrease in Rds_On doubles the effective input gate charge, which must be supplied by the driver. The Rds_On power savings can be offset by the switching and dead-time losses with a suboptimum driver. While discrete solution can achieve reasonable drive capability, implementing shoot-through, programmable delay and other housekeeping functions necessary for safe operation can become cumbersome and
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costly. The SC1205H presents a total solution for the high-speed, high power density applications. Wide input supply range of 4.5V-18V allows use in battery powered applications, new high voltage, distributed power servers. Shoot Through Protection The control input (CO) to the SC1205H is typically supplied by a PWM controller that regulates the power supply output. (See Application Evaluation Schematic, .igure 6). The timing diagram demonstrates the sequence of events by which the top and bottom drive signals are applied. The shoot-through protection is implemented by holding the bottom .ET off until the voltage at the phase node (intersection of top .ET source, the output inductor and the bottom .ET drain) has dropped below 1V. This assures that the top .ET has turned off and that a direct current path does not exist between the input supply and ground, a shoot-through condition during which both the top and bottom .ETs could be on momentarily. The top .ET is also prevented from turning on until the bottom .ET is off. This time is internally set to 20ns (typical). The EN (enable) pin may be used to turn both TG and BG drives off. This would allow lower power operation by reducing the quiescent current draw of the SC1205H to less than 10A.
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SC1205H
POWER MANAGEMENT Applications Information (Cont.)
LAYOUT GUIDELINES As with any high speed , high current, switching regulator circuit, proper layout is critical in achieving optimum performance of the SC1205H. The Evaluation board schematic (Refer to figure 6) shows a two-phase synchronous design with all surface mountable components. Tight placement and short, wide traces must be used in layout of The gate drives, DRN, and especially PGND pin. The top gate driver supply voltage is provided by bootstrapping the boost supply and adding it to the phase node (DRN) voltage. Since the bootstrap capacitor supplies the charge to the top gate, it must be less than .5 away from the SC1205H. Ceramic X7R capacitors are a good choice for supply bypassing near the chip. Supply Voltage The Vcc supply must be derived from a voltage that does not vary significantly with output load. This is especially true if the MOS.ET drain voltage is a +5V supply bus and the Vcc of the SC1205H is connected to +5V. As the load increases, or during sudden load transients, the 5V supply dips significantly due to trace resistance and inductance. If the Vcc of the SC1205H is derived from the end of this +5V bus, the drop in the +5V can cause the Vcc to fall lower than the required under voltage lockout threshold of the SC1205H and cause intermittent drive shutdown. To avoid this occurrence, connect the Vcc of the SC1205H to the beginning point of the +5V bus with a separate trace, directly to the input connector. The Vcc pin bypass capacitor must also be less than .5 away from the SC1205H. The ground node of this capacitor, the SC1205H PGND pin and the Source of the bottom .ET must be very close to each other, preferably with common PCB copper land with multiple vias to the ground plane (if used). The parallel Schottky (if used) must be physically next to the Bottom .ETs drain and source pins. Any trace or lead inductance in these connections will drive current way from the Schottky and allow it to flow through the .ETs Body diode, thus reducing efficiency.
PRELIMINARY
Preventing Inadvertent Bottom .ET Turn-on At high input voltages, (12V and greater) a fast turn-on of the top .ET creates a positive going spike on the Bottom .ETs gate through the Miller capacitance, Crss of the bottom .ET. The voltage appearing on the gate due to this spike is:
V SPIKE = Vin * crss ( Crss + ciss
Where Ciss is the input gate capacitance of the bottom .ET. This is assuming that the impedance of the drive path is too high compared to the instantaneous impedance of the capacitors. (since dV/dT and thus the effective frequency is very high). If the BG pin of the SC1205H is very close to the bottom .ET, Vspike will be reduced depending on trace inductance, rate of rise of current, etc. While not shown in .igure 6, a capacitor may be added from the gate of the Bottom .ET to its source, preferably less than .5 away. This capacitor will be added to Ciss in the above equation to reduce the effective spike voltage. The bottom MOS.ET must be selected with attention paid to the Crss/Ciss ratio. A low ratio reduces the Miller feedback and thus reduces Vspike. Also MOS.ETs with higher Turn-on threshold voltages will conduct at a higher voltage and will not turn on during the spike. The MOS.ET shown in the schematic (.igure 6) has a 2 volt threshold and will require approximately 4.5 volts Vgs to be conducting, thus reducing the possibility of shoot-through. A zero ohm bottom .ET gate resistor will obviously help keeping the gate voltage low during off time. Ultimately, slowing down the top .ET by adding gate resistance will reduce di/dt which will in turn make the effective impedance of the capacitors higher, thus allowing the BG driver to hold the bottom gate voltage low. It does this at the expense of increased switching times (and switching losses) for the top .ET.
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SC1205H
POWER MANAGEMENT Applications Information (Cont.)
The top MOS.ET source must be close to the bottom MOS.ET drain to prevent ringing and the possibility of the phase node going negative. This frequency is determined by:
Fring = 1 ( 2 * Sqrt (L ST * Coss )
PRELIMINARY
Prevent Driver Overvoltage The negative voltage spikes on the phase node adds to the bootstrap capacitor voltage, thus increasing the voltage between VBST - VDRN. This is of special importance if higher boost voltages are used. If the phase node negative spikes are too large, the voltage on the boost capacitor could exceed devices absolute maximum rating of 12V. To eliminate the effect of the ringing on the boost capacitor voltage, place a 4.7 - 10 Ohm resistor between boost Schottky diode and Vcc to filter the negative spikes on DRN Pin. Alternately, a Silicon diode, such as the commonly available 1N4148 can substitute for the Schottky diode and eliminate the need for the series resistor. Proper layout will guarantee minimum ringing and eliminate the need for external components. Use of SO-8 or other surface mount MOS.ETs while increasing thermal resistance, will reduce lead inductance as well as radiated EMI. Over Temperature Shutdown The SC1205H will shutdown by pulling both driver if its junction temperature, TJ, exceeds 165C.
-Where: Lst = The effective stray inductance of the top .ET added to trace inductance of the connection between top .ETs source and the bottom .ETs drain added to the trace resistance of the bottom .ETs ground connection. Coss = Drain to source capacitance of bottom .ET. If there is a Schottky used, the capacitance of the Schottky is added to this value. Although this ringing does not pose any power losses due to a fairly high Q, it could cause the phase node to go too far negative, thus causing improper operation, double pulsing or at worst driver damage. On the SC1205H, the drain node, DRN, can go as far as 2V below ground without affecting operation or sustaining damage. The ringing is also an EMI nuisance due to its high resonant frequency. Adding a capacitor, typically 10002000pf, in parallel with Coss of the bottom .ET can often eliminate the EMI issue.
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SC1205H
POWER MANAGEMENT Typical Performance Plots .igure 1: Rise and fall time and propagation delay of SC1205H PRELIMINARY
SC1205H Rise Time and Fall Time Vin = 5V Vcc/Vbst = 8V I out = 20A Chan. 1 = CO pin Chan. 2 = Top gate Chan. 3 = Phase node Chan. 4 = Bottom gate See Schematic, Figure 6
.igure 2: Rise and fall time and propagation delay of SC1205H
SC1205H Rise Time and Fall Time Vin = 5V Vcc/Vbst = 8V I out = 20A Chan. 1 = CO pin Chan. 2 = Top gate Chan. 3 = Phase node Chan. 4 = Bottom gate, Propagation delay between CO pin and Bottom Gate = 14ns See Schematic, Figure 6
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SC1205H
PRELIMINARY POWER MANAGEMENT .igure 3: Rise and fall time and propagation delay of SC1205H, driving two top and two bottom .ETs, All .ETS , .DB7030BL
Rise and fall time of gate drives of the SC1205H with VCC = VBST = +8V. Ch1:Top gate drive, Ch2:Bottom Gate drive Note that these rise and fall times are achieved while driving 2X .DB7030BL MOS.ETs on top and 2X .DB7030BL on the bottom (synchronous). Vin = 5V Vcc = Vbst = 8V Iout = 20A/phase All gate drive resistors are set to zero for this test.
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SC1205H
POWER MANAGEMENT .igure 4: SC1205H driving a 3n. capacitive load. VCC = VBOOST = 8V. PRELIMINARY
SC1205H Timing Delay Chan. 1 = Top gate .all time Chan. 2 = Bott. Gate rise time Chan. 3 = CO pin going low
.igure 5: SC1205H driving a 3n. capacitive load. VCC = VBOOST = 8V.
SC1205H Propagation Delay Chan. 1 = Top gate .all time Chan. 3 = CO pin going low
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R1 .005 1uf R3 10u,CER 22nf ^ D7 LL42 U1 3 Q1 2 1 FDB7030BL 5 EN BG Q3 10u,CER C17 4 CO SC1205H 8 5 VID0 4.7-10 ohm 6 ERROUT R32 24.3K R20 3 R9 2 0 1 L2 FDB7030BL EN BG 4 CO SC1205H 8 GND 1uf 7 R13 0 Q5 10u,CER C28 10u,CER C29 10u,CER C31 10u,CER C24 Q4 TTIB1106-708 10k R33 8 RREF 10.0K VS GND 9 6 TG BST DRN U3 10 FB UVLO OCLL42 FDB7030BL 7 11 1uf C22 10u,CER C23 10u,CER C20 OUT2 D6 12 ^ GND 13 7 R8 0 L1 R5 0 1uf C15 TTIB1106-708 FDB7030BL 820uf,16V C14 1uf 4.7-10 ohm C13 U2 1 VID4 6 VS VID3 C18 14 VID2 VID1 OUT1 OC+ BGOUT 15 VCC 16 C11 R30 133 R31 100 820uf,16V C12 10 C6 R2 10 C1 C4 820uf,16V C5 1uf VIN
+5V
Vin
820uf,OS C33
J1
1 2 3 4 5 6
1u,16V C9
820uf,16V C7
820uf,16V C10
820uf,16V C34
INPUT
S1
EN * +8V
1uf 2
ENABLE
X EN
TG BST DRN
820uf,16V C35 10u,CER C16
9 10 11 12 13 14 15 16 3 4
POWER MANAGEMENT Evaluation Board Schematic - SC1205H
8 7 6 5 4 3 2 1
Figure 6: Microprocessor Core Supply
Vout/Clk switch
Vin
10u,CER C19
12
E N5
SC2422A C21 .1 R14 11.5k
R10
R11
1.7V
100K
10k
100pf
C25
R19 26.7k
local gnd
C26
R17
6.49k
VCORE
R18 1
^ Install resistor to limit voltage rise on boost capacitor due to large phase node negative spikes.
PRELIMINARY
SC1205H
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SC1205H
POWER MANAGEMENT Outline Drawing - SO-8 PRELIMINARY
Land Pattern - SO-8
Contact Information
Semtech Corporation Power Management Products Division 200 .lynn Road, Camarillo, CA 93012 Phone: (805)498-2111 .AX (805)498-3804
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