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PD - 95290
HEXFET(R) Chip-Set for DC-DC Converters
* * * * * N Channel Application Specific MOSFETs Ideal for Mobile DC-DC Converters Low Conduction Losses Low Switching Losses Lead-Free
S S S G
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IRF7807PbF IRF7807APBF
A D D D D
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Description These new devices employ advanced HEXFET Power MOSFET technology to achieve an unprecedented balance of on-resistance and gate charge. The reduced conduction and switching losses make them ideal for high efficiency DC-DC Converters that power the latest generation of mobile microprocessors. A pair of IRF7807 devices provides the best cost/ performance solution for system voltages, such as 3.3V and 5V.
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5
SO-8
T o p V ie w
Device Features IRF7807 IRF7807A Vds 30V 30V Rds(on) 25m 25m Qg 17nC 17nC Qsw 5.2nC Qoss 16.8nC 16.8nC
Absolute Maximum Ratings Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain or Source Current (VGS 4.5V) Pulsed Drain Current Power Dissipation 25C 70C Junction & Storage Temperature Range Continuous Source Current (Body Diode) Pulsed source Current TJ, TSTG IS ISM 2.5 66 25C 70C IDM PD Symbol VDS VGS ID 8.3 6.6 66 2.5 1.6 -55 to 150 2.5 66 C A IRF7807 30 12 8.3 6.6 66 W A IRF7807A Units V
Thermal Resistance Parameter Maximum Junction-to-Ambient
RJA
Max. 50
Units C/W
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IRF7807/APbF
Electrical Characteristics Parameter Drain-to-Source Breakdown Voltage* Static Drain-Source on Resistance* Gate Threshold Voltage* Drain-Source Leakage Current* V(BR)DSS RDS(on) VGS(th) IDSS 1.0 30 150 IGSS Qg Q gs1 Q gs2 Qgd QSW Q oss Rg td(on) tr td (off) tf 12 2.1 0.76 2.9 3.66 14 1.2 12 17 25 6 5.2 16.8 100 17 12 2.1 0.76 2.9 3.66 14 1.2 12 17 25 6 ns 16.8 VDD = 16V ID = 7A Rg = 2 VGS = 4.5V Resistive Load Conditions IS = 7A, VGS = 0V di/dt = 700A/s VDS = 16V, VGS = 0V, IS = 7A di/dt = 700A/s (with 10BQ040) VDS = 16V, VGS = 0V, IS = 7A VDS = 16V, VGS = 0 nC IRF7807 Min Typ Max 30 - 17 - 25 1.0 30 150 100 17 nA IRF7807A Min Typ Max Units 30 - 17 - 25 V m V A Conditions VGS = 0V, ID = 250A VGS = 4.5V, ID = 7A VDS = VGS, ID = 250A VDS = 24V, VGS = 0 VDS = 24V, VGS = 0, Tj = 100C VGS = 12V VGS = 5V, ID = 7A VDS = 16V, ID = 7A
Gate-Source Leakage Current* Total Gate Charge* Pre-Vth Gate-Source Charge Post-Vth Gate-Source Charge Gate to Drain Charge Switch Charge* (Qgs2 + Qgd) Output Charge* Gate Resistance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time
Source-Drain Rating & Characteristics Parameter Diode Forward Voltage* Reverse Recovery Charge Reverse Recovery Charge (with Parallel Schotkky) Notes:
*
Min VSD Qrr Qrr(s)
Typ Max 1.2 80 50
Min
Typ Max Units 1.2 80 50 V nC
Repetitive rating; pulse width limited by max. junction temperature. Pulse width 300 s; duty cycle 2%. When mounted on 1 inch square copper board, t < 10 sec. Typ = measured - Q oss Devices are 100% tested to these parameters.
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IRF7807/APbF
Power MOSFET Selection for DC/DC Converters
Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by;
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Drain Current
1
Gate Voltage t2 VGTH t0 t1 t3
QGS1
QGS2
2
QGD
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
Drain Voltage
Figure 1: Typical MOSFET switching waveform
Ploss = (Irms 2 x Rds(on ) ) Qgd +I x x Vin x ig + (Qg x Vg x f ) Q + oss x Vin x f 2
This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 1. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached (t1) and the time the drain current rises to Idmax (t2) at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure 2 shows how Qoss is formed by the parallel combination of the voltage dependant (non-linear) capacitance's Cds and Cdg when multiplied by the power supply input buss voltage.
Synchronous FET
Qgs2 f + I x x Vin x ig
f
The power loss equation for Q2 is approximated by;
* Ploss = P conduction + P drive + P output
Ploss = Irms x Rds(on)
+ (Qg x Vg x f )
(
2
)
Q + oss x Vin x f + ( rr x Vin x f ) Q 2
*dissipated primarily in Q1.
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IRF7807/APbF
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs' susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn Typical Mobile PC Application The performance of these new devices has been tested in circuit and correlates well with performance predictions generated by the system models. An advantage of this new technology platform is that the MOSFETs it produces are suitable for both control FET and synchronous FET applications. This has been demonstrated with the 3.3V and 5V converters. (Fig 3 and Fig 4). In these applications the same MOSFET IRF7807 was used for both the control FET (Q1) and the synchronous FET (Q2). This provides a highly effective cost/performance solution. the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Spice model for IRF7807 can be downloaded in machine readable format at www.irf.com.
Figure 2: Qoss Characteristic
3.3V Supply : Q1=Q2=IRF7807 93 92 91 Efficiency (%)
Efficiency (%) 94 93 92 91 95
5V Supply : Q1=Q2=IRF7807
90 89 88 87 86 85 84 1 1.5 2 2.5 3 3.5 Load Current (A) 4 4.5 5 Vin = 10V Vin = 14V Vin = 24V
Vin = 10V 90 89 1 1.5 2 2.5 3 3.5 Load Current (A) 4 4.5 5 Vin = 14V Vin=24V
Figure 3
Figure 4
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IRF7807/APbF
Typical Characteristics IRF7807 IRF7807A
Figure 5. Normalized On-Resistance vs. Temperature
Figure 6. Normalized On-Resistance vs. Temperature
Figure 7. Typical Gate Charge vs. Gate-to-Source Voltage
Figure 8. Typical Gate Charge vs. Gate-to-Source Voltage
Figure 9. Typical Rds(on) vs. Gate-to-Source Voltage
Figure 10. Typical Rds(on) vs. Gate-to-Source Voltage
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IRF7807/APbF
IRF7807
10 10
IRF7807A
ISD , Reverse Drain Current (A)
ISD , Reverse Drain Current (A)
TJ = 150 C
1
TJ = 150 C
1
TJ = 25 C
TJ = 25 C
0.1 0.4
V GS = 0 V
0.5 0.6 0.7 0.8 0.9
0.1 0.4
V GS = 0 V
0.5 0.6 0.7 0.8 0.9
VSD ,Source-to-Drain Voltage (V)
Figure 11. Typical Source-Drain Diode Forward Voltage
VSD ,Source-to-Drain Voltage (V)
Figure 12. Typical Source-Drain Diode Forward Voltage
100
Thermal Response (Z thJA )
D = 0.50 0.20 0.10 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) P DM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJA + TA 0.01 0.1 1 10 100 1000
10
1
0.1 0.001
t1 , Rectangular Pulse Duration (sec)
Figure 13. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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IRF7807/APbF
SO-8 Package Outline
Dimensions are shown in millimeters (inches)
D A 5 B
DIM A b INCHE S MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00
A1 .0040
8 6 E 1
7
6
5 H 0.25 [.010] A
c D E e e1 H K L y
2
3
4
.050 BASIC .025 BASIC .2284 .0099 .016 0 .2440 .0196 .050 8
1.27 BASIC 0.635 BASIC 5.80 0.25 0.40 0 6.20 0.50 1.27 8
6X
e
e1 A C 0.10 [.004] 8X b 0.25 [.010] A1 CAB y
K x 45
8X L 7
8X c
NOT ES : 1. DIMENS IONING & TOLERANCING PER ASME Y14.5M-1994. 2. CONT ROLLING DIMENS ION: MILLIMET ER 3. DIMENS IONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE CONFORMS TO JEDEC OUTLINE MS -012AA. 5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS . MOLD PROTRUS IONS NOT TO EXCEED 0.15 [.006]. 6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS . MOLD PROTRUS IONS NOT TO EXCEED 0.25 [.010]. 7 DIMENS ION IS T HE LENGT H OF LEAD FOR SOLDERING TO A S UBST RAT E. 3X 1.27 [.050]
F OOTPRINT 8X 0.72 [.028]
6.46 [.255]
8X 1.78 [.070]
SO-8 Part Marking
EXAMPLE: T HIS IS AN IRF7101 (MOSFET ) DAT E CODE (YWW) P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) Y = LAS T DIGIT OF T HE YEAR WW = WEEK A = AS S EMBLY S IT E CODE LOT CODE PART NUMBER
INT ERNAT IONAL RECT IFIER LOGO
XXXX F7101
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IRF7807/APbF
SO-8 Tape and Reel
Dimensions are shown in millimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 ) 11.7 ( .461 )
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES: 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00 (12.992) MAX.
14.40 ( .566 ) 12.40 ( .488 ) NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualifications Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.09/04
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