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XRK4993
3.3V PROGRAMMABLE SKEW CLOCK BUFFER
FEBRUARY 2007 REV. 1.0.0
FUNCTIONAL DESCRIPTION
The XRK4993 is a 3.3V High-Speed Low-Voltage Programmable Skew Clock Buffer. It is intended for high-performance computer systems and offers user selectable control over system clock functions to optimize timing. Eight ouputs, arranged in four banks, can each drive 75 terminated transmission lines while delivering minimal and specified output skews and full-swing Low Voltage TTL logic levels. Banks A, B, C (two outputs per bank) can be individually selected for one of nine delay or function configurations through two dedicated three-level inputs. These outputs are able to lead or lag the CLKIN input reference clock by up to 6 time units from their nominal "zero" skew position. The integrated PLL allows external load and transmission line delay effects to be canceled achieving zero delay capability. Combining the zero delay capability with the selectable output skew functions, output-to-output delays of up to +12 time units can be created. The XRK4993's divide functions (divide-by-two and divide-by-four) allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This feature facilitates clock distribution while allowing maximum system clock flexibility. When the OE pin is held low, all the outputs are synchronously enabled. However, if OE is held high, FIGURE 1. BLOCK DIAGRAM OF THE XRK4993
all the outputs except synchronously disabled.
QC0
and
QC1
are
When PE is held high, all the outputs are synchronized with the positive edge of the CLKIN clock input. When PE is held low, all the outputs are synchronized with the negative edge of CLKIN. The device has LVTTL outputs with 12mA balanced drive. FEATURES
* 3 pairs of programmable skew outputs * Low skew: 200ps same pair, 250ps all outputs * Selectable positive or negative edge
synchronization: Excellent for DSP applications
* * * * * * * * * * *
Synchronous output enable Output frequency: 3.75MHz to 85MHz 2x, 4x, 1/2, and 1/4 output frequencies 3 skew grades 3-level inputs for skew and PLL range control PLL bypass mode External feedback, internal loop filter 12mA balanced drive outputs Available in 28 pin QSOP package Jitter < 200 ps peak-to-peak CLKIN input is 5V tolerant
H M CLKIN Ref L
QA0 QA1
PLL
FB_IN
Feedback
QB0 QB1
PE FSEL* PLL_BYPASS*
SELA[1:0]* SELB[1:0]* SELC [1:0]* 2 2 2
Bank "SKEW" Control
QC0 QC1
QD0 QD1
OE * Three-level inputs
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRK4993
3.3V PROGRAMMABLE SKEW CLOCK BUFFER
REV. 1.0.0
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER XRK4993IR-2 XRK4993CR-2 XRK4993IR-5 XRK4993CR-5 XRK4993IR-7 XRK4993CR-7 ACCURACY 250 ps 250 ps 500 ps 500 ps 750 ps 750 ps OPERATING TEMPERATURE RANGE -40C to +85C 0C to +70C -40C to +85C 0C to +70C -40C to +85C 0C to +70C
FIGURE 2. PIN OUT OF THE XRK4993
CLKIN VCCQ FSEL SELC0 SELC1 PE VCCN QD1 QD0 GND QC1 QC0 VCCN FB_IN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 QSOP Top View
28 27 26 25 24 23 22 21 20 19 18 17 16 15
GND PLL_BYPASS SELB1 SELB0 OE SELA1 SELA0 VCCN QA0 QA1 GND GND QB0 QB1
TABLE 1: FREQUENCY RANGE SELECT AND tU CALCULATION [1] fNOM (MHZ)
FSEL[2,3] LOW MID HIGH MIN 15 25 40 MAX 35 60 85
tU = 1 / (fNOM X N)
WHERE
APPROXIMATE FREQUENCY (MHZ) AT
WHICH tU
N=
= 1.0ns
44 26 16
22.7 38.5 62.5
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XRK4993
REV. 1.0.0
3.3V PROGRAMMABLE SKEW CLOCK BUFFER
PIN DESCRIPTIONS
PIN NAME CLKIN FB_IN PLL_BYPASS PIN # 1 14 27 TYPE Input Input Threelevel Input Input Reference Clock Input Feedback Input When MID or HIGH, disables PLL (see Special Functions). CLKIN goes to all outputs. Skew Selections (see Control Summary Table) remain in effect. Set LOW for normal operations. Synchronous Output Enable. When HIGH, it stops clock outputs (except QC[1:0]). QC[1:0] may be used as the feedback signal to maintain phase lock. Set OE LOW for normal operation. Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the falling/rising edge of the reference clock. 3-level inputs for selecting 1 of 9 skew taps or frequency functions. DESCRIPTION
OE
24
PE SELA0 SELA1 SELB0 SELB1 SELC0 SELC1 FSEL
6 22 23 25 26 4 5 3
Input Threelevel Input Threelevel Input Threelevel Input Threelevel Input Output
Selects appropriate oscillator circuit based on anticipated frequency range. (See PLL Programmable Skew Range.) Three output banks of two outputs with programmable skew (QA[1:0], QB[1:0], QC[1:0]). QD[1:0] outputs have fixed zero skew outputs.
QA0 QA1 QB0 QB1 QC0 QC1 QD0 QD1 VCCN
20 19 16 15 12 11 9 8 7 13 21 2 10 17 18 28
Output
Output
Output
PWR
Power supply for output buffers.
VCCQ GND
PWR PWR
Power supply for phase locked loop and other internal circuitry. Ground.
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XRK4993
3.3V PROGRAMMABLE SKEW CLOCK BUFFER SKEW SELECT CONTROL The skew select control consists of four independent sections. Each bank has two low-skew, high-fanout drivers (Qx0, Qx1), and two corresponding three-level function select (SELx0, SELx1) inputs. The nine possible output states for each bank as shown in Table 2 as determined by each bank's select inputs. All timing measurements are made with respect to the CLKIN input assuming that the output connected to the FB_IN input configured for 0 tU operation. TABLE 2: PROGRAMMABLE SKEW CONFIGURATIONS [1]
FUNCTION SELECTS SELX1 LOW LOW LOW MID MID MID HIGH HIGH HIGH SELX0 LOW MID HIGH LOW MID HIGH LOW MID HIGH OUTPUT FUNCTIONS QA[1:0], QB[1:0] -4tU -3tU -2tU -1tU 0tU +1tU +2tU +3tU +4tU QC[1:0] Divide by 2 -6tU -4tU -2tU 0tU +2tU +4tU +6tU Divide by 4
REV. 1.0.0
NOTES: 1. For all three-level (three-state) inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 2. The level to be set on FSEL is determined by the "normal" operating frequency (fNOM) of the PLL. Nominal frequency (fNOM) always appears at QA0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the CLKIN and FB_IN inputs will be fNOM when the output connected to FB_IN is undivided. The frequency of the CLKIN and FB_IN inputs will be fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication. When the FSEL pin is selected HIGH, the CLKIN input must not transition upon power-up until VCC has reached 2.8V. QD[1:0] fixed at zero skew.
3. 4.
BYPASS MODE BYPASS mode allows the chip to be used in applications where the relative timing between outputs is maintained but the system clocking is interrupted or at a much lower frequency. An example might be "singlestepping" the system for diagnostics. The PLL_BYPASS pin is normally held at Ground (Low). To accommodate low frequency (below the PLL lock range) or infrequent pulses, the PLL_BYPASS, in conjunction with the FSEL pin (see Table 3) can be used to by-pass the PLL and generate an output sequence for the CLKIN signal. Relative timing as set by the SEL(x)1:0 for the various banks will be maintained. The relative timing includes plus and minus n tu and divide-by (2 or 4) settings. There will be a propagation delay as shown in Table 3. A tu will be approximately 2.5nS with PLL_BYPASS at Mid voltage and 0.4nS in the High state.
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XRK4993
REV. 1.0.0
3.3V PROGRAMMABLE SKEW CLOCK BUFFER
In the PLL_BYPASS mode the PE input can be used to invert the outputs. Thus, for a 20% (High) duty cycle input, all outputs will retain the 20% high condition with PE High. For PE Low, however, they will be 80% High. PE does not effect the duty cycle of the divided outputs. TABLE 3: TYPICAL PROPAGATION DELAY WITH ZERO SKEW SETTING
PLL_BYPASS INPUT Mid FSEL INPUT Low or Mid High High Low or Mid High TOTAL PROPAGATION DELAY 52nS 29nS 12nS 10nS
SPECIAL FUNCTIONS The following special functions have been implemented in the chip. PE pin: * In Normal operation, PE controls the "alignment" edge of the CLKIN and the FB-IN signals. (All other output signals are
aligned to the Feedback). PE=Low, aligns the FB_IN faliing edge to the CLKIN falling edge. PE=High, aligns rising edges.
* In the "disabled output mode (see below), the disabled state is forced to the opposite state of PE. This keeps the off
condition in a low-noise state.
* In PLL_BYPASS mode, PE controls the duty cycle (inversion) of the outputs (see PLL_BYPASS mode above). OE pin: * In Normal mode, OE is used to disable all outputs except QC[1,0]. These are maintained to provide PLL Feedback to
keep frequency lock. OE is kept low to enable the outputs and High to disable them. This is a synchronized operation to prevent "partial" clocks When OE goes high, the outputs will go to their disabled level at the end of the next active clock cycle. The level is determined by the state of PE. If PE is high, the output will go low at the end of the cycle and remain there until OE return to a low state. If PE is low, at the end of the next clock high state it will continue to remain high until OE returns low.
* If OE is high when PLL_BYPASS is at the Mid level, the PLL is enabled to provide an individual bank output control. In
this mode, taking both SEL(x)1 & 0 to the Low state will disable that bank's outputs.
FIGURE 3. TYPICAL OUTPUTS WITH FB_IN CONNECTED TO A ZERO-SKEW OUTPUT
t0+1tU t0+2tU t0+3tU t0+4tU t0+5tU t0+6tU t0-6tU t0-5tU t0-4tU t0-3tU t0-2tU t0-1tU
FB_IN SELA [1:0] SELB [1:0] (N/A) LL LM LH ML MM MH HL HM HH (N/A) (N/A) CLKIN SELC [1:0] -6tU LM -4tU LH -3tU (N/A) -2tU ML -1tU (N/A) 0tU MM +1tU (N/A) +2tU MH +3tU (N/A) +4tU HL +6tU HM LL/HH DIVIDED
5
t0
XRK4993
3.3V PROGRAMMABLE SKEW CLOCK BUFFER
REV. 1.0.0
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground Potential DC Input Voltage Output Current into Outputs (LOW) Static Discharge Voltage (per MIL-STD-883, Method 3015) Latch-Up Current. -65C to +150C -55C to +125C -0.5V to +7.0V -0.5V to +7.0V 64 mA >2001V >200 mA
OPERATING RANGE
RANGE Industrial Commercial AMBIENT TEMPERATURE -40C to +85C 0C to +70C VCC 3.3 + 10% 3.3 + 10%
ELECTRICAL CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE
SYMBOL VOH VOL VIH VIL VIHH DESCRIPTION Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Three-Level Input HIGH Voltage (PLL_Bypass, FSEL, SELx[1:0]) [5] VIMM Three-Level Input MID Voltage (PLL_Bypass, FSEL, SELx[1:0]) [5] VILL Three-Level Input LOW Voltage (PLL_Bypass, FSEL, SELx[1:0]) [5] IIH IIL IIHH IIMM IILL Input HIGH Leakage Current (CLKIN and FB_IN inputs only) Input LOW Leakage Current (CLKIN and FB_IN inputs only) Input HIGH Current (PLL_Bypass, FSEL, SELx[1:0]) Input MID Current (PLL_Bypass, FSEL, SELx[1:0]) Input LOW Current PLL_Bypass, FSEL, SELx[1:0] -200 -20 20 A A VCC = Max., VIN = Max. VCC = Max., VIN = 0.4V VIN = VCC VIN = VCC/2 VIN = GND 0.0 0.13 * VCC V Min. < V CC < Max. 0.47*V CC 0.53 * VCC V Min. < V CC < Max. 2.0 -0.5 0.87*V CC MIN 2.4 0.45 VCC 0.8 VCC MAX UNIT V V V V V Min. < V CC < Max. CONDITION VCC = Min., IOH = -18mA VCC = Min., IOL = 35mA CLKIN, FB_IN, PE, and OE
400
200
-400
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XRK4993
REV. 1.0.0
3.3V PROGRAMMABLE SKEW CLOCK BUFFER
ELECTRICAL CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE
SYMBOL IOS DESCRIPTION Short Circuit Current [6] MIN MAX -200 UNIT mA CONDITION VCC = Max, VOUT = GND (25C only) ICCQ Operating Current Used by Internal Circuitry Com'l Ind 95 100 19 mA mA VCCN = VCCQ = Max., All Inputs Selects Open VCCN = VCCQ = Max., IOUT = 0 mA Inputs Selects Open, fMAX PD Power Dissipation per Output Pair 104 mW VCCN = VCCQ = Max., IOUT = 0 mA Input Selects Open, fMAX
ICCN
Output Buffer Current per Output Pair
CAPACITANCE[7]
SYMBOL CIN Input Capacitance DESCRIPTION MAX. 10 UNIT pF CONDITION TA = 25C, f=1MHz, VCC=3.3V NOTES: 5. These inputs are normally wired to VCC, GND or left unconnected (actual threshold voltages vary as a percentage of V CC). Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an addtional tLOCK time before all data sheet limits are achieved. XRK4993 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. Applies to CLKIN and FB_IN inputs only.
6. 7.
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XRK4993
3.3V PROGRAMMABLE SKEW CLOCK BUFFER
REV. 1.0.0
FIGURE 4. AC TEST LOAD
VCC R1 CL R2 LOAD R1 = 150 R2 = 150 CL = 20pF (includes fixture and probe capacitance
FIGURE 5. INPUT/OUTPUT TEST WAVEFORM
3.0V 2.0V Vth = 1.5V 0.8V 0.0V <1ns <1ns 2.0V Vth = 1.5V 0.8V
SWITCHING CHARACTERISTICS OVER THE OPERATING RANGE [2,8]
SYMBOL fNOM DESCRIPTION Operating Clock Frequency in MHz FSEL = LOW [1, 2] FSEL = MID [1, 2] FSEL = HIGH [1, 2, 3] MIN 15 25 40 MAX 35 60 85 UNIT MHz
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XRK4993
REV. 1.0.0
3.3V PROGRAMMABLE SKEW CLOCK BUFFER
SWITCHING CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE [2,8]
XRK4993-2 SYMBOL tRPWH tRPWL tu tSKEWPR DESCRIPTION MIN CLKIN Pulse Width HIGH CLKIN Pulse Width LOW Programmable Skew Unit Zero Output Matched-Pair Skew (Qx[1:0]) [10, 11] tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tDEV tPD tODCV tPWH tPWL tORISE tOFALL tLOCK tJR Zero Output Skew (All Outputs) [10, 12] Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)[10, 13] Output Skew (Rise-Fall) [10, 13] Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs) [10, 13] Output Skew (Nominal-Divided) [10, 13] Device-to-Device Skew [9, 14] Propagation Delay, CLKIN Rise to FB_IN Rise Output Duty Cycle Variation [15] Output HIGH Time Deviation from 50%
[16]
XRK4993-5 MIN 4 4 See Table 1 TYP MAX
XRK4993-7 UNIT MIN 4 4 TYP MAX ns ns
TYP
MAX
4 4
0.05
0.2
0.1
0.25
0.1
0.25
ns
0.1 0.25
0.25 0.5
0.25 0.6
0.5 0.7
0.3 0.6
0.75 1
ns ns
0.3 0.25
1 0.5
0.5 0.5
1 0.7
1 0.7
1.5 1.2
ns ns
0.5
0.9 0.75
0.5
1 1.25
1.2
1.7 1.65
ns ns ns ns ns ns ns ns ms ps
-0.25 -1
0 0
0.25 1 2 1.5
-0.5 -1
0 0
0.5 1 2.5 3
-0.7 -1.2
0 0
0.7 1.2 3 3.5
Output LOW Time Deviation from 50%
[16]
Output Rise Time [16, 17] Output Fall Time [16, 17] PLL Lock Time [18] Cycle-to-Cycle Output Jitter RMS [9] Peak-to-Peak
[9]
0.15 0.15
1 1
1.2 1.2 0.5 25 200
0.15 0.15
1 1
1.5 1.5 0.5 25 200
0.15 0.15
1.5 1.5
2.5 2.5 0.5 25 200
NOTES: 8. Test measurement levels for the XRK4993 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with 75 to VCC/2 (XRK4993).
9. 10.
9
XRK4993
3.3V PROGRAMMABLE SKEW CLOCK BUFFER
11. 12. 13. 14. 15. 16. 17. 18.
REV. 1.0.0
tSKEWPR is defined as the skew between a pair of outputs (Qx0 and Qx1) when all eight outputs are selected for 0tU. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided, but not shifted. There are two classes of outputs: Nominal (multiple of tU delay) and Divided (QC[1:0] or Divide-by-4 mode). tDEV is the output-to-output skew between any two devices operating under the same conditions (V CC ambient temperature, air flow, etc.) tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. Specified with outputs loaded with 20pF for the XRK4993 devices. Devices are terminated through 75 to VCC/2. tPWH is measured at 2.0V. tPWL is measured at 0.8V. tORISE and tOFALL measured between 0.8V and 2.0V. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at CLKIN or FB_IN until tPD is within specified limits
FIGURE 6. AC TIMING DIAGRAM (SHOWN WITH PE=HIGH)
tREF tRPWH CLKIN tPD FB_IN tJR Any Q tODCV tODCV tRPWL
tSKEWPR, tSKEW0, 1
OTHER Q
tSKEWPR, tSKEW0, 1
tSKEW3, 4
CLKIN DIVIDED BY 2
tSKEW3, 4
tSKEW3, 4
tSKEW1, 3, 4
CLKIN DIVIDED BY 4
tSKEW2, 4
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XRK4993
REV. 1.0.0
3.3V PROGRAMMABLE SKEW CLOCK BUFFER
FIGURE 7. TIMING DIAGRAM PE=LOW
Clkin
FB_In
Qxn
QC div2
QC div4
PE = LOW TIMING:
All output changes occur on the falling edge of the Clkin reference signal. Programmable skews are made relative to this edge.
FIGURE 8. TIMING DIAGRAM PE=HIGH
Clkin
FB_In
Qxn
QC div2
QC div4
PE=HIGH TIMING:
When the PE pin is High, all changes begin relative to the rising edge of the Clkin reference signal. This includes not only the "zero tu" signals but also the divided output signals. The divided-by-two outputs will change on each rising edge. As QD can only be 0tu, QC is the only "divide by" output providing either divideby- two or divide-by-four, not both.
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XRK4993
3.3V PROGRAMMABLE SKEW CLOCK BUFFER
REV. 1.0.0
PACKAGE DIMENSIONS 28 LEAD SHRINK SMALL OUTLINE PACKAGE ( QSOP 150 mils body)
Rev. 1.00
D
28
15
E
1 14
H
C A Seating Plane e B A1 L
SYMBOL A A1 B C D E e H L
MIN 0.053 0.004 0.008 0.006 0.380 0.144 0.0256 0.220 0.016 0
MAX 0.068 0.010 0.012 0.010 0.400 0.164 BSC 0.250 0.050 8
MIN MAX 1.35 1.73 0.10 0.25 0.20 0.30 0.15 0.25 9.65 10.16 3.66 4.17 0.65 BSC 5.59 6.35 0.54 1.27 0 8
Note: The control dimension is the millimeter column
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XRK4993
REV. 1.0.0
3.3V PROGRAMMABLE SKEW CLOCK BUFFER
REVISION HISTORY
REVISION # DATE DESCRIPTION
1.0.0
February 2007 Initial release.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2007 EXAR Corporation Datasheet February 2007. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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