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X60250
Data Sheet September 14, 2005 FN8146.1
Micro Power Programmable Voltage Reference
FEATURES * * * * * * * * * * * * 1.25V 1.0%, 20ppm/C Tempco Reference Adjustable to 0.25% Over the 0 to 1.25V Range 8 bit, 100k XDCP on-chip Programmable Resolution of 4.9mV (255 steps) Extra Matched 100k Resistor Available for Increased Resolution Over a Smaller Range 2.7V to 5.5V Supply Range 2-Wire Interface for Programming Reference Setting Low Supply Current: 12A in Normal Mode 8-pin TSSOP Package Programmable Reference NV Memory Pb-Free Plus Anneal Available (RoHS Compliant)
PROGRAMMABLE VOLTAGE REFERENCE APPLICATIONS * * * * * * * Sensor Bias Variable DAC reference Linear Voltage Regulators DC/DC converters Voltage comparators Motor controllers Amplifier biasing
DESCRIPTION The Intersil X60250 combines a temperature compensated voltage reference with a Intersil Digitally Controlled Potentiometer (XDCP) to provide a precision adjustable reference with a range of 0.0V to 1.25V. The device includes a serial bus interface to enable in-circuit programming of the reference voltage. The XDCP contains a resistor chain with 255 taps to provide 8 bits of digital adjustment to the reference voltage. Non-volatile storage retains the digital wiper setting, for permanent reference programming. An additional matched 100k resistor is available to increase resolution of the output voltage while retaining accuracy.
IC BLOCK DIAGRAM
VCC VREFOUT
Pwr On Recall
1.25V Reference 256 Tap DCP
100K VOUT R1
EE PROM
SCL SDA
Serial Interface 100k Digital Wiper Control
GND
VREFL
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X60250 Ordering Information
PART NUMBER X60250V8I X60250V8IZ (Note) PART MARKING 60250 I 60250I Z OUTPUT VOLTAGE (V) 1.250 1.250 RESOLUTION 8 bits 8 bits TEMP RANGE (C) -40 to 85 -40 to 85 PACKAGE 8 Ld TSSOP 8 Ld TSSOP (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN CONFIGURATION
TSSOP VREFL VCC VREFOUT VOUT 1 2 3 4 8 7 6 5 SCL SDA GND R1
PIN ASSIGNMENTS TSSOP
1 2 3 4 5 6 7 8
Symbol
VREFL VCC VREFOUT VOUT R1 GND SDA SCL Positive Power Supply Bandgap Reference Output DCP Wiper Output Auxiliary resistor input Ground Serial Data Input/Output Serial Clock Input
Description
DCP and auxiliary resistor reference input
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ABSOLUTE MAXIMUM RATINGS Supply Voltage Range...................................-1V to 7V Bias Temperature Range .................... -40C to +85C Storage Temperature Range............. -65C to +150C Voltage on VREF(LOW) pin .............................0V to VCC Voltage on all other pins ................ -0.3V to VCC+0.3V Lead temperature (soldering, 10 seconds) ........ 300C RECOMMENDED OPERATING CONDITIONS Min
Temperature Supply Voltage -40C 2.7V
COMMENTS Absolute Maximum Ratings indicate limits beyond which permanent damage to the device and impaired reliability may occur. These are stress ratings provided for information only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. For guaranteed specifications and test conditions, see Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Max
+85C 5.5V
ELECTRICAL CHARACTERISTICS (Over operating conditions unless otherwise specified. IOUT = 12.5 A, R1 = N/C (Floating).) ANALOG PARAMETERS Limits Symbol
Power Supply VCC IQ Supply Voltage Range Supply Current VCC = 2.7V VCC = 3V VCC = 5.5V Write Non-Volatile Supply Current VCC = 2.7V VCC = 3V VCC = 5.5V 2.7 3.0 5.5 20 15 60 1100 600 1300 DC Parameters VREFOUT VREFL TCOref PSRR IOUT Output Voltage DCP and auxilliary resistor reference input Temperature coefficient of VREF output voltage Power Supply Rejection Output Current Sourcing Sinking Output Impedance Short Circuit Current Sourcing Sinking Load Capacitance 55 1.237 GND 20 66 400 1 1 5 0 0.001 0.003 2.5 mA F Given by ROUT = (VREF/IOUT) (2) At 5.5V Reference output stable for all CL up to specifications (2) 1.250 1.263 VREFOUT 70 V V ppm/C dB A
(2, 5)
Parameter
Min.
Typ. (1)
Max.
Unit
V A
Test Conditions
RL=0, VREFL, VOUT, RAUX = floating
IQ(NV)
A
RL=0, VREFL, VOUT, RAUX = floating
Reference Output Voltage TA = 25C
(6)
(2)
ROUT ISC
CL
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ANALOG PARAMETERS (CONTINUED) Limits Symbol
VN
Parameter
Output Voltage Noise Power-on Response Line Ripple Rejection
Min.
Typ. (1)
100 200 250 60
Max.
Unit
Test Conditions
AC Parameters VP-P 0.1Hz to 10Hz (2) VRMS 10Hz to 10kHz (2) s dB 8 85 100 115 5000 1200 bits k LSB LSB ppm/C ppm/C 115 k ppm/C RL=0, VREFL, VOUT, RAUX = floating % ppm/C
(2)
1% Settling (2) VDD = 3V 100mV, f = 120 Hz (2)
Reference DCP Resolution RTOT RW End to end resistance Wiper Resistance VCC = 2.7V VCC = 3V Absolute Linearity (INL) Relative Linearity (DNL) RTOT Temperature Coeff. Ratiometric Temp. Coeff. RAUX (Auxiliary Resistor) RTOT End to end resistance RTOT Temperature Coeff. DCP Matching Tolerance DCP Matching Temp. Coeff. 85 100 300 0.1 20
600 0.2 0.1 300 20
DIGITAL PARAMETERS Limits Symbol
ILI ILO VIL VIH CIN VOL VOH CL
Parameter
Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input Capacitance Output Low Voltage Output High Voltage Output Load
Min.
Typ. (1)
Max.
2 2
Unit
A A V V pF %VDD %VDD pF
Test Conditions
VIN = GND to VCC VOUT = GND to VCC
0 VCC x 0.7 5 0 90
VCC x 0.2 VCC 10 100 100
IOL = 100 A (2) IOH = 100 A (2) (2)
EEPROM PARAMETERS (Erase at VCC = 5.0 V min, T = 25C) Parameter
Write Cycle Endurance
Min.
100,000
Units
Cycles per bit
CAPACITANCE Symbol
CIN/OUT CIN
Test
Input/Output capacitance (SDA) Input capacitance (SCL)
4
Max.
8 6
Units
pF pF
Test Conditions
VOUT = 0V (2) VIN = 0V (2)
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X60250
A.C. TEST CONDITIONS
Input Pulse Levels Input rise and fall times Input and output timing threshold level External load at pin SDA VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 2.3k to VCC and 100 pF to VSS
AC SPECIFICATIONS Symbol
fSCL tIN tAA tBUF tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tDH tR tF Cb SCL Clock Frequency Pulse width Suppression Time at inputs SCL LOW to SDA Data Out Valid Clock LOW Time Clock HIGH Time Start Condition Setup Time Start Condition Hold Time Data In Setup Time Data In Hold Time Stop Condition Setup Time Data Output Hold Time
(2) (2, 3) (2) (2) (2) (2)
Parameter
Min.
0 50 0.1 1.3 1.3 0.6 0.6 0.6 100 0 0.6 50 20 +.1Cb 20 +.1Cb
Max.
400 0.9
Unit
kHz ns s s s s s s ns s s ns
Time the bus must be free before a new transmission can start
SDA and SCL Rise Time
300 300 400
ns ns pF
SDA and SCL Fall Time (2, 3) Capacitive load for each bus line (2, 3)
TIMING DIAGRAMS Bus Timing
tBUF SCL tSU:STA SDA IN tSU:DAT tHD:STA tHD:DAT tSU:STO tHD:STO tF tHIGH tLOW tR tBUF
tAA SDA OUT
tDH
tHD:DAT
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WRITE CYCLE TIMING
SCL
SDA
8th Bit of Last Byte
ACK tWC Stop Condition Start Condition
POWER-UP TIMING Symbol
VCC/t tPUR tPUW VCC Power-up rate
Parameter
(2)
Min.
0.2
Max.
50 1 5
Unit
V/ms ms ms
Time from Power-up to
Read (2)
(2)
Time from Power-up to Write
NONVOLATILE WRITE CYCLE TIMING Symbol
tWC
Notes: (1) (2) (3) (4)
Parameter
Write Cycle Time
(4)
Min.
Typ.
5
Max.
10
Unit
ms
Typical values are for TA = 25C and VCC = 3.0V This parameter is guaranteed by characterization. Cb = total capacitance of one bus line in pF. tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. (5) Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT is divided by the temperature range; in this case, -40C to +85C = 125C. TCOref = [Max V(VREF) - Min V(VREF)] x 106 / (1.25V x 125C)
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FUNCTIONAL DESCRIPTION The X60250 combines a micropower precision reference with an 8-bit, 256 tap digitally controlled 100k potentiometer (DCP) which allows nonvolatile setting of an output reference voltage. When normally configured with the VREFL pin tied to ground, the device provides an output range of 0V to 1.25V with 4.90mV resolution. The device can also be configured with an optional 100k series resistor to ground, which effectively halves the output voltage range while doubling the resolution. Grounding the R1 pin while floating the VREFL pin places the device in this mode. Output voltage setting accuracy can be as high as 0.10% while permitting adjustment from 0.625V to 1.25V (2.45mV resolution). Reference Section The reference is designed to provide an accurate, low tempco voltage source while requiring less than 12A (typical) of supply current. This supply current is for the reference section only. Keep in mind that the DCP will increase supply current draw by VREF/RTOTAL (typically 1.25/100k or 12.5A). The total current drawn by the adjustable reference circuit will be less than 25A (typically). The reference output has a typical impedance of 1 and can provide up to 400A of load current. It is intended to drive the resistive load of the DCP, which is a minimum of 85k, but can also be used to drive off chip circuitry provided the loading does not exceed the 400A maximum. Also, highly capacitive loads can make the reference oscillate, so no more than 2000pF should be placed directly on the output of the VREFOUT pin. The reference output produces about 200V RMS of noise (10kHz bandwidth) due to its micropower design. This is easily reduced in normal applications, as shown in the applications section for optimizing circuits for reducing output noise levels. DCP Section The 256 tap DCP has an 8-bit nonvolatile wiper control register which controls which tap is selected. The register is changed by performing a serial data write to its address (0h, see Serial Interface section). The resulting wiper position will produce an output voltage at VOUT, depending on whether the DCP VREFL is grounded or the R1 pin is grounded. The wiper consists of CMOS transistors and has a finite resistance, typically 600 at VCC = 5V (this parameter increases with decreasing VCC). The wiper resistance will produce errors in reference circuits due to I-R drops if current flows through the wiper. However, typically these circuits will have the wiper connected to a high impedance comparator or amplifier input which results in very small
7
wiper currents and thus only a small output voltage error. If the X60250 is used with the wiper connected to VREFL to produce a current source, care must be taken to avoid exceeding the maximum output current of the reference (typically 400A). Power-Up considerations The X60250 contains EEPROM nonvolatile storage cells which are recalled during power-up. This recall process works best with power supply (VCC) ramping that is monotonic and free of excessive glitches (<100mV disturbances give best results). The ramp rate spec should be adhered to, although the most sensitive part of recall is between VCC = 1.0V and 2.5V. Effort should be made to make sure the device receives a power-up ramp between those voltage levels that meet the ramp rate spec and have no glitches. Recall of the stored wiper position happens in < 1ms from VCC reaching 2.5V. Note that any excursions of VCC below 2.5V, although temporary, can cause the wiper to be loaded with the midpoint value (80h) until VCC recovers to its normal voltage. Register Organization There are 2 nonvolatile registers and 1 volatile register available for storage and recall via the serial bus. They contain the current wiper position, a general purpose data register and a status register. The wiper register is nonvolatile and is at address 0h and contains 8 bits, with the 00h setting corresponding to the tap position nearest VREFL, and the FFh setting nearest to VREFOUT. The general purpose register is nonvolatile and is at address 1h, and contains 8 bits for use as scratchpad memory or serial number information. The Status register is volatile and is at address 7h. It has one active bit, D3, which is the WEL bit. This bit must be set to 1 berfore any nonvolatile writes are performed to the other registers. See the register information on the next page.
FN8146.1 September 14, 2005
X60250
X60250 REGISTER BIT MAP Addr
0 1 7
D7
D7 (MSB) D7 (MSB) 0
D6
D6 D6 0
D5
D5 D5 0
D4
D4 D4 0
D3
D3 D3 WEL
D2
D2 D2 0
D1
D1 D1 0 D0 D0
D0
(LSB) (LSB) 0
REGISTER DESCRIPTIONS Reg
0 1 7
Nonvolatile
Y Y N
Description
VOUT wiper setting General Purpose data storage register Status register
REGISTER 0 (NONVOLATILE)
This register is used to hold the DCP wiper position, which is given by:
Code V OUT = V REF x -------------- (with 255
VREFL = GND)
REGISTER 1 (NONVOLATILE)
This 8 bit register is used for general storage such as date code, temp setting, etc.
STATUS REGISTER Bit
D - D4 D3
Value
0 0-1
Description
Must remain 0 WEL bit Must be programmed to "1" for Reg 0 or 1 EEPROM write. When accessing, only WEL bit may be changed Must remain 0
D2 - D0
0
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X60250 BUS INTERFACE INFORMATION Figure 1. Slave Address, Word Address, and Data Bytes - Write Mode
Device Identifier Slave Address*
Slave Address Byte 0 1 0 1 0 0 0/1 0 Byte 0
A7
A6
A5
A4
A3
A2
A1
A0
Byte Address Byte 1
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte Byte 2
Figure 2. Slave Address, Word Address, and Data Bytes - Read Mode
Device Identifier Slave Address*
0
1
0
1
0
0
0/1
1
Slave Address Byte Byte 0
Data Byte D7 D6 D5 D4 D3 D2 D1 D0 Byte 1
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte Byte 2
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X60250 BUS INTERFACE INFORMATION Slave Address, Address Byte, and Data Byte The byte communication format for the serial bus is shown in Figure 1 on the previous page. The first byte, BYTE 0, defines the device identifier, 0101 in the upper half; and the device slave address in the low half of the byte. The slave address is set to 0. The next byte, BYTE 1, is the Address Byte. The Address Byte identifies a unique address for the Status or Control Registers as shown in the Register Descriptions table. The following byte, Byte 2, is the byte used for READ and WRITE operations. Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. On powerup, the SCL pin must be brought LOW prior to the START condition. See Figure 3. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH followed by a HIGH to LOW transistion on SCL. After going LOW, SCL can stay LOW or return to HIGH. See Figure 3. Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 4. The device will respond with an acknowledge after recognition of a start condition and if the correct Device Identifier and Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. The device will acknowledge all incoming data and address bytes, except for: - The Slave Address Byte when the Device Identifier and/or Select bits are incorrect - The 2nd Data Byte of a Status Register Write Operation (only 1 data byte is allowed) Pin Descriptions VREFOUT Reference voltage output. The 1.25V bandgap reference output (VREF) is available at this pin for application to other circuits. Maximum output current is 400A. The VREFOUT pin also connects to the Rh terminal of the 256-tap DCP. VOUT DCP Wiper Output. This pin functions as the wiper of the DCP, and can be used as a variable voltage source for voltages between GND and VREF . Since it is connected to the DCP resistor, any loads on this pin must be high impedance for best performance. R1 Auxiliary Resistor Input. The R1 pin is connected to one end of a 100k resistor (R1) which closely matches the DCP resistance. The other end of R1 is tied to the RREFL terminal of the DCP. When R1 is grounded and VREFL is left open, the output voltage range of VOUT will be from VREF/2 to VREF , and the effective resolution (mV/step) of the Reference control is doubled. R1 should be left open if not used. GND This pin is common for the VREF output and for control signal inputs. SDA Serial Data Input/Output. Bidirectional pin used for serial data transfer. As an output, it is open drain and may be wire-ored with any number of open drain or open collector outputs. A pullup resistor is required and the value is dependent on the speed of the serial data bus and the number of outputs tied together. SCL Serial Clock Input. Accepts a clock signal for clocking serial data into and out of the device. VREFL DCP and Auxiliary Resistor Input. This pin is connected to one end of the 256-tap DCP, and also to one end of the 100k auxiliary resistor. When connected to ground, VOUT range will be from 0V to VREF . When left open and R1 is connected to ground, the voltage at this pin will be from VREF/2 to VREF .
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VCC Positive Power Supply. Connect to a voltage supply in the range of 2.7V < VCC < 5.5V, with minimum noise and ripple. For best performance, bypass with a 0.1F capacitor to ground. Figure 3. Valid Start and Stop Conditions
SCL
SDA Start Stop
Figure 4. Acknowledge Response From Receiver
SCL from Master Data Output from Transmitter Data Output from Receiver Start Acknowledge
1
8
9
Figure 5. Valid Data Changes on the SDA Bus
SCL
SDA Data Stable Data Change Data Stable
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Figure 6. Byte Write Sequence
Signals from the Master S t Device a ID r t 01 0 1 0 Slave Address* S t o p
Byte Address 0
Data
SDA Bus Signals From The Slave
0 0/1 0 A C K A C K A C K
*Note: The X60250 will respond to either 000 or 001 slave addresses.
Byte Write For a write operation, the device requires the Slave Address Byte and the Word Address Bytes. This gives the master access to any one of the words in the array. Upon receipt of each address byte, the X60250 responds with an acknowledge. After receiving the address bytes the X60250 awaits the eight bits of data. After receiving the 8 data bits, the X60250 again responds with an acknowledge. The master then terminates the transfer by generating a stop condition. The X60250 then begins an internal write cycle of the data to the nonvolatile memory. During the internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. The SDA output is at high impedance. See Figure 6. Figure 7. Random Address Read Sequence
Signals from the Master S t a r t
A write to a protected block of memory is ignored, but will still receive an acknowledge. At the end of the write command, the X60250 will not initiate an internal write cycle, and will continue to okay commands. Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and its associated ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte + ACK is sent, then the X60250 resets itself without performing the write. The contents of the array are not affected.
Device ID
Slave Address
Byte Address 0
S t a r t
Device ID
Slave Address
S t o p
SDA Bus Signals from the Slave
01 0 1 0
0 0/1 0 A C K A C K
01 0 1 0
0
01 A C K Data
Random Address Read Random read operation allows the master to access any location in the X60250. Prior to issuing the Slave Address Byte, the master must first perform a "dummy" write operation. The master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. After acknowledging receipt of each word address byte, the master immediately issues another start condition and the slave address byte. This is followed by an acknowledge from the device and then by the eight bit data word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. Refer to Figure 7 for the address, acknowledge, and data transfer sequence.
In a similar operation called "Set Current Address," the device sets the address if a stop is issued instead of the second start shown in Figure 7. The X60250 then goes into standby mode after the stop and all bus activity will be ignored until a start is detected. This operation loads the new address into the address counter. The next Current Address Read operation will read from the newly loaded address. This operation could be useful if the master knows the next address it needs to read, but is not ready for the data.
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TYPICAL PERFORMANCE CHARACTERISTIC CURVES
VRefout vs Temperature (2 representative units)
1.25120 1.25070 1.25020 1.24970 Refout Rf t
1.2550 1.2540 1.2530 1.2520
IREFOOUT vs VREFOUT
VREFOUT (V)
+25 deg C -40 deg C
VRefout (V)
1.24920 1.24870 1.24820 1.24770 1.24720 1.24670 1.24620 -50
1.2510 1.2500 1.2490 1.2480
+85 deg C
1.2470 1.2460 1.2450 0.00
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
Temperature (C)
IREFOUT (mA)
VRefout vs Vcc
1.257E+0 1.256E+0 1.255E+0 Refout (-40C) Refout (25C) Refout (85C)
Icc vs Vcc
50.00E-6 45.00E-6 40.00E-6 35.00E-6
Icc (-40C) Icc (25C) Icc (85C)
VRefout (V)
1.254E+0 1.253E+0 1.252E+0 1.251E+0 1.250E+0 1.249E+0 2.50
Icc (A)
3.00 3.50 4.00 4.50 5.00 5.50 6.00
30.00E-6 25.00E-6 20.00E-6 15.00E-6 10.00E-6 2.50
Vcc (V)
3.00
3.50
4.00
4.50
5.00
5.50
Vcc (V)
Vref Output Voltage Noise, 0.1Hz to 10Hz
VREF Output Noise Spectrum 10
Filter = 1 zero at 0.1Hz 2 poles at 10Hz
Noise, uV/rt*Hz
9 8 7 6 5 4 3 2 1 0
10 100 1000 10000
Vertical = 50V/div Horizontal = 1 sec/div
Frequency
INL
0.50 0.40 0.30 0.20
ERROR (LSB)
DNL
0.50 0.40 0.30 0.20
ERROR (LSB)
0.10 0.00 -0.10 -0.20 -0.30 -0.40 -0.50 0 50 100 Tap Position 150 200 250
0.10 0.00 -0.10 -0.20 -0.30 -0.40 -0.50 0 50 100 150 Tap Position 200 250
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TYPICAL PERFORMANCE CHARACTERISTIC CURVES (Continued)
Power On Settling Time
APPLICATIONS INFORMATION Standard Reference configurations Figure 8 shows the device connections to produce a 0 to 1.250V adjustable reference with 8 bits of resolution. VREFL will be grounded in this case. Figure 9 has device connections to produce a 0.625V to 1.250V reference with 8 bits of resolution, with R1 grounded. This configuration effectively doubles the output voltage control resolution, increasing the accuracy of the desired reference output voltage. Since the auxiliary resistor is matched to the DCP resistor, temperature drift is minimized. Figure 8. Standard Configuration
VREFOUT
Figure 9. Using Auxilliary Resistor
VREFOUT
VOUT 1.25V Reference 100K R1
0.625V to 1.25V Range
100K
GND
VREFL
Reducing Output Noise
VOUT Adjusted Reference Voltage 0.0 to 1.25V Range
1.25V Reference
100K R1
The output noise voltage of the reference is typically 200V rms in the 10kHz bandwidth. An advantage of the adjustable reference configuration is the ease in filtering this noise. Simply adding a capacitor to the VOUT pin will produce a single pole filter with a corner frequency of:
1 F CORNER = -- x x R DCP x C FILTER 2
100K
GND
VREFL
RDCP will vary with tap position and wiper resistance. If the approximate tap position of the DCP is known, it can be used to calculate this resistance as follows:
255 - tapw tapw # #R DCP = ----------------------------- x R TOTAL || ------------- x R TOTAL + R WIPER 255 255
For example, with VCC = 5V, tap # = 127 (corresponding to VOUT = 0.623V), CFILTER = 0.1F, using typical values:
R DCP = 25K + 0.6K = 25.6k F CORNER = 62Hz
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Since this is a single pole rolloff, the actual noise bandwidth is 1.57 times this, or 97Hz. This should reduce typical output noise to about 45V rms. Note that if the wiper is set to the highest tap positon (tap# = 255) to give a VOUT of 1.25V, the resulting RDCP = RWIPER or 600, and the filter bandwidth will now be 2.6kHz, increasing noise significantly. If tap positions near VREFOUT will be used, then a series resistor ROUT should be added to better control noise bandwidth. Figure 10. Reducing Output Noise
VREFOUT ROUT VOUT 1.25V Reference 100K R1
(optional)
Higher Reference Voltages If a reference voltage higher than 1.25V is required, then an opamp can be added to amplify the VOUT voltage. There are many micropower opamps available, such as the LMV341, which can produce an output at very close to either supply rail. Figure 11 shows a circuit for a 0V to 5.0V adjustable reference, which has 8 bits of control. Note that if the auxiliary resistor is connected to ground instead of VREFL, then the output voltage range will be 2.5V to 5.0V, but resolution will double. Total current draw from that circuit will be 156A (typically, with VOUT = 5V) including reference and opamp circuitry. Note that due to VCC supply variations, the output may not span up to 5.00V which would result in missing codes at the top end of the DCP range. Figure 11. Increasing Reference Output Voltage
VREFOUT +5V
Filtered Reference Voltage CFILTER
100K 1.25V Reference 100K
R1 20K
5 1 3
+ -
6 2
4
0 to 5.0V
LMV341
GND
VREFL
CFILTER
100K 100K 33K
GND
VREFL
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X60250
PACKAGING INFORMATION 8-Lead Plastic, TSSOP, Package Code V8
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.114 (2.9) .122 (3.1) .041 (1.05) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) (1.78) .031 (.80) .041 (1.05) See Detail "A" (0.42) (0.65) All Measurements Are Typical Seating Plane (4.16) (7.72)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 16
FN8146.1 September 14, 2005

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