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WM8773
24-bit, 96kHz ADC with 8 Channel I/P Multiplexer
DESCRIPTION
The WM8773 is a high performance, stereo audio ADC with an 8 channel input selector. The WM8773 is ideal for digitising multiple analogue sources for surround sound processing applications for home hi-fi, automotive and other audio visual equipment. A stereo 24-bit multi-bit sigma delta ADC is used with an eight stereo channel input selector. Each channel has analogue domain mute and programmable gain control. Digital audio output word lengths from 16-32 bits and sampling rates from 8kHz to 96kHz are supported. The audio data interface supports I2S, left justified, right justified and DSP digital audio formats. The device is controlled via a 3 wire serial interface. The interface provides access to all features including channel selection, volume controls, mutes, de-emphasis and power management facilities. The device is available in a 64-pin TQFP package.
FEATURES
* * * * * Audio Performance - 102dB SNR (`A' weighted @ 48kHz) ADC ADC Sampling Frequency: 8kHz - 96kHz 3-Wire SPI MPU Serial Control Interface Master or Slave Clocking Mode Programmable Audio Data Interface Modes - * * * * I2S, Left, Right Justified or DSP - 16/20/24/32 bit Word Lengths Analogue Record Monitor Outputs Eight stereo ADC inputs with analogue gain adjust from +19dB to -12dB in 1dB steps 2.7V to 5.5V Analogue, 2.7V to 3.6V Digital supply Operation 5V tolerant digital inputs
APPLICATIONS
* * Surround Sound AV Processors and Hi-Fi systems Automotive Audio
BLOCK DIAGRAM
VMIDADC AINVGR AGND1 AVDD1 REFADC AINVGL
AIN1L AIN1R AIN2L AIN2R AIN3L AIN3R AIN4L AIN4R AIN5L AIN5R AIN6L AIN6R AIN7L AIN7R AIN8L AIN8R
WM8773
INPUT SOURCE SELECTOR
AUDIO INTERFACE STEREO ADC AND DIGITAL FILTERS
MCLK DOUT ADCLRC BCLK
AINOPL AINOPR RECL RECR
MUTE
CONTROL INTERFACE
CL
CE
DGND
DVDD
WOLFSON MICROELECTRONICS LTD w :: www.wolfsonmicro.com
RESETB
DI
Product Preview, April 2002, Rev 1.0 Copyright 2002 Wolfson Microelectronics Ltd.
WM8773 PIN CONFIGURATION
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ORDERING INFORMATION
DEVICE WM8773IFT/V TEMP. RANGE -40 to +85oC PACKAGE 64-pin TQFP
ADCLRC
RESETB
MCLK
BCLK
AIN1L AIN1R AIN2L AIN2R AIN3L AIN3R AIN4L AIN4R AIN5L AIN5R AIN6L AIN6R AIN7L AIN7R AIN8L AIN8R
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
DVDD
DOUT
NC
NC
NC
NC
NC
NC
NC
CE
CL
DI
DGND AGND2 NC NC NC NC NC NC NC NC NC NC NC NC NC AVDD2
10 11 12 13 14 15
33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC
AINVGR
AINOPR
RECL
REFADC
AINOPL
AINVGL
VMIDADC
NC
NC
NC
RECR
AGND1
AVDD1
NC
NC
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WM8773
NAME AIN1L AIN1R AIN2L AIN2R AIN3L AIN3R AIN4L AIN4R AIN5L AIN5R AIN6L AIN6R AIN7L AIN7R AIN8L AIN8R AINOPL AINVGL AINVGR AINOPR RECL RECR REFADC VMIDADC AGND1 AVDD1 TYPE Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Output Analogue Input Analogue Input Analogue Output Analogue Output Analogue Output Analogue Output Analogue Output Supply Supply NC NC NC NC NC NC AVDD2 Supply NC NC NC NC NC NC NC NC NC NC NC NC NC AGND2 DGND DVDD Supply Supply Supply DESCRIPTION Channel 1 left input multiplexor virtual ground Channel 1 right input multiplexor virtual ground Channel 2 left input multiplexor virtual ground Channel 2 right input multiplexor virtual ground Channel 3 left input multiplexor virtual ground Channel 3 right input multiplexor virtual ground Channel 4 left input multiplexor virtual ground Channel 4 right input multiplexor virtual ground Channel 5 left input multiplexor virtual ground Channel 5 right input multiplexor virtual ground Channel 6 left input multiplexor virtual ground Channel 6 right input multiplexor virtual ground Channel 7 left input multiplexor virtual ground Channel 7 right input multiplexor virtual ground Channel 8 left input multiplexor virtual ground Channel 8 right input multiplexor virtual ground Left channel multiplexor output Left channel multiplexor virtual ground Right channel multiplexor virtual ground Right channel multiplexor output Left channel input mux select output Right channel input mux select output ADC reference buffer decoupling pin; 10uF external decoupling ADC midrail divider decoupling pin; 10uF external decoupling Analogue negative supply and substrate connection Analogue positive supply No connection No connection No connection No connection No connection No connection Analogue positive supply No connection No connection No connection No connection No connection No connection No connection No connection No connection No connection No connection No connection No connection Analogue negative supply and substrate connection Digital negative supply Digital positive supply
PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
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WM8773
PIN 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ADCLRC BCLK MCLK CL DI CE RESETB DOUT NAME TYPE NC NC Digital output NC NC NC NC NC Digital input/output Digital input/output Digital input Digital input Digital input Digital input Digital input No connection No connection ADC data output No connection No connection No connection No connection No connection ADC left/right word clock ADC audio interface bit clock DESCRIPTION
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Master ADC clock; 256, 384, 512 or 768fs (fs = word clock frequency) Serial interface clock (5V tolerant) Serial interface data (5V tolerant) Serial interface Latch signal (5V tolerant) Device reset input (resets gain stages to 0dB) (5V tolerant)
Note : Digital input pins have Schmitt trigger input buffers and are 5V tolerant.
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WM8773
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.
CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs (DI, CL, CE & RESETB) Voltage range digital inputs (MCLK, ADCLRC & BCLK) Voltage range analogue inputs Master Clock Frequency Operating temperature range, TA Storage temperature Package body temperature (soldering 10 seconds) Package body temperature (soldering 2 minutes) Notes: 1. Analogue and digital grounds must always be within 0.3V of each other.
MIN -0.3V -0.3V DGND -0.3V DGND -0.3V AGND -0.3V
MAX +3.63V +7V +7V DVDD + 0.3V AVDD +0.3V 37MHz
-40C -65C
+85C +150C +240C +183C
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WM8773 RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analogue supply range Ground Difference DGND to AGND Note: Digital supply DVDD must never be more than 0.3V greater than AVDD. SYMBOL DVDD AVDD AGND, DGND -0.3 TEST CONDITIONS MIN 2.7 2.7 0 0 +0.3 TYP MAX 3.6 5.5
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UNIT V V V V
ELECTRICAL CHARACTERISTICS
Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER Digital Logic Levels (TTL Levels) Input LOW level Input HIGH level Output LOW Output HIGH Analogue Reference Levels Reference voltage Potential divider resistance VVMID RVMID AVDD to VMIDADC and VMIDADC to AGND AVDD/2 - 50mV 40k AVDD/2 50k AVDD/2 + 50mV 60k V Ohms VIL VIH VOL VOH IOL=1mA IOH-1mA 0.9 x DVDD 2.0 0.1 x DVDD 0.8 V V V V SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
ADC Performance Input Signal Level (0dB) SNR (Note 1,2) SNR (Note 1,2) Dynamic Range (note 2) Total Harmonic Distortion (THD) ADC Channel Separation Programmable Gain Step Size Programmable Gain Range Mute Attenuation Power Supply Rejection Ratio PSRR 1kHz Input 1kHz Input, 0dB gain 1kHz 100mVpp 20Hz to 20kHz 100mVpp A-weighted, 0dB gain @ fs = 48kHz A-weighted, 0dB gain @ fs = 96kHz A-weighted, -60dB full scale input kHz, 0dBFs 1kHz, -3dBFs 1kHz Input 0.5 -12 97 50 45 93 1.0 x AVDD/5 102 98 102 -90 -95 90 1.0 1.5 +19 -80 -85 Vrms dB dB dB dB dB dB dB dB dB dB dB
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WM8773
Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER 0dB Full scale output voltage SNR (Note 1) THD Power Supply Rejection Ratio PSRR 1kHz, 0dB 1kHz, -3dB 1kHz 100mVpp 20Hz to 20kHz 100mVpp Mute Attenuation (REC Output Only) Supply Current Analogue supply current Digital supply current Notes: 1. 2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A' weighted. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). AVDD = 5V DVDD = 3.3V 100 20 mA mA 1kHz, 0dB 90 SYMBOL TEST CONDITIONS MIN TYP 1.0 x AVDD/5 100 -90 -95 50 45 100 MAX UNIT Vrms dB dB dB dB dB dB Analogue input (AIN) to Analogue output (VOUT) (Load=10k ohms, 50pF, gain = 0dB) Record Monitor Output
3.
TERMINOLOGY
1. 2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
3. 4. 5. 6.
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WM8773
MASTER CLOCK TIMING
tMCLKL MCLK tMCLKH tMCLKY
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Figure 1 Master Clock Timing Requirements Test Conditions o AVDD = 5V, DVDD = 3.3V, AGND = 0V, AGND, DGND = 0V, TA = +25 C, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER System Clock Timing Information
MCLK System clock pulse width high MCLK System clock pulse width low MCLK System clock cycle time MCLK Duty cycle
SYMBOL tMCLKH tMCLKL tMCLKY
TEST CONDITIONS
MIN 11 11 28 40:60
TYP
MAX
UNIT ns ns ns
60:40
Table 1 Master Clock Timing Requirements
DIGITAL AUDIO INTERFACE - MASTER MODE
BCLK WM8773 ADCLRC ADC DOUT
DSP/ ENCODER/ DECODER
Figure 2 Audio Interface - Master Mode
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WM8773
BCLK (Output) tDL ADCLRC tDDA DOUT
Figure 3 Digital Audio Data Timing - Master Mode
Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER ADCLRC propagation delay from BCLK falling edge DOUT propagation delay from BCLK falling edge SYMBOL tDL tDDA TEST CONDITIONS MIN 0 0 TYP MAX 10 10 UNIT ns ns
Audio Data Input Timing Information
Table 2 Digital Audio Data Timing - Master Mode
DIGITAL AUDIO INTERFACE - SLAVE MODE
BCLK WM8773 CODEC ADCLRC DOUT
DSP ENCODER/ DECODER
Figure 4 Audio Interface - Slave Mode
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WM8773
tBCH BCLK tBCY ADCLRC tDD DOUT tBCL
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Figure 5 Digital Audio Data Timing - Slave Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER BCLK cycle time BCLK pulse width high BCLK pulse width low DOUT propagation delay from BCLK falling edge SYMBOL tBCY tBCH tBCL tDD TEST CONDITIONS MIN 50 20 20 0 10 TYP MAX UNIT ns ns ns ns
Audio Data Input Timing Information
Table 3 Digital Audio Data Timing - Slave Mode Note: 1. ADCLRC should be synchronous with MCLK, although the WM8773 interface is tolerant of phase variations or jitter on these signals.
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WM8773
MPU INTERFACE TIMING
tRCSU RESETB tCSL CE tSCY tSCH CL tSCL tSCS tCSS tCSH tRCHO
DI tDSU tDHO
LSB
Figure 6 SPI compatible Control Interface Input Timing Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated PARAMETER CE to RESETB hold time RESETB to CL setup time CL rising edge to CE rising edge CL pulse cycle time CL pulse width low CL pulse width high DI to CL set-up time CL to DI hold time CE pulse width low CE pulse width high CE rising to CL rising SYMBOL tRCSU tRCHO tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS MIN 20 20 60 80 30 30 20 20 20 20 20 TYP MAX UNIT ns ns ns ns ns ns ns ns ns ns ns
Table 4 3-wire SPI compatible Control Interface Input Timing Information
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WM8773 DEVICE DESCRIPTION
INTRODUCTION
WM8773 is a complete stereo audio ADC with 8-channel multiplexed input.
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The input multiplexor to the ADC is configured to allow large signal levels to be input to the ADC, using external resistors to reduce the amplitude of larger signals to within the normal operating range of the ADC. The ADC input PGA also allows input signals to be gained up to +19dB and attenuated down to -12dB. This allows the user maximum flexibility in the use of the ADC. Analogue record monitor outputs are also available, to allow stereo analogue signals from any of the 8 stereo inputs to be sent to sent to one of the two stereo outputs. This allows the user to monitor the signal that is being digitised either prior to the input programmable gain amplifier (PGA) or after gain has been applied. It is intended that the RECL/R outputs are only used to drive a high impedance buffer. The Audio Interface may be configured to operate in either master or slave mode. In Slave mode ADCLRC and BCLK are both inputs. In Master mode ADCLRC and BCLK are all outputs. Control of internal functionality of the device is by 3-wire serial control interface. The control interface may be asynchronous to the audio data interface as control data will be re-synchronised to the audio processing internally. CE, CL, DI and RESETB are 5V tolerant with TTL input thresholds, allowing the WM8773 to used with DVDD = 3.3V and be controlled by a controller with 5V output. Operation using system clock of 256fs, 384fs, 512fs or 768fs is provided. In Slave mode selection between clock rates is automatically controlled. In master mode the master clock to sample rate ratio is set by control bit ADCRATE. Sample rates (fs) from less than 8ks/s up to 96ks/s are allowed, provided the appropriate system clock is input. The audio data interface supports right, left and I S interface formats along with a highly flexible DSP serial port interface.
2
AUDIO DATA SAMPLING RATES
In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's Master Clock. The external master system clock can be applied directly through the MCLK input pin with no software configuration necessary. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the ADC. The master clock for WM8773 supports ADC audio sampling rates from 256fs to 768fs, where fs is the audio sampling frequency (ADCLRC) typically 32kHz, 44.1kHz, 48kHz or 96kHz. The master clock is used to operate the digital filters and the noise shaping circuits. In Slave mode the WM8773 has a master detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If there is a greater than 32 clocks error the interface is disabled and maintains the output level at the last sample. The master clock must be synchronised with ADCLRC, although the WM8773 is tolerant of phase variations or jitter on this clock. Table 5 shows the typical master clock frequency inputs for the WM8773. The signal processing for the WM8773 typically operates at an oversampling rate of 128fs for the ADC. For ADC operation at 96kHz, it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate to 64fs. SAMPLING RATE (ADCLRC) 32kHz 44.1kHz 48kHz System Clock Frequency (MHz) 256fs 384fs 512fs 768fs
8.192 11.2896 12.288
12.288 16.9340 18.432
16.384 22.5792 24.576
24.576 33.8688 36.864
Table 5 System Clock Frequencies Versus Sampling Rate
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WM8773
In Master mode BCLK and ADCLRC are generated by the WM8773. The frequency of ADCLRC is determined by setting the required ratio of MCLK to ADCLRC using the ADCRATE control bits (Table 6). ADCRATE[2:0] MCLK:ADCLRC RATIO
010 011 100 101
256fs 384fs 512fs 768fs
Table 6 Master Mode MCLK:ADCLRC ratio select Table 7 shows the settings for ADCRATE for common sample rates and MCLK frequencies. SAMPLING RATE ADCLRC System Clock Frequency (MHz) 256fs
ADCRATE =010
384fs
ADCRATE =011
512fs
ADCRATE =100
768fs
ADCRATE =101
32kHz 44.1kHz 48kHz 96kHz
8.192 11.2896 12.288 24.576
12.288 16.9340 18.432 36.864
16.384 22.5792 24.576
24.576 33.8688 36.864
Unavailable Unavailable
Table 7 Master Mode ADC frequency selection BCLK is also generated by the WM8773. The frequency of BCLK depends on the mode of operation. In 256/384/512fs modes (ADCRATE=010 or 011, 100 or 101) BCLK = MCLK/4. However if DSP mode is selected as the audio interface mode then BCLK=MCLK.
POWERDOWN MODES
The WM8773 has powerdown control bits allowing specific parts of the WM8773 to be powered off when not being used. The 8-channel input source selector and input buffer may be powered down using control bit AINPD. When AINPD is set all inputs to the source selector (AIN1l/R to AIN8L/R) are switched to a buffered VMIDADC. Control bit ADCPD powers off the ADC and also the ADC input PGAs. Setting AINPD and ADCPD will powerdown everything except the references VMIDADC and ADCREF. These may be powered down by setting PDWN. Setting PDWN will override all other powerdown control bits. It is recommended that the 8-channel input mux and buffer and ADC are powered down before setting PDWN. The default is for all powerdown bits to be set except PDWN. The Powerdown control bits allow parts of the device to be powered down when not in use.
DIGITAL AUDIO INTERFACE
MASTER AND SLAVE MODES
The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In both Master and Slave modes, ADCDAT is always an output. The default is Slave mode. In Slave mode (MS=0) ADCLRC and BCLK are inputs to the WM8773 (Figure 7). ADCLRC is sampled by the WM8773 on the rising edge of BCLK. ADC data is output on DOUT and changes on the falling edge of BCLK. By setting control bit BCLKINV the polarity of BCLK may be reversed so that ADCLRC is sampled on the falling edge of BCLK and DOUT changes on the rising edge of BCLK.
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WM8773
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BCLK WM8773 CODEC ADCLRC DOUT
DSP ENCODER/ DECODER
Figure 7 Slave Mode In Master mode (MS=1) ADCLRC and BCLK are outputs from the WM8773 (Figure 8). ADCLRC and BITCLK are generated by the WM8773. ADCDAT is output on DOUT and changes on the falling edge of BCLK. By setting control bit BCLKINV the polarity of BCLK may be reversed so that DOUT changes on the rising edge of BCLK.
BCLK WM8773 ADCLRC ADC DOUT
DSP/ ENCODER/ DECODER
Figure 8 Master Mode
AUDIO INTERFACE FORMATS
Audio data is output from the ADC filters, via the Digital Audio Interface. 5 popular interface formats are supported: * * * * * Left Justified mode Right Justified mode I2S mode DSP Early mode DSP Late mode
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. In left justified, right justified and I2S modes, the digital audio interface outputs ADC data on DOUT. Audio Data for each stereo channel is time multiplexed with ADCLRC indicating whether the left or right channel is present. ADCLRC is also used as a timing reference to indicate the beginning or end of the data words. In left justified, right justified and I2S modes, the minimum number of BCLKs per ADCLRC period is 2 times the selected word length. ADCLRC must be high for a minimum of word length BCLKs and low for a minimum of word length BCLKs. Any mark to space ratio on ADCLRC is acceptable provided the above requirements are met. PP Rev 1.0 June 2002 14
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WM8773
The ADC data may also be output in DSP early or late modes, with ADCLRC used as a frame sync to identify the MSB of the first word. The minimum number of BCLKs per ADCLRC period is 2 times the selected word length
LEFT JUSTIFIED MODE
In left justified mode, the MSB of the ADC data is output on DOUT and changes on the same falling edge of BCLK as ADCLRC and may be sampled on the rising edge of BCLK. ADCLRC is high during the left samples and low during the right samples (Figure 9).
1/fs
LEFT CHANNEL ADCLRC
RIGHT CHANNEL
BCLK
DOUT
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 9 Left Justified Mode TIming Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB of the ADC data is output on DOUT and changes on the falling edge of BCLK preceding an ADCLRC transition and may be sampled on the rising edge of BCLK. ADCLRC is high during the left samples and low during the right samples).
1/fs
LEFT CHANNEL ADCLRC
RIGHT CHANNEL
BCLK
DOUT
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 10 Right Justified Mode TIming Diagram
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WM8773
I S MODE
2
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In I2S mode, the MSB of the ADC data is output on DOUT and changes on the first falling edge of BCLK following an ADCLRC transition and may be sampled on the rising edge of BCLK. ADCLRC is low during the left samples and high during the right samples.
1/fs
LEFT CHANNEL ADCLRC
RIGHT CHANNEL
BCLK
1 BCLK 1 BCLK 3 n-2 n-1 n 1 2 3 n-2 n-1 n
DOUT
1
2
MSB
LSB
MSB
LSB
Figure 11 I2S Mode TIming Diagram
DSP EARLY MODE
The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of BCLK following a low to high ADCLRC transition and may be sampled on the rising edge of BCLK. The right channel ADC data is contiguous with the left channel data (Figure 12)
1 BCLK 1/fs 1 BCLK
ADCLRC
BCK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
1
2
n-1
n
1
2
n-1
n
MSB
Word Length (WL)
LSB
Figure 12 DSP Early Mode Timing Diagram - ADC Data Output
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WM8773
DSP LATE MODE
The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of BCLK as the low to high ADCLRC transition and may be sampled on the rising edge of BCLK. The right channel ADC data is contiguous with the left channel data (Figure 13).
1/fs
ADCLRC
BCK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
DOUT
1
2
n-1
n
1
2
n-1
n
1
MSB
Word Length (WL)
LSB
Figure 13 DSP Late Mode Timing Diagram - ADC Data Output
CONTROL INTERFACE OPERATION
The WM8773 is controlled using a 3-wire SPI compatible serial configuration. The control interface is 5V tolerant, meaning that the control interface input signals CE, CL and DI may have an input high level of 5V while DVDD is 3V. Input thresholds are determined by DVDD. RESETB is also 5V tolerant.
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
DI is used for the program data, CL is used to clock in the program data and CE is used to latch the program data. DI is sampled on the rising edge of CL. The 3-wire interface protocol is shown in Figure 14.
CE
CL
DI
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 14 3-wire SPI compatible Interface Note: 1. 2. 3. B[15:9] are Control Address Bits B[8:0] are Control Data Bits CE is edge sensitive - the data is latched on the rising edge of CE.
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WM8773
CONTROL INTERFACE REGISTERS
DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the FMT[1:0] register bits: REGISTER ADDRESS 10110 Interface Control BIT 1:0 LABEL FMT[1:0] DEFAULT 10
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DESCRIPTION Interface format Select 00 : right justified mode 01: left justified mode 10: I2S mode 11: DSP (early or late) mode
In left justified, right justified or I S modes, the LRP register bit controls the polarity of ADCLRC. If this bit is set high, the expected polarity of ADCLRC will be the opposite of that shown Figure 9, and. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes, the LRP register bit is used to select between early and late modes. REGISTER ADDRESS 10110 Interface Control BIT 2 LABEL LRP DEFAULT 0 DESCRIPTION In left/right/I2S modes: ADCLRC Polarity (normal) 0 : normal ADCLRC polarity 1: inverted ADCLRC polarity In DSP mode: 0 : Early DSP mode 1: Late DSP mode By default, ADCLRC is sampled on the rising edge of BCLK and should ideally change on the falling edge. Data sources that change ADCLRC on the rising edge of BCLK can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the inverse of that shown in Figure 9, Figure 10, Figure 11, Figure 12, and Figure 13. REGISTER ADDRESS 10110 Interface Control BIT 3 LABEL BCP DEFAULT 0 DESCRIPTION BCLK Polarity (DSP modes) 0 : normal BCLK polarity 1: inverted BCLK polarity
2
The WL[1:0] bits are used to control the word length. REGISTER ADDRESS 10110 Interface Control BIT 5:4 LABEL WL[1:0] DEFAULT 10 DESCRIPTION Word Length 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data
Note: 1. 2. If 32-bit mode is selected in right justified mode, the WM8773 defaults to 24 bits. In 24 bit I2S mode, any width of 24 bits or less is supported provided that ADCLRC is high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs.
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WM8773
Control bit MS selects between audio interface Master and Slave Modes. In Master mode ADCLRC and BCLK are outputs and are generated by the WM8773. In Slave mode ADCLRC and BCLK are inputs to WM8773. REGISTER ADDRESS 10111 Interface Control BIT 8 LABEL MS DEFAULT 0 DESCRIPTION Audio Interface Master/Slave Mode select: 0 : Slave Mode 1: Master Mode
MASTER MODE ADCLRC FREQUENCY SELECT
In Master mode the WM8773 generates ADCLRC and BCLK. These clocks are derived from master clock and the ratio of MCLK to ADCLRC and are set by ADCRATE. REGISTER ADDRESS BIT LABEL ADCRATE[2:0] DEFAULT 010 DESCRIPTION Master Mode MCLK:ADCLRC ratio select: 010: 256fs 011: 384fs 100: 512fs 101: 768fs
0111 ADCLRC frequency 2:0 select
ADC OVERSAMPLING RATE SELECT
For ADC operation at 96kHz it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate to 64fs. REGISTER ADDRESS 10111 ADC Oversampling Rate BIT 3 LABEL ADCOSR DEFAULT 0 DESCRIPTION ADC oversampling rate select 0: 128x oversampling 1: 64x oversampling
MUTE MODES
Each ADC channel has an individual mute control bit, which mutes the input to the ADC. In addition both channels may be muted by setting ADCMUTE. REGISTER ADDRESS 11001 ADC Mute BIT 7 LABEL ADCMUTE DEFAULT 0 DESCRIPTION ADC MUTE Left and Right 0 : Normal Operation 1: mute ADC left and ADC right ADC Mute select 0 : Normal Operation 1: mute ADC left ADC Mute select 0 : Normal Operation 1: mute ADC right
11001 ADC Mute Left 11010 ADC Mute Right
5
MUTE
0
5
MUTE
0
The Record outputs may be enabled by setting RECEN, where RECEN enables the RECL and RECR outputs. REGISTER ADDRESS 10100 REC Enable BIT 5 LABEL RECEN DEFAULT 0 DESCRIPTION REC Output Enable 0 : REC output muted 1: REC output enabled
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WM8773
POWERDOWN MODE AND ADC DISABLE
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Setting the PDWN register bit immediately powers down the WM8773, including the references, overriding all other powerdown control bits. All trace of the previous input samples are removed, but all control register settings are preserved. When PDWN is cleared the digital filters will be reinitialised. It is recommended that the 8-channel input mux and buffer, and ADC are powered down before setting PDWN. REGISTER ADDRESS 11000 Powerdown Control BIT 0 LABEL PDWN DEFAULT 0 DESCRIPTION Power Down Mode Select: 0 : Normal Mode 1: Power Down Mode
The ADC may also be powered down by setting the ADCD disable bit. Setting ADCD will disable the ADC and select a low power mode. The ADC digital filters will be reset and will reinitialise when ADCD is reset. REGISTER ADDRESS 11000 ADC Powerdown Control BIT 1 LABEL ADCD DEFAULT 1 DESCRIPTION ADC Disable: 0 : Normal Mode 1: Power Down Mode
ADC GAIN CONTROL
Control bits LAG[4:0] and RAG[4:0] control the ADC input gain, allowing the user to attenuate the ADC input signal to match the full-scale range of the ADC. The gain is independently adjustable on left and right inputs. Left and right inputs may also be independently muted. The LRBOTH control bit allows the user to write the same attenuation value to both left and right volume control registers. The ADC volume and mute also applies to the bypass signal path.
REGISTER ADDRESS 11001 Attenuation ADCL
BIT 4:0 5
LABEL LAG[4:0] MUTE
DEFAULT 01100 (0dB) 0
DESCRIPTION Attenuation data for Left channel ADC gain in 1dB steps. See Table 8 Mute for Left channel ADC: 0: Mute off 1: Mute on Setting LRBOTH will write the same gain value to LAG[4:0] and RAG[4:0] Attenuation data for right channel ADC gain in 1dB steps. See Table 8 Mute for Right channel ADC: 0: Mute off 1: Mute on Setting LRBOTH will write the same gain value to RAG[4:0] and LAG[4:0]
6 11010 Attenuation ADCR 4:0 5
LRBOTH RAG[4:0] MUTE
0 01100 (0dB) 0
6
LRBOTH
0
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WM8773
ADC INPUT GAIN
Registers LAG and RAG control the left and right channel gain into the stereo ADC in 1dB steps from +19dB to -12dB Table 8 shows how the attenuation levels are selected from the 5-bit words. L/RAG[6:0] 0 : 01100 : 11111 Table 8 ADC Gain Control ATTENUATION LEVEL -12dB : 0dB : +19dB
ADC HIGHPASS FILTER DISABLE
The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled using software control bit ADCHPD. REGISTER ADDRESS 10110 ADC control BIT 8 LABEL ADCHPD DEFAULT 0 DESCRIPTION ADC Highpass filter disable: 0: Highpass filter enabled 1: Highpass filter disabled
ADC INPUT MUX AND POWERDOWN CONTROL
REGISTER ADDRESS 11011 ADC mux and powerdown control BIT 2:0 6:4 8 LABEL LMX[2:0] RMX[2:0] AINPD DEFAULT 000 000 1 DESCRIPTION ADC left channel input mux control bits (see Table 9) ADC right channel input mux control bits (see Table 9) Input mux and buffer powerdown 0: Input mux and buffer enabled 1: Input mux and buffer powered down
Register bits LMX and RMX control the left and right channel inputs into the stereo ADC. The default is AIN1. However if the analogue input buffer is powered down, by setting AINPD, then all 8-channel mux inputs are switched to buffered VMIDADC. LMX[2:0] 000 001 010 011 100 101 110 111 LEFT ADC INPUT AIN1L AIN2L AIN3L AIN4L AIN5L AIN6L AIN7L AIN8L RMX[2:0] 000 001 010 011 100 101 110 111 RIGHT ADC INPUT AIN1R AIN2R AIN3R AIN4R AIN5R AIN6R AIN7R AIN8R
Table 9 ADC Input Mux Control
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WM8773
SOFTWARE REGISTER RESET
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Writing to register 11111 will cause a register reset, resetting all register bits to their default values.
REGISTER MAP
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8773 can be configured using the Control Interface. All unused bits should be set to `0'.
REGISTER R20(14h) R22(16h) R23(17h) R24(18h) R25(19h) R26(1Ah) R27(1Bh) R31(1Fh) B15 0 0 0 0 0 0 0 0 B14 0 0 0 0 0 0 0 0 B13 1 1 1 1 1 1 1 1 B12 0 0 0 1 1 1 1 1 B11 1 1 1 0 0 0 0 1 B10 0 1 1 0 0 1 1 1 B9 0 0 1 0 1 0 1 1 B8 x ADCHPD MS x x x AINPD B7 x x x x ADCMUTE x x B6 x x x x LRBOT H LRBOT H B5 RECEN WL[1:0] x x MUTE MUTE RMX[2:0] RESET DATA x x x B4 x B3 x BCP ADCOSR x x B2 x LRP B1 x B0 x DEFAULT 000000000 000100010 000010010 000111110 000001100 000001100 LMX[2:0] 100000000 not reset DEFAULT
FMT[1:0]
ADCRATE[2:0] ADCD PWDN
LAG[4:0] RAG[4:0]
ADDRESS
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WM8773
BIT 5 LABEL RECEN DEFAULT 0 DESCRIPTION REC Output Enable 0 : REC output muted 1: REC output enabled
REGISTER ADDRESS 10100 Mute
1:0 10110 Interface Control 2
FMT[1:0]
10
Interface format select
00: right justified mode 01: left justified mode 10: I2S mode 11: DSP mode ADCLRC Polarity or DSP Early/Late mode select Left Justified / Right Justified / 2 IS 0: Standard ADCLRC Polarity 1: Inverted ADCLRC Polarity DSP Mode 0: Early DSP mode 1: Late DSP mode
LRP
0
3
BCP
0
BITCLK Polarity 0: Normal - ADCLRC sampled on rising edge of BCLK; DOUT changes on falling edge of BCLK. 1: Inverted - ADCLRC sampled on falling edge of BCLK; DOUT changes on rising edge of BCLK. Input Word Length 00: 16-bit Mode 01: 20-bit Mode 10: 24-bit Mode 11: 32-bit Mode (not supported in right justified mode) ADC Highpass Filter Disable: 0: Highpass Filter enabled 1: Highpass Filter disabled Master Mode MCLK:ADCLRC ratio select: 010: 256fs 011: 384fs 100: 512fs ADC oversample rate select 0: 128x oversampling 1: 64x oversampling Maser/Slave interface mode select 0: Slave Mode - ADCLRC and BCLK are inputs 1: Master Mode - ADCLRC and BCLK are outputs Chip Powerdown Control (works in together with ADCD) 0: All circuits running, outputs are active 1: All circuits in power save mode, outputs muted ADC powerdown: 0: ADC enabled 1: ADC disabled Attenuation data for left channel ADC gain in 1dB steps Mute for Left channel ADC: 0: Mute off 1: Mute on Setting LRBOTH will write the same gain value to LAG[4:0] and RAG[4:0] Mute for Left and Right channel ADC: 0: Mute off 1: Mute on PP Rev 1.0 June 2002 23
5:4
WL[1:0]
10
8
ADCHPD
0
10111 Master Mode control
2:0
ADCRATE[2:0]
010
3
ADCOSR
0
8
MS
0
11000 Powerdown Control
0
PWDN
0
1
ADCD
1
11001 Attenuation ADCL
4:0 5
LAG[4:0] MUTE
01100 (0dB) 0
6 7
LRBOTH ADCMUTE
0 0
WM8773
REGISTER ADDRESS 11010 Attenuation ADCR BIT 4:0 5 LABEL RAG[4:0] MUTE DEFAULT 01100 (0dB) 0 DESCRIPTION
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Attenuation data for right channel ADC gain in 1dB steps Mute for Right channel ADC: 0: Mute off 1: Mute on Setting LRBOTH will write the same gain value to RAG[4:0] and LAG[4:0] ADC left channel input mux control bits ADC right channel input mux control bits Input mux and buffer powerdown 0: Input mux and buffer enabled 1: Input mux and buffer powered down Writing to this register will apply a reset to the device registers.
6 11011 ADC mux control 2:0 6:4 8
LRBOTH LMX[2:0] RMX[2:0] AINPD
0 000 000 1
11111
Software reset
[8:0]
RESET
Not reset
Table 10 Register Map Description
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WM8773
DIGITAL FILTER CHARACTERISTICS
PARAMETER ADC Filter Passband Passband ripple Stopband Stopband Attenuation Group Delay Table 11 Digital Filter Characteristics f > 0.5465fs 0.5465fs -65 22 dB fs 0.01 dB -6dB 0 0.5fs 0.01 dB 0.4535fs TEST CONDITIONS MIN TYP MAX UNIT
ADC FILTER RESPONSES
0.02
0
0.015 0.01
-20
Response (dB)
Response (dB)
0.005 0 -0.005 -0.01 -0.015 -0.02
-40
-60
-80
0
0.5
1
1.5 Frequency (Fs)
2
2.5
3
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency (Fs)
0.35
0.4
0.45
0.5
Figure 15 ADC Digital Filter Frequency Response
Figure 16 ADC Digital Filter Ripple
ADC HIGH PASS FILTER
The WM8773 has a selectable digital highpass filter to remove DC offsets. The filter response is characterised by the following polynomial.
1 - z-1 1 - 0.9995z-1
H(z) =
0
Response (dB)
-5
-10
-15
0
0.0005
0.001 Frequency (Fs)
0.0015
0.002
Figure 17 ADC Highpass Filter Response PP Rev 1.0 June 2002 25
WM8773 EXTERNAL CIRCUIT CONFIGURATION
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In order to allow the use of 2V rms and larger inputs to the ADC inputs, a structure is used that uses external resistors to drop these larger voltages. This also increases the robustness of the circuit to external abuse such as ESD pulse.
Figure 18 shows the ADC input multiplexor circuit with external components allowing 2Vrms inputs to be applied.
5K
AINOPL
10uF 10K
AINVGL AIN1L
10uF
10K
AIN2L
10uF 10K
AIN3L
10uF
10K
AIN7L
10uF 10K
AIN8L
SOURCE SELECTOR INPUTS
5K
AINOPR
10uF 10K
AINVGR AIN1R
10uF
10K
AIN2R
10uF 10K
AIN3R
10uF
10K
AIN7R
10uF 10K
AIN8R
Figure 18 ADC Input Multiplexor Configuration
PP Rev 1.0 June 2002 26
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WM8773
PACKAGE DIMENSIONS
FT: 64 PIN TQFP (10 x 10 x 1.0 mm)
b e
48 33
DM027.A
49
32
E1
E
64
17
1
16
4
c
D1 D L
A
A2
A1
-Cccc C
SEATING PLANE
Symbols A A1 A2 b c D D1 E E1 e L
4
ccc REF:
Dimensions (mm) MIN NOM MAX --------1.20 0.05 ----0.15 1.00 1.05 0.95 0.27 0.17 0.22 0.09 ----0.20 12.00 BSC 10.00 BSC 12.00 BSC 10.00 BSC 0.50 BSC 0.45 0.60 0.75 o o o 0 3.5 7 Tolerances of Form and Position 0.08 JEDEC.95, MS-026
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ACD. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
PP Rev 1.0 June 2002 27
WM8773 IMPORTANT NOTICE
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Wolfson Microelectronics Ltd (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is neither responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics Ltd 20 Bernard Terrace Edinburgh EH8 9NX United Kingdom
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
PP Rev 1.0 June 2002 28
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WM8773
REVISION HISTORY
DATE REV ORIGINATOR CHANGES
PP Rev 1.0 June 2002 29
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