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WM2627 Quad 8-Bit Serial Input Voltage Output DAC
Production Data, April 2001, Rev 1.0
FEATURES
* * * * * * Four 8-bit voltage output DACs Dual 2.7V to 5.5V supply (separate digital and analogue supplies) DNL 0.03 LSB, INL 0.3 LSB typical Low power consumption: - 3mW, slow mode - 3V supply - 9mW, fast mode - 3V supply DSP and microprocessor compatible serial interface Programmable settling time of 2.5s or 8.5s typical
DESCRIPTION
The WM2627 is a quadruple 8-bit voltage output, resistor string, digital-to-analogue converter. Each DAC can be individually powered down under software control. A hardware controlled mode is provided that powers down all DACs. Power down reduces current consumption to 1 A. The device has been designed to interface efficiently to industry standard microprocessors and DSPs. It is programmed with a 16-bit serial word comprising of a DAC address, individual DAC control bits and an 8-bit value. The WM2627 has provision for two supplies: one supply for the serial interface (DVDD, DGND), and one for the DACs, reference buffers and output buffers (AVDD, AGND). This enables a typical application where the device can be controlled via a microprocessor operating on a 3V supply, with the DACs operating on a 5V supply. Alternatively, the supplies can be tied together in a single supply application. Excellent performance is delivered with a typical DNL of 0.03 LSB. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The output stage is buffered by a x2 gain near rail-to-rail amplifier, which features a Class AB output stage. DACs A and B can have a different reference voltage to DACs C and D. The device is available in a 16-pin TSSOP package. Commercial temperature (0 to 70C) and Industrial temperature (-40 to 85C) variants are supported.
APPLICATIONS
* * * * * * * Battery powered test instruments Digital offset and gain adjustment Battery operated/remote industrial controls Machine and motion control devices Wireless telephone and communication systems Arbitrary waveform generation Robotics
ORDERING INFORMATION
DEVICE WM2627CDT WM2627IDT TEMP. RANGE 0 to 70C -40 to 85C PACKAGE 16-pin TSSOP 16-pin TSSOP
BLOCK DIAGRAM
AVDD (16) DVDD (1) REFINAB (15) REFINCD (10) DAC A REFERENCE INPUT BUFFER X1 DAC OUTPUT BUFFER X2 (14) OUTA
TYPICAL PERFORMANCE
0.04
AVDD = DVDD = 5V, VREF = 2.048V, Slow Mode
0.03 Differential Non-Linearity (LSBs) 0.02 0.01 0 -0.01 -0.02 -0.03
WM2627
DIN (4) data FS (7) 16-BIT SHIFT REGISTER AND CONTROL LOGIC 10-BIT DATA AND CONTROL HOLDING LATCH
8-BIT DAC LATCH
SCLK (5) NCS (6)
2-BIT CONTROL LATCH
POWERDOWN/ SPEED CONTROL
DAC B
(13) OUTB
DAC C POWER-ON RESET DAC D
(12) OUTC
(11) OUTD
-0.04 0 32 64 96 128 DIGITAL CODE 160 192 224 256
(9) AGND
(8) DGND
(3) NLDAC
(2) NPD
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk www.wolfsonmicro.com
Production Data Datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics' Terms and Conditions.
2001 Wolfson Microelectronics Ltd.
WM2627
Production Data
PIN CONFIGURATION
DVDD NPD NLDAC DIN SCLK NCS FS DGND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 AVDD REFINAB OUTA OUTB OUTC OUTD REFINCD AGND
PIN DESCRIPTION
PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME DVDD NPD NLDAC DIN SCLK NCS FS DGND AGND REFINCD OUTD OUTC OUTB OUTA REFINAB AVDD TYPE Supply Digital input Digital input Digital input Digital input Digital input Digital input Ground Ground Analogue input Analogue output Analogue output Analogue output Analogue output Analogue input Supply Digital supply. Power down. Powers down all DACs overriding their individual power down settings and all output stages. This pin is active low. Load DAC. Digital input active low. NLDAC must be taken low to update the DAC latch from the holding latches. Serial data input. Serial clock input. Chip select. This pin is active low. Frame synchronisation for serial input data. Digital ground. Analogue ground. Voltage reference input for DACs C and D. DAC D output. DAC C output. DAC B output. DAC A output. Voltage reference input for DACs A and B. Analogue supply. DESCRIPTION
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Production Data
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION Supply voltages, AVDD to AGND, DVDD to DGND Supply voltage differences, AVDD to DVDD Digital input voltage Reference input voltage Operating temperature range, TA Storage temperature Soldering lead temperature, 1.6mm (1/16 inch) from package body for 10 seconds WM2627C WM2627I -2.8V -0.3V -0.3V 0C -40C -65C MIN MAX 7V 2.8V DVDD + 0.3V AVDD + 0.3V 70C 85C 150C 260C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage High-level digital input voltage Low-level digital input voltage Reference voltage to REFINAB, REFINCD Load resistance Load capacitance Serial clock rate Operating free-air temperature SYMBOL AVDD, DVDD VIH VIL VREF RL CL fSCLK TA WM2627CDT WM2627IDT 0 -40 DVDD = 2.7V to 5.5V DVDD = 2.7V to 5.5V See Note 0 2 10 100 20 70 85 TEST CONDITIONS MIN 2.7 2 0.8 AVDD - 1.5 TYP MAX 5.5 UNIT V V V V k pF MHz C C
Note: Reference voltages greater than AVDD/2 will cause output saturation for large DAC codes.
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Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions: RL = 10k, CL = 100pF. AVDD = DVDD = 5V 10%, VREF = 2.048V and AVDD = DVDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). PARAMETER Static DAC Specifications Resolution Integral non-linearity Differential non-linearity Zero code error Gain error Power supply rejection ratio Zero code error temperature coefficient Gain error temperature coefficient DAC Output Specifications Output voltage range Output load regulation Power Supplies Active supply current IDD No load, VIH = DVDD, VIL = 0V AVDD = 5V, VREF = 2.048V Slow AVDD = 5V, VREF = 2.048V Fast AVDD = 3V, VREF = 1.024V Slow AVDD = 3V, VREF = 1.024V Fast See Note 8 Power down supply current Dynamic DAC Specifications Slew rate Fast Slow See Note 9 To 0.1LSB Slow Fast See Note 10 Code 127 to 128 SNR fs = 400ksps, fOUT = 1kHz, BW = 20kHz See Note 11 fs = 400ksps, fOUT = 1kHz, BW = 20kHz See Note 11 fs = 400ksps, fOUT = 1kHz, BW = 20kHz See Note 11 fs = 400ksps, fOUT = 1kHz, BW = 20kHz See Note 11 1.0 5.0 V/s V/s No load, all digital inputs 0V or DVDD 1.4 3.5 1.0 3.0 2.2 5.5 1.5 4.5 mA RL = 10k 2k to 10k load See Note 7 0 0.1 AVDD-0.1 0.25 V % of FS voltage INL DNL ZCE GE PSRR See Note 1 See Note 2 See Note 3 See Note 4 See Note 5 See Note 6 See Note 6 -68 10 10 8 0.3 0.03 0.5 0.5 10 0.6 bits LSB LSB mV % FSR dB ppm/C ppm/C SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
1
A
Settling time
8.5 2.5 10 57
s s nV-s dB
Glitch energy Signal to noise ratio
Signal to noise and distortion ratio
SINAD
49
dB
Total harmonic distortion
THD
-50
dB
Spurious free dynamic range
SFDR
60
dB
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WM2627
Production Data
Test Conditions: RL = 10k, CL = 100pF. AVDD = DVDD = 5V 10%, VREF = 2.048V and AVDD = DVDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise). PARAMETER Reference Reference input resistance Reference input capacitance Reference feedthrough Reference input bandwidth RREFIN CREFIN VREF = 1VPP at 1kHz + 1.024V dc, DAC code 0 VREF = 0.2VPP + 1.024V dc DAC code 128 Slow Fast IIH IIL CI Input voltage = DVDD Input voltage = 0V 3 10 5 -75 M pF dB SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
0.5 1 1 1
MHz MHz A A pF
Digital Inputs High level input current Low level input current Input capacitance
Notes: 1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors). 2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. 3. Zero code error is the voltage output when the DAC input code is zero. 4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error. 5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. Zero code error and Gain error temperature coefficients are normalised to full scale voltage. 7. Output load regulation is the difference between the output voltage at full scale with a 10k load and 2k load. It is expressed as a percentage of the full scale output voltage with a 10k load. 8. IDD is measured while continuously writing code 512 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V supply current will increase. 9. Slew rate results are for the lower value of the rising and falling edge slew rates. 10. Settling time is the time taken for the signal to settle to within 0.1LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested. 11. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with a sampling frequency fs.
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WM2627
Production Data
SERIAL INTERFACE
tWL SCLK 1 tSUD DIN D15 tSUCSFS NCS tWHFS FS tSUFSCLK tSUC16FS tHD D14 D13 D12 D1 D0 2 tWH 3 4 5 15 16 tSUC16CS
Figure 1 Timing Diagram
Test Conditions: RL = 10k, CL = 100pF. AVDD = DVDD = 5V 10%, VREF = 2.048V and AVDD = DVDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) SYMBOL tSUCSFS tSUFSCLK tSUC16FS TEST CONDITIONS Setup time NCS low before negative FS edge. Setup time FS low before first negative SCLK edge. Setup time, sixteenth negative SCLK edge after FS low on which D0 is sampled before rising edge of FS. Setup time, sixteenth positive SCLK edge (first positive after D0 sampled) before NCS rising edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup time is between the FS rising edge and the NCS rising edge. Pulse duration, SCLK high. Pulse duration, SCLK low. Setup time, data ready before SCLK falling edge. Hold time, data held valid after SCLK falling edge. Pulse duration, FS high. MIN 10 8 10 10 TYP MAX UNIT ns ns ns ns
tSUC16CS
tWHCLK tWLCLK tSUDCLK tHDCLK tWHFS
25 25 8 5 20
ns ns ns ns ns
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Production Data
TYPICAL PERFORMANCE GRAPHS
0.2
AVDD = DVDD = 5V, VREF = 2.048V, Slow Mode
0.15 Integral Non-Linearity (LSBs) 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 0 32 64 96 128 DIGITAL CODE 160 192 224 256
Figure 2 Integral Non-Linearity
0.4
0.4
AVDD = DVDD = 3V, VREF = 1V, Input Code = 0
0.35
AVDD = DVDD = 5V, VREF = 2V, Input Code = 0
0.35
0.3 OUTPUT VOLTAGE - V
0.3
OUTPUT VOLTAGE - V
0.25
0.25
0.2
0.2
0.15
0.15
0.1
0.1
0.05
0.05
0
0 0 1 2 3 4 5 6 7 8
Slow
0
9
Fast
1
2
3
4
5 ISINK - mA
6
7
8
9
Slow Fast
10
10
ISINK - mA
Figure 3 Sink Current AVDD = DVDD = 3V
2.054
Figure 4 Sink Current AVDD = DVDD = 5V
4.092
AVDD = DVDD = 3V, VREF = 1V, Input Code = 1023
2.052 2.05 2.048
OUTPUT VOLTAGE - V 4.09 4.088 4.086 4.084 4.082 4.08 4.078 4.076
AVDD = DVDD = 5V, VREF = 2V, Input Code = 1023
OUTPUT VOLTAGE - V
2.046 2.044 2.042 2.04 2.038
4.074
2.036 2.034 2.032
0 1 2 3 4 5 6 7 8 9 10
4.072 4.07 0 1 2 3 4 5 ISOURCE - mA 6 7 8 Slow 9 10 Fast
ISOURCE - mA
Slow
Fast
Figure 5 Source Current AVDD = DVDD = 3V
Figure 6 Sink Current AVDD = DVDD = 5V
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WM2627
Production Data
DEVICE DESCRIPTION
GENERAL FUNCTION
The device uses a resistor string network buffered with an op amp to convert 8-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship:
= 2 VREFIN V out
(
) CODE
256
INPUT 1111 : 1000 0001 1111
OUTPUT
2 VREF
( ) 255
256
:
2 VREF
( ) 129
128 256
256 = VREF
1000
0000
2 VREF
()
0111 : 0000 0000
1111
2 VREF
( ) 127
:
256 1 256
0001 0000
2 VREF
()
0V
Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC registers to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2k load with a 100pF load capacitance.
EXTERNAL REFERENCE
The reference voltage input is buffered which makes the DAC input resistance independent of code. REFINAB and REFINCD pins have an input resistance of 10M and an input capacitance of typically 5pF. The reference voltage determines the DAC full-scale output.
HARDWARE CONFIGURATION OPTIONS
DEVICE POWER DOWN
The device can be powered-down by pulling pin NPD (Pin 2) high. This powers down all DACs overriding their individual power down settings. This will reduce power consumption to typically 10nA. When the power down function is released the device reverts to the DAC code set prior to power down.
SIMULTANEOUS DAC UPDATE
The NLDAC pin (Pin 3) can be held high to prevent serial word writes from updating the DAC latches. By writing new values to multiple DACs then pulling NLDAC low, all new DAC codes are loaded into the DAC latches simultaneously.
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WM2627
Production Data
SERIAL INTERFACE
To start transferring data, the device first has to be enabled with NCS set to low. Then, a falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred, the next rising edge on SCLK or FS causes the content of the shift register to be moved to the DAC holding latch. If NLDAC is low, the DAC latch will also be updated immediately. The serial interface of the device can be used in two basic modes: * * four wire (with chip select) three wire (without chip select)
Using chip select (four wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). If there is no need to have more than one device on the serial bus, then NCS can be tied low.
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the device timing. The maximum serial rate is: fSCLKmax =
1 = 20MHz tWCH min+ tWCL min
The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC settling time to 8 bits limits the update rate for large input step transitions.
SOFTWARE CONFIGURATION OPTIONS
The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D2 contains the 8-bit data word. D15-D12 hold the programmable options. D15 D14 D13 D12 D11 D10 A1 A0 PWR SPD Table 2 Register Map D9 D8 D7 D6 D5 D4 D3 0 D2 0 D1 0 D0 0
New DAC value (8 bits)
DAC ADDRESSING
A particular DAC (A, B, C, D) within the device is selected by A1 and A0 within the input word. A1 0 0 1 1 A0 0 1 0 1 DAC ADDRESS DAC A DAC B DAC C DAC D
PROGRAMMABLE SETTLING TIME (SPD - BIT D12)
Settling time is a software selectable 2.5s or 8.5s, typical to within 0.1LSB of final value. This is controlled by the value of SPD - Bit D12 and an associated DAC address. A ONE defines a settling time of 2.5s, a ZERO defines a settling time of 8.5s for that DAC.
PROGRAMMABLE POWER DOWN
The power down function is controlled by PWR - Bit D13 and an associated DAC address. A ZERO configures that DAC as active, a ONE configures that DAC into power down mode.
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WM2627
Production Data
APPLICATIONS INFORMATION
LINEARITY, OFFSET, AND GAIN ERROR
Amplifiers operating from a single supply can have positive or negative voltage offsets. With a positive offset, the output voltage changes on the first code transition. However, if the offset is negative, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. This is because with the most negative supply rail being ground, any attempt to drive the output amplifier below ground will clamp the output at 0 V. The output voltage then remains at zero until the input code is sufficiently high to overcome the negative offset voltage, resulting in the transfer function shown in Figure 7.
Output Voltage 0V Negative Offset DAC code
Figure 7 Effect of Negative Offset This offset error, not the linearity error, produces the breakpoint. The transfer function would follow the dotted line if the output buffer could drive below the ground rail. DAC linearity is measured between zero-input code (all input bits at 0) and full-scale code (all inputs at 1), disregarding offset and full-scale errors. However, due to the breakpoint in the transfer function, single supply operation does not allow for adjustment when the offset is negative. In such cases, the linearity is therefore measured between full-scale and the lowest code that produces a positive (nonzero) output voltage.
POWER SUPPLY DECOUPLING AND GROUNDING
Printed circuit boards with separate analogue and digital ground planes deliver the best system performance. The two ground planes should be connected together at the low impedance power supply source. Ground currents should be managed so as to minimise voltage drops across the ground planes. A 0.1F decoupling capacitor should be connected between the positive supply and ground pins of the DAC, with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analogue supply from the digital supply.
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WM2627
Production Data
PACKAGE DIMENSIONS
DT: 16 PIN TSSOP (5.0 x 4.4 x 1.0 mm) DM013.B
b
16
e
9
E1
E
GAUGE PLANE 1 8
D 0.25 c A A2 A1 -C0.1 C
SEATING PLANE
L
Symbols A A1 A2 b c D e E E1 L REF: MIN ----0.05 0.80 0.19 0.09 4.90
4.30 0.45 0o
Dimensions (mm) NOM --------1.00 --------5.00 0.65 BSC 6.4 BSC 4.40 0.60 ----JEDEC.95, MO-153
MAX 1.20 0.15 1.05 0.30 0.20 5.10
4.50 0.75 8o
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AB. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001 11

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