View UT62L6416MC-70LLE_1333056.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

UTRON
Preliminary Rev. 0.1
64K X 16 BIT LOW POWER CMOS SRAM GENERAL DESCRIPTION
The UT62L6416 is a 1,048,576-bit low power CMOS static random access memory organized as 65,536 words by 16 bits. The UT62L6416 operates from a single 2.7V ~ 3.6V power supply and all inputs and outputs are fully TTL compatible. The UT62L6416 is design for upper and low byte access by data byte control( UB LB ).
UT62L6416
FEATURES
Fast access time : 55ns(max) for Vcc=3.0V~3.6V 70/100ns(max) for Vcc=2.7V~3.6V CMOS Low operating power Operating current: 45/35/25mA (Icc max) Standby current: 20 uA(TYP.) L-version 3 uA(TYP.) LL-version Single 2.7V~3.6V power supply Operating temperature: Commercial : 0~70 Extended : -20~80 All inputs and outputs TTL compatible Fully static operation Three state outputs Data retention voltage: 1.5V (min) Data byte control : LB (I/O1~I/O8) UB (I/O9~I/O16) Package : 44-pin 400mil TSOP 48-pin 6mm x 8mm TFBGA
PIN DESCRIPTION
SYMBOL A0 - A15 I/O1 - I/O16 CE
WE OE LB UB VCC VSS NC
VCC VSS
DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Lower-Byte Control High-Byte Control Power Supply Ground No Connection
FUNCTIONAL BLOCK DIAGRAM
A0 A1 A2 A3 A4 A8 A12 A13 A14 A15 I/O1 I/O16
I/O ROW DECODER
.
MEMORY ARRAY
. .
1024 Rows x 64 Columns x 16 bits
. . .
. . .
CONTROL
. . .
.
.
.
COLUMN I/O
CE WE
OE
COLUMN DECODER LOGIC CONTROL
LB
UB
A11 A10
A9
A7 A6 A5
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80073
1
UTRON
Preliminary Rev. 0.1
64K X 16 BIT LOW POWER CMOS SRAM
UT62L6416
PIN CONFIGURATION
A4 A3 A2 A1 A0 A5 A6 A7 OE
UB
1 2 3 4 5 6
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A B C D E F G H
LB I/O9
I/O10
OE UB
I/O11 I/O12 I/O13
A0 A3 A5 NC NC A14 A12 A9
A1 A4 A6 A7 NC A15 A13 A10
A2 CE I/O2 I/O4 I/O5 I/O6
NC I/O1 I/O3 Vcc Vss I/O7 I/O8 NC
CE
I/O1 I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8
WE
LB
I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC
UT62L6416
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Vss Vcc
I/O15 I/O16
I/O14
NC A8
WE
A11
NC
A15 A14 A13 A12 NC
1
2
3
4
5
6
TFBGA
TSOP II
TRUTH TABLE
MODE Standby Output Disable Read
CE
OE X X H H L L L X X X
WE
LB
UB X H X L H L L H L L
Write
H X L L L L L L L L
X X H H H H H L L L
X H L X L H L L H L
SUPPLY CURRENT I/O OPERATION I/O1-I/O8 I/O9-I/O16 High - Z High - Z ISB, ISB1 High - Z High - Z ISB, ISB1 High - Z High - Z ICC,ICC1,ICC2 High - Z High - Z DOUT High - Z ICC,ICC1,ICC2 High - Z DOUT DOUT DOUT DIN High - Z ICC,ICC1,ICC2 High - Z DIN DIN DIN
Note:
H = VIH, L=VIL, X = Don't care.
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80073
2
UTRON
Preliminary Rev. 1.0
64K X 16 BIT LOW POWER CMOS SRAM
UT62L6416
ABSOLUTE MAXIMUM RATINGS*
PARAMETER Terminal Voltage with Respect to VSS Operating Temperature Commercial Extended Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 secs) SYMBOL VTERM TA TA TSTG PD IOUT Tsolder RATING -0.5 to 4.6 0 to 70 -20 to 80 -65 to +150 1 50 260 UNIT V W mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V, TA = 0 to 70 / -20 to 80(E))
PARAMETER MIN. TYP. MAX. SYMBOL TEST CONDITION Power Voltage VCC 2.7 3.0 3.6 Input High Voltage VIH 2.2 VCC+0.3 Input Low Voltage VIL -0.2 0.6 Input Leakage Current ILI -1 1 VSS VIN VCC Output Leakage Current ILO -1 1 VSS VI/O VCC; Output Disabled Output High Voltage VOH IOH= -1mA 2.2 Output Low Voltage VOL IOL= 2 mA 0.4 Operating Power ICC Cycle time=min, 100%duty, 55 30 45 Supply Current 70 25 35 I/O=0mA, CE =VIL ; 100 20 25 Average Operation Icc1 4 5 Cycle time=1s,100%duty,I/O=0mA, Current CE 0.2V,other pins at 0.2V or Vcc-0.2V, Icc2 Standby Current (TTL) Standby Current (CMOS) ISB ISB1
Cycle time=500ns,100%duty,I/O=0mA, -
UNIT V V V A A V V mA mA mA mA mA mA A A
8 0.3 20 3
10 0.5 80 25
CE 0.2V,other pins at 0.2V or Vcc-0.2V, 1. CE =VIH, other pins =VIL or VIH, 2. UB = LB = VIH, other pins =VIL or VIH, -L 1. CE =VCC-0.2V, other pins at 0.2V or Vcc-0.2V, -LL 2. UB = LB =VCC-0.2V, other pins at 0.2V or Vcc-0.2V,
-
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80073
3
UTRON
Preliminary Rev. 1.0
64K X 16 BIT LOW POWER CMOS SRAM
UT62L6416
CAPACITANCE (TA=25, f=1.0MHz)
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN.
-
MAX 6 8
UNIT pF pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 5ns 1.5V CL = 30pF, IOH/IOL = -1mA / 2mA
AC ELECTRICAL CHARACTERISTICS (VCC =2.7V~3.6V, TA =0 to 70 / -20 to 80(E))
(1) READ CYCLE
PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change
LB , UB Access Time LB , UB to High-Z Output LB , UB to Low-Z Output
SYMBOL
UT62L6416-55
UT62L6416-70
UT62L6416-100 UNIT
tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH tBA tBHZ tBLZ
MIN. 55 10 5 5 0
MAX. 55 55 30 20 20 55 25 -
MIN. 70 10 5 5 0
MAX. 70 70 35 25 25 70 30 -
MIN. 100 10 5 5 0
MAX. 100 100 50 30 30 100 40 -
ns ns ns ns ns ns ns ns ns ns ns ns
(2) WRITE CYCLE
PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High Z SYMBOL UT62L6416-55 UT62L6416-70 UT62L6416-100 UNIT
LB , UB Valid to End of Write *These parameters are guaranteed by device characterization, but not production tested. *55ns for Vcc=3.0V~3.6V
tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* tBW
MIN. 55 50 50 0 45 0 25 0 5 45
MAX. 30 -
MIN. 70 60 60 0 55 0 30 0 5 60
MAX. 30 -
MIN. 100 80 80 0 70 0 40 0 5 80
MAX. 40 -
ns ns ns ns ns ns ns ns ns ns ns
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80073
4
UTRON
Preliminary Rev. 1.0
64K X 16 BIT LOW POWER CMOS SRAM
UT62L6416
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled)
(1,2,4)
tRC
Address
tAA tOH tOH
DOUT
Data Valid
READ CYCLE 2 ( CE and OE Controlled) (1,3,5,6)
t
Address
RC
CE
t AA t ACE t OE t OLZ t
BLZ
t
CHZ
OE
t
BA
OHZ
LB , UB
t t
CLZ
t
OH
t
BHZ
Dout
HIGH-Z Data Valid
HIGH-Z
Notes : 1.
WE is HIGH for read cycle.
2. Device is continuously selected CE =VIL. 3. Address must be valid prior to or coincident with CE transition; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. tCLZ, tOLZ, tCHZ , tOHZ, tBHZ and tBLZ are specified with CL = 5pF. Transition is measured 500mV from steady state. 6. At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ. , tBHZ is less than tBLZ.
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80073
5
UTRON
Preliminary Rev. 1.0 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5)
64K X 16 BIT LOW POWER CMOS SRAM
UT62L6416
t
WC
Address
t
AW
CE t WE
t
AS
CW
t t
WP
WR
LB , UB
t
WHZ
t
BW
t
High-Z
OW
Dout Din
WRITE CYCLE 2 ( CE Controlled) (1,2,5)
(4)
(4)
t
DW
t
Data Valid
DH
t Address t CE WE t
AS AW
WC
t t
CW
t
WR
WP
LB , UB t Dout
WHZ
t
BW
High-Z
t Din
Notes : 1.
DW
t
DH
Data Valid
WE or CE must be HIGH during all address transitions.
2. A write occurs during the overlap of of CE low , WE low , LB and/or UB low.. 3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the bus. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after WE LOW transition, the outputs remain in a high impedance state. 6. tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80073
6
UTRON
Preliminary Rev. 1.0
64K X 16 BIT LOW POWER CMOS SRAM
UT62L6416
DATA RETENTION CHARACTERISTICS (TA = 0 to 70 / -20 to 80(E))
PARAMETER Vcc for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time SYMBOL VDR IDR tCDR tR TEST CONDITION CE VCC-0.2V Vcc=1.5V CE VCC-0.2V See Data Retention Waveforms (below) MIN. 1.5 -L - LL 0 5 TYP. 1 0.5 MAX. 3.6 50 20 UNIT V A A ms ms
DATA RETENTION WAVEFORM
Data Retention Mode
VCC
2.7V VDR 1.5V
CE
2.7V tCDR tR
VSS
CE
VCC -0.2V
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80073
7
UTRON
Preliminary Rev. 1.0
64K X 16 BIT LOW POWER CMOS SRAM
UT62L6416
PACKAGE OUTLINE DIMENSION
44 pin 400mil TSOP- PACKAGE OUTLINE DIMENSION
SYMBOLS A A1 A2 b c D E E1 e L 2D y
DIMENSIONS IN MILLMETERS MIN NOM MAX. 1.00 1.20 0.05 0.15 0.95 1.00 1.05 0.30 0.35 0.45 0.12 0.21 18.313 18.415 18.517 11.854 11.836 11.838 10.058 10.180 10.282 0.800 0.40 0.50 0.60 0.805 0.00 0.076 o o 0 5
DIMENSIONS IN INCHS MIN. NOM. MAX. 0.039 0.047 0.002 0.006 0.037 0.039 0.041 0.012 0.014 0.018 0.0047 0.083 0.721 0.725 0.728 0.460 0.466 0.470 0.398 0.400 0.404 0.0315 0.0157 0.020 0.0236 0.0317 0.000 0.003 o o 0 5
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80073
8
UTRON
Preliminary Rev. 1.0
64K X 16 BIT LOW POWER CMOS SRAM
UT62L6416
48 pin 6mmx8mm TFBGA PACKAGE OUTLINE DIMENSION
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80073
9
UTRON
Preliminary Rev. 1.0
64K X 16 BIT LOW POWER CMOS SRAM
UT62L6416
ORDERING INFORMATION
COMMERCIAL TEMPERATURE PART NO. UT62L6416MC-55L UT62L6416MC-55LL UT62L6416MC-70L UT62L6416MC-70LL UT62L6416BS-55L UT62L6416BS-55LL UT62L6416BS-70L UT62L6416BS-70LL EXTENDED TEMPERATURE PART NO. UT62L6416MC-55LE UT62L6416MC-55LLE UT62L6416MC-70LE UT62L6416MC-70LLE UT62L6416BS-55LE UT62L6416BS-55LLE UT62L6416BS-70LE UT62L6416BS-70LLE ACCESS TIME (ns) 55 55 70 70 55 55 70 70 STANDBY CURRENT (A) TYP. 20 3 20 3 20 3 20 3 PACKAGE 44 PIN TSOP- 44 PIN TSOP- 44 PIN TSOP- 44 PIN TSOP- 48 PIN TFBGA 48 PIN TFBGA 48 PIN TFBGA 48 PIN TFBGA
ACCESS TIME (ns) 55 55 70 70 55 55 70 70
STANDBY CURRENT (A) TYP. 20 3 20 3 20 3 20 3
PACKAGE 44 PIN TSOP- 44 PIN TSOP- 44 PIN TSOP- 44 PIN TSOP- 48 PIN TFBGA 48 PIN TFBGA 48 PIN TFBGA 48 PIN TFBGA
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80073
10
UTRON
Preliminary Rev. 1.0
64K X 16 BIT LOW POWER CMOS SRAM
UT62L6416
REVISION HISTORY
REVISION Preliminary Rev. 0.1 DESCRIPTION Original. DATE Sep 5, 2001
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80073
11

▲Up To Search▲

Price & Availability of UT62L6416MC-70LLE

	To Download UT62L6416MC-70LLE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .