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WIRELESS COMMUNICATIONS DIVISION
TQ3131
C2
Control Logic C2
L1
DATA SHEET
VDD
GND
GND
3V Cellular Band CDMA/AMPS LNA IC
RF IN
RF 50 ohm OUT RF Out Control Logic
GND
C3
Features
Small size: SOT23-8 Single 3V operation Low-current operation
Product Description
The TQ3131 is a 3V, RF LNA IC designed specifically for Cellular band CDMA/AMPS applications. It's RF performance meets the requirements of products designed to the IS-95 and AMPS standards. The TQ3131 is designed to be used with the TQ5131 (CDMA/AMPS mixer) which provides a complete CDMA receiver for 800MHz dual-mode phones. The LNA incorporates on-chip switches which determine CDMA, AMPS, and bypass mode select. When used with the TQ5131 (CDMA RFA/mixer), four gain states are available. The RF output port is internally matched to 50 , greatly simplifying the design and keeping the number of external components to a minimum. The TQ3131 achieves good RF performance with low current consumption, supporting long standby times in portable applications. Coupled with the very small SOT23-8 package, the part is ideally suited for Cellular band mobile phones. Electrical Specifications1
Parameter Frequency Gain Noise Figure Input 3rd Order Intercept DC supply Current Min 832 13.0 1.4 10.0 10.5 Typ Max 894 Units MHz dB dB dBm mA
Gain Select Mode Select High IP3 performance Few external components
Applications
IS-95 CDMA Mobile Phones AMPS Mobile Phones Dual Mode CDMA Cellular applications 832-870MHz CDMA applications
Note 1: Test Conditions: Vdd=2.8V, Tc=25C, RF frequency=881MHz, CDMA High Gain state.
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TQ3131 Data Sheet
Electrical Characteristics
Parameter RF Frequency Conditions Min. 832 Typ/Nom 881 Max. 894 Units MHz
CDMA Mode-High Gain
Gain Noise Figure Input IP3 LNA IN Return Loss (with external matching) LNA OUT Return Loss Supply Current 8.0 10 10 10.5 13.5 11.5 13.0 1.4 10.0 2.0 dB dB dBm dB dB mA
Bypass Mode
Gain Noise Figure Input IP3 LNA IN Return Loss (with external matching) LNA OUT Return Loss Supply Current 18.0 10 10 1.2 2.5 -3.0 -2.0 2.0 30.0 3.0 dB dB dBm dB dB mA
AMPS Mode
Gain Noise Figure Input IP3 LNA IN Return Loss (with external matching) LNA OUT Return Loss Supply Current Supply Voltage
Note 1: Test Conditions: Vdd=2.8V, RF=881MHz, TC = 25 C, unless otherwise specified. Note 2: Min/Max limits are at +25C case temperature, unless otherwise specified.
8.5 2.0 10 10
11.0 1.6 3.0 2.2
dB dB dBm dB dB
4.0 2.7 2.8
5.5 3.3
mA V
Absolute Maximum Ratings
Parameter DC Power Supply Power Dissipation Operating Temperature Storage Temperature Signal level on inputs/outputs Voltage to any non supply pin Value 5.0 500 -40 to 85 -60 to 150 +20 +0.3 Units V mW C C dBm V
2
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TQ3131 Data Sheet
Typical Performance
Test Conditions, unless Otherwise Specified: Vdd=2.8V, Tc=+25C, RF=881MHz CDMA High Gain Mode Gain v Freq v Temp 15.0 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 850 860 870 880 890 Frequency (MHz) 13.50 13.00 12.50 12.00 11.50 11.00 10.50 10.00 9.50 9.00 2.5 2.7 2.9 Vdd (V) 3.1 CDMA High Gain Mode Idd v Vdd v Temp
Gain (dB)
Idd (mA)
-30C +25C +85C
-30C +25C +85C
900
910
3.3
CDMA High Gain Mode IIP3 v Freq v Temp 13.5 13.0 IIP3 (dBm) 12.5 12.0 11.5 11.0 850 860 870 880 890 Frequency (MHz) 900 910
-30C +25C +85C
AMPS Mode Gain v Freq v Temp 13.0 12.5 12.0 Gain (dB) 11.5 11.0 10.5 10.0 9.5 9.0 850 860 870 880 890 900 910 Frequency (MHz)
-30C +25C +85C
CDMA High Gain Mode Noise Figure v Freq v Temp 1.90 Noise Figure (dB) 1.70 IIP3 (dBm) 1.50 1.30 1.10 0.90 0.70 0.50 850 860 870 880 890 900 910 Frequency (MHz)
-30C +25C +85C
AMPS Mode IIP3 v Freq v Temp 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 850 860 870 880 890 900 910 Frequency (MHz)
-30C +25C +85C
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3
TQ3131 Data Sheet
AMPS Mode Noise Figure v Freq v Temp 2.50 Noise Figure (dB) 2.00 1.50 1.00 0.50 0.00 850 860 870 880 890 Frequency (MHz)
AMPS Mode Idd v Vdd v Temp 5.50
-30C +25C +85C
BYPASS Mode Gain v Freq v Temp -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -2.2 -2.4 -2.6 -2.8 -3.0 850 860 870 880 890 Frequency (MHz) BYPASS Mode Noise Figure v Freq v Temp 2.50 2.00 1.50 1.00
-30C
Gain (dB)
-30C +25C +85C 900 910
900
910
Idd (mA)
4.50 4.00
-30C
Noise Figure (dB)
5.00
3.50 3.00 2.5 2.7 2.9 Vdd (V) 3.1
+25C +85C
0.50 0.00 850 860 870 880 890
+25C +85C
3.3
900
910
Frequency (MHz)
BYPASS Mode Idd v Vdd v Temp 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 2.5 2.7 2.9 Vdd (V) 3.1
BYPASS Mode IIP3 v Freq v Temp 35.0 34.0 33.0 IIP3 (dBm) 32.0 31.0 30.0 29.0 28.0 27.0 850 860 870 880 890 900 910 Frequency (MHz)
-30C +25C +85C
Idd (mA)
-30C +25C +85C
3.3
4
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TQ3131 Data Sheet
Application/Test Circuit
Vdd R1 Control Logic
C2 Vdd
C2
GND
(paddle)
GND
LNA input C1
L1
RF in
RF out C3
LNA output Control Logic
Lbrd
LNA GND
Bill of Material for TQ3131 LNA Application/Test Circuit
Component Receiver IC Capacitor Capacitor Resistor Inductor Inductor Reference Designator U1 C1 C2 R1 L1 Lbrd Part Number TQ3131 3.3pFd 8.2pF 3.3 15nH See application note Value Size SOT23-8 0402 0402 0402 0402 Manufacturer TriQuint Semiconductor
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5
TQ3131 Data Sheet
TQ3131 Product Description
The TQ3131 LNA uses a cascode low noise amplifier, along with signal path switching. A bias control circuit sets the quiescent current for each mode and ensures peak performance over process and temperature, (refer to Figure 1). In the application, CMOS level signals are applied to pins 1 and 5 and are decoded by internal logic in order to set the device to the desired mode. (see Table 1 for logic control states) In the high gain mode, switches S1, S2, and S5 are closed, with switches S3 and S4 open. In the bypass mode, switches S1, S2, and S5 are open, with switches S3 and S4 closed. Having five switches ensures that there are no parasitic feedback paths for the signal. In the AMPS mode, control logic switches the LNA into a low current bias condition. Only three external components are needed in an application. The chip uses an external cap and inductor for the input match to pin 3. The output is internally matched to 50 ohms at pin 6. A Vdd bypass cap is required close to pin 8. External degeneration of the cascode is required between pin 4 and ground. However, a small amount of pc board trace can be used as the inductor (Lbrd). Alternatively, if an extra component can be tolerated, a small value chip inductor can be used. (see Figure 2)
VDD
Operation
MODE High Gain C2 0 1 AMPS Bypass 0 1 C3 0 0 1 1 11(dB) -2(dB) Typical Gain 13(dB)
Table 1 LNA States and Control Bits
LNA Input Network Design
Input network design for most LNA's is a straightforward compromise between noise figure and gain. The TQ3131 is no exception, even though it has 3 different modes. The device was designed so that one only needs to optimize the input match in the high gain mode. As long as the proper grounding and source inductance are used, the other two modes will perform well with the same match. It is probably wise to synthesize the matching network component values for some intermediate range of Gamma values, and then by experimentation, find the one which provides the best compromise between noise figure and gain. The quality of the chip ground will have some effect on the match, which is why some experimentation will likely be needed. The input match will affect the output match to some degree, so S22 should be monitored. The values used on our evaluation board may be used as a starting point.
VDD
R1 8
C2
1
C2
Bias and Switch Control Logic
C2 2
GND
S6
7
GND
Noise Parameter Analysis
6 LNA OUT
S2
LNA IN
L1
3
RFIN
S1
RF OUT
S3 S5 S4
C1 4 Lbrd
LNA GND
5
C3
C3
A noise parameter analysis is shown on the next page for both the high gain and AMPS modes. A "nominal" device was mounted directly on a solid copper ground plane with semi-rigid probes attached to the device input and output pins. A value of Lbrd was chosen so that 13.0dB of gain was attained at conjugate match. Then the tuner was removed and noise data was taken. Please note that although data was taken at 700MHz and 1000MHz, the device was designed to operate satisfactorily only over a much more limited range.
Figure 1 TQ3131 Simplified Schematic
6
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TQ3131 Data Sheet
Gamma Opt analysis for TQ3131 High Gain Mode
Freq (MHz) 700 880 1000 Opt 0.53 0.53 0.48 Angle 43.3 52.4 58.5 Fmin (dB) R noise 18.5 16.5 15.4
0.90 0.92 1.01
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7
TQ3131 Data Sheet
Gamma Opt analysis for TQ3131 Amps Mode
Freq (MHz) 700 880 1000 Opt 0.61 0.70 0.56 Angle 40.6 54.2 56.6 Fmin (dB) 1.22 1.09 1.42 R noise 33.0 27.4 27.0
Figure 2 shows how a spiral pc board trace can be used as the external inductance. It is suggested that such a circuit be used for the initial design prototype. Then the optimum inductance can be found by simply solder bridging across the inductor. The final pc board design can then include the proper shorted version of the inductor.
Gain Control via Pin 4 Inductance
The source connection of the LNA cascode is brought out separately through pin 4. That allows the designer to make some range of gain adjustment. The total amount of inductance present at the source of the cascode is equal to the bond wire plus package plus external inductance. One should generally use an external inductance such that gain in the high gain CDMA mode = 13.0. Although it is possible to increase the gain of the TQ3131 by using little or no degeneration, input intercept will be degraded.
Figure 2 Showing Lbrd and Grounding on Evaluation Board
8
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TQ3131 Data Sheet
Selection of the Vdd Bypass Cap for Optimum Performance
The Vdd bypass capacitor has the largest effect on the LNA output match, and is required for proper operation. Because the input match affects the output match to some degree as well, the process of picking the bypass cap value involves some iteration. First, an input match is selected which gives adequate gain and noise figure. Then the bypass capacitor is varied to give the best output match. Generally, the poorer the chip grounding, the smaller the bypass capacitor value will be. The demo board achieves 11-12dB of return loss which is adequate for connection directly to the input of a SAW filter. Symptoms of a poor ground include reduced gain and the inability to achieve >2:1 VSWR at the output when the input is matched. It is recommended to use multiple vias to a mid ground plane layer. The vias at pins 2 and 7 to this layer should be as close to the lead pads as possible Additionally, the ground return on the Vdd bypass cap should provide minimal inductance back to chip pins 2 and 7.
TQ3131 S-Parameters
Following are S-Parameter graphs for both the high gain and the AMPS modes. Data was taken on a single "nominal" device at 2.8v Vdd. The reference planes were set at the end of the package pins. Note that the plots are almost identical for both modes.
Grounding
An optimal ground for the device is important in order to achieve datasheet specified performance.
TQ3131 High Gain Mode S-Parameters
S11
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9
TQ3131 Data Sheet
S12
S21
10
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TQ3131 Data Sheet
S22
TQ3131 Amps Mode S-Parameters
S11
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11
TQ3131 Data Sheet
S12
S21
12
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TQ3131 Data Sheet
S22
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TQ3131 Data Sheet
C2
Control Logic C2
L1
VDD
GND
GND
RF IN
RF 50 ohm OUT RF Out Control Logic
GND
C3
Package Pinout
Pin Descriptions
Pin Name C2 GND RF IN LNA GND C3 RF OUT LNA GND Vdd Pin # 1 2 3 4 5 6 7 8 Description and Usage Control logic 2 Ground, paddle RF input, off-chip matching required Ground Control logic 3 RF output, no matching required Ground LNA Vdd, typical 2.8V, C2 capacitor required
14
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TQ3131 Data Sheet
Package Type: SOT23-8 Plastic Package
Note 1
PIN 1 FUSED LEAD
b A c
E E1
Note 2
DIE
e
A1
L
DESIGNATION A A1 b c D e E E1 L Theta
DESCRIPTION OVERALL HEIGHT STANDOFF LEAD WIDTH LEAD THICKNESS PACKAGE LENGTH LEAD PITCH LEAD TIP SPAN PACKAGE WIDTH FOOT LENGTH FOOT ANGLE
METRIC 1.20 +/-.25 mm .100 +/-.05 mm .365 mm TYP .127 mm TYP 2.90 +/-.10 mm .65 mm TYP 2.80 +/-.20 mm 1.60 +/-.10 mm .45 +/-.10 mm 1.5 +/-1.5 DEG
ENGLISH 0.05 +/-.250 in .004 +/-.002 in .014 in .005 in .114 +/-.004 in .026 in .110 +/-.008 in .063 +/-.004 in .018 +/-.004 in 1.5 +/-1.5 DEG
NOTE 3 3 3 3 1,3 3 3 2,3 3
Notes 1. The package length dimension includes allowance for mold mismatch and flashing. 2. The package width dimension includes allowance for mold mismatch and flashing. 3. Primary dimensions are in metric millimeters. The English equivalents are calculated and subject to rounding error.
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TQ3131 Data Sheet
Additional Information
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: info_wireless@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900
For technical questions and additional information on specific applications: Email: info_wireless@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright (c) 1998 TriQuint Semiconductor, Inc. All rights reserved. Revision A, January, 2000
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