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| SPICE Device Model SUM110N08-05 Vishay Siliconix N-Channel 75-V (D-S) 200C MOSFET CHARACTERISTICS * N-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70511 09-Jun-04 www.vishay.com 1 SPICE Device Model SUM110N08-05 Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Simulated Data Measured Data Unit Static Gate Threshold Voltage On-State Drain Currenta Drain-Source On-State Resistancea VGS(th) ID(on) VDS = VGS, ID = 250 A VDS > 5 V, VGS = 10 V VGS = 10 V, ID = 30 A rDS(on) VGS = 10 V, ID = 30 A, TJ = 125C VGS = 10 V, ID = 30 A, TJ = 200C Forward Transconductancea Forward Voltage a gfs VSD VDS = 15 V, ID = 30 A IS = 110 A, VGS = 0 V 3.1 1197 0.0038 0.0063 0.0084 109 0.92 1 S V 0.0038 V A Dynamic b Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Chargec Gate-Source Charge Gate-Drain Charge c c Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf trr IF = 85 A, di/dt = 100 A/s VDD = 35 V, RL = 0.40 ID 110 A, VGEN = 10 V, RG = 2.5 VDS = 35 V, VGS = 10 V, ID = 110 A VGS = 0 V, VDS = 25 V, f = 1 MHz 7663 936 406 139 36 45 88 110 130 149 55 7900 950 550 145 30 45 25 200 65 165 80 Ns NC Pf Turn-On Delay Time c Rise Time c Turn-Off Delay Time c Fall Time c Reverse Recovery Time Notes: a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. c. Independent of operating temperature. www.vishay.com 2 Document Number: 70511 09-Jun-04 SPICE Device Model SUM110N08-05 Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 70511 09-Jun-04 www.vishay.com 3 SPICE Device Model SUM110N08-05 Vishay Siliconix www.vishay.com 4 Document Number: 70511 09-Jun-04 |
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