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SP9500 12-Bit, Voltage Output D/A Converter
s s s s Low Power - 1.1mW Voltage Output, 0.5V to 4.5V Range Single +5 Volt Supply 1.4 MHz Multiplying Bandwidth (2-Quadrant) s Standard 3-Wire Serial Interface s 8-pin (0.15") SOIC and Plastic DIP Packages
DESCRIPTION... The SP9500 is a low power 12-Bit Digital-to-Analog Converter. It features 0.5 to 4.5V output swing when using +5volt supply. The converter uses a standard 3-wire serial interface compatible with SPITM, QSPITM and MicrowireTM. The output settling-time is specified at 7.5s. The SP9500 is available in 8-pin 0.15" SOIC and DIP packages, specified over commercial and industrial temperature ranges.
VREF DAC REGISTER LATCH DAC
+ -
VOUT
AGND SHIFT REGISTER
CS DIN SCLK
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
(c) Copyright 2000 Sipex Corporation
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. VDD - DGND .................................................................. -0.3V,+6.0V VREF ................................................................................ DGND, VDD AGND .......................................................................... DGND, V REF DIN .................................................................................. DGND, VDD Power Dissipation Plastic DIP .......................................................................... 375mW (derate 7mW/C above +70C) Small Outline ...................................................................... 375mW (derate 7mW/C above +70C)
SPECIFICATIONS
(Typical at 25C; TMIN TA TMAX; VDD = +5V, DGND = 0V, VREF = +3.5V; AGND = +1.5V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER DIGITAL INPUTS Logic Levels VIH VIL 2 Quad, Input Coding REFERENCE INPUTS VREF Voltage Range AGND Voltage Range Input Resistance ANALOG OUTPUT Gain -B, -K -A, -J Initial Offset Bipolar Voltage Range Output Current STATIC PERFORMANCE Resolution Integral Linearity -B, -K -A, -J Differential Linearity -B, -K -A, -J Monotonicity DYNAMIC PERFORMANCE Settling Time Small Signal Full Scale Slew Rate Multiplying Bandwidth STABILITY Gain Scale Zero
MIN.
TYP.
MAX.
UNITS
CONDITIONS
2.4 0.8 Binary
Volts Volts Note 5
0.5 0.5 11
4.5 4.5 13.9
Volts Volts k
DIN = 1365; code dependent
0.5 1.0 1.0 0.25 0.5 1.0
2.0 4.0 5.0 3.0 4.5
LSB LSB LSB LSB Volts mA
Note 3 Note 3 VREF = 4.5V; AGND = 0.5V DIN = 0
12 0.25 0.5 0.5 0.5 1.0
Bits LSB LSB LSB LSB LSB Note 3 Note 3 VREF = 4.5V; AGND = 0.5V
0.25 0.75 0.25 1.0 Guaranteed
1 7.5 0.6 1.4 15 15
s s V/s MHz ppm/C ppm/C
to 0.012% to 0.012%, VOUT = 0.5 to 4.5V
tMIN to tMAX tMIN to tMAX
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
(c) Copyright 2000 Sipex Corporation
2
SPECIFICATIONS (continued)
(Typical at 25C; TMIN TA TMAX; VDD = +5V, DGND = 0V, VREF = +3.5V; AGND = +1.5V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)
PARAMETER POWER REQUIREMENTS VDD -J, -K -A, -B Power Dissipation SWITCHING CHARACTERISTICS CS Setup Time (tCSS) SCLK Fall to CS Fall Hold Time (tCSH0) SCLK Fall to CS Rise Hold Time (tCSH1) SCLK High Width (tCH) SCLK Low Width (tCL) DIN Setup Time (tDS) DIN Hold Time (tDH) CS High Pulse Width (tCSW) ENVIRONMENTAL AND MECHANICAL Operating Temperature -J, -K -A, -B Storage Package -_N -_S
MIN.
TYP.
MAX.
UNITS
CONDITIONS Note 5 +5V, 3%; Note 4, 5
0.22 0.22 1.1
0.34 0.50
mA mA mW
25
ns
20
ns
0 40 40 50 0 30
ns ns ns ns ns ns
0 -40 -60
+70 +85 +150
C C C
8-pin Plastic DIP 8-pin 0.15" SOIC
Notes: 1. Integral Linearity, for the SP9500, is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the greatest negative deviation from the theoretical value for any given input condition. 2. Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two adjacent digital input codes. 3. 1 LSB = (VREF-AGND)/4,096. 4. VREF = AGND = 2.5V. 5. The following Power up sequence is recommended: VDD (+5V), VREF.
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
(c) Copyright 2000 Sipex Corporation
3
PINOUT - 8-PIN PLASTIC DIP & SOIC VOUT VDD SCLK DIN 1 2 3 4 8 7 VREF AGND DGND CS
THEORY OF OPERATION The SP9500 consists of four main functional blocks - the input shift register, DAC register, 12-Bit D/A converter and a output buffer amplifier, Figure 1. The input shift register is used to convert the serial input data stream to a parallel 12-Bit digital word. The input data is shifted on positive clock (SCLK) edges when the Chip Select (CS) signal is in the "low" state. The MSB is loaded first and LSB last. No shifting of the input data occurs when the Chip Select (CS) signal is in the "high" state. The DAC register is used to store the digital word which is sent to the R-2R DAC. Its value is updated on the positive transition of the Chip Select (CS) signal. The 12-Bit D/A converter is an "inverted" R-2R ladder network. The DAC itself is implemented with precision thin-film resistors and CMOS transmission gate switches. The resistor network is laser-trimmed to achieve better than 12- Bit accuracy. The D/A converter is used to convert the 12-bit input word to a precision voltage. The operational amplifier is a rail-to-rail input, rail-to-rail output CMOS amplifier. It is capable of supplying 1mA of load current in the 1.5 to 3.5 output voltage range. The initial offset voltage is laser-trimmed to improve accuracy. Settling time is 7.5 s for a full scale output transition to 0.012% accuracy.
SP9500
6 5
PIN ASSIGNMENTS Pin 1- VOUT - Voltage Output. Pin 2- VDD - +5V Power Supply Input. Pin 3- SCLK - Serial Clock Input. Pin 4- DIN - Serial Data Input. Pin 5- CS - Chip Select Input. Pin 6 - DGND - Digital Ground Pin 7- AGND - Analog Ground. Pin 8- VREF - Reference Input. FEATURES... The SP9500 is a low power 12-Bit Digital-toAnalog Converter. The converter features 0.5 to 4.5 volt output swings with a single +5V supply. The input coding format used is standard binary, Table 1. This Digital-to Analog Converter uses a standard 3-wire interface compatible with SPITM, QSPITM and MicrowireTM. The output settling time is specified at 7.5 s to full 12-bit accuracy when driving a 10K, 10pF load combination. The SP9500 Digital-to-Analog Converter is ideally suited for applications such as ATE, process controllers, robotics and instrumentation. The SP9500 is available in an 8-pin 0.15" SOIC and 0.3" PDIP packages, specified over commercial and industrial temperature ranges.
INPUT MSB 1111 1111 0000 0000 1111 1111 0000 0000 LSB 1111 1110 0001 0000
OUTPUT VREF - 1 LSB VREF - 2 LSB AGND + 1 LSB AGND (VREF-AGND) 2 12
1 LSB = Table 1. Binary Coding
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
(c) Copyright 2000 Sipex Corporation
4
+0.5 lsb DNLE -0.5 lsb +0.5 lsb INLE -0.5 lsb 0 DNLE, INLE Plots CODE 4095
USING THE SP9500 External Reference The R-2R DAC input resistance is code dependent and is minimum (11k) at code 1365 and 2731. And, it is nearly infinite at code 0. Because of the code-dependent nature of the reference inputs, a high quality, low output impedance amplifier should be used to drive the VREF and AGND inputs. Serial Clock and Update Rate The SP9500 maximum serial clock rate (SCLK) is given by 1/(tCH+tCL) which is approximately 12.5 MHz. The digital word update rate is limited by the chip select period, which is 12 X SCLK periods plus the CS high pulse width tCSW. This is equal to a 1 s or 1 MHz update rate. However, the DAC settling time to 12-Bits is 7.5 s, which for full scale output transitions would limit the update rate to 125 kHz. Logic Interface The SP9500 is designed to be compatible with TTL and CMOS logic levels. However, driving the digital inputs with TTL level signals will increase the power consumption of the part by 300 A. In order to achieve the lowest power consumption use rail-to-rail CMOS levels to drive the digital inputs.
DAC DAC REGISTER REGISTER
DIN
1
VREF
SHIFT REGISTER
12
LATCH
12
DAC
+ -
VOUT
AGND
Figure 1. Detailed Block Diagram
VREF
WHERE... VOUT = VDAC
DIN
+ -
VOUT
VDAC =
(
DIN 4096
)
x (VREF - AGND) + AGND
AGND Figure 2. Transfer Function
VDAC
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
(c) Copyright 2000 Sipex Corporation
5
CS
tCSHO tCSS tCH tCL tCSH1 tCSW
SCLK
tDH tDS
DIN
DB11
DB10
DB9
DB8
DB0
Figure 3. Timing Diagram
SCLK DIN CS N/C
SP9500
SK SO I/O SI
MICROWIRE PORT
Figure 4. Microwire Connection
SCLK DIN CS N/C
SP9500
SK MOSI I/O MISO
SPI PORT CPOL = 0, CPHA = 0
Figure 5. SPI Connection
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
(c) Copyright 2000 Sipex Corporation
6
PACKAGE: PLASTIC DUAL-IN-LINE (NARROW)
E1 E
D1 = 0.005" min. (0.127 min.) D
A1 = 0.015" min. (0.381min.) A = 0.210" max. (5.334 max). A2 C O eA = 0.300 BSC (7.620 BSC) L
e = 0.100 BSC (2.540 BSC)
B1 B
ALTERNATE END PINS (BOTH ENDS)
DIMENSIONS (Inches) Minimum/Maximum (mm) A2 B B1 C D E E1 L O
8-PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356)
14-PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356)
16-PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356)
18-PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356)
20-PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356)
22-PIN 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356)
0.355/0.400 0.735/0.775 0.780/0.800 0.880/0.920 0.980/1.060 1.145/1.155 (9.017/10.160) (18.669/19.685) (19.812/20.320) (22.352/23.368) (24.892/26.924) (29.083/29.337) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0/ 15 (0/15) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0/ 15 (0/15) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0/ 15 (0/15) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0/ 15 (0/15) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0/ 15 (0/15) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0/ 15 (0/15)
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
(c) Copyright 2000 Sipex Corporation
7
PACKAGE: PLASTIC SMALL OUTLINE (SOIC) (NARROW)
E
H
h x 45 D A O e B A1 L
DIMENSIONS (Inches) Minimum/Maximum (mm) A A1 B D E e H h L O
8-PIN 0.053/0.069 (1.346/1.748) 0.004/0.010 (0.102/0.249 0.014/0.019 (0.35/0.49) 0.189/0.197 (4.80/5.00) 0.150/0.157 (3.802/3.988) 0.050 BSC (1.270 BSC) 0.228/0.244 (5.801/6.198) 0.010/0.020 (0.254/0.498) 0.016/0.050 (0.406/1.270) 0/8 (0/8)
14-PIN 0.053/0.069 (1.346/1.748) 0.004/0.010 (0.102/0.249) 0.013/0.020 (0.330/0.508)
16-PIN 0.053/0.069 (1.346/1.748) 0.004/0.010 (0.102/0.249) 0.013/0.020 (0.330/0.508)
0.337/0.344 0.386/0.394 (8.552/8.748) (9.802/10.000) 0.150/0.157 (3.802/3.988) 0.050 BSC (1.270 BSC) 0.228/0.244 (5.801/6.198) 0.010/0.020 (0.254/0.498) 0.016/0.050 (0.406/1.270) 0/8 (0/8) 0.150/0.157 (3.802/3.988) 0.050 BSC (1.270 BSC) 0.228/0.244 (5.801/6.198) 0.010/0.020 (0.254/0.498) 0.016/0.050 (0.406/1.270) 0/8 (0/8)
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
(c) Copyright 2000 Sipex Corporation
8
ORDERING INFORMATION
Model .................................................................................. Temperature Range ....................................................................................... Package Monolithic 12-Bit DAC Voltage Output: SP9500JN ................................................................................ 0C to +70C .......................................................................... 8-pin, 0.3" Plastic DIP SP9500KN ............................................................................... 0C to +70C .......................................................................... 8-pin, 0.3" Plastic DIP SP9500JS ................................................................................ 0C to +70C ................................................................................. 8-pin, 0.15" SOIC SP9500KS ............................................................................... 0C to +70C ................................................................................. 8-pin, 0.15" SOIC SP9500AN ............................................................................... -40C to +85C ...................................................................... 8-pin, 0.3" Plastic DIP SP9500BN ............................................................................... -40C to +85C ...................................................................... 8-pin, 0.3" Plastic DIP SP9500AS ............................................................................... -40C to +85C ............................................................................. 8-pin, 0.15" SOIC SP9500BS ............................................................................... -40C to +85C ............................................................................. 8-pin, 0.15" SOIC
Corporation
SIGNAL PROCESSING EXCELLENCE
Sipex Corporation Headquarters and Sales Office 22 Linnell Circle Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.
SP9500DS/04
SP9500 12-Bit, Voltage Output D/A Converter
(c) Copyright 2000 Sipex Corporation
9

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