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| PDF: 2001 Nov 15 Philips Semiconductors Package outline PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 eD y X A ZE eE 39 29 28 bp 40 b1 wM 44 HE A e A4 A1 (A 3) k 7 e D HD 17 ZD B vMB vM A 6 18 Lp detail X 1 pin 1 index E 0 5 scale 10 mm DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 UNIT A A3 D(1) E(1) e eD eE HD bp b1 max. min. mm 4.57 4.19 0.51 0.25 0.01 3.05 0.53 0.33 0.81 0.66 HE k Lp 1.44 1.02 v 0.18 w 0.18 y 0.1 ZD(1) ZE(1) max. max. 2.16 2.16 16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07 0.63 0.59 0.63 0.59 45 o 0.180 inches 0.02 0.165 0.021 0.032 0.656 0.656 0.05 0.12 0.013 0.026 0.650 0.650 0.695 0.695 0.048 0.057 0.007 0.007 0.004 0.085 0.085 0.685 0.685 0.042 0.040 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT187-2 REFERENCES IEC 112E10 JEDEC MS-018 JEITA EDR-7319 EUROPEAN PROJECTION ISSUE DATE 99-12-27 01-11-14 |
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