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INTEGRATED CIRCUITS
DATA SHEET
SAA9750H Camera Digital Signal Processor (CAMDSP)
Preliminary specification File under Integrated Circuits, IC02 1996 Feb 16
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
FEATURES * Y/C separator for mosaic filter colour CCD which can be used with PAL or NTSC CCDs with horizontal resolution of 510, 670, 720 or 768 pixels * Line sequential colour processing (R-Y) and (B-Y) * 9 bit input signal (the internal processing is 10-bit) * Digital feedback clamp control for Y/C separation * Two 768 x 9 line memories for Y/C separation * Aperture correction using phase linear filters * Coring of LOW level signals to reduce noise * Colour encoder in accordance with the PAL or NTSC system. Colour subcarrier is made by a discrete time oscillator (DTO) operating on system clock * Slew rate controlled outputs for reduction of digital noise * RGB inputs for title mix * High accuracy 8 bit DAC outputs for luminance and chrominance signals QUICK REFERENCE DATA SYMBOL VDDA1 VDDA2 VDDD1 VDDD2 VDDD3 VIH VIL VOH VOL Tamb PARAMETER Y-DAC analog supply voltage (pin 1) C-DAC analog supply voltage (pin 2) digital supply voltage (pin 41) digital supply voltage (pin 53) digital supply voltage (pin 65) HIGH level digital input voltage LOW level digital input voltage HIGH level digital output voltage LOW level digital output voltage operating ambient temperature MIN. 2.7 2.7 2.7 2.7 2.7 0.7VDDD 0 - -20 TYP. 3.0 3.0 3.0 3.0 3.0 - - - -
SAA9750H
* Sync Signal Generator (SSG) to generate all necessary timing signals * Serial interface for microprocessor control of CAMDSP settings * Y and C signals accessible to incorporate digital features * Including digital feature functions (mosaic, sepia, solarization, slice and negative/positive inversion). GENERAL DESCRIPTION The Camera Digital Signal Processor (CAMDSP) is intended for use with a mosaic filter colour CCD. The IC generates luminance and chrominance signals from the CCD signal. The device consists of a luminance and colour separator employing two 768 x 9 line memories, a PAL/NTSC encoder, a dual 8-bit video DAC, a Sync Signal Generator (SSG) and a simple serial interface to control many settings.
MAX. 3.3 3.3 3.3 3.3 3.3 VDDD 0.3VDDD - 0.5 +70 V V V V V V V V V C
UNIT
VDDD - 0.5 -
ORDERING INFORMATION TYPE NUMBER SAA9750H PACKAGE NAME LQFP80 DESCRIPTION plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm VERSION SOT315-1
1996 Feb 16
2
handbook, full pagewidth
1996 Feb 16
VDDD2 VDDD3 VDDD1 UVSEL UV0 to UV7 R B WCLIP TSW G LSW VDDA1 VDDA2 65 53 41 29 8 21 to 28 20 8 9 10 11 7 8 D 5 12 to 19 1 A 2 3
BLOCK DIAGRAM
Philips Semiconductors
Camera Digital Signal Processor (CAMDSP)
SAA9750H
CDS0 to CDS8 CPOB CLAMP
C PROCESSING
ENCODER
COUT
9 68 to 76 62 61 CLAMP
X0H FIFO 768 x 9
X2H X1H FIFO 768 x 9
+
UVENC TITLE SWITCH
title mix 8
VrefC UVENC0 to UVENC7 YENC7 to YENC0
8 title mix 8
43 to 50
CLAMP settings Y settings C settings ENCODER settings SSG settings
Y PROCESSING YENC DELAY
CS CK DI VRST HRST CLK1 CLK2
30 31 32 51 52 66 67 64
MICROPROCESSOR INTERFACE
sync
A 80 D 78
3
YOUT VrefY
CLOCK
SYNC SIGNAL GENERATOR 8 77 6 59 55 56 63 57 58 33 to 40 60 4 79
MHA302
54
42
VSSD2 VSSD3 VSSD1 TEST1 TEST2 CSYNC HD FLD Y0 to Y7 VD CP2 HSYNC
SYNCI
VSSA1
VSSA2
Preliminary specification
SAA9750H
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
PINNING SYMBOL VDDA1 VDDA2 COUT VSSA1 VrefC TEST2 LSW TSW R G B UVENC0 UVENC1 UVENC2 UVENC3 UVENC4 UVENC5 UVENC6 UVENC7 WCLIP UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 UVSEL CS CK DI Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 1996 Feb 16 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 INPUT/OUTPUT ANALOG/DIGITAL supply supply output supply - input input input input input input input input input input input input input input output output output output output output output output output output input input input output output output output output output output output - - analog - - digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital digital 4
SAA9750H
DESCRIPTION analog supply voltage 1 for Y-DAC analog supply voltage 2 for C-DAC C-DAC output analog ground 1 for C-DAC C-DAC decoupling voltage test 2 pin line switch for SECAM title memory switch title memory colour (red) title memory colour (green) title memory colour (blue) B-Y and R-Y signal to encoder (LSB) B-Y and R-Y signal to encoder B-Y and R-Y signal to encoder B-Y and R-Y signal to encoder B-Y and R-Y signal to encoder B-Y and R-Y signal to encoder B-Y and R-Y signal to encoder B-Y and R-Y signal to encoder (MSB) white-clip time multiplexed B-Y and R-Y (MSB) time multiplexed B-Y and R-Y time multiplexed B-Y and R-Y time multiplexed B-Y and R-Y time multiplexed B-Y and R-Y time multiplexed B-Y and R-Y time multiplexed B-Y and R-Y time multiplexed B-Y and R-Y (LSB) B-Y or R-Y active at UV output microprocessor interface (chip select) microprocessor interface (clock) microprocessor interface (data input) luminance signal (LSB) luminance signal luminance signal luminance signal luminance signal luminance signal luminance signal luminance signal (MSB)
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
SYMBOL VDDD1 VSSD1 YENC7 YENC6 YENC5 YENC4 YENC3 YENC2 YENC1 YENC0 VRST HRST VDDD3 VSSD3 VD HD FLD HSYNC CSYNC SYNCI CLAMP CPOB CP2 VSSD2 VDDD2 CLK1 CLK2 CDS0 CDS1 CDS2 CDS3 CDS4 CDS5 CDS6 CDS7 CDS8 TEST1 VrefY VSSA2 YOUT PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 INPUT/OUTPUT ANALOG/DIGITAL supply supply input input input input input input input input input input supply supply output output output output output input output (3-state) input output supply supply input input input input input input input input input input input input - supply output - - digital digital digital digital digital digital digital digital digital digital - - digital digital digital digital digital digital digital digital digital - - digital digital digital digital digital digital digital digital digital digital digital digital - - analog digital ground 1
SAA9750H
DESCRIPTION digital supply voltage 1 luminance signal to encoder (MSB) luminance signal to encoder luminance signal to encoder luminance signal to encoder luminance signal to encoder luminance signal to encoder luminance signal to encoder luminance signal to encoder (LSB) external VD (vertical drive) external HD (horizontal drive) digital supply voltage 3 digital ground 3 VD timing for PPG IC HD timing for PPG IC field pulse output horizontal timing for YC processing composite sync pulse sync input for bypass mode clamp voltage control optical black pulse clamping pulse digital ground 2 digital supply voltage 2 clock 1 clock 2 CDS signal (LSB) CDS signal CDS signal CDS signal CDS signal CDS signal CDS signal CDS signal CDS signal (MSB) test 1 pin Y-DAC decoupling voltage analog ground 2 for Y-DAC Y-DAC output
1996 Feb 16
5
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
SAA9750H
handbook, full pagewidth
61 CLAMP 60 SYNCI 59 CSYNC 58 HSYNC 57 FLD 56 HD 55 VD 54 VSSD3 53 VDDD3 52 HRST 51 VRST 50 YENC0 49 YENC1 48 YENC2 47 YENC3 46 YENC4 45 YENC5 44 YENC6 43 YENC7 42 VSSD1 41 VDDD1 Y7 40
MHA301
65 VDDD2
64 VSSD2
79 VSSA2
77 TEST1
VDDA1 1 VDDA2 2 COUT 3 VSSA1 4 VrefC 5 TEST2 6 LSW 7 TSW 8 R9 G 10
SAA9750H
B 11 UVENC0 12 UVENC1 13 UVENC2 14 UVENC3 15 UVENC4 16 UVENC5 17 UVENC6 18 UVENC7 19 WCLIP 20 UV7 21 UV6 22 UV5 23 UV4 24 UV3 25 UV2 26 UV1 27 UV0 28 UVSEL 29 CS 30 CK 31 DI 32 Y0 33 Y1 34 Y2 35 Y3 36 Y4 37 Y5 38 Y6 39
Fig.2 Pin configuration.
1996 Feb 16
6
62 CPOB
80 YOUT
76 CDS8
75 CDS7
74 CDS6
73 CDS5
72 CDS4
71 CDS3
70 CDS2
69 CDS1
68 CDS0
78 VrefY
67 CLK2
66 CLK1
63 CP2
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
FUNCTIONAL DESCRIPTION The Camera Digital Signal Processor (CAMDSP) is intended for use with a mosaic filter colour CCD. The input signal is an 8-bit or 9-bit digitized CCD signal. After AGC and gamma correction, clamping of the input signal is achieved by feedback clamp level control. In the luminance processing, symmetrical horizontal and vertical aperture correction are carried out. Coring is also carried out to reduce noise at LOW signal levels. In the chrominance processing, white balance control and matrix control is adjustable. A false colour correction circuit reduces aliasing of high frequency input signals. A white-clip makes the colour white at highlights. In the encoder part, the colour encoder subcarrier is made by the discrete time oscillator thus eliminating the use of an extra crystal. The subcarrier frequency for PAL or NTSC is selectable. The encoding can be in PAL or NTSC format.
SAA9750H
The encoded signal is output via separate 8-bit digital-to-analog converters (DACs) for luminance and chrominance. In the event of SECAM the output is a line sequential -(R-Y)/(B-Y) signal. A line memory interface allows for mixing of RGB signals in the main signal. The encoder can be bypassed completely, in this event only the title mix is carried out before digital-to-analog conversion. The SSG generates all necessary timing signals. Timing signals for external devices NTSC, PAL and SECAM are also made. The SSG can be locked to an external video source. CAMDSP can operate with 510H, 670H, 720H and 768H colour mosaic CCDs both PAL and NTSC type. In the 510H CCD application the upsampling clock is used for the encoder part, therefore two clock frequencies (fs and 2fs) are required.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD VDDA Ptot VI VO Tstg Tamb Ves Ilatch Note 1. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 57 UNIT K/W PARAMETER digital supply voltage analog supply voltage total power dissipation digital input voltage digital output voltage storage temperature operating ambient temperature electrostatic handling latch-up protection current note 1 CONDITIONS MIN. -0.5 -0.5 - -0.5 -0.5 -65 -20 -2000 100 MAX. +5.0 +5.0 500 VDDD + 0.5 VDDD + 0.5 +150 +70 +2000 - V V mW V V C C V mA UNIT
1996 Feb 16
7
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
DC CHARACTERISTICS VDD = 2.7 to 3.3 V; Tamb = -20 to +70 C; unless otherwise specified. SYMBOL IDD PARAMETER supply current CONDITIONS note 1 - MIN. TYP. 60
SAA9750H
MAX. 150
UNIT mA
Inputs: LSW, TSW, R, G, B, UVENC0 to UVENC7, CS, CK, DI, YENC0 to YENC7, VRST, HRST, SYNCI, CPOB, CLK1, CLK2, CDS0 to CDS7, TEST1 and TEST2 VIH VIL IIH IIL HIGH level input voltage LOW level input voltage HIGH level input current LOW level input current VIH = VDD VIL = VSS IOH = -20 A IOH = -2 mA VOL LOW level output voltage IOL = +20 A IOL = +2 mA Output: CLAMP (3-state output) VOH VOL ITL Note 1. 510H PAL; VDD = 3 V; DAC RL = 2 k. DAC CHARACTERISTICS VDD = 3.0 V; Tamb = +25 C; RL = open-circuit; unless otherwise specified. SYMBOL Outputs: YOUT and COUT fCmax INL DNL VO(p-p) RO conversion frequency speed DC integral linearity error DC differential linearity error full scale output except sync (peak-to-peak value) internal series output resistance 20 -0.5 -0.5 1.61 - - - - 1.66 75 - +0.5 +0.5 1.72 - MHz LSB LSB V PARAMETER MIN. TYP. MAX. UNIT HIGH level output voltage LOW level output voltage 3-state leakage current IOH = -20 A IOH = -8 mA IOL = +20 A IOL = +8 mA VIH = VDD; VIL = VSS VDD - 0.1 - VDD - 0.5 - - - - - - - - - 0.1 0.5 5 V V V V A 0.7VDD - - - - - - - - 0.3VDD 1 -1 - - 0.1 0.5 V V A A
Outputs: WCLIP, UV0 to UV7, UVSEL, Y0 to Y7, VD, HD, FLD, HSYNC, CSYNC and CP2 VOH HIGH level output voltage VDD - 0.1 - VDD - 0.5 - - - - - V V V V
1996 Feb 16
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Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
AC CHARACTERISTICS
SAA9750H
Microprocessor interface VDD = 2.7 to 3.3 V; VIL = 0 V; VIH = VDD; Vref = 0.5VDD; Tamb = -20 to +70 C; input tr and tf = 30 ns; unless otherwise specified. SYMBOL tCSs tCSh tCSd tDs tDh fCK tWCKH tWCKL tr tf CS hold time CS deselection time DI set-up time DI hold time CK frequency HIGH level pulse width of CK LOW level pulse width of CK rise time of CK fall time of CK PARAMETER CS set-up time 0.4 0.4 0.2 0.4 0.4 - 1.0 1.0 - - MIN. - - - - - - - - - - TYP. - - - - - 0.5 - - 100 100 MAX. s s s s s MHz s s ns ns UNIT
tCSs
tCSd VIH
CS
Vref VIL tWCKH tWCKL 90% 90% Vref 10% tr tf tDs tDh VIH 10% VIL VIH tCSh
CK
DI
Vref
MHA305
VIL
Fig.3 Microprocessor interface timing.
1996 Feb 16
9
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
SAA9750H
Data input/output timing (CLK1 and CLK2) VDD = 2.7 to 3.3 V; VIL = 0 V; VIH = VDD; Vref = 0.5VDD;Tamb = -20 to +70 C; tr and tf = 6 ns; output load capacitance = 20 pF; unless otherwise specified. SYMBOL tDIs tDIh tDOd tDOh tduty Notes 1. Data inputs: SYNCI, CPOB, CDS0 to CDS8, VRST, HRST, R, G, B, TSW, YENC0 to YENC7, LSW and UVENC0 to UVENC7. 2. Data outputs: UVSEL, UV0 to UV7, Y0 to Y7, WCLIP, CSYNC, HSYNC, FLD, HD, VD and CP2. 3. Tamb = +25 C; VDD = 3.0 V. PARAMETER data input set-up time data input hold time data output delay time data output hold time duty factor of CLK1 and CLK2 CONDITIONS note 1 note 1 notes 2 and 3 notes 2 and 3 5 8 - - - MIN. - - - - 50 TYP. - - 50 50 - MAX. UNIT ns ns ns ns %
tf 90% CLK1 and CLK2 Vref 10%
tr 90% VIH
10%
VIL
tDIs 90% data inputs 10%
tDIh 90% VIH
10%
VIL
tDOd 90% data outputs 10%
tDOh 90% VOH
10%
MHA306
VOL
Fig.4 Data input/output timing (CLK1 and CLK2).
1996 Feb 16
10
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
SSG TIMING Clock count for NTSC and PAL mode
SAA9750H
handbook, full pagewidth
CCD 510H -10 (-15)
0 50 (45)
1H 606 (618) clocks 596 (603)
SHD 60 (60) HD
CP2
Y0 to Y7
HSYNC
YDA and CDA
SYNC
,, ,, ,,,,, ,, ,,,,,,,, ,,, ,,,,,, ,,, ,,,,,,,
24 (24) 75 (75) 33 (33) 139 (151) 48 (48) 93 (93) 57 (57) 165 (177) 62 (62) 107 (107) 0 80 (80) 1H 806 (824) clocks 80 (80)
CCD 670H SHD
HD
CP2
Y0 to Y7
HSYNC
YDA and CDA
,, ,,,
28 (28) 48 (48) 51 (51) 61 (61)
32 (32)
100 (100)
108 (108)
121 (121)
,,,,,,, ,,,,,,
168 (184) 195 (203)
MHA307
SYNC
Fig.5 SSG timing (continued in Fig.6).
1996 Feb 16
11
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
SAA9750H
handbook, full pagewidth
CCD 720H
0 83 (83)
1H 858 (864) clocks
SHD 83 (83) HD 36 (36) CP2 104 (104)
Y0 to Y7
HSYNC
YDA and CDA
SYNC
,,, ,,,
34 (34) 50 (50) 0
113 (113)
63 (63)
67 (67)
130 (130)
,,,,,,, ,,,,,,,
172 (182) 209 (229) 1H 910 (908) clocks
CCD 768H SHD
89 (89)
89 (89) HD
CP2
Y0 to Y7
HSYNC
YDA and CDA
SYNC
,,, ,,, ,,, ,,,
36 (36) 33 (33) 54 (54)
108 (108)
121 (121)
65 (63)
71 (71)
138 (138)
,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,,
191 (203) 223 (235)
MHA308
Fig.6 SSG timing (continued from Fig.5).
SHD: HD output can be changed by microprocessor to SHD outputs. HD: For timing of input CDS signal for PPG IC. HSYNC: For output luminance signal Y7 to Y0 and chrominance signal UV7 to UV0 of CAMDSPs YC processing. SYNC: Composite SYNC pulse of DACs output. Output of CSYNC (pin 59): SYNC + 1 clock (see Figs 5 and 6). 1996 Feb 16 12
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
Clock Table 1 Clock frequency MODE NTSC 510H 670H 720H 768H PAL SECAM 510H 670H 720H 768H Table 2 Clock used for each block SSG BLOCK CLK1 CLK1 Y/C BLOCK CLK1 CLK1 ENCODER BLOCK CLK1 and CLK2 (upsampling) CLK1 Y-DAC BLOCK CLK1 CLK1 CCD 9.5350 12.7132 13.5000 14.3182 9.6563 12.8750 13.5000 14.1875 CLK1 (MHz) - - - 19.3125 - - -
SAA9750H
CLK2 (MHz) 19.0699
MODE 510H NTSC/PAL Other modes
C-DAC BLOCK CLK2 CLK1
MICROPROCESSOR INTERFACE FORMAT
handbook, full pagewidth CS
CK
DI
MSB
LSB
MSB subaddress
LSB
MSB data
LSB
MHA304
slave address(1)
(1) Slave address 001.
Fig.7 Microprocessor interface format.
1996 Feb 16
13
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
Table 3 Microprocessor interface format DATA FUNCTION Field delay Title enable Title polarity False colour +6 dB UV +6 dB Y +6 dB Y clear HAP LOW clip VAP LOW clip AP HIGH clip AP gain Y gain Y pedestal Slice Mosaic Slice level Subcarrier SUBADDRESS MSB 00000 00000 00000 00000 00000 00000 00000 00001 00010 00011 00011 00100 00101 00110 00110 00111 01000 01001 01010 UV polarity SYNCI Encoder mode Burst level HRST delay CCD type 525/625 line Master/slave ADC delay Solarization Sepia Negative/positive R gain B gain U gain 01010 01010 01010 01011 01101 01110 01110 01110 01110 01110 01111 01111 01111 01111 10000 10001 10010 10011 X X X X X X X X X X X X YP7 X X SLL7 S7 S15 - - - EM1 X D7 - - - - AD1 X X X X X X X X - - - - - - YCL X X - AG2 X YP6 X X SLL6 S6 S14 - - - EM0 BL6 D6 - - - - AD0 X X X X RG6 BG6 X X - - - - - YUP - HA5 VA5 - AG1 YG5 YP5 X X SLL5 S5 S13 - - SYN - BL5 D5 - - - MS - X X X X RG5 BG5 UGP5 UGN5 - - - - CUP - - HA4 VA4 - AG0 YG4 YP4 - MOS SLL4 S4 S12 - UVP - - BL4 D4 - - LL - - - - - NP RG4 BG4 UGP4 UGN4 - - - FCU - - - HA3 VA3 AP3 - YG3 YP3 - PX1 SLL3 S3 S11 S19 - - - BL3 D3 - H1 - - - - - SEP - RG3 BG3 UGP3 UGN3 - - TP - - - - HA2 VA2 AP2 - YG2 YP2 - PX0 SLL2 S2 S10 S18 - - - BL2 D2 - H0 - - - - SOL - - RG2 BG2 UGP2 UGN2
SAA9750H
LSB - TE - - - - - HA1 VA1 AP1 - YG1 YP1 SLI - SLL1 S1 S9 S17 - - - BL1 D1 D9 - - - - TR1 - - - RG1 BG1 UGP1 UGN1 FD - - - - - - HA0 VA0 AP0 - YG0 YP0 SNP - SLL0 S0 S8 S16 - - - BL0 D0 D8 - - - - TR0 - - - RG0 BG0 UGP0 UGN0
1996 Feb 16
14
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
DATA FUNCTION V gain U matrix 1 gain U matrix 2 gain V matrix 1 gain V matrix 2 gain SP polarity FH2 polarity Colour filter HD, VD polarity Sub LPF False colour White-clip level Y delay C delay Table 4 SUBADDRESS MSB 10100 10101 10110 10111 11000 11001 11010 11010 11010 11010 11010 11011 11100 11101 11101 X X X X X X X X X X X TH7 WC7 X X X X X X X X X X X X X TH6 WC6 X X VGP5 VGN5 UM5 UN5 VM5 VN5 X X X X X TH5 WC5 X X VGP4 VGN4 UM4 UN4 VM4 VN4 - - - - JGM TH4 WC4 X X VGP3 VGN3 UM3 UN3 VM3 VN3 - - - SHV - TH3 WC3 - CDL1 VGP2 VGN2 UM2 UN2 VM2 VN2 - - LPF - - TH2 WC2 - CDL0
SAA9750H
LSB VGP1 VGN1 UM1 UN1 VM1 VN1 - FHP - - - TH1 WC1 YDL1 - VGP0 VGN0 UM0 UN0 VM0 VN0 SPP - - - - TH0 WC0 YDL0 -
Explanation of functions of Table 3 DESCRIPTION field delay control title enable control title polarity control false colour plus 6 dB up UV +6 dB up Y gain +6 dB up Y clear control horizontal aperture LOW clip level control vertical aperture LOW clip level control aperture HIGH clip level control aperture gain control Y gain control Y pedestal control slice effect polarity slice ON/OFF mosaic effect pixels control mosaic ON/OFF slice level control subcarrier control UVSEL polarity control SYNC signal selection
SYMBOL FD TE TP FCU CUP YUP YCL HA0 to HA5 VA0 to VA5 AP0 to AP3 AG0 to AG2 YG0 to YG5 YP0 to YP7 SNP SLI PX0 and PX1 MOS SLL0 to SLL7 S0 to S19 UVP SYN
1996 Feb 16
15
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
SYMBOL EM0 and EM1 BL0 to BL6 D0 to D9 H0 and H1 LL MS AD0 and AD1 TR0 and TR1 SOL SEP NP RG0 to RG6 BG0 to BG6 UGP0 to UGP5 UGN0 to UGN5 VGP0 to VGP5 VGN0 to VGN5 UM0 to UM5 UN0 to UN5 VM0 to VM5 VN0 to VN5 SPP FHP LPF SHV JGM TH0 to TH7 WC0 to WC7 YDL0 and YDL1 CDL0 and CDL1 encoder mode control burst level control HRST and VRST preset control CCD type selection 525/625 line control master/slave control ADC delay control solarization effect control solarization ON/OFF sepia ON/OFF negative/positive ON/OFF red gain control blue gain control U gain control for positive side U gain control for negative side V gain control for positive side V gain control for negative side U matrix 1 gain control U matrix 2 gain control V matrix 1 gain control V matrix 2 gain control SP polarity control FH2 polarity control colour filter control HD and VD polarity control sub LPF control for false colour threshold control for false colour suppression white-clip level control Y delay control C delay control DESCRIPTION
SAA9750H
1996 Feb 16
16
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
MICROPROCESSOR SETTING Table 5 Field delay control FIELD DELAY CONTROL Normal One field delay Table 6 Title enable control TITLE ENABLE CONTROL Title insertion OFF Title insertion ON Table 7 Title polarity control Negative TITLE POLARITY CONTROL Negative Positive Table 8 False colour +6 dB up OFF normal FALSE COLOUR +6 dB UP 0 dB gain +6 dB gain Table 9 UV +6 dB up UV +6 dB UP 0 dB gain +6 dB gain Table 10 Y gain +6 dB up Y GAIN +6 dB UP 0 dB gain +6 dB gain Table 11 Y clear control Y CLEAR CONTROL Normal Clear YCL 0 1 YUP 0 1 OFF normal ON mosaic Slice level control = SLL7 to SLL0. CUP 0 1 FCU 0 1 Table 14 Mosaic effect pixels control ON slice TP 0 1 Table 13 Slice ON/OFF SLICE ON/OFF Positive TE 0 1 Table 12 Slice effect polarity FD 0 1
SAA9750H
Horizontal aperture LOW clip level control = HA5 to HA0. Vertical aperture LOW clip level control = VA5 to VA0. Aperture HIGH clip level control = AP3 to AP0. AG [ 2:0 ] Aperture gain control = -----------------------8 YG [ 5:0 ] Y gain control = -----------------------32 Y pedestal level control = YP7 to YP0.
SLICE EFFECT POLARITY
SNP 0 1
SLI 0 1
MOSAIC EFFECT PIXELS CONTROL 4 x 4 pixels 8 x 8 pixels 16 x 16 pixels 32 x 32 pixels Table 15 Mosaic ON/OFF MOSAIC ON/OFF
PX1 0 0 1 1
PX0 0 1 0 1
MOS 0 1
S [ 19:0 ] x f encoder Subcarrier frequency control = -----------------------------------------------1048576
1996 Feb 16
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Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
Table 16 UVSEL polarity control UVSEL POLARITY CONTROL Normal Invert UVP Master 0 HIGH: U(B-Y) LOW: V(R-Y) 1 HIGH: V(R-Y) LOW: U(B-Y) Table 22 AD converter delay control Table 17 SYNC signal selection SYNC SIGNAL SELECTION Internal SYNC External SYNC (from SYNCI pin 60) Table 18 Encoder mode control ENCODER MODE CONTROL PAL NTSC SECAM Bypass EM1 0 0 1 1 EM0 0 1 0 1 Table 23 Solarization effect control SYN 0 1 3Ts 4Ts 5Ts 6Ts ADC DELAY CONTROL (CAMDSP DELAY) Slave Table 21 Master/slave control
SAA9750H
MASTER/SLAVE CONTROL
MS 0 1
AD1 0 0 1 1
AD0 0 1 0 1
SOLARIZATION EFFECT CONTROL (SLICE OF BITS) 3 bits (LSB) 4 bits (LSB) 5 bits (LSB) 6 bits (LSB) Table 24 Solarization ON/OFF SOLARIZATION ON/OFF
TR1 0 0 1 1
TR0 0 1 0 1
BL [ 6:0 ] Burst level control = ---------------------- (of full-scale DAC output). 128 HRST and VRST preset control = D9 to D0, preset horizontal counter to count D9 to D0. Table 19 CCD type selection CCD TYPE SELECTION 510H 670H 720H 768H Table 20 525/625 line control 525/625 LINE CONTROL 525 line 625 line LL 0 1 H1 0 0 1 1 H0 0 1 0 1
SOL 0 1
Normal Solarization ON Table 25 Sepia ON/OFF SEPIA ON/OFF Normal Sepia ON Table 26 Negative/positive ON/OFF NEGATIVE/POSITIVE ON/OFF Normal Negative
SEP 0 1
NP 1 0
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Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
RG [ 6:0 ] R channel gain control = 1 + ------------------------ (1) 128 BG [ 6:0 ] B channel gain control = 1 + ------------------------ (1) 128 UGP [ 5:0 ] U gain control for positive side = ---------------------------16 UGN [ 5:0 ] U gain control for negative side = ----------------------------16 VGP [ 5:0 ] V gain control for positive side = ---------------------------16 VGN [ 5:0 ] V gain control for negative side = ---------------------------16 UM [ 5:0 ] U matrix 1 gain control = ------------------------ (1) 32 UN [ 5:0 ] U matrix 2 gain control = ------------------------ (1) 32 VM [ 5:0 ] V matrix 1 gain control = ------------------------ (1) 32 VN [ 5:0 ] V matrix 2 gain control = ----------------------- (1) 32 Table 27 SP polarity control SP POLARITY CONTROL Normal Invert 0 1 SPP H: Ye + Mg or Ye + Gr L: Cy + Gr or Cy + Mg H: Cy + Gr or Cy + Mg L: Ye + Mg or Ye + Gr Table 29 Colour filter control COLOUR FILTER CONTROL LPF1 LPF2 0 1
SAA9750H
LPF [1,1,3,3,4,4,4,4,3,3,1,1]/32 [-1,0,4,8,10,8,4,0,-1]/32
Table 30 HD and VD polarity control HD AND VD POLARITY CONTROL Normal Invert Table 31 Sub LPF control for false colour SUB LPF CONTROL FOR FALSE COLOUR Normal Sub LPF JGM 0 1 SHV 0 1
Threshold control for false colour suppress = TH7 to TH0. White clip level control = 2 x WC7 to WC0. Table 32 Y delay control Y DELAY CONTROL 0 clock period +1 clock period +2 clock periods +3 clock periods Table 33 C delay control C DELAY CONTROL 0 clock period +1 clock period FHP 0 1 H: 2B-G L: 2R-G H: 2R-G L: 2B-G +2 clock periods +3 clock periods CDL1 0 0 1 1 CDL0 0 1 0 1 YDL1 0 0 1 1 YDL0 0 1 0 1
Table 28 FH2 polarity control FH2 POLARITY CONTROL Normal Invert
(1) RG, BG, UM, UN, VM and VN are twos complement.
1996 Feb 16
19
1996 Feb 16
handbook, full pagewidth
CAMERA
Philips Semiconductors
Camera Digital Signal Processor (CAMDSP)
CAMERA
zoom encoder
focus sensor
hall sensor LPF CCD CDS AGC, GAMMA CLAMP BPF
Y C
ADC
AGC zoom lens focus lens iris PPG DAC
CAMDSP SIGNAL PROCESSOR 8-bit Y/C SEPARATION SSG serial ENCODER data bus HD/VD SAA9750H UVSEL HSYNC WCLIP A2CF AF/AE/AWB CDS(8) SAA9750H 3 UV(8) Y(5)
Y (8-bit) UV (8-bit)
20
ADC
MOTOR DRIVER
MOTOR DRIVER
IRIS DRIVER
high speed shuffle control
I/F(8)
MICROPROCESSOR
MHA303
Preliminary specification
SAA9750H
Fig.8 Camera block diagram (SAA9750H and SAA9740H).
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
PACKAGE OUTLINE LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SAA9750H
SOT315-1
c
y X A 60 61 41 40 Z E
e E HE wM bp 80 1 pin 1 index 20 ZD bp D HD wM B vM B vM A L 21 detail X Lp A A2 A1 (A 3)
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT315-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 1.6 A1 0.16 0.04 A2 1.5 1.3 A3 0.25 bp 0.27 0.13 c 0.18 0.12 D (1) 12.1 11.9 E (1) 12.1 11.9 e 0.5 HD HE L 1.0 Lp 0.75 0.30 v 0.2 w 0.15 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7 0o
o
14.15 14.15 13.85 13.85
ISSUE DATE 95-12-19 97-07-15
1996 Feb 16
21
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all LQFP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
SAA9750H
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Feb 16
22
Philips Semiconductors
Preliminary specification
Camera Digital Signal Processor (CAMDSP)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA9750H
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Feb 16
23
Philips Semiconductors - a worldwide company
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Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCDS47 (c) Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1100/01/pp24 Document order number: Date of release: 1996 Feb 16 9397 750 00641

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