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Data Sheet October 2001
ORCA(R) ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Introduction
Agere Systems Inc. has developed a new ORCA Series 4 based FPSC which combines a high-speed line interface with a flexible FPGA logic core. Built on the Series 4 reconfigurable embedded system-onchips (SoC) architecture, the ORLI10G consists of an OIF standard (OIF 99.102.5) compliant XSBI or OIF-SFI4-01.0 SFI-4, 10 Gbits/s or 12.5 Gbits/s transmit and 10 Gbits/s or 12.5 Gbits/s receive line interface. Both transmit and receive interfaces consist of 16-bit LVDS data up to 850 Mbits/s, integrated transmit and receive programmable PLLs for data rate conversions between the line-side and systemside data rates, and a programmable logic interface at the system end for use with SONET/SDH, Ethernet, or OTN/digital wrapper with strong FEC system device data standards. In addition to the embedded functionality, the device will include up to 400k of usable FPGA gates. The line interface includes logic to divide the data rate down to 212 MHz or less (1/4 line rate) or 106 MHz or less (1/8 line rate) for transfer to the FPGA logic. The ORLI10G is designed to connect directly to Agere's 10 Gbits/s TTRN0110G MUX and TRCV0110G deMUX or Agere's 12.5 Gbits/s TTRN0126 MUX and TRCV01126 deMUX on the line side, as well as other industrystandard devices. The programmable logic interface on the system side allows for direct connection to a 10 Gbits/s Ethernet MAC, a 10 Gbits/s SONET/SDH framer/data engine, or a 10 Gbits/s/12.5 Gbits/s digital wrapper/FEC framer/data engine. For 10 Gbits/s Ethernet, the ORLI10G supports the physical coding sublayer (PCS), interfaces to the physical media attachment (PMA), and connects to the system interface (host or switch) for the proposed IEEE (R) 802.3ae 10 Gbits/s serial LAN PHY. The ORLI10G FPSC is a high-speed programmable device for 10G/s data solutions. It can be used as the interface between the line interface and the system interface in a variety of emerging networks, including 10 Gbits/s SONET/SDH (OC-192/STM-48), 10 Gbits/s optical transport networks (OTN) using digital wrapper and strong FEC, or 10 Gbits/s Ethernet. Other functions include use in Quad OC-48/ STM-16 SONET/SDH systems, interfaces between Quad OC-48/STM-16 and OC-192/STM-64 components, and use as a generic data transfer mechanism between two devices at 10 Gbits/s rates. Data is received at the line interface and then sent to either a 4-bit or 8-bit serial-to-parallel converter. On the transmit interface, either a 4-bit or 8-bit parallel-to-serial converter is used. Thus, the data rate at the internal FPGA interface is either 1/4 or 1/8 the line rate. The programmable PLLs on the ORLI10G provide for great flexibility in handling clock rate conversion due to differing amounts of overhead bits in various system data standards. For example, the ORLI10G can divide down the STS-192/STM-64 SONET/SDH data line rate of 622 MHz by 4 to synchronize with a 155 MHz system clock, or the 12.5 Gbits/s SuperFEC data line rate of 781 MHz can be divided by 8 to 98 MHz system clock or by 8 x 4/5 to provide a 78 MHz system data rate.
Table 1. ORCA ORLI10G--Available FPGA Logic Device ORLI10G PFU Rows 36 PFU Columns 36 Total PFUs 1296 User I/Os* 432 LUTs 10,368 EBR Blocks 12 EBR Bits (k) 111 Usable Gates (k) 380--800
* 192 user I/Os for the 416 PBGAM package and 316 user I/Os for the 680 PBGAM package are available out of the 432 possible user I/Os. Note: The embedded core and interface are not included in the above gate counts. The usable gate counts range from a logic-only gate count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. Embedded block RAM (EBR) is counted as four gates per bit, plus each block has an additional 25k gates. 7k gates are used for each PLL and 50k gates for the embedded system bus and microprocessor interface logic. Both the EBR and PLLs are conservatively utilized in the gate count calculations.
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Table of Contents
Contents Page Contents Page
Introduction..................................................................1 Embedded Function Features .....................................4 Intellectual Property Features......................................4 Programmable Features..............................................4 Programmable Logic System Features .......................6 Description...................................................................7 FPSC Definition ........................................................7 FPSC Overview ........................................................7 FPSC Gate Counting ................................................7 FPGA/Embedded Core Interface ..............................7 ORCA Foundry Development System ......................7 FPSC Design Kit .......................................................8 FPGA Logic Overview...............................................8 PLC Logic .................................................................8 Programmable I/O.....................................................9 Routing......................................................................9 System-Level Features..............................................10 Microprocessor Interface ........................................10 System Bus.............................................................10 Phase-Locked Loops ..............................................10 Embedded Block RAM............................................10 Configuration...........................................................11 Additional Information .............................................11 ORLI10G Overview ...................................................11 Device Layout .........................................................11 10G Mode ...............................................................11 2.5G Mode ..............................................................12 Receive Path Details .................................................15 Line Interface ..........................................................15 DeMUX ...................................................................15 Onboard Receive PLLs...........................................15 Transmit Path Details ................................................17 MUX ........................................................................17 Onboard Transmit PLLs..........................................17 Line Interface ..........................................................17 ORLI10G Demultiplexer (Rx) Detail ..........................19 ORLI10G Multiplexer (Tx) Detail ...............................25 ORLI10G Embedded PLLs........................................31
ORLI10G Embedded Programmable PLLs Specifications ........................................................... 32 ORLI10G Reset Requirements................................. 32 Line Interface Circuit Specifications ......................... 33 Power Supply Decoupling LC Circuit ..................... 33 XGMII ORCA 4E Receive Analysis .......................... 34 XGMII Considerations ............................................ 34 Absolute Maximum Ratings...................................... 35 Recommended Operating Conditions ...................... 35 Embedded Core LVDS I/O ....................................... 36 LVDS Receiver Buffer Requirements..................... 37 Timing Characteristics .............................................. 38 Receive Input Data Interface.................................. 38 Transmit STS-48/STS-192 (2.5G/10G) Data Outputs ..................................................................... 39 Input/Output Buffer Measurement Conditions (Non-LVDS Buffer) ................................................... 40 LVDS Buffer Characteristics..................................... 41 Termination Resistor .............................................. 41 LVDS Driver Buffer Capabilities ............................. 41 Pin Information ......................................................... 42 Package Pinouts .................................................... 47 Package Thermal Characteristics Summary ............ 65 JA ........................................................................ 65 JC ........................................................................ 65 JC ........................................................................ 65 JB ........................................................................ 65 FPSC Maximum Junction Temperature ................. 65 Package Thermal Characteristics............................. 66 Heat Sink Vendors for BGA Packages ..................... 66 Package Coplanarity ................................................ 66 Package Parasitics ................................................... 67 Package Outline Diagrams....................................... 68 Terms and Definitions ............................................ 68 416-Pin PBGAM..................................................... 69 680-Pin PBGAM..................................................... 70 Hardware Ordering Information ................................ 71 Software Ordering Information ................................. 71
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Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Table of Contents (continued)
List of Figures Page List of Tables Page
Figure 1. ORCA ORLI10G Block Diagram ...............13 Figure 2. 10G (Single-Channel) and 2.5G (Quad-Channel) Modes .........................................14 Figure 3. ORLI10G Embedded Core Receive Path Diagram .........................................................16 Figure 4. ORLI10G Embedded Core Transmit Path Diagram .................................................................18 Figure 5. Demultiplexer Output Data Structure ........20 Figure 6. Demultiplexer Serial-to-Parallel Conversion--Divide by 8, 10G Mode .....................21 Figure 7. Demultiplexer Serial-to-Parallel Conversion--Divide by 4, 10G Mode .....................22 Figure 8. Demultiplexer Serial-to-Parallel Conversion--Divide by 8, 2.5G Mode ....................23 Figure 9. Demultiplexer Serial-to-Parallel Conversion--Divide by 4, 2.5G Mode ....................24 Figure 10. Multiplexer Input Data Structure ..............26 Figure 11. Multiplexer Parallel-to-Serial Conversion--Divide by 8, 10G Mode .....................27 Figure 12. Multiplexer Parallel-to-Serial Conversion--Divide by 4, 10G Mode .....................28 Figure 13. Multiplexer Parallel-to-Serial Conversion--Divide by 8, 2.5G Mode ....................29 Figure 14. Multiplexer Parallel-to-Serial Conversion--Divide by 4, 2.5G Mode ....................30 Figure 15. ORLI10G Programmable PLL Block Diagram .................................................................31 Figure 16. Sample Power Supply Filter Network for Analog LI Power Supply Pins .................................33 Figure 17. Simplified XGMII Block Diagram .............34 Figure 18. Receive Input Data Timing ......................38 Figure 19. Transmit Output Data Timing ..................39 Figure 20. ac Test Loads ..........................................40 Figure 21. Output Buffer Delays ...............................40 Figure 22. Input Buffer Delays ..................................40 Figure 23. LVDS Driver and Receiver and Associated Internal Components ..............................................41 Figure 24. LVDS Driver and Receiver ......................41 Figure 25. LVDS Driver ............................................41 Figure 26. Package Parasitics ..................................67
Table 1. ORCA ORLI10G--Available FPGA Logic ... 1 Table 2. Programmable PLL Specifications ............ 32 Table 3. ORLI10G Reset Requirements .................. 32 Table 4. HSTL Input Requirements to FPGA .......... 35 Table 5. Absolute Maximum Ratings ....................... 35 Table 6. Recommended Operating Conditions ....... 35 Table 7. Driver dc Data ............................................ 36 Table 8. Driver ac Data ............................................ 36 Table 9. Driver Power Consumption ........................ 36 Table 10. Receiver ac Data ..................................... 37 Table 11. Receiver Power Consumption ................. 37 Table 12. Receiver dc Data ..................................... 37 Table 13. LVDS Operating Parameters ................... 37 Table 14. Receive Data Input Timing ...................... 38 Table 15. Transmit Data Output Timing .................. 39 Table 16. FPGA Common-Function Pin Description ............................................................ 42 Table 17. FPSC Function Pin Description ............... 45 Table 18. Embedded Core/FPGA Interface Signal Description ............................................................ 46 Table 19. ORCA Programmable I/Os Summary ...... 47 Table 20. PBGA Pinout Table ................................. 48 Table 21. ORCA ORLI10G Plastic Package Thermal Guidelines ............................................... 66 Table 22. Heat Sink Vendors ................................... 66 Table 23. . ORCA ORLI10G Package Parasitics .... 67 Table 24. Device Type Options ............................... 71 Table 25. Temperature Options ............................... 71 Table 26. Package Options ..................................... 71 Table 27. Package Matrix (Speed Grade) ............... 71
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Embedded Function Features
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Quad 2.5 Gbits/s SONET/SDH to 10 Gbits/s SONET/ SDH MUX/deMUX functions. 66-bit word aligner and 64b/66b receive path decoder, 64b/66b transmit path encoder, and 66b/64b transmit path conversion for Ethernet overhead bits.
Provides a line interface-to-interface with various system standards such as OC-192/STM-64 SONET/ SDH, Quad OC-48/STM-16 10 Gbits/s Ethernet, and 10 Gbits/s OTN (digital wrapper/strong FEC) or 12.5 Gbits/s SuperFEC. Embedded PLLs with programmable M/N multiplication/division values provide for flexible data rate conversion between line side and system side. Line side provides for 16-bit LVDS data with multiple line frequencies supported up to 850 MHz, depending on system standard. Line side interface, including timing and jitter specifications, compliant to OIF 99.102.5 standard. Receive side interface can be split into four separate asynchronous 2.5 Gbits/s interfaces (4-bit LVDS data interface for each) with a separate clock for each for transfer to the FPGA logic. Data and clock rates divided by 4 or 8 for use in FPGA logic. Direct interface to Agere's 10 Gbits/s MUX (TTRN0110G) and deMUX (TRCV0110G) or 12.5 Gbits/s MUX (TTRN01126) and deMUX (TRCV01126) for XSBI, SFI-4, or SuperFEC applications. LVDS I/Os compliant with EIA(R)-644 support hot insertion. All embedded LVDS I/Os include both input and output on-board termination to allow high-speed operation. Low-power LVDS buffers.
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Programmable Features
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High-performance programmable logic: -- 0.16 m 7-level metal technology. -- Internal performance of >250 MHz. -- 400k usable system gates. -- Meets multiple I/O interface standards. -- 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance. Traditional I/O selections: -- LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V) I/Os. -- Per pin-selectable I/O clamping diodes provide 3.3 V PCI compliance. -- Individually programmable drive capability: 24 mA sink/12 mA source, 12 mA sink/6 mA source, or 6 mA sink/3 mA source. -- Two slew rates supported (fast and slew limited). -- Fast-capture input latch and input flip-flop (FF) latch for reduced input setup time and zero hold time. -- Fast open-drain drive capability. -- Capability to register 3-state enable signal. -- Off-chip clock drive capability. -- Two input function generator in output path. New programmable high-speed I/O: -- Single-ended: GTL, GTL+, PECL, SSTL3/2 (class I & II), HSTL (Class I, III, IV), ZBT, and DDR. -- Double-ended: LVDS, bused-LVDS, LVPECL. Programmable parallel termination (100 ) also supported for these I/Os. -- Customer-defined: ability to substitute arbitrary standard cell I/O to meet fast-moving standards. New capability to (de)multiplex I/O signals: -- New DDR on both input and output at rates up to 311 MHz (622 MHz effective rate). -- New 2x and 4x downlink and uplink capability per I/O (i.e., 50 MHz internal to 200 MHz I/O).
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Intellectual Property Features
Programmable logic provides a variety of yet-to-be standardized interface functions, including the following IP core functions:
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10 Gbits/s Ethernet as defined by IEEE 802.3ae: -- XGMII for interfacing to 10 Gbits/s Ethernet MACs. XGMII is a 156 MHz double data rate parallel short-reach (typically less than 2 in.) interconnect interface. -- Elastic store buffers for clock domain transfer to/ from the XGMII interface. -- X59 + X39 + X1 scrambler/descrambler for 10 Gbits/s Ethernet. -- 64b/66b encoders/decoders for 10 Gbits/s Ethernet. POS-PHY4 interface for 10 Gbits/s SONET/SDH and OTN systems and some 10 Gbits/s Ethernet systems.
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Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
-- 1--256 x 36 (dual-port, one read/one write). -- 1--1k x 9 (dual-port, one read/one write). -- 2--512 x 9 (dual-port, one read/one write for each). -- 2 RAMs with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). -- Supports joining of RAM blocks. -- Two 16 x 8-bit content addressable memory (CAM) support. -- FIFO 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9. -- Constant multiply (8 x 16 or 16 x 8). -- Dual variable multiply (8 x 8).
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Programmable Features (continued)
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Enhanced twin-quad programmable function unit (PFU): -- Eight 16-bit look-up tables (LUTs) per PFU. -- Nine user registers per PFU, one following each LUT, and organized to allow two nibbles to act independently, plus one extra for arithmetic operations. -- New register control in each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. -- New LUT structure allows flexible combinations of LUT4, LUT5, new LUT6, 4 1 MUX, new 8 1 MUX, and ripple mode arithmetic functions in the same PFU. -- 32 x 4 RAM per PFU, configurable as single- or dual-port. Create large, fast RAM/ROM blocks (128 x 8 in only eight PFUs) using the SLIC decoders as bank drivers. -- Soft-wired LUTs (SWL) allow fast cascading of up to three levels of LUT logic in a single PFU through fast internal routing which reduces routing congestion and improves speed. -- Flexible fast access to PFU inputs from routing. -- Fast-carry logic and routing to all four adjacent PFUs for nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out.
Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, microprocessor interface (MPI), embedded RAM blocks, and embedded standard cell blocks with 100 MHz bus performance. Included are built-in system registers that act as the control and status center for the device. Built-in testability: -- Full boundary scan (IEEE 1149.1 and draft 1149.2 JTAG) for the programmable I/Os only. -- Programming and readback through boundaryscan port compliant to IEEE Draft 1532:D1.7. -- TS_ALL testability function to 3-state all I/O pins. -- New temperature-sensing diode. Improved built-in clock management with programmable phase-locked loops (PPLLs) provides optimum clock modification and conditioning for phase, frequency, and duty cycle from 20 MHz up to 420 MHz. Multiplication of input frequency up to 64x and division of input frequency down to 1/64x possible. New cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route. This feature also enables compliance with many setup/hold and clock to out I/O specifications and may provide reduced ground bounce for output buses by allowing flexible delays of switching output buffers.
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Abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over previous architectures. Hierarchical routing optimized for both local and global routing with dedicated routing resources. This results in faster routing times with predictable and efficient performance. SLIC provides eight 3-stable buffers, up to a 10-bit decoder, and PALTM-like and-or-invert (AOI) in each programmable logic cell. New 200 MHz embedded quad-port RAM blocks, two read ports, two write ports, and two sets of byte lane enables. Each embedded RAM block can be configured as: -- 1--512 x 18 (quad-port, two read/two write) with optional built-in arbitration.
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Programmable Logic System Features
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PCI local bus compliant for FPGA I/Os. Improved PowerPC (R)/PowerQUICC 860 and PowerPC/PowerQUICC II MPC8260 high-speed synchronous microprocessor interface can be used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the FPGA logic, RAMs, and embedded standard-cell blocks. Glueless interface to synchronous PowerPC processors with userconfigurable address space provided. New embedded AMBATM specification 2.0 AHB system bus (ARM (R) processor) facilitates communication among the microprocessor interface, configuration logic, embedded block RAM, FPGA logic, and embedded standard cell blocks. Variable-size bused readback of configuration data capability with the built-in microprocessor interface and system bus. Internal, 3-state, and bidirectional buses with simple control provided by the SLIC. New clock routing structures for global and local clocking significantly increases speed and reduces skew (<200 ps for OR4E4). New local clock routing structures allow creation of localized clock trees.
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Two new edge clock structures allow up to six highspeed clocks on each edge of the device for improved setup/hold and clock to out performance. New double-data rate (DDR) and zero-bus turnaround (ZBT) memory interfaces support the latest high-speed memory interfaces. New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced-speed internal logic. ORCA Foundry development system software. Supported by industry-standard CAE tools for design entry, synthesis, simulation, and timing analysis. Meets universal test and operations PHY interface for ATM (UTOPIA) Levels 1, 2, and 3 as well as POS-PHY3. Also meets proposed specifications for UTOPIA Level 4 and POS-PHY4 for 10 Gbits/s interfaces. Meets POS-PHY3 (2.5 Gbits/s) and POS-PHY4 (10 Gbits/s) interface standards for packet-overSONET as defined by the Saturn Group.
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Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
signals off-chip, this on-chip interface is much faster and requires less power. All of the delays for the interface are precharacterized and accounted for in the ORCA Foundry Development System. Series 4 based FPSCs expand this interface by providing a link between the embedded block and the multimaster 32-bit system bus in the FPGA logic. This system bus allows the core easy access to many of the FPGA logic functions, including the embedded block RAMs and the microprocessor interface. Clock spines also can pass across the FPGA/embedded core boundary. This allows for fast, low-skew clocking between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the FPGA as a system. For even greater system flexibility, FPGA configuration RAMs are available for use by the embedded core. This allows for user-programmable options in the embedded core, in turn allowing for greater flexibility. Multiple embedded core configurations may be designed into a single device with user-programmable control over which configurations are implemented, as well as the capability to change core functionality simply by reconfiguring the device.
Description
FPSC Definition
FPSCs, or field-programmable system chips, are devices that combine field-programmable logic with ASIC or mask-programmed logic on a single device. FPSCs provide the time to market and the flexibility of FPGAs, the design effort savings of using soft intellectual property (IP) cores, and the speed, design density, and economy of ASICs.
FPSC Overview
Agere's Series 4 FPSCs are created from Series 4 ORCA FPGAs. To create a Series 4 FPSC, several columns of programmable logic cells (see FPGA Logic Overview section for FPGA logic details) are added to an embedded logic core. Other than replacing some FPGA gates with ASIC gates, at greater than 10:1 efficiency, none of the FPGA functionality is changed--all of the Series 4 FPGA capability is retained: embedded block RAMs, MPI, PCMs, boundary scan, etc. The columns of programmable logic are replaced at the right of the device, allowing pins from the replaced columns to be used as I/O pins for the embedded core. The remainder of the device pins retain their FPGA functionality. The embedded cores can take many forms and generally come from Agere's ASIC libraries. Other offerings allow customers to supply their own core functions for the creation of custom FPSCs.
ORCA Foundry Development System
The ORCA Foundry development system is used to process a design from a netlist to a configured FPGA. This system is used to map a design onto the ORCA architecture and then place and route it using ORCA Foundry's timing-driven tools. The development system also includes interfaces to, and libraries for, other popular CAE tools for design entry, synthesis, simulation, and timing analysis. The ORCA Foundry development system interfaces to front-end design entry tools and provides the tools to produce a configured FPGA. In the design flow, the user defines the functionality of the FPGA at two points in the design flow: design entry and the bit stream generation stage. Recent improvements in ORCA Foundry allow the user to provide timing requirement information through logical preferences only; thus, the designer is not required to have physical knowledge of the implementation.
FPSC Gate Counting
The total gate count for an FPSC is the sum of its embedded core (standard-cell/ASIC gates) and its FPGA gates. Because FPGA gates are generally expressed as a usable range with a nominal value, the total FPSC gate count is sometimes expressed in the same manner. Standard-cell ASIC gates are, however, 10 to 25 times more silicon-area efficient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with a much larger gate count.
FPGA/Embedded Core Interface
The interface between the FPGA logic and the embedded core has been enhanced to allow for a greater number of interface signals than on previous FPSC architectures. Compared to bringing embedded core Agere Systems Inc.
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Description (continued)
Following design entry, the development system's map, place, and route tools translate the netlist into a routed FPGA. A floor planner is available for layout feedback and control. A static timing analysis tool is provided to determine design speed, and a back-annotated netlist can be created to allow simulation and timing. Timing and simulation output files from ORCA Foundry are also compatible with many third-party analysis tools. A bit stream generator is then used to generate the configuration data which is loaded into the FPGAs internal configuration RAM, embedded block RAM, and/or FPSC memory. When using the bit stream generator, the user selects options that affect the functionality of the FPGA. Combined with the front-end tools, ORCA Foundry produces configuration data that implements the various logic and routing options discussed in this data sheet.
FPSC Design Kit
Development is facilitated by an FPSC design kit which, together with ORCA Foundry and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an FPSC implementation. Included in the kit are the FPSC configuration manager, Synopsys Smart Model (R), and complete online documentation. The kit's software couples with ORCA Foundry, providing a seamless FPSC design environment. More information can be obtained by visiting the ORCA website or contacting a local sales office, both listed on the last page of this document.
The architecture consists of four basic elements: programmable logic cells (PLCs), programmable I/O cells (PIOs), embedded block RAMs (EBRs), and systemlevel features. These elements are interconnected with a rich routing fabric of both global and local wires. An array of PLCs are surrounded by common interface blocks which provide an abundant interface to the adjacent PLCs or system blocks. Routing congestion around these critical blocks is eliminated by the use of the same routing fabric implemented within the programmable logic core. Each PLC contains a PFU, SLIC, local routing resources, and configuration RAM. Most of the FPGA logic is performed in the PFU, but decoders, PAL-like functions, and 3-state buffering can be performed in the SLIC. The PIOs provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplexing, uplink and downlink functions, and other functions on two output signals. Large blocks of 512 x 18 quadport RAM complement the existing distributed PFU memory. The RAM blocks can be used to implement RAM, ROM, FIFO, multiplier, and CAM. Some of the other system-level functions include the MPI, PLLs, and the embedded system bus (ESB).
PLC Logic
Each PFU within a PLC contains eight 4-input (16-bit) LUTs, eight latches/FFs, and one additional flip-flop that may be used independently or with arithmetic functions. The PFU is organized in a twin-quad fashion; two sets of four LUTs and FFs that can be controlled independently. Each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects. LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be configured as a synchronous 32 x 4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable clock polarity, clock enables, and local set/reset.
FPGA Logic Overview
The ORCA Series 4 architecture is a new generation of SRAM-based programmable devices from Agere. It includes enhancements and innovations geared toward today's high-speed systems on a single chip. Designed with networking applications in mind, the Series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. ORCA Series 4 devices contain many new patented enhancements and are offered in a variety of packages and speed grades. The hierarchical architecture of the logic, clocks, routing, RAM, and system-level blocks create a seamless merge of FPGA and ASIC designs. Modular hardware and software technologies enable system-on-chip integration with true plug-and-play design implementation. 8
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
The Series 4 I/O logic has been enhanced to include modes for speed uplink and downlink capabilities. These modes are supported through shift register logic, which divides down incoming data rates or multiplies up outgoing data rates. This new logic block also supports high-speed DDR mode requirements where data is clocked into and out of the I/O buffers on both edges of the clock. The new programmable I/O cell allows designers to select I/Os which meet many new communication standards, permitting the device to hook up directly without any external interface translation. They support traditional FPGA standards as well as high-speed, singleended, and differential-pair signaling (as shown in Table 1). Based on a programmable, bank-oriented I/O ring architecture, designs can be implemented using 3.3 V, 2.5 V, 1.8 V, and 1.5 V referenced output levels.
Description (continued)
The SLIC is connected from PLC routing resources and from the outputs of the PFU. It contains eight 3-state, bidirectional buffers, and logic to perform up to a 10-bit AND function for decoding, or an AND-OR with optional INVERT to perform PAL-like functions. The 3-state drivers in the SLIC and their direct connections from the PFU outputs make fast, true, 3-state buses possible within the FPGA, reducing required routing and allowing for real-world system performance.
Programmable I/O
The Series 4 PIO addresses the demand for the flexibility to select I/Os that meet system interface requirements. I/Os can be programmed in the same manner as in previous ORCA devices, with the additional new features that allow the user the flexibility to select new I/O types that support high-speed interfaces. Each PIO contains four programmable I/O pads and is interfaced through a common interface block to the FPGA array. The PIO is split into two pairs of I/O pads with each pair having independent clock enables, local set/reset, and global set/reset. On the input side, each PIO contains a programmable latch/flip-flop which enables very fast latching of data from any pad. The combination provides for very low setup requirements and zero hold times for signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the signals without explicitly building a demultiplexer with a PFU. On the output side of each PIO, an output from the PLC array can be routed to each output flip-flop, and logic can be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals and other functions of two output signals. The output FF, in combination with output signal multiplexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The output buffer signal can be inverted, and the 3-state control can be made active-high, active-low, or always enabled. In addition, this 3-state signal can be registered or nonregistered.
Routing
The abundant routing resources of the Series 4 architecture are organized to route signals individually or as buses with related control signals. Both local and global signals utilize high-speed buffered and nonbuffered routes. One PLC segmented (x1), six PLC segmented (x6), and bused half-chip (xHL) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance. Eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be sourced from dedicated I/O pads, PLLs, or the PLC logic. Secondary and edge-clock routing are available for fast regional clock or control signal routing for both internal regions and on device edges. Secondary clock routing can be sourced from any I/O pin, PLLs, or the PLC logic. The improved routing resources offer great flexibility in moving signals to and from the logic core. This flexibility translates into an improved capability to route designs at the required speeds when the I/O signals have been locked to specific pins.
Agere Systems Inc.
9
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
System-Level Features
The Series 4 also provides system-level functionality by means of its microprocessor interface, embedded system bus, quad-port embedded block RAMs, universal programmable phase-locked loops, and the addition of highly tuned networking specific phaselocked loops. These functional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in today's high-speed networking systems.
Phase-Locked Loops
Up to eight PLLs are provided on each Series 4 device, with four PLLs generally provided for FPSCs. Programmable PLLs can be used to manipulate the frequency, phase, and duty cycle of a clock signal. Each PPLL is capable of manipulating and conditioning clocks from 20 MHz to 420 MHz. Frequencies can be adjusted from 1/8x to 8x, the input clock frequency. Each programmable PLL provides two outputs that have different multiplication factors but can have the same phase relationships. Duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. An automatic input buffer delay compensation mode is available for phase delay. Each PPLL provides two outputs that can have programmable (12.5% steps) phase differences. Additional highly tuned and characterized, dedicated phase-locked loops (DPLLs) are included to ease system designs. These DPLLs meet ITU-T G.811 primaryclocking specifications and enable system designers to very tightly target specified clock conditioning not traditionally available in the universal PPLLs. Initial DPLLs are targeted to low-speed networking DS1 and E1, and also high-speed SONET/SDH networking STS-3 and STM-1 systems.
Microprocessor Interface
The MPI provides a glueless interface between the FPGA and PowerPC microprocessors. Programmable in 8-, 16-, and 32-bit interfaces with optional parity to the Motorola (R) PowerPC 860 bus, it can be used for configuration and readback, as well as for FPGA control and monitoring of FPGA status. All MPI transactions utilize the Series 4 embedded system bus at 66 MHz performance. A system-level microprocessor interface to the FPGA user-defined logic following configuration, through the system bus, including access to the embedded block RAM and general user-logic, is provided by the MPI. The MPI supports burst data read and write transfers, allowing short, uneven transmission of data through the interface by including data FIFOs. Transfer accesses can be single beat (1 x 4 bytes or less), 4-beat (4 x 4 bytes), 8-beat (8 x 2 bytes), or 16-beat (16 x 1 bytes).
Embedded Block RAM
New 512 x 18 quad-port RAM blocks are embedded in the FPGA core to significantly increase the amount of memory and complement the distributed PFU memories. The EBRs include two write ports, two read ports, and two byte lane enables which provide four-port operation. Optional arbitration between the two write ports is available, as well as direct connection to the high-speed system bus. Additional logic has been incorporated to allow significant flexibility for FIFO, constant multiply, and two-variable multiply functions. The user can configure FIFO blocks with flexible depths of 512k, 256k, and 1k, including asynchronous and synchronous modes and programmable status and error flags. Multiplier capabilities allow a multiple of an 8-bit number with a 16-bit fixed coefficient or vice versa (24-bit output), or a multiply of two 8-bit numbers (16-bit output). On-the-fly coefficient modifications are available through the second read/write port. Two 16 x 8-bit CAMs per embedded block can be implemented in single match, multiple match, and clear modes. The EBRs can also be preloaded at device configuration time.
System Bus
An on-chip, multimaster, 8-bit system bus with 1-bit parity facilitates communication among the MPI, configuration logic, FPGA control, and status registers, embedded block RAMs, as well as user logic. Utilizing the AMBA specification Rev 2.0 AHB protocol, the embedded system bus offers arbiter, decoder, master, and slave elements. The system bus control registers can provide control to the FPGA such as signaling for reprogramming, reset functions, and PLL programming. Status registers monitor INIT, DONE, and system bus errors. An interrupt controller is integrated to provide up to eight possible interrupt resources. Bus clock generation can be sourced from the microprocessor interface clock, configuration clock (for slave configuration modes), internal oscillator, user clock from routing, or port clock (for JTAG configuration modes). 10
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
The ORLI10G is a line interface device that contains an FPGA base array, a 10 Gbits/s line interface block, and programmable PLLs to do the overhead clock rate conversions on a single monolithic chip. The embedded portion includes:
s
System-Level Features (continued)
Configuration
The FPGAs functionality is determined by internal configuration RAM. The FPGAs internal initialization/configuration circuitry loads the configuration data at powerup or under system control. The configuration data can reside externally in an EEPROM or any other storage media. Serial EEPROMs provide a simple, low pin-count method for configuring FPGAs. The RAM is loaded by using one of several configuration modes. Supporting the traditional master/slave serial, master/slave parallel, and asynchronous peripheral modes, the Series 4 also utilizes its microprocessor interface and embedded system bus to perform both programming and readback. Daisy chaining of multiple devices and partial reconfiguration are also permitted. Other configuration options include the initialization of the embedded-block RAM memories and FPSC memory as well as system bus options and bit stream error checking. Programming and readback through the JTAG (IEEE 1149.2) port is also available meeting in-system programming (ISP) standards (IEEE 1532 Draft).
Line Interface: This consists of a 16-bit LVDS receive data bus and a 16-bit LVDS transmit bus operating up to 850 Mbits/s per input/output pair. Each 4-bit LVDS I/O has a high-speed LVDS clock (operating up to 850 MHz) associated with it. MUX/deMUX: This performs the MUXing and deMUXing between the high-speed line interface data operating at the line rate and system data operating at 1/4 or 1/8 the line rate. On-board PLLs: This is used to align system-side data with the line-side data, which is at a slightly higher data bandwidth than the system data because of the addition of overhead due to encoding.
s
s
Figure 1 shows the ORLI10G block diagram.
10G Mode
The ORLI10G can operate in one of two data modes: 10G mode or Quad 2.5G mode. In 10G (or single-channel) mode, all 16 LVDS transmit data outputs are assumed to be one data bus with one LVDS clock provided off chip for the data. Likewise, all 16 LVDS receive data inputs are assumed to be one data bus with one LVDS input clock provided for the data. Transmit Path
Additional Information
Contact your local Agere representative for additional information regarding the ORCA Series 4 FPGA devices, or visit our website at: http://www.agere.com/orca
ORLI10G Overview
Device Layout
The ORLI10G FPSC provides a high-speed transmit and receive line interface combined with FPGA logic. The device is based on the 1.5 V OR4E4 FPGA. The ORLI10G consists of an embedded backplane transceiver core and a full OR4E4 36x36 FPGA array.
In 10G mode, the transmit data from the FPGA logic is passed to the embedded core as a single 128- or 64-bit bus. An off-chip transmit reference clock is divided down in the core by 8 (for 128-bit to 16-bit MUX) or by 4 (for 64-bit to 16-bit MUX). All four transmit clock outputs are therefore synchronized.
Agere Systems Inc.
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
ORLI10G Overview (continued)
Receive Path The 16-bit receive data is deMUXed in the embedded core to a single 128-bit or 64-bit data bus and passed to the FPGA logic. The lowest-order LVDS input clock (rx_clk_in[0]) is used as the receive clock for all 16 data bits (the other three LVDS input clock pairs should be tied low). This clock is divided down in the core by 8 (for 16-bit to 128-bit deMUX) or by 4 (for 16-bit to 64-bit deMUX) and passed to the FPGA logic with the data. The ORLI10G supports transmit and receive data rates up to 850 Mbits/s. Therefore, the total data rate for this mode is 850 Mbits/s x 16 or 13.6 Gbits/s.
16-bit buses. A separate clock for each of the four busses is also passed to the core. An off-chip transmit reference clock is divided down in the core by 8 (for each 32 to 8-bit MUX) or by 4 (for each 16 to 4 MUX). This divided down clock is used to resynchronize the output data and clocks. All four transmit clock outputs are therefore synchronized. Receive Path Each of the four 4-bit receive data buses are deMUXed in the embedded core to one of four independent 32- or 16-bit data buses and passed to the FPGA logic. The four receive clock inputs are divided down in the core by 8 (for each 4- to 32-bit deMUX) or by 4 (for each 4- to 16-bit deMUX), and each divided clock is passed to the FPGA logic with its associated data bus. All four data paths act as separate data interfaces that are asynchronous to each other. The ORLI10G supports transmit and receive data rates up to 850 Mbits/s. Therefore, the total data rate each of the quad channels is 850 Mbits/s x 4 or 3.4 Gbits/s. Figure 2 shows a representation of the 10G and 2.5G modes in both transmit and receive directions.
2.5G Mode
In 2.5G (or quad-channel) mode, the 16 LVDS transmit data outputs are assumed to be four 4-bit data buses with four LVDS clocks provided off chip for each data bus. Likewise, the 16 LVDS receive data inputs are assumed to be four independent 4-bit data buses with four LVDS asynchronous input clocks provided for each data bus. Transmit Path In 2.5G mode, the transmit data from the FPGA logic is passed to the embedded core as four separate 32- or
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Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
ORLI10G Overview (continued)
EMBEDDED CORE
FPGA LOGIC (400K GATES)
TRANSMIT PLLs
TXCLK (167 MHz--78 MHz)
2
REFERENCE CLOCK TRANSMIT DATA 16 x 622 OR 16 x 645 OR 16 x 667 OR 16 x 781 Mbits/s TRANSMIT CLOCK
64:16 MUX OR 128:16 MUX
64-bit OR 128-bit
SYSTEM INTERFACE: -- POS-PHY 4 -- XGMII -- 156 MHz PECL (OC-48/STM-16 SONET/SDH) -- USER DEFINED
RECEIVE PLLs RECEIVE DATA 16 x 622 OR 16 x 645 OR 16 x 667 OR 16 x 781 Mbits/s
RXCLK (167 MHz--78 MHz)
2
16:64 DEMUX OR 16:128 DEMUX
64-bit OR 128-bit
FOUR 2.5 Gbit RXCLKs
1018(F)
Figure 1. ORCA ORLI10G Block Diagram
Agere Systems Inc.
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
ORLI10G Overview (continued)
10G MODE FPGA DATA DEMUX 128 or 64 DIV BY 8 OR DIV BY 4 CLOCK 1 2 TX[1:2]VCOP 128 OR 64 DIV BY 8 DIV BY 4 FPGA DATA MUX 16
RECEIVE PATH CORE LVDS DATA 16 RX_CLK_IN[0] RX_CLK_IN[31:1] UNUSED
TRANSMIT PATH CORE LVDS DATA
TX_CLK_IN REFERENCE CLOCK
2.5G MODE RECEIVE PATH CORE LVDS DATA 4 LVDS CLOCK 1 LVDS DATA 4 LVDS CLOCK 1 LVDS DATA 4 LVDS CLOCK 1 LVDS DATA 4 LVDS CLOCK 1 DEMUX DIV BY 8 OR DIV BY 4 DEMUX DIV BY 8 OR DIV BY 4 DEMUX DIV BY 8 OR DIV BY 4 DEMUX DIV BY 8 OR DIV BY 4 FPGA DATA 32 OR 16 CLOCK 1 DATA 32 OR 16 CLOCK 1 DATA 32 OR 16 CLOCK 1 DATA 32 OR 16 CLOCK 1 4 TX_CLK8_IN[3:0] DIV BY 8 DIV BY 4 TX_CLK_OUT[3:0] LVDS CLOCKS TX_CLK_IN REFERENCE CLOCK
1335(F)
TRANSMIT PATH FPGA DATA MUX 32 OR 16 CORE LVDS DATA 4
DATA MUX 32 OR 16
LVDS DATA 4
DATA MUX 32 OR 16
LVDS DATA 4
DATA MUX 32 OR 16
LVDS DATA 4
Figure 2. 10G (Single-Channel) and 2.5G (Quad-Channel) Modes
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Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
10G (or single channel): The demultiplexer converts the incoming 16 bits of data at 622 Mbits/s to 850 Mbits/s into 128 bits at 78 Mbits/s to 106 Mbits/s. The incoming clocks are divided by 8. 2.5G (or quad channel): The demultiplexer converts the incoming four bits of data at 622 Mbits/s to 850 Mbits/s into 32 bits at 78 Mbits/s to 106 Mbits/s. The associated clock is also divided by 8. This is repeated four times with each 4-bit data/clock group assumed to be asynchronous to the others.
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Receive Path Details
In the receive path, the ORLI10G embedded core can be broken down into three sections: the high-speed line interface, the demultiplexer, and the receive-side onboard PLLs. Note that both transmit and receive PLLs are in addition to the four programmable PLLs (PPLLs) in the FPGA portion of the ORLI10G.
Line Interface
In the receive path, 16-bit data and associated clocks are inputs to the line interface. Typical data rates are expected to range from 622 Mbits/s to 850 Mbits/s for most applications. The 16-bit LVDS input data bus is actually composed of four 4-bit data buses with one clock for each 4-bit data bus. In the 10G mode, all four input clocks are tied together internal to the device and driven by the lowest-order input clock. In 2.5G mode, the four clocks may be asynchronous to each other. The ORLI10G uses LVDS (low-voltage differential signaling) drivers/receivers, which are intended to provide point-to-point connection between the ORLI10G and optical transceiver (MUX/deMUX) parts. The LVDS inputs are hot-swap compatible and can connect to other vendor's LVDS I/O buffers. The LVDS inputs are terminated with a 100 resistor to improve performance. The receive line interface on the ORLI10G can connect to devices that are compliant to either the XSBI standard or the SFI-4 standard. The major difference for these standards is that for XSBI (IEEE 802.3ae version 2.1), the least significant bit [0] is received first after deserialization by the external deMUX device, whereas SFI-4 receives the most significant bit first. In some cases, bits [15:0] on the ORLI10G should be connected to bits [0:15] on the device to which the ORLI10G device interfaces to. An example of this is the PCS IP core in the ORLI10G when the ORLI10G is connected to an XSBI version 2.1 device. It should be noted that IEEE 802.3ae version 3.1 swaps XSBI so that the most significant bit is received first, thus requiring that bits [0:15] on the ORLI10G be connected directly to bits [0:15] on the XSBI device.
Divide-by-4
10G (or single channel): The demultiplexer converts the incoming 16 bits of data at 622 Mbits/s to 850 Mbits/s into 64 bits at 156 Mbits/s to 212 Mbits/s. The incoming clocks are divided by 4. 2.5G (or quad channel): The demultiplexer converts the incoming 4 bits of data at 622 Mbits/s to 850 Mbits/s into 16 bits at 156 Mbits/s to 212 Mbits/s. The associated clock is also divided by 4. This is repeated four times with each 4-bit data/clock group assumed to be asynchronous to the others.
Onboard Receive PLLs
The function of the onboard PLLs is to align the system data with the line data which will be at a slightly higher rate owing to the addition of the overhead bits. There are two PLLs on the receive path. The input to the first PLL, RX1_PLL (see Figure 3), is the divided down lowest-order clock from the demultiplexer. The RX1_PLL generates a clock with a user-defined frequency ratio of M/N to the divided clock. This clock would generally be used to compensate for different data rates due to overhead bits. M and N can independently be set from 1 to 8. The RX2_PLL also takes its input from the divided down clock and is used to provide a balanced divided clock across the FPGA-embedded core interface. Both PLLs have delay loops which compensate for routing delays to the embedded core/FPGA logic interface for minimum clock skew. In addition, the user can specify an additional skew on each clock in increments of 1/8 the clock period. The selection of the deMUX width (and corresponding clock division value), the RX1_PLL M and N values, and the additional skew for RX1_PLL and RX2_PLL are specified by the user in a GUI interface provided in the ORLI10G design kit. A detailed block diagram of the receive path in shown in Figure 3. 15
DeMUX
The demultiplexer takes the high-speed line data and clocks and converts the data and clock to rates appropriate for transfer to the FPGA logic. The demultiplexer supports two modes of operation:
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Divide-by-8
Agere Systems Inc.
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Receive Path Details (continued)
ORLI10G CORE DATA RX_DAT_IN 16 128 TO 16 MUX OR 64 TO 16 MUX FPGA LOGIC DIVIDE BY 8 MODE RX_DAT_OUT[127:96] RX_DAT_OUT[95:64] OR RX_DAT_OUT[63:32] RX_DAT_OUT[31:0] RX_ENB_OUT[3:0] RX_DAT_OUT[47:32] RX_DAT_OUT[15:0] RX_ENB_OUT[3:0] CLOCK RX_CLK_IN 4 DIVIDE BY 4 MODE RX_DAT_OUT[111:96] RX_DAT_OUT[79:64]
DIV BY 8 OR DIV BY 4 DIV BY 8 OR DIV BY 4 DIV BY 8 OR DIV BY 4 DIV BY 8 OR DIV BY 4
RX_CLK8_OUT[0]
RX_CLK8_OUT[1]
RX_CLK8_OUT[2]
RX_CLK8_OUT[3]
RX1_PLL (M/N) RX2_PLL (X1)
RX1_VCOP (X M/N CLOCK) RX1_VCO RX_LOCK RX2_VCOP (X 1 CLOCK) RX2_VCO
1333(F)
Figure 3. ORLI10G Embedded Core Receive Path Diagram
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Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
The selection of the MUX width (and corresponding clock division value), the TX1_PLL M and N values, and the additional skew for TX1_PLL and TX2_PLL are specified by the user in a GUI interface provided in the ORLI10G design kit. A detailed block diagram of the transmit path in shown in Figure 4. In 10 Gbit mode, either TX1_VCOP or TX2_VCOP must be used to clock TX_DAT_IN[127:0] that is transmitted to the embedded block. These PLLs can also be bypassed, where the divided transmit reference clock is sent directly to the FPGA. In 2.5 Gbit mode, TX_CLK8_IN[3:0] is used to clock data transmitted to the embedded block.
Transmit Path Details
In the transmit path, the ORLI10G embedded core can be broken down into three sections: the multiplexer, the transmit side onboard PLLs, and the high-speed line interface. Note that both transmit and receive PLLs are in addition to the four programmable PLLs (PPLLs) in the FPGA portion of the ORLI10G.
MUX
The multiplexer takes data from the FPGA logic and multiplexes the data to rates for transfer by the highspeed line interface. The multiplexer supports two modes of operation:
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Line Interface
In the transmit path, 16-bit data and associated clocks are outputs from the line interface. Typical data rates are expected to range from 622 Mbits/s to 850 Mbits/s for most applications. The 16-bit LVDS output data bus is actually composed of four 4-bit data buses with one clock for each 4-bit data bus. On the transmit side, these clocks will all be synchronized. The ORLI10G uses LVDS (low-voltage differential signaling) drivers/receivers, which are intended to provide pointto-point connection between the ORLI10G and optical transceiver (MUX/deMUX) parts. The LVDS drivers are hot-swap compatible and can connect to other vendor's LVDS I/O buffers. The LVDS drivers are terminated with a 100 resistor to improve performance. The transmit line interface on the ORLI10G can connect to devices that are compliant to either the XSBI standard or the SFI-4 standard. The major difference for these standards is that for XSBI, the least significant bit [0] is transferred first after serialization by the external MUX device, whereas SFI-4 transmits the most significant bit first. In some cases, bits [15:0] on the ORLI10G should be connect to bits [0:15] on the device to which the ORLI10G device interfaces to. An example of this is the PCS IP core in the ORLI10G when the ORLI10G is connected to an XSBI version 2.1 device. It should be noted that IEEE 802.3ae version 3.1 swaps XSBI so that the most significant bit is transferred first, thus requiring that bits [0:15] on the ORLI10G be connected directly to bits [0:15] on the XSBI device.
Multiplex-by-8
The multiplexer converts the incoming 128 bits of data at 78 Mbits/s to 106 Mbits/s into 16 bits at 622 Mbits/s to 850 Mbits/s. The incoming transmit reference clock is divided by 8.
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Multiplex-by-4
10G (or single channel): The multiplexer converts the incoming 64 bits of data at 156 Mbits/s to 212 Mbits/s into 16 bits at 622 Mbits to 850 Mbits/s. The transmit reference clock is divided by 4.
Onboard Transmit PLLs
The function of the onboard PLLs is to align the system data with the line data which will be at a slightly higher rate owing to the addition of the overhead bits. There are two PLLs on the transmit path. The input to the first PLL, TX1_PLL (see Figure 4), is the divided down transmit reference clock from the multiplexer. The TX1_PLL generates a clock with a user-defined frequency ratio of M/N to the divided clock. This clock would generally be used to compensate for different data rates due to overhead bits. M and N can be independently set from 1 to 8. The TX2_PLL also takes its input reference from the divided down reference clock and is used to provide a balanced divided clock across the FPGA-embedded core interface. Both PLLs have delay loops which compensate for routing delays to the embedded core/FPGA logic interface for minimum clock skew. In addition, the user can specify an additional skew on each clock in increments of 1/8 the clock period.
Agere Systems Inc.
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Transmit Path Details (continued)
FPGA LOGIC DIVIDE BY 8 MODE TX_DAT_IN[127:96] TX_DAT_IN[95:64] OR TX_DAT_IN[63:32] TX_DAT_IN[31:0] TX_ENB_IN[3:0] TX_DAT_IN[47:32] TX_DAT_IN[15:0] TX_ENB_IN[3:0] 10G TX_CLK8_IN[0] TX_CLK8_IN[1] TX_CLK8_IN[2] TX_CLK8_IN[3] 2.5G 10G 2.5G 10G 2.5G 10G TRANSMIT REFERENCE CLOCK TX_CLK_IN 2.5G DIVIDE BY 4 MODE TX_DAT_IN[111:96] TX_DAT_IN[79:64] 128 TO 16 MUX OR 64 TO 16 MUX ORLI10G CORE DATA TX_DAT_OUT 16 CLOCK TX_CLK8_OUT 4
TX1_VCOP (X M/N CLOCK) TX1_VCO TX_LOCK TX2_VCOP (X 1 CLOCK) TX2_VCO
TX1_PLL (M/N) TX2_PLL (X1)
DIV BY 8 OR DIV BY 4
1332(F)
Figure 4. ORLI10G Embedded Core Transmit Path Diagram
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Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
The high-speed demultiplexer converts the incoming data as blocks of bytes. The byte boundaries of incoming data are unknown and are irrelevant to this module. This data is then interleaved to the 128/64 bits of output data, depending on the mode of operation (divideby-4/divide-by-8). In 10G mode, the output data is assigned the retimed 128/64 bits of data from the first stage of line interface registered at the input clock [0]. In 2.5G mode, the output data is assigned four concatenated 32/16 bits of data from the first stage of line interface registered at input clocks [0 to 3]. The interleaving is done at bit level because the serial-to-parallel converter operates on bits of incoming data. In 10G mode, it is assumed that all the incoming 16 bits of data are synchronized to the input clock [0]. This block also generates the clock enables used by the output line interface (multiplexer) module for registering the data on the high-speed clock. These enables along with the enables from other clocks are selected through the high-speed clock MUX for the output line interface block.
ORLI10G Demultiplexer (Rx) Detail
The demultiplexer module converts the incoming 16 bits of data at 622 MHz/850 MHz into 128 bits of data at 78 MHz/106 MHz or 64 bits of data at 156 MHz/212 MHz and sends it to the FPGA logic. It has been implemented in two stages: the first stage converts each incoming bit into a byte stream and the second stage bit interleaves these bytes into 128/64 bits, depending upon the mode of operation. The low-speed clocks are generated by this block. These clocks are then driven back to this block from the low-speed clock tree network. Functionally, the demultiplexer architecture consists of three blocks: the serial to parallel conversion, the counters, and the interleaving. The first stage of the line interface module (demultiplexer) converts each incoming bit of data into a byte stream on a divided-by-8 clock. The data is first registered on the rising edge of the clock input. The clock dividers also runs parallel to data shift (serial to parallel), on the rising edge of the input clock. An enable is created when a complete byte is taken in. This enable signal is used to register the serial-to-parallel converted data at the high-speed input clock. This ensures that the data can be safely transferred to the low-speed clock. This data is then transferred to the divided clock, allowing a timing margin of approximately half the divided clock period.
Agere Systems Inc.
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
ORLI10G Demultiplexer (Rx) Detail (continued)
Figure 5 shows the valid data output bits from the demultiplexer in each of the four modes (divide-by-8, 10G and 2.5G modes, and divide-by-4, 10G and 2.5G modes). Figure 6--Figure 9 show the demultiplexer input data and clock waveforms and output clock, enable, and data waveforms for all four modes.
128 RX_DAT_OUT 16 OR 32 96 RX_DAT_IN 16 RX_CLK_IN 4 4x4 TO 32 DEMUX OR 4x4 TO 16 DEMUX RX_DAT_OUT 16 OR 32 64 RX_DAT_OUT 16 OR 32 32 RX_DAT_OUT 16 OR 32 10G 2.5G / 8 MODE UNDEFINED SINGLE CHANNEL 10G 2.5G / 4 MODE 0 16 48 80 112
CHANNEL 3 CHANNEL 2 CHANNEL 1 CHANNEL 0
1338(F)
Figure 5. Demultiplexer Output Data Structure
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Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
ORLI10G Demultiplexer (Rx) Detail (continued)
RX_CLK_IN0
RX_CLK8_OUT0 (RX_CLK8_OUT[1:3] = 0)
RX_ENB8_OUT0 (RX_ENB8_OUT[1:3] = 0)
RX_DAT_IN 0 0 4 8 C1 9 0 8 [15:12]
0
RX_DAT_IN 0 1 5 9 D3 B2A 0 [11:8]
RX_DAT_IN 0 2 6 AE5 D4C 0 [7:4]
RX_DAT_IN 037BF7F6E 0 [3:0]
RX_DAT_OUT [127:96]
00000000
01234567
0
RX_DAT_OUT [95:64]
00000000
89ABCDEF
0
RX_DAT_OUT [63:32]
00000000
13579BDF
0
RX_DAT_OUT [31:0]
00000000
02468ACE
0
1340(F)
Figure 6. Demultiplexer Serial-to-Parallel Conversion--Divide by 8, 10G Mode
Agere Systems Inc.
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
ORLI10G Demultiplexer (Rx) Detail (continued)
RX_CLK_IN0
RX_CLK8_OUT0 (RX_CLK8_OUT[1:3] = 0)
RX_ENB8_OUT0 (RX_ENB8_OUT[1:3] = 0)
RX_DAT_IN [15:12]
0
0
4
8
C
1
9
0
8
0
RX_DAT_IN [11:8]
0
1
5
9
D
3
B
2
A
0
RX_DAT_IN [7:4]
0
2
6
A
E
5
D
4
C
0
RX_DAT_IN [3:0]
0
3
7
B
F
7
F
6
E
0
RX_DAT_OUT [63:32]
00000000
01234567
13579BDF
0
RX_DAT_OUT [31:0]
00000000
89ABCDEF
02468ACE
0
1341(F)
Figure 7. Demultiplexer Serial-to-Parallel Conversion--Divide by 4, 10G Mode
22
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
ORLI10G Demultiplexer (Rx) Detail (continued)
RX_CLK_IN[0:3]
RX_CLK8_OUT[0:3]
RX_ENB8_OUT[3:0]
RX_DAT_IN [15:12]
001234567
0
RX_DAT_IN [11:8]
0 8 9 ABCDEF 0
RX_DAT_IN [7:4]
0 1 3 5 7 9 BDF 0
RX_DAT_IN [3:0]
0 0 2 4 6 8 ACE 0
RX_DAT_OUT [127:96]
00000000
01234567
0
RX_DAT_OUT [95:64]
00000000
89ABCDEF
0
RX_DAT_OUT [63:32]
00000000
13579BDF
0
RX_DAT_OUT [31:0]
00000000
02468ACE
0
1342(F)
Figure 8. Demultiplexer Serial-to-Parallel Conversion--Divide by 8, 2.5G Mode
Agere Systems Inc.
23
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
ORLI10G Demultiplexer (Rx) Detail (continued)
RX_CLK_IN[3:0]
RX_CLK8_OUT[3:0]
RX_ENB8_OUT[3:0]
RX_DAT_IN [15:12]
0
0
1
2
3
4
5
6
7
0
RX_DAT_IN [11:8]
0
8
9
A
B
C
D
E
F
0
RX_DAT_IN [7:4]
0
1
3
5
7
9
B
D
F
0
RX_DAT_IN [3:0]
0
0
2
4
6
8
A
C
E
0
RX_DAT_OUT [111:96]
0000
0123
4567
0
RX_DAT_OUT [79:64]
0000
89AB
CDEF
0
RX_DAT_OUT [47:32]
0000
1357
9BDF
0
RX_DAT_OUT [15:0]
0000
0246
8ACE
0
1343(F)
Figure 9. Demultiplexer Serial-to-Parallel Conversion--Divide by 4, 2.5G Mode
24
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
core, thus removing the need to supply TX_ENB8_IN0 when that mode is selected. A second new option for the version 2 ORLI10G devices will synchronize the TX_ENB8_IN0 enable with the divided version of TX_CLK_IN in the embedded core to simplify timing. In both 2.5G and 10G modes, the TX_CLK_OUT[3:0] clock outputs from the ORLI10G are provided for transferring each 4 bits of data per clock. For both 2.5G modes and 10G modes, all data to be transmitted to the embedded core must be frequency locked to the TX_CLK_IN signal. Thus, the divided version of this clock found at the embedded core interface should always be used to transfer data from the FPGA logic to the embedded core. In 2.5G modes, this same clock signal should also be used to generate the enable signals as discussed previously. These clock signals are available from the TX PLL outputs (TX1_VCO, TX1_VCOP, TX2_VCO, TX2_VCOP). Figure 10 shows the valid data input bits to the multiplexer in each of the four modes (divide-by-8, 10G and 2.5G modes, and divide-by-4, 10G and 2.5G modes). Figure 11--Figure 14 show the multiplexer input transmit reference clock, data, enable, and clock waveforms and output clock and data waveforms for all four modes. In version 2 of the ORLI10G device, additional capabilities are added to the Multiplexer block. The first allows the clock inputs TX_CLK8_IN[3:0] to be optionally generated in the embedded core in 2.5G mode, as is done for 10G mode for version 1. The second option allows all enables TX_ENB8_IN[3:0] to be generated in the embedded core for both 2.5G and 10 G modes. The third option allows the enable inputs TX_ENB8_IN[3:0] to continue to be used, but they are re-synchronized in the embedded core before being used. All options allow for simplification of the FPGA to embedded core interface. If none are selected, the ORLI10G defaults to version 1 compatible operation.
ORLI10G Multiplexer (Tx) Detail
The multiplexer module converts the incoming 128 bits of data from the FPGA logic at 78 MHz/106 MHz or 64 bits of data from the FPGA logic at 156 MHz/212 MHz into 16 bits of data at 622 MHz/850 MHz. It has been implemented as two stages. The first stage deinterleaves each incoming byte into a different byte stream that can be serially output on the output data pins. The second stage outputs these bytes into 16 bits or four groups of 4 bits, depending upon the mode of operation. Functionally, the multiplexer architecture consists of three blocks: the parallel-to-serial conversion, the counters, and the deinterleaving. For 2.5G divide-by-8 mode, the first stage of the line interface module deinterleaves each incoming byte of data into a different byte stream on the 78 MHz/106 MHz (TX_CLK8_IN[3:0]) clock. This data is then registered on the rising edge of the 622 MHz/850 MHz (TX_CLK_IN) clock at the falling edge of the 78 MHz/106 MHz clock. The enable inputs (TX_ENB8_IN[3:0]) are used to transfer data from the low-speed clock to the high-speed clock, as well as synchronizing the counters of parallel-to-serial conversion which are running at the high-speed clock. For 2.5G divide-by-4 mode, the first stage of the line interface module deinterleaves each incoming byte of data into a different byte stream on the 156 MHz/212 MHz (TX_CLK8_IN[3:0]) clock. This data is then registered on the rising edge of the 622 MHz/850 MHz (TX_CLK_IN) clock at the falling edge of the 156 MHz/212 MHz clock. The enable inputs (TX_ENB8_IN[3:0]) are used to transfer data from the low-speed clock to the high-speed clock, as well as synchronizing the counters of parallel-to-serial conversion which are running at the high-speed clock. In 2.5G modes, the enable inputs (TX_ENB8_IN[3:0]) are required to be four (divide by 4) or eight (divide by 8) TX_CLK_IN clock cycles wide. They have to be synchronous to their corresponding TX_CLK8_IN[3:0] clock. Each of these four TX_CLK8_IN[3:0] clocks must also be frequency locked to the TX_CLK_IN signal. In 10G modes, the enable inputs (TX_ENB8_IN[3:0]) are also required to be four (divide by 4) or eight (divide by 8) TX_CLK_IN clock cycles wide. In 10G modes, the other enable inputs (TX_ENB8_IN[3:1]) are unused. Unlike 2.5G modes, this enable is synchronous to a divided version of TX_CLK_IN from the embedded core. In 10G modes, the TX_CLK8_IN[3:0] inputs are not used. For version 2 ORLI10G devices, the enable signal can also optionally be generated automatically in the embedded Agere Systems Inc.
25
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
ORLI10G Multiplexer (Tx) Detail (continued)
128 112 96 80 64 48 32 16 0 TX_DAT_IN 16 OR 32 TX_DAT_OUT TX_DAT_IN 16 OR 32 TX_DAT_IN 16 OR 32 TX_DAT_IN 16 OR 32 4x4 TO 32 DEMUX OR 4x4 TO 16 DEMUX 16 TX_CLK_OUT 4 TRANSMIT REFERENCE CLOCK TX_CLK_IN
10G 2.5G / 8 MODE UNDEFINED SINGLE CHANNEL
10G 2.5G / 4 MODE
CHANNEL 3 CHANNEL 2 CHANNEL 1 CHANNEL 0
1339(F)
Figure 10. Multiplexer Input Data Structure
26
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
ORLI10G Multiplexer (Tx) Detail (continued)
TX_CLK_IN
TX_CLK8_OUT[3:0]
TX_ENB8_IN0
TX_DAT_IN [127:96]
00000000
01234567
0
TX_DAT_IN [95:64]
00000000
89ABCDEF
0
TX_DAT_IN [63:32]
00000000
13579BDF
0
TX_DAT_IN [31:0]
00000000
02468ACE
0
TX_DAT_OUT [15:12]
0
048C1908 0
TX_DAT_OUT [11:8]
0
159D3B2A 0
TX_DAT_OUT [7:4]
0
2 6AE5 D4C 0
TX_DAT_OUT [3:0]
0
37BF7F6E 0
1344(F)
Figure 11. Multiplexer Parallel-to-Serial Conversion--Divide by 8, 10G Mode
Agere Systems Inc.
27
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
ORLI10G Multiplexer (Tx) Detail (continued)
TX_CLK_IN
TX_CLK_OUT[3:0]
TX_ENB8_IN0
TX_DAT_IN [63:32]
00000000
01234567 13579BDF
0
TX_DAT_IN [31:0]
00000000
89ABCDEF 02468ACE
0
TX_DAT_OUT [15:12]
0
048C19080
TX_DAT_OUT [11:8]
0
159D3B2A0
TX_DAT_OUT [7:4]
0
26AE5D4C0
TX_DAT_OUT [3:0]
0
37BF7F6E0
1345(F)
Figure 12. Multiplexer Parallel-to-Serial Conversion--Divide by 4, 10G Mode
28
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
ORLI10G Multiplexer (Tx) Detail (continued)
TX_CLK_IN
TX_CLK8_OUT[3:0]
TX_CLK8_IN[3:0]
TX_ENB8_IN[3:0]
TX_DAT_IN [127:96]
00000000
01234567
0
TX_DAT_IN [95:64]
00000000
89ABCDEF
0
TX_DAT_IN [63:32]
00000000
13579BDF
0
TX_DAT_IN [31:0]
00000000
02468ACE
0
TX_DAT_OUT [15:12]
0
0123 4567
0
TX_DAT_OUT [11:8]
0
8 9 AB CDEF
0
TX_DAT_OUT [7:4]
0
1 3 57 9 BDF
0
TX_DAT_OUT [3:0]
0
0 2 46 8 ACE
0
1346(F)
Figure 13. Multiplexer Parallel-to-Serial Conversion--Divide by 8, 2.5G Mode
Agere Systems Inc.
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
ORLI10G Multiplexer (Tx) Detail (continued)
TX_CLK_IN
TX_CLK_OUT[3:0]
TX_CLK8_IN[3:0]
TX_ENB8_IN[3:0]
TX_DAT_IN [111:96]
0000
0123
4567
0
TX_DAT_IN [79:64]
0000
89AB
CDEF
0
TX_DAT_IN [47:32]
0000
1357
9BDF
0
TX_DAT_IN [15:0]
0000
0246
8ACE
0
TX_DAT_OUT [63:32]
0
012345670
TX_DAT_OUT [31:0]
0
8 9 AB CDEF 0
TX_DAT_OUT [63:32]
0
1 3 5 7 9 B DF 0
TX_DAT_OUT [31:0]
0
0 2 4 6 8 ACE 0
1347(F)
Figure 14. Multiplexer Parallel-to-Serial Conversion--Divide by 4, 2.5G Mode
30
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
ORLI10G Embedded PLLs
The ORLI10G embedded (transmit and receive) PLLs are based on the 4E series FPGA high-speed programmable PLL (HPPLL). The 4E PLL consists of a phase/frequency detector (PFD), a charge pump/filter, a multitap voltage controlled oscillator (VCO), a duty cycle synthesis circuitry, a power regulator, two programmable dividers, phase shift selector multiplexers, a lock signal generator, and a current DAC. A block diagram of the programmable PLL is shown in Figure 15. The receive path RX1_PLL and transmit path TX1_PLL, which can be programmed to create a N/M frequency clock, are based on this design. The receive path RX2_PLL and transmit path TX2_PLL create a X1 clock. This is essentially the same PLL without the M and N divider. The RCKI input to the PLLs comes from an input clock to the ORLI10G that has been divided in frequency by either 4 or 8 (programmable). As shown in Figure 3, RX1_PLL and RX2_PLL are driven by the divided version of RX_CLK_IN0. As shown in Figure 4, TX1_PLL and TX2_PLL are driven by the divided versions of TX_CLK_IN. It should be noted that the speed of the ORLI10G line interface is therefore either 4X or 8X the operating speed of the embedded PLLs. The clock feedback loops for the RX2_PLL and TX2_PLL should be routed from the clock network in the FPGA core so as to compensate for the routing delays to the FPGA logic interface. The source to the TX2_FBCKI or RX2_FBCKI inputs must come from an FPGA clock network driven by the VCO output (otherwise any phase shifting on VCOP is removed by the feedback loops). In this way, the clock skew at the embedded core/FPGA logic boundary is zero for the receive and transmit PLLs. All PLLs include a phase shift selector which allows phase shift adjustments of each clock in increments of 1/8 the period of the clock. This phase shifted output is available on the VCOP output of the PLL. All functions of the embedded core PLLs are user controlled through a GUI provided with the ORLI10G Design Kit software.
RCKO M DIVIDER LOCK GENERATOR
RCKI
LOCK VCOP
M<5:0> PFD N<5:0>
CHARGE PUMP AND FILTER
VCO
PHASE SELECT
TX2_FBCKI RX2_FBCKI
N DIVIDER
VCO
SEL<2:0> BYPASS
1331(F)
Figure 15. ORLI10G Programmable PLL Block Diagram
Agere Systems Inc.
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
ORLI10G Embedded Programmable PLLs Specifications
Table 2. Programmable PLL Specifications Parameters VDD15 VDD33 Operating Temperature Input Clock Frequency Input Duty Cycle Input Clock Jitter Requirement Input Jitter Transfer Output Clock Frequency Output Duty Cycle dc Power Consumption Total On Current (dc) Total Off Current (dc) Cycle to Cycle Jitter (p-p) Period Jitter (p-p) Duty Cycle Jitter (p-p) VCO Output vs. VCOP Output Jitter Lock Time Frequency Multiplication (TX1_PLL and RX1_PLL) Frequency Division (TX1_PLL and RX1_PLL) Duty Cycle Adjust of Output Clock(s) Delay Adjust of Output Clock Phase Shift Between VCO and VCOP Min 1.425 3.0 -40 60 30 -- -- 60 45 -- -- -- -- TBD TBD -- -- Nom Max Unit V V C MHz % UIp-p UIp-p MHz % mW mA pA UIp-p UIp-p UIp-p ps S -- -- % degrees degrees
1.5 1.575 3.3 3.6 -- 125 -- 420 -- 70 -- TBD -- TBD -- 420 50 55 50 -- 14 -- 30.0 -- <0.02 TBD TBD TBD TBD TBD -- TBD <50 -- 2x, 3x, 4x, 5x, 6x, 7x, 8x 1/8x, 1/7x, 1/6x, 1/5x, 1/4x, 1/3x, 1/2x 12.5, 25, 37.5, 50, 62.5, 75, 87.5 0, 45, 90, 135, 180, 225, 270, 315 0, 45, 90, 135, 180, 225, 270, 315
Notes: Multiplication and division values can both be used on one PLL output (example 3/4x). For more information, see the Series 4 PLL Application Note.
ORLI10G Reset Requirements
Both the embedded core portion and the FPGA portion are reset at powerup. The embedded core is also reset, as shown in Table 3, based on other conditions. For version 1 ORLI10G devices, these resets are all asynchronous and must be held in reset for at least 8 ns. For version 2, the resets can also optionally be set to be asynchronous on with synchronous release. Table 3 also shows the conditions upon which the I/O are 3-stated. Table 3. ORLI10G Reset Requirements Condition Powerup FPGA Configuration TS_ALL Pin = 1 RESET_TX Pin = 1 RESET_RX Pin = 1 PWRON Pin = 1 TX MUX Block Reset Reset -- Reset -- -- TX PLL Reset Reset -- Reset -- Powerdown RX DeMUX Block Reset Reset -- -- Reset -- RX PLL Reset Reset -- -- Reset Powerdown Embedded I/O 3-state Active 3-state Active Active Active
Typically, the following reset sequence should be followed for the ORLI10G:
s s s
Place the device in reset by driving RESET_TX = 1, RESET_RX = 1, and by placing the FPGA portion into reset. Release the embedded core from reset by driving RESET_TX = 0 and RESET_RX = 0. Agere Systems Inc.
Release the FPGA portion from reset. 32
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Line Interface Circuit Specifications
Power Supply Decoupling LC Circuit
The 622 MHz--850 MHz line interface macro contains both analog and digital circuitry. The line interface function, for example, is implemented as primarily a digital function, but it relies on a conventional analog phase-locked loop to provide its divided clocks. The internal analog phase-locked loop contains a voltage-controlled oscillator. This circuit will be sensitive to digital noise generated from the rapid switching transients associated with internal logic gates and parasitic inductive elements. Generated noise that contains frequency components beyond the bandwidth of the internal phase-locked loop (about 3 MHz) will not be attenuated by the phase-locked loop and will impact bit error rate directly. Thus, separate power supply pins are provided for these critical analog circuit elements. Additional power supply filtering in the form of an LC pi filter section will be used between the power supply source and these device pins as shown in Figure 16. The corner frequency of the LC filter is chosen based on the power supply switching frequency, which is between 100 kHz and 300 kHz in most applications. Capacitors C1 and C2 are large electrolytic capacitors to provide the basic cutoff frequency of the LC filter. For example, the cutoff frequency of the combination of these elements might fall between 5 kHz and 50 kHz. Capacitor C3 is a smaller ceramic capacitor designed to provide a low-impedance path for a wide range of high-frequency signals at the analog power supply pins of the device. The physical location of capacitor C3 must be as close to the device lead as possible. Multiple instances of capacitors C3 can be used if necessary. The recommended filter for the HSI macro is shown below: L = 4.7 H, RL = 1 , C1 = 0.01 F, C2 = 0.01 F, C3 = 4.7 F.
FROM POWER SUPPLY SOURCE
L
TO DEVICE VDD33, VDD33_A[7:4]
+
C1
+
C2
+
C3 VSS, VSS33_A[7:4]
5-9344(F).a
Figure 16. Sample Power Supply Filter Network for Analog LI Power Supply Pins
Agere Systems Inc.
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
XGMII ORCA 4E Receive Analysis
XGMII Considerations
The stringent 10 Gbit media independent interface specifications from the IEEE 802.3ae standards are met in the FPGA side of the ORLI10G device. Figure 17 and Table 4 show a simplified block diagram for this interface and the receive voltage levels for the HSTL inputs to the ORLI10G device. Further details are available in the Series 4 I/O application note. The ORLI10G device meets the 480 ps input setup time and 480 ps input hold time requirements for the XGMII receiver inputs into the FPGA side of the FPSC with the embedded IO DDR cells on the FPGA side of the FPSC. The PLLs are not used on input due to this being a forward clocked interface. The ORLI10G meets the clock-to-out specification on the XGMII DDR outputs by using the output shift register to produce a nonduty cycle-dependent output. An embedded output DDR capability is also available. The output clock is then centered around this data eye using internal PLLs. There are two considerations to note about the pinout location of the XGMII input clocks: 1. The XGMII input clocks must be located at the C pad of the programmable I/O cells (PICs). In the pinout tables, the pads are labeled on a pin-by-pin basis. For example, a pin whose pad is referenced as PL1C can be used as an XGMII input clock, but pins referenced as PL1A, PL1B, or PL1D cannot be used as an XGMII input clock. 2. The XGMII input data pins can be no further then six PICs away from the XGMII input clock pin. This means that in the 416 PBGA package, the clock needs to be driven on two pins to be able to clock in the 32-bit XGMII input data bus. Due to the strict pinout locations mentioned above, when implementing a XGMII interface, the microprocessor interface (MPI) will not be available in the 416 PBGA package.
VDDIO VDD15
CLOCK DDR DATA
SYSTEM INTERFACE
HSTL VDDIO = 1.5 V NOM
CLOCK DDR DATA
HSTL VDDIO = 1.5 V NOM
VREF VDDIO / 2
CUSTOMER DEVICE
ORLI10G
1550.a(F)
Figure 17. Simplified XGMII Block Diagram
34
LINE INTERFACE
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
XGMII ORCA 4E Receive Analysis (continued)
Table 4. HSTL Input Requirements to FPGA Inputs VDDIO VIH (min level) VREF VIL (max level) Low 1.4 V 0.88 V 0.68 V 0.48 V Nom 1.5 V 0.95 V 0.75 V 0.55 V High 1.6 V 1.10 V 0.90 V 0.70 V
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. The ORCA Series 4 FPSCs include circuitry designed to protect the chips from damaging substrate injection currents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress. Table 5. Absolute Maximum Ratings Parameter Storage Temperature Power Supply Voltage with Respect to Ground Symbol Tstg VDD33 VDDIO VDD33, VDD33_A VDD15 Input Signal with Respect to Ground Signal Applied to High-impedance Output Maximum Package Body Temperature VIN -- -- Min -65 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -- Max 150 4.2 4.2 2.0 2.0 VDDIO + 0.3 VDDIO + 0.3 220 Unit C V V V V V V C
Recommended Operating Conditions
Table 6. Recommended Operating Conditions Parameter Power Supply Voltage with Respect to Ground Symbol VDD33 VDDIO VDD33, VDD33_A VDD15 Input Voltages Junction Temperature VIN TJ Min 2.7 1.4 1.4 1.4 -0.3 -40 Max 3.6 3.6 1.6 1.6 VDDIO + 0.3 125 Unit V V V V V C
Notes: The maximum recommended junction temperature (TJ) during operation is 125 C. Timing parameters in this data sheet and ORCA Foundry are characterized under tighter voltage and temperature conditions than the recommended operating conditions in this table. The internal PLLs operate from the VDD33 and VDD33_A power supplies. These power supplies should be well isolated from all other power supplies on the board for proper operation.
Agere Systems Inc.
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Embedded Core LVDS I/O
Table 7. Driver dc Data* Parameter Output Voltage High, VOA or VOB Output Voltage Low, VOA or VOB Output Differential Voltage Output Offset Voltage Output Impedance, Differential RO Mismatch Between A and B Change in Differential Voltage Between Complementary States Change in Output Offset Voltage Between Complementary States Output Current Output Current Power-off Output Leakage Symbol VOH VOL VOD VOS Ro RO VOD VOS ISA, ISB ISAB |Ixa|, |Ixb| Test Conditions RLOAD = 100 1% RLOAD = 100 1% RLOAD = 100 1% RLOAD = 100 1% VCM = 1.0 V and 1.4 V VCM = 1.0 V and 1.4 V RLOAD = 100 1% RLOAD = 100 1% Driver shorted to GND Drivers shorted together VDD = 0 V VPAD, VPADN = 0 V--2.5 V Min -- 0.925 0.25 1.125* 80 -- -- -- -- -- --
Typ -- -- -- -- 100 -- -- -- -- -- --
Max 1.475 -- 0.45 120 10 25 25 24 12 10

Unit V V V V % mV mV mA mA mA
1.275
* VDD33 = 3.1 V--3.5 V, VDD15 = 1.4 V--1.6 V, -40 C, and slow-fast process. External reference, REF10 = 1.0 V 3%, REF14 = 1.4 V 3%.
Table 8. Driver ac Data* Parameter VOD Fall Time, 80% to 20% VOD Rise Time, 20% to 80% Differential Skew: |tPHLA - tPLHB| or |tPHLB - tPLHA| Channel-to-channel Skew: |tpDIFFm - tpDIFFn| Propagation Delay Time Symbol tF tR tSKEW1 Test Conditions ZL = 100 1% CPAD = 3.0 pF, CPAD = 3.0 pF ZL = 100 1% CPAD = 3.0 pF, CPAD = 3.0 pF Any differential pair on package at 50% point of the transition Any two signals on package at 0 V differential ZL = 100 1% CPAD = 3.0 pF, CPADN = 3.0 pF Min 100 100 -- Max 210 210 50 Unit ps ps ps
tSKEW2 tPLH tPHL
-- 0.54 0.55
-- 1.10 1.09
ps ns ns
* VDD33 = 3.1 V--3.5 V, VDD15 = 1.4 V--1.6 V, -40 C, and slow-fast process.
Table 9. Driver Power Consumption* Parameter Driver dc Power Driver ac Power Symbol PDdc PDac Test Conditions ZL = 100 1% ZL = 100 1% CPAD = 3.0 pF, CPADN = 3.0 pF Min -- -- Max 26.0 64 Unit mW W/MHz
* VDD33 = 3.1 V--3.5 V, VDD15 = 1.4 V--1.6 V, -40 C, and slow-fast process.
36
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Embedded Core LVDS I/O (continued)
LVDS Receiver Buffer Requirements
Table 10. Receiver ac Data* Parameter Pulse-width Distortion Propagation Delay Time With Common-mode Variation (0 V to 2.4 V) Output Rise Time, 20% to 80% Output Fall Time, 80% to 20%
* VDD = 3.1 V--3.5 V, 0 C --125 C, slow-fast process.
Symbol tpwd tPLH tPHL tPD tR tF
Test Conditions VIDTH = 100 mV, 311 MHz CL = 0.5 pF CL = 0.5 pF CL = 0.5 pF CL = 0.5 pF
Min -- 0.60 0.60 -- 150 150
Max 160 1.42 1.47 50 350 350
Unit ps ns ns ps ps ps
Table 11. Receiver Power Consumption* Parameter Receiver dc Power Receiver ac Power
* VDD = 3.1 V--3.5 V, 0 C --125 C, slow-fast process.
Symbol PRdc PRac
Test Conditions dc ac CL = 1.5 pF
Min -- --
Max 20.4 4.5
Unit mW W/MHz
Table 12. Receiver dc Data* Parameter Input Voltage Range, VIA or VIB Input Differential Threshold Input Differential Hysteresis Receiver Differential Input Impedance Symbol VI VIDTH VHYST RIN Test Conditions VGPD < 925 mV dc - 1 MHz VGPD < 925 mV 400 MHz (+VIDTHH) - (-VIDTHL) With build-in termination, center-tapped Min 0.0 -100 -- 80 Typ 1.2 -- -- 100 Max 2.4 100 -- 120 Unit V mV mV
* VDD = 3.1 V--3.5 V, 0 C --125 C, slow-fast process. External reference, REF10 = 1.0 V 3%, REF14 = 1.4 V 3%.
Table 13. LVDS Operating Parameters Parameter Transmit Termination Resistor Receiver Termination Resistor Temperature Range Power Supply VDD33 Power Supply VDD15 Power Supply VSS Test Conditions -- -- -- -- -- -- Min 80 80 -40 3.1 1.4 -- Normal 100 100 -- -- -- 0 Max 120 120 125 3.5 1.6 -- Unit C V V V
Note: Under worst-case operating condition, the LVDS driver will withstand a disabled or unpowered receiver for an unlimited period of time without being damaged. Similarly, when outputs are short-circuited to each other or to ground, the LVDS will not suffer permanent damage. The LVDS driver supports hot insertion. Under a well-controlled environment, the LVDS I/O can drive backplane as well as cable.
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Timing Characteristics
Receive Input Data Interface
Receive STS-48/STS-192 (2.5G/10G) Data Inputs Figure 18 illustrates the timing for the receive STS-48/STS-192 data stream. Both the clock and data pins are lowvoltage differential signal (LVDS) input buffers. The expected clock rate is 622 MHz--850 MHz, and the receive data is clocked on the rising edge of the clock. In 2.5G mode, each of the four channels uses one set of RX_CLK_INn and 4 RX_DAT_INn data pins. In 10G mode, only RX_CLK_IN0 is used, along with the RX_DAT_IN[15:0] pins.
t1 P RX_CLK_IN_[3:0] N t2 N RX_DATA_IN_[15:0] P
5-9085.b (F)
t3
Figure 18. Receive Input Data Timing Table 14. Receive Data Input Timing Symbol Parameter Min t1 t2 t3 Clock Frequency Data Setup Time Required Data Hold Time Required -- 300 300 -1 Max 667 -- -- Min -- 225 225 -2 Max 790 -- -- Min -- 210 210 -3 Max 850 -- -- MHz ps ps Unit
It is recommended that the Rx clock be inverted by crossing the LVDS pin pair, that is, connect the N to the P and the P to the N. This is because the embedded LI requires the Rx data to be centered on the Rx clock, and typically the devices that drive the ORLI10G transmit clock and data on the same clock edge. The timing values for the diagram are given in Table 14.
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Timing Characteristics (continued)
Transmit STS-48/STS-192 (2.5G/10G) Data Outputs
Figure 19 illustrates the timing for the transmit STS-48/STS-192 data stream. Both the clock and data pins are driven with low-voltage differential signal (LVDS) output buffers. The expected clock rate is 622 MHz--850 MHz and the transmit data is clocked out on the rising edge of the clock. In 2.5G mode, each of the four channels uses one set of TX_CLK_OUTn with four TX_DAT_OUTn data pins. In 10G mode, only TX_CLK_OUT[0] is used with the 16 TX_DAT_OUT[15:0] pins. The timing values for the diagram are given in Table 15.
t4 N TX_CLK_OUT[3:0] P
t5 P TX_DAT_OUT[15:0] N t6 t7
5-9089.c(F)
Figure 19. Transmit Output Data Timing Table 15. Transmit Data Output Timing Symbol Parameter Min t4 -- t5 t6 t7 Clock Frequency Duty Cycle Data Delay from Clock Edge Data Rise Time: 20%--80% Data Fall Time: 80%--20% -- 45 -300 100 100 -1 Max 667 55 300 200 200 Min -- 45 -225 100 100 -2 Max 790 55 225 200 200 Min -- 45 -210 100 100 -3 Max 850 55 210 200 200 MHz % ps ps ps Unit
* This requirement is for all sources of the output clocks (e.g., RCLKSI, etc.).
It is recommended that the Tx clock be inverted by crossing the LVDS pin pair, that is, connect the N to the P and the P to the N. This is because the receiving device that will be driven by the ORLI10G typically requires that data be centered around the clock, but the ORLI10G drives both the clock and data from the same clock edge.
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Input/Output Buffer Measurement Conditions (Non-LVDS Buffer)
VCC GND
TO THE OUTPUT UNDER TEST 50 pF TO THE OUTPUT UNDER TEST
1 k
50 pF
A. Load Used to Measure Propagation Delay
Note: Switch to VDD for TPLZ/TPZL; switch to GND for TPHZ/TPZH.
B. Load Used to Measure Rising/Falling Edges
5-3234(F)
Figure 20. ac Test Loads
ts[i]
out[i]
PAD ac TEST LOADS (SHOWN ABOVE) OUT
VDD out[i] VDD/2 VSS PAD 1.5 V OUT 0.0 V TPLL TPHH
5-3233.a(F)
Figure 21. Output Buffer Delays
PAD IN
in[i]
3.0 V PAD IN 1.5 V 0.0 V VDD in[i] VDD/2 VSS TPLL TPHH
5-3235(F)
Figure 22. Input Buffer Delays 40 Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
LVDS Buffer Characteristics
Termination Resistor
The LVDS drivers and receivers operate on a 100 differential impedance, as shown below. External resistors are not required. The differential driver and receiver buffers include termination resistors inside the device package, as shown in Figure 23.
LVDS DRIVER LVDS RECEIVER
100
50 CENTER TAP 50
EXTERNAL DEVICE PINS
5-8703(F)
Figure 23. LVDS Driver and Receiver and Associated Internal Components
LVDS Driver Buffer Capabilities
Under worst-case operating condition, the LVDS driver must withstand a disabled or unpowered receiver for an unlimited period of time without being damaged. Similarly, when its outputs are short-circuited to each other or to ground, the LVDS driver will not suffer permanent damage. Figure 24 illustrates the terms associated with LVDS driver and receiver pairs.
DRIVER
INTERCONNECT
RECEIVER
VOA
A
AA
VIA
VOB
B
BB
VIB
VGPD
5-8704(F)
Figure 24. LVDS Driver and Receiver
CA VOA A RLOAD VOB B CB V VOD = (VOA - VOB)
5-8705(F)
Figure 25. LVDS Driver Agere Systems Inc. 41
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Pin Information
This section describes the pins and signals that perform FPGA-related functions. During configuration, the userprogrammable I/Os are 3-stated and pulled up with an internal resistor. If any FPGA function pin is not used (or not bonded to package pin), it is also 3-stated and pulled up after configuration. Table 16. FPGA Common-Function Pin Description Symbol Dedicated Pins VDD33 VDD15 VDDIO GND PTEMP
RESET
I/O -- 3 V positive power supply.
Description
-- 1.5 V positive power supply for internal logic. -- Positive power supply used by I/O banks. -- Ground supply. I I Temperature-sensing diode pin. Dedicated input. During configuration, RESET forces the restart of configuration and a pull-up is enabled. After configuration, RESET can be used as a general FPGA input or as a direct input, which causes all PLC latches/FFs to be asynchronously set/reset.
CCLK
In the master and asynchronous peripheral modes, CCLK is an output which strobes configuration data in. In the slave or readback after configuration, CCLK is input synchronous O with the data on DIN or D[7:0]. CCLK is an output for daisy-chain operation when the lead device is in master, peripheral, or system bus modes. I I As an input, a low level on DONE delays FPGA start-up after configuration.* O As an active-high, open-drain output, a high level on this signal indicates that configuration is complete. DONE has an optional pull-up resistor.
DONE
PRGM RD_CFG
I I
PRGM is an active-low input that forces the restart of configuration and resets the bound-
ary-scan circuitry. This pin always has an active pull-up. This pin must be held high during device initialization until the INIT pin goes high. This pin always has an active pull-up. During configuration, RD_CFG is an active-low input that activates the TS_ALL function and 3-states all of the I/O. After configuration, RD_CFG can be selected (via a bit stream option) to activate the TS_ALL function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on RD_CFG will initiate readback of the configuration data, including PFU output states, starting with frame address 0. RD_DATA/TDO
CFG_IRQ/MPI_IRQ
O RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configuration data out. If used in boundary-scan, TDO is test data out. O During JTAG, slave, master, and asynchronous peripheral configuration assertion on this CFG_IRQ (active-low) indicates an error or errors for block RAM or FPSC initialization. MPI active-low interrupt request output.
* The FPGA States of Operation section in the ORCA Series 4 data sheet contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Pin Information (continued)
Figure 16. FPGA Common-Function Pin Description (continued)
Symbol M[3:0] I/O I Description During powerup and initialization, M0--M3 are used to select the configuration mode with their values latched on the rising edge of INIT. During configuration, a pull-up is enabled.
Special-Purpose Pins (Can also be used as a general I/O.)
I/O After configuration, these pins are user-programmable I/O.* PLL_CK[0:1,6:7] I/O Dedicated PCM clock pins. These pins are a user-programmable I/O pins if not used by PLLs.
P[TBLR]CLK[1:0] I/O Pins dedicated for the primary clock. These are input pins on the middle of each side with [TC] differential pairing. They may be used as general I/O pins if not needed for clocking purposes. TDI, TCK, TMS I If boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. If boundary-scan is not selected, all boundary-scan functions are inhibited once configuration is complete. Even if boundary-scan is not used, either TCK or TMS must be held at logic 1 during configuration. Each pin has a pull-up enabled during configuration.
I/O After configuration, these pins are user-programmable I/O.* RDY/BUSY/RCLK O During configuration in peripheral mode, RDY/RCLK indicates another byte can be written to the FPGA. If a read operation is done when the device is selected, the same status is also available on D7 in asynchronous peripheral mode. After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.* I/O During the master parallel configuration mode, RCLK is a read output signal to an external memory. This output is not normally used. HDC O High during configuration is output high until configuration is complete. It is used as a control output, indicating that configuration is not complete. I/O After configuration, this pin is a user-programmable I/O pin.* LDC O Low during configuration is output low until configuration is complete. It is used as a control output, indicating that configuration is not complete. I/O After configuration, this pin is a user-programmable I/O pin.* INIT I/O INIT is a bidirectional signal before and during configuration. During configuration, a pull-up is enabled, but an external pull-up resistor is recommended. As an active-low, open-drain output, INIT is held low during power stabilization and internal clearing of memory. As an active-low input, INIT holds the FPGA in the wait-state before the start of configuration. After configuration, this pin is a user-programmable I/O pin.*
CS0, CS1
I
CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor configuration modes. The FPGA is selected when CS0 is low and CS1 is high. During configuration, a pull-up is enabled. RD is used in the asynchronous peripheral configuration mode. A low on RD changes D7 into a status output. As a status indication, a high indicates ready, and a low indicates busy. WR and RD should not be used simultaneously. If they are, the write strobe overrides. This pin is also used as the MPI data transfer strobe.
I/O After configuration, these pins are user-programmable I/O pins.*
RD/MPI_STRB
I
I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*
* The FPGA States of Operation section in the ORCA Series 4 data sheet contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Pin Information (continued)
Figure 16. FPGA Common-Function Pin Description (continued)
Symbol A[17:0] I/O I Description During MPI mode, the A[17:0] are used as the address bus driven by the PowerPC bus master utilizing the least significant bits of the PowerPC 32-bit address.
MPI_BURST MPI_BDIP
MPI_TSZ[1:0]
A[21:0] MPI_ACK MPI_CLK
O During master parallel configuration mode, A[17:0] address the configuration EPROM. In MPI mode, many of the A[n] pins have alternate uses as described below. See the special function blocks section for more MPI information. During configuration, if not in master parallel or an MPI configuration mode, these pins are 3-stated with a pull-up enabled. A[21] is used as the MPI_BURST. It is driven low to indicate a burst transfer is in progress. Driven high indicates that the current transfer is not a burst. A[20] is used as the MPI_BDIP. It is driven by the PowerPC processor; assertion of this pin indicates that the second beat in front of the current one is requested by the master. Negated before the burst transfer ends to abort the burst data phase. A[19:18] are used as the MPI_TSZ[1:0] signals and are driven by the bus master to indicate the data transfer size for the transaction. Set 01 for byte, 10 for half-word, and 00 for word. During master parallel mode A[21:0], address the configuration EPROMs up to 4 Mbytes. If not used for MPI, these pins are user-programmable I/O pins.* O In PowerPC mode MPI operation, this is driven low indicating the MPI received the data on the write cycle or returned data on a read cycle. I
MPI_TEA MPI_RTRY D[31:0]
O O I/O I
DP[3:0]
I/O
DIN
I
I/O DOUT O I/O
This is the PowerPC synchronous, positive-edge bus clock used for the MPI interface. It can be a source of the clock for the embedded system bus. If MPI is used, this can be the AMBA bus clock. A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the internal system bus for the current transaction. This pin requests the MPC860 to relinquish the bus and retry the cycle. Selectable data bus width from 8-, 16-, 32-bit. Driven by the bus master in a write transaction. Driven by MPI in a read transaction. D[7:0] receive configuration data during master parallel, peripheral, and slave parallel configuration modes and each pin has a pull-up enabled. During serial configuration modes, D0 is the DIN input. D[7:3] output internal status for asynchronous peripheral mode when RD is low. After configuration, the pins are user-programmable I/O pins.* Selectable parity bus width from 1, 2, 4-bit, DP[0] for D[7:0], DP[1] for D[15:8], DP[2] for D[23:16], and DP[3] for D[32:24]. After configuration, this pin is a user-programmable I/O pin.* During slave serial or master serial configuration modes, DIN accepts serial configuration data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. During configuration, a pull-up is enabled. After configuration, this pin is a user-programmable I/O pin.* During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained slave devices. Data out on DOUT changes on the rising edge of CCLK. After configuration, DOUT is a user-programmable I/O pin.*
* The FPGA States of Operation section in the ORCA Series 4 data sheet contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Pin Information (continued)
This table describes the I/O signal ports on the embedded core portion of the device. Table 17. FPSC Function Pin Description Symbol Control and Global Pins PLL_BYPASS PWRDN RESET_RX RESET_TX Receive I/O Pins RX_DAT_IN_N<15:0> RX_DAT_IN_P<15:0> RX_CLK_IN_N<3:0> RX_CLK_IN_P<3:0> Transmit I/O Pins TX_DAT_OUT_N<15:0> TX_DAT_OUT_N<15:0> TX_CLK_OUT_N<3:0> TX_CLK_OUT_N<3:0> TX_CLK_IN_N TX_CLK_IN_P LV_REF10 LV_REF14 LV_RESHI LV_RESLO LVCTAP_[6:1] O O O O I I -- -- -- -- -- LVDS data outputs on transmit side. LVDS data outputs on transmit side. LVDS clock outputs on transmit side. LVDS clock outputs on transmit side. LVDS transmit reference clock input. LVDS transmit reference clock input. LVDS reference voltage: 1.0 V 3%. LVDS reference voltage: 1.4 V 3%. LVDS resistor high pin (use 100 to LV_RESLO pin). LVDS resistor low pin (use 100 to LV_RESHI pin). LVDS input centertap (use 0.01 F to GND). I I I I LVDS data input for receive side. LVDS data input for receive side. LVDS clock inputs for receive side. LVDS clock inputs for receive side. I I I I 3.3 V active-high. Enables the bypass mode for both receive and both transmit PLLs. 3.3 V active-high. Power down all LVDS links and both receive and both transmit PLLs. 3.3 V active-high. Resets the receive PLLs and the demultiplexer block. 3.3 V active-high. Resets the transmit PLLs and the multiplexer block. I/O Description
LVDS Input Reference Pins
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Pin Information (continued)
In Figure 18, an output refers to a signal flowing into the FGPA logic (out of the embedded core) and an input refers to a signal flowing out of the FPGA logic (into the embedded core). Table 18. Embedded Core/FPGA Interface Signal Description Pin Name Receive Signals RX_DAT_OUT<127:0> RX_CLK8_OUT<3:0> RX_ENB8_OUT<3:0> RX1_VCOP RX1_VCO RX2_VCOP RX2_VCO RX2_FBCKI RX1_BYPASS RX2_BYPASS RX_LOCK O O O O O O O I I I O Data from demultiplexer on receive side. Divided down clocks on receive side. Data enables on receive side. RX1_PLL output clock on receive side (M/N clock) after phase select. RX1_PLL output clock on receive side (M/N clock) before phase select. RX2_PLL output clock on receive side (x1 clock) after phase select. RX2_PLL output clock on receive side (x1 clock) before phase select. PLL feedback input to RX2_PLL. This allows for the removal of the FPGA clock routing delay. Set to 1 to bypass the RX1 PLL. Set to 1 to bypass the RX2 PLL. Lock signal for RX1_PLL and RX2_PLL. This signal is a logical OR of the lock signal from both PLLs. It is not integrated; thus, small glitches can occur on this signal during normal PLL operation. Data to multiplexer on transmit side. Clocks to multiplexer on transmit side. Data enables on transmit side. TX1_PLL output clock on transmit side (M/N clock) after phase select. TX1_PLL output clock on transmit side (M/N clock) before phase select. TX2_PLL output clock on transmit side (x1 clock) after phase select. TX2_PLL output clock on transmit side (x1 clock) before phase select. PLL feedback input to TX2 PLL. This allows for the removal of the FPGA clock routing delay. Set to 1 to bypass the TX1 PLL. Set to 1 to bypass the TX2 PLL. Lock signal for TX1_PLL and TX2_PLL. This signal is a logical OR of the lock signal from both PLLs. It is not integrated; thus, small glitches can occur on this signal during normal PLL operation. Analog ground for the embedded line interface PLLs. Analog power supply for the embedded line interface PLLs. I/O Description
Transmit Signals TX_DAT_IN<127:0> TX_CLK8_IN<3:0> TX_ENB8_IN[3:0] TX1_VCOP TX1_VCO TX2_VCOP TX2_VCO TX2_FBCKI TX1_BYPASS TX2_BYPASS TX_LOCK I I I O O O O I I I O
Vss_A<7:4> VDD33_A<7:4>
-- --
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Pin Information (continued)
Package Pinouts
Table 14 provides the number of user programmable I/Os available for each available package. Table 20 provides the package pin and pin function for the ORLI10G FPSC and packages. The bond pad name is identified in the PIO nomenclature used in the ORCA Foundry design editor. The bank column provides information as to which output voltage level bank the given pin is in. The group column provides information as to the group of pins the given pin is in. This is used to show which VREF pin is used to provide the reference voltage for single-ended limited-swing I/Os. If none of these buffer types (such as SSTL, GTL, HSTL) are used in a given group, then the VREF pin is available as an I/O pin. When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects). When a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device column for the FPGA. The tables provide no information on unused pads. Table 19. ORCA Programmable I/Os Summary Device User programmable I/O Available programmable differential pair pins FPGA configuration pins FPGA dedicated function pins Core function pins VDD15 VDD33_A VDD33 VDDIO VSS VSS_A LVCTAP for dedicated differential channels Core LV_REF pins Total package pins 416 PBGAM 192 184 7 2 86 28 4 14 21 48 4 6 4 416 680 PBGAM 316 272 7 2 86 84 4 28 44 95 4 6 4 680
It is very important to note the pinout limitations for 10 Gbits/s Ethernet applications. Specifically, the very stringent timing requirements of the XGMII specification coupled with the I/O availability and locations in the 416-pin PBGA requires that the XGMII output pins be located on three sides of the device. This may cause issues with routing the XGMII bus at a board level since the XGMII specification for routing this bus on a board is only 2 in. In addition, the built-in microprocessor interface (MPI) cannot be fully utilized in the 416-pin PBGA and the 680-pin PBGA packages because the implementation of the XGMII interface limits the number of available address and data pins. As shown in the Pair columns in Table 20, differential pairs and physical locations are numbered within each bank (e.g., L19C_A0 is the nineteenth pair in an associated bank). A C indicates complementary differential whereas a T indicates true differential. An _A0 indicates the physical location of adjacent balls in either the horizontal or vertical direction. Other physical indicators are as follows:
s s s s
_A1 indicates one ball between pairs. _A2 indicates two balls between pairs. _D0 indicates balls are diagonally adjacent. _D1 indicates balls are diagonally adjacent separated by one physical ball.
VREF pins, shown in the Pin Description column in Table 20, are associated to the bank and group (e.g., VREF_TL_01 is the VREF for group one of the top left (TL) bank). Agere Systems Inc. 47
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Pin Information (continued)
Table 20. PBGA Pinout Table BM416 BM680 VDDIO Bank
A2 D4 D3 A1 C1 E4 F4 C2 D2 E3 -- -- D1 A25 E2 F3 -- -- -- E1 F2 B1 -- -- G4 H4 G3 F1 G2 -- H2 H3 -- G1 H1 -- -- J4 K4 A26 J3 J2 -- -- J1 K2 A1 E5 E4 -- C1 D1 E2 A2 F4 F3 A3 G5 F5 A18 G4 F2 B1 H5 G3 F1 G2 A33 H4 J5 H3 G1 B3 J4 H2 A34 K5 J3 C2 H1 J2 B2 K4 L5 K3 -- J1 K2 B33 K1 M5 L4 -- -- -- -- -- -- -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) -- 0 (TL) 7 (CL) 7 (CL)
VREF Group
-- -- -- -- -- -- -- -- 7 7 -- 7 7 -- 7 7 -- 8 8 8 8 -- 8 8 9 9 -- 9 9 -- 9 9 -- 10 10 -- 10 10 10 -- 10 10 -- 10 1 1
I/O
Vss VDD33 O VDD15 I I I VDDIO0 I/O I/O VDDIO0 I/O I/O Vss I/O I/O VDDIO0 I/O I/O I/O I/O Vss I/O I/O I/O I/O VDDIO0 I/O I/O Vss I/O I/O VDDIO0 I/O I/O Vss I/O I/O I/O VDD15 I/O I/O Vss I/O I/O I/O
Pin Description
Vss VDD33 PRD_DATA VDD15 PRESET_N PRD_CFG_N PPRGRM_N VDDIO0 PL2D PL2C VDDIO0 PL3D PL3C Vss PL4D PL4C VDDIO0 PL4B PL4A PL5D PL5C Vss PL5B PL5A PL6D PL6C VDDIO0 PL7D PL7C Vss PL8D PL8C VDDIO0 PL9D PL9C Vss PL9A PL10D PL10C VDD15 PL11D PL11C Vss PL11A PL12D PL12C
Additional Function
-- -- RD_DATA/TDO -- RESET_N RD_CFG_N PRGRM_N -- PLL_CK0C/HPPLL PLL_CK0T/HPPLL -- -- VREF_0_07 -- D5 D6 -- -- VREF_0_08 HDC LDC_N -- -- -- TESTCFG D7 -- VREF_0_09 A17/PPC_A31 -- CS0_N CS1 -- -- -- -- -- INIT_N DOUT -- VREF_0_10 A16/PPC_A30 -- -- A15/PPC_A29 A14/PPC_A28
BM416 Pair
-- -- -- -- -- -- -- -- L14C_D0 L14T_D0 -- -- -- -- L15C_D0 L15T_D0 -- -- -- L16C_D0 L16T_D0 -- -- -- L17C_A0 L17T_A0 -- L18C_D0 L18T_D0 -- L19C_A0 L19T_A0 -- L20C_A0 L20T_A0 -- -- L21C_A0 L21T_A0 -- L22C_A0 L22T_A0 -- -- L1C_D0 L1T_D0
BM680 Pair
-- -- -- -- -- -- -- -- L21C_A0 L21T_A0 -- L22C_A0 L22T_A0 -- L23C_D1 L23T_D1 -- L24C_D1 L24T_D1 L25C_A0 L25T_A0 -- L26C_A0 L26T_A0 L27C_D1 L27T_D1 -- L28C_D1 L28T_D1 -- L29C_D1 L29T_D1 -- L30C_A0 L30T_A0 -- -- L31C_D1 L31T_D1 -- L32C_A0 L32T_A0 -- -- L1C_A0 L1T_A0
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ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Pin Information (continued)
Table 20. PBGA Pinout Table (continued) BM416 BM680 VDDIO Bank
K1 -- -- K3 L3 U16 -- -- L4 M4 L2 L1 M1 U17 M3 M2 -- -- N1 N2 AE1 -- -- -- U14 -- -- N3 N4 AE26 -- -- P4 P3 P2 -- -- AF1 AF2 P1 R1 AF25 -- -- R2 L1 M4 N5 L3 L2 B34 N4 P5 M2 M1 M3 N3 N2 C3 P4 P3 R3 R5 N1 P2 C13 R4 P1 R2 -- T2 R1 T5 T4 C22 U5 T3 T1 U3 U1 U4 U2 -- C32 V1 V2 D4 V3 V4 V5 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL)
VREF Group
-- 1 1 1 1 -- 2 2 2 2 -- 2 2 -- 3 3 -- 3 3 3 -- 3 3 3 -- 3 3 4 4 -- 4 4 4 4 -- 4 4 -- -- 5 5 -- 5 5 5
I/O
VDDIO7 I/O I/O I/O I/O Vss I/O I/O I/O I/O VDDIO7 I/O I/O Vss I/O I/O VDDIO7 I/O I/O I/O Vss I/O I/O I/O VDD15 I/O I/O I/O I/O Vss I/O I/O I/O I/O VDDIO7 I/O I/O VDD15 Vss I/O I/O Vss I/O I/O I/O
Pin Description
VDDIO7 PL12B PL12A PL13D PL13C Vss PL13B PL13A PL14D PL14C VDDIO7 PL15D PL15C Vss PL16D PL16C VDDIO7 PL16A PL17D PL17C Vss PL17A PL18D PL18C VDD15 PL18B PL18A PL19D PL19C Vss PL19B PL19A PL20D PL20C VDDIO7 PL20B PL20A VDD15 Vss PL21D PL21C Vss PL21B PL21A PL22D
Additional Function
-- -- -- VREF_7_01 D4 -- -- -- RDY/BUSY_N/RCLK VREF_7_02 -- A13/PPC_A27 A12/PPC_A26 -- -- -- -- -- A11/PPC_A25 VREF_7_03 -- -- -- -- -- -- -- RD_N/MPI_STRB_N VREF_7_04 -- -- -- PLCK0C PLCK0T -- -- -- -- -- A10/PPC_A24 A9/PPC_A23 -- -- -- A8/PPC_A22
BM416 Pair
-- -- -- L2C_A0 L2T_A0 -- -- -- L3C_A0 L3T_A0 -- L4C_A0 L4T_A0 -- L5C_A0 L5T_A0 -- -- L6C_A0 L6T_A0 -- -- -- -- -- -- -- L7C_A0 L7T_A0 -- -- -- L8C_A0 L8T_A0 -- -- -- -- -- L9C_A0 L9T_A0 -- -- -- L10C_A0
BM680 Pair
-- L2C_A0 L2T_A0 L3C_A0 L3T_A0 -- L4C_A0 L4T_A0 L5C_A0 L5T_A0 -- L6C_A0 L6T_A0 -- L7C_A0 L7T_A0 -- -- L8C_A0 L8T_A0 -- -- L9C_A0 L9T_A0 -- L10C_A0 L10T_A0 L11C_A0 L11T_A0 -- L12C_D1 L12T_D1 L13C_D1 L13T_D1 -- L14C_A1 L14T_A1 -- -- L15C_A0 L15T_A0 -- L16C_A0 L16T_A0 L17C_A0
Agere Systems Inc.
49
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Pin Information (continued)
Table 20. PBGA Pinout Table (continued) BM416 BM680 VDDIO Bank
R3 AF26 -- -- -- -- T1 T2 -- -- T4 R4 -- -- U1 U2 T3 V1 V2 U3 -- -- W1 Y1 -- V4 U4 -- -- V3 W2 Y2 W3 -- -- AA1 AA2 -- -- Y3 W4 T16 Y4 AA3 AB1 W4 -- W3 W2 D30 Y1 W5 Y4 W1 Y2 Y5 AA3 D31 AA2 AA1 AB1 Y3 AA4 AB2 AB3 AA5 AB4 AC2 AC1 AC3 AB5 AC4 D33 AD2 AC5 AD3 AE1 AE2 E34 AF1 AD5 AD4 AK4 AE3 AE5 AE4 F33 AF2 AG1 AK5 7 (CL) -- 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 7 (CL) 7 (CL) 7 (CL) 7 (CL) -- 7 (CL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL)
VREF Group
5 -- 5 5 -- 5 6 6 -- 6 6 6 -- 6 6 6 -- 7 7 7 7 7 8 8 -- 8 8 -- 8 8 8 8 8 -- 8 1 1 -- 1 1 1 -- 2 2 --
I/O
I/O VDD15 I/O I/O Vss I/O I/O I/O VDDIO7 I/O I/O I/O Vss I/O I/O I/O VDDIO7 I/O I/O I/O I/O I/O I/O I/O VDDIO7 I/O I/O Vss I/O I/O I/O I/O I/O Vss I/O I/O I/O VDDIO6 I/O I/O I/O Vss I/O I/O VDDIO6
Pin Description
PL22C VDD15 PL23D PL23C Vss PL23A PL24D PL24C VDDIO7 PL24A PL25D PL25C Vss PL25A PL26D PL26C VDDIO7 PL26B PL27D PL27C PL27B PL27A PL28D PL28C VDDIO7 PL29D PL29C Vss PL29A PL30D PL30C PL31D PL31C Vss PL31A PL32D PL32C VDDIO6 PL32A PL33D PL33C Vss PL34D PL34C VDDIO6
Additional Function
VREF_7_05 -- -- -- -- -- PLCK1C PLCK1T -- -- VREF_7_06 A7/PPC_A21 -- -- A6/PPC_A20 A5/PPC_A19 -- -- WR_N/MPI_RW VREF_7_07 -- -- A4/PPC_A18 VREF_7_08 -- A3/PPC_A17 A2/PPC_A16 -- -- A1/PPC_A15 A0/PPC_A14 DP0 DP1 -- -- D8 VREF_6_01 -- -- D9 D10 -- -- VREF_6_02 --
BM416 Pair
L10T_A0 -- -- -- -- -- L11C_A0 L11T_A0 -- -- L12C_A0 L12T_A0 -- -- L13C_A0 L13T_A0 -- -- L14C_D0 L14T_D0 -- -- L15C_A0 L15T_A0 -- L16C_A0 L16T_A0 -- -- L17C_D0 L17T_D0 L18C_D0 L18T_D0 -- -- L1C_A0 L1T_A0 -- -- L2C_D0 L2T_D0 -- L3C_D0 L3T_D0 --
BM680 Pair
L17T_A0 -- L18C_A0 L18T_A0 -- -- L19C_A0 L19T_A0 -- -- L20C_D1 L20T_D1 -- -- L21C_A0 L21T_A0 -- -- L22C_A0 L22T_A0 L23C_A0 L23T_A0 L23C_A0 L23T_A0 -- L23C_A0 L23T_A0 -- -- L24C_D1 L24T_D1 L25C_A0 L25T_A0 -- -- L1C_A0 L1T_A0 -- -- L2C_A0 L2T_A0 -- L3C_A0 L3T_A0 --
50
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Pin Information (continued)
Table 20. PBGA Pinout Table (continued) BM416 BM680 VDDIO Bank
-- -- T17 AB2 AC1 -- -- -- AC2 AB3 -- U10 -- AD1 -- -- -- -- AA4 AB4 U11 -- -- U12 AC3 AD2 R14 AE2 AD3 U15 AC4 T13 AE3 -- -- AC5 AD4 -- -- -- -- AE4 AF3 -- AC6 AF3 AF5 H34 AG2 AF4 AH1 AG3 AL1 AH2 AJ1 AG4 J33 AH3 AG5 AJ2 AL3 AK1 AH4 AJ3 AK2 L34 AH5 AJ4 N13 AK3 AM1 -- AN1 AJ5 N14 AL5 -- AM5 AN4 AM2 AK6 AL6 AK7 N15 AN5 AM6 AN6 AP5 AM4 AL7 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) -- -- 6 (BL) -- -- -- -- -- -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL)
VREF Group
2 2 -- 3 3 3 3 -- 3 3 4 -- 4 4 4 -- 4 4 4 4 -- 4 4 -- -- -- -- -- -- -- -- -- 5 5 -- 5 5 5 -- 5 5 5 5 -- 6
I/O
I/O I/O Vss I/O I/O I/O I/O VDDIO6 I/O I/O I/O Vss I/O I/O I/O VDDIO6 I/O I/O I/O I/O Vss I/O I/O Vss I VDDIO6 VDD15 I/O VDD33 Vss VDD33 VDD15 I/O I/O VDDIO6 I/O I/O I/O Vss I/O I/O I/O I/O VDDIO6 I/O
Pin Description
PL34B PL34A Vss PL35B PL35A PL36D PL36C VDDIO6 PL36B PL36A PL37D Vss PL37B PL37A PL38C VDDIO6 PL38B PL38A PL39D PL39C Vss PL39B PL39A Vss PTEMP VDDIO6 VDD15 LVDS_R VDD33 Vss VDD33 VDD15 PB2A PB2B VDDIO6 PB2C PB2D PB3A Vss PB3C PB3D PB4A PB4B VDDIO6 PB4C
Additional Function
-- -- -- D11 D12 -- -- -- VREF_6_03 D13 -- -- -- VREF_6_04 -- -- -- -- PLL_CK7C/HPPLL PLL_CK7T/HPPLL -- -- -- -- PTEMP -- -- LVDS_R -- -- -- -- DP2 -- -- PLL_CK6T/PPLL PLL_CK6C/PPLL -- -- -- -- VREF_6_05 DP3 -- --
BM416 Pair
-- -- -- L4C_D0 L4T_D0 -- -- -- L5C_D0 L5T_D0 -- -- -- -- -- -- -- -- L6C_A0 L6T_A0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L7T_D0 L7C_D0 -- -- -- -- L8T_D0 L8C_D0 -- L9T_D0
BM680 Pair
L4C_A1 L4T_A1 -- L5C_D1 L5T_D1 L6C_D1 L6T_D1 -- L7C_A0 L7T_A0 -- -- L8C_D1 L8T_D1 -- -- -- -- L9C_A0 L9T_A0 -- L10C_A0 L10T_A0 -- -- -- -- -- -- -- -- -- L11T_A0 L11C_A0 -- L12T_A0 L12C_A0 -- -- L13T_A0 L13C_A0 L14T_A0 L14C_A0 -- L15T_A0
Agere Systems Inc.
51
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Pin Information (continued)
Table 20. PBGA Pinout Table (continued) BM416 BM680 VDDIO Bank
AD5 -- AF4 AE5 -- AD6 AF5 AC7 AC8 -- -- AD7 AE6 -- -- AE7 AD8 -- -- AF6 AF7 -- T14 AE8 AD9 -- -- -- AC9 AC10 -- -- -- AF8 AE9 -- -- -- AD10 AE10 -- -- AF9 AE11 AD11 AM7 N20 AN7 AP6 AK8 AL8 AN3 AM8 AK9 AP7 N21 AL9 AK10 AN8 AP2 AM9 AL10 AP8 N22 AL11 AK11 AM10 -- AN9 AP9 AM11 AK12 P13 AN10 AP10 AL12 AK13 AP3 AN11 AN12 AK14 AL13 P14 AP12 AN13 AL14 AK15 -- AP13 AP14 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL)
VREF Group
6 -- 6 6 6 6 -- 7 7 7 -- 7 7 7 -- 7 7 8 -- 8 8 8 -- 8 8 9 9 -- 9 9 9 9 -- 9 9 9 9 -- 10 10 10 10 -- 10 10
I/O
I/O Vss I/O I/O I/O I/O VDDIO6 I/O I/O I/O Vss I/O I/O I/O VDDIO6 I/O I/O I/O Vss I/O I/O I/O VDD15 I/O I/O I/O I/O Vss I/O I/O I/O I/O VDDIO6 I/O I/O I/O I/O Vss I/O I/O I/O I/O VDDIO6 I/O I/O
Pin Description
PB4D Vss PB5C PB5D PB6A PB6B VDDIO6 PB6C PB6D PB7A Vss PB7C PB7D PB8A VDDIO6 PB8C PB8D PB9A Vss PB9C PB9D PB10A VDD15 PB10C PB10D PB11A PB11B Vss PB11C PB11D PB12A PB12B VDDIO6 PB12C PB12D PB13A PB13B Vss PB13C PB13D PB14A PB14B VDDIO6 PB14C PB14D
Additional Function
-- -- VREF_6_06 D14 -- -- -- D15 D16 -- -- D17 D18 -- -- VREF_6_07 D19 -- -- D20 D21 -- -- VREF_6_08 D22 -- -- -- D23 D24 -- -- -- VREF_6_09 D25 -- -- -- D26 D27 -- -- -- VREF_6_10 D28
BM416 Pair
L9C_D0 -- L10T_D0 L10C_D0 -- -- -- L11T_A0 L11C_A0 -- -- L12T_D0 L12C_D0 -- -- L13T_D0 L13C_D0 -- -- L14T_A0 L14C_A0 -- -- L15T_D0 L15C_D0 -- -- -- L16T_A0 L16C_A0 -- -- -- L17T_D0 L17C_D0 -- -- -- L18T_A0 L18C_A0 -- -- -- L19T_A0 L19C_A0
BM680 Pair
L15C_A0 -- L16T_A0 L16C_A0 L17T_A0 L17C_A0 -- L18T_D1 L18C_D1 -- -- L19T_A0 L19C_A0 -- -- L20T_A0 L20C_A0 -- -- L21T_A0 L21C_A0 -- -- L22T_A0 L22C_A0 L23T_D1 L23C_D1 -- L24T_A0 L24C_A0 L25T_A0 L25C_A0 -- L26T_A0 L26C_A0 L27T_A0 L27C_A0 -- L28T_A0 L28C_A0 L29T_A0 L29C_A0 -- L30T_A0 L30C_A0
52
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Pin Information (continued)
Table 20. PBGA Pinout Table (continued) BM416 BM680 VDDIO Bank
-- -- AC12 AC11 -- AF10 AF11 -- R16 AD12 AE12 -- P16 AF12 AF13 P17 R17 -- -- T10 AD13 AE13 -- -- AF14 AC14 AC13 -- -- R13 AE14 AD14 -- T11 AF15 AE15 -- AF16 AD15 AE16 -- T12 AC15 AC16 -- AN14 P15 AM14 AL15 AN15 AM16 AL16 AP15 P20 AN16 AP16 AK16 -- AL17 AK17 -- P21 AM17 AN17 P22 AP18 AM18 AN18 AL18 AM12 AN19 AK18 AM19 AP20 -- AL19 AN20 AP21 P34 AL20 AK19 AN21 AM15 AK20 AM21 AP22 R13 AL21 AN22 AP23 6 (BL) -- 6 (BL) 6 (BL) 6 (BL) 6 (BL) 6 (BL) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) -- -- 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC)
VREF Group
11 -- 11 11 11 11 11 1 -- 1 1 1 -- 1 1 -- -- 2 2 -- 2 2 2 2 -- 2 2 2 2 -- 3 3 3 -- 3 3 3 -- 3 3 3 -- 4 4 4
I/O
I/O Vss I/O I/O I/O I/O I/O I/O Vss I/O I/O I/O VDD15 I/O I/O VDD15 Vss I/O I/O Vss I/O I/O I/O I/O VDDIO5 I/O I/O I/O I/O VDD15 I/O I/O I/O Vss I/O I/O I/O VDDIO5 I/O I/O I/O Vss I/O I/O I/O
Pin Description
PB15A Vss PB15C PB15D PB16A PB16C PB16D PB17A Vss PB17C PB17D PB18A VDD15 PB18C PB18D VDD15 Vss PB19A PB19B Vss PB19C PB19D PB20A PB20B VDDIO5 PB20C PB20D PB21A PB21B VDD15 PB21C PB21D PB22A Vss PB22C PB22D PB23A VDDIO5 PB23C PB23D PB24A Vss PB24C PB24D PB25A
Additional Function
-- -- D29 D30 -- VREF_6_11 D31 -- -- -- -- -- -- VREF_5_01 -- -- -- -- -- -- PBCK0T PBCK0C -- -- -- VREF_5_02 -- -- -- -- -- VREF_5_03 -- -- -- -- -- -- PBCK1T PBCK1C -- -- -- -- --
BM416 Pair
-- -- L20T_A0 L20C_A0 -- L21T_A0 L21C_A0 -- -- L1T_A0 L1C_A0 -- -- L2T_A0 L2C_A0 -- -- -- -- -- L3T_A0 L3C_A0 -- -- -- L4T_A0 L4C_A0 -- -- -- L5T_A0 L5C_A0 -- -- L6T_A0 L6C_A0 -- -- L7T_D0 L7C_D0 -- -- L8T_A0 L8C_A0 --
BM680 Pair
-- -- L31T_A0 L31C_A0 -- L32T_A0 L32C_A0 -- -- L1T_A0 L1C_A0 -- -- L2T_A0 L2C_A0 -- -- L3T_A0 L3C_A0 -- L4T_A1 L4C_A1 L5T_A1 L5C_A1 -- L6T_D2 L6C_2 L7T_D1 L7C_D1 -- L8T_D1 L8C_D1 -- -- L9T_A0 L9C_A0 -- -- L10T_D1 L10C_D1 -- -- L11T_D1 L11C_D1 --
Agere Systems Inc.
53
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Pin Information (continued)
Table 20. PBGA Pinout Table (continued) BM416 BM680 VDDIO Bank
AF17 AD16 AE17 -- -- T15 AF18 AE18 -- -- AD17 AF19 AF20 -- -- AC18 AC17 -- -- -- -- -- AD18 AE19 -- AE20 AD19 -- AF21 AE21 AD20 AC19 -- -- -- -- -- M14 AC20 AF22 N10 AE22 AM20 AN23 AN24 AK21 AL22 R14 AP25 AM24 AK22 AL23 AM23 AN25 AL24 AP26 R15 AM25 AK23 AN26 AL25 AK24 AP27 R20 AM26 AN27 AP11 AP28 AM27 R21 AL26 AK25 AP17 AN28 AP29 R22 AP19 T16 T17 A31 AL27 AM28 C30 AN29 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) 5 (BC) 5 (BC) 5 (BC) 5 (BC) -- 5 (BC) -- -- -- -- -- -- --
VREF Group
-- 4 4 4 4 -- 5 5 5 5 -- 5 5 6 -- 6 6 6 6 6 7 -- 7 7 -- 7 7 -- 7 7 -- 8 8 -- -- -- -- -- -- -- -- --
I/O
VDDIO5 I/O I/O I/O I/O Vss I/O I/O I/O I/O VDDIO5 I/O I/O I/O Vss I/O I/O I/O I/O I/O I/O Vss I/O I/O VDDIO5 I/O I/O Vss I/O I/O VDDIO5 I/O I/O Vss VDDIO5 Vss Vss VDD15 I I VDD15 I
Pin Description
VDDIO5 PB25C PB25D PB26A PB26B Vss PB26C PB26D PB27A PB27B VDDIO5 PB27C PB27D PB28A Vss PB28C PB28D PB29A PB29C PB29D PB30A Vss PB30C PB30D VDDIO5 PB31C PB31D Vss PB32C PB32D VDDIO5 PB33C PB33D Vss VDDIO5 Vss Vss VDD15 RX_DAT_IN_10_P/ RX_DAT_IN_0_P RX_DAT_IN_10_N/ RX_DAT_IN_0_N VDD15 RX_DAT_IN_11_P/ RX_DAT_IN_1_P
Additional Function
-- -- VREF_5_04 -- -- -- -- VREF_5_05 -- -- -- -- -- -- -- -- VREF_5_06 -- -- -- -- -- -- -- -- VREF_5_07 -- -- -- -- -- -- VREF_5_08 -- -- -- -- -- -- -- -- --
BM416 Pair
-- L9T_D0 L9C_D0 -- -- -- L10T_A0 L10C_A0 -- -- -- L11T_A0 L11C_A0 -- -- L12T_A0 L12C_A0 -- -- -- -- -- L13T_D0 L13C_D0 -- L14T_D0 L14C_D0 -- L15T_A0 L15C_A0 -- -- -- -- -- -- -- -- L1_D2 L1_D2 -- L2_D0
BM680 Pair
-- L12T_A0 L12C_A0 L13T_A0 L13C_A0 -- L14T_D1 L14C_D1 L15T_A0 L15C_A0 -- L16T_D1 L16T_D1 -- -- L17T_D1 L17C_D1 -- L18T_A0 L18C_A0 -- -- L19T_A0 L19C_A0 -- L20T_D1 L20C_D1 -- L21T_A0 L21C_A0 -- L22T_A0 L22C_A0 -- -- -- -- -- L1_A0 L1_A0 -- L2_A0
Note: The pin description for RX_DAT_IN* shows both the naming conventions, 2.5 Gbit/10 Gbit, where only one is valid depending on the mode of operation.
54
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Pin Information (continued)
Table 20. PBGA Pinout Table (continued) BM416 BM680 VDDIO Bank
AD21 AF23 AE23 AF24 L12 -- AC21 AD22 AD23 AE24 AC22 AC23 AD24 L15 L16 N11 AE25 AC24 AD25 AD26 L17 -- N12 AB23 AA23 AC25 AB24 M10 AB25 AA24 AC26 AB26 N15 AP30 -- AL28 AM29 Y34 AN30 AK27 AK28 AL29 AM30 AN31 AP32 AK30 AA13 AA14 C33 AK31 AJ30 AK32 AJ31 AA15 AH30 C34 AK33 AJ32 AH31 AG30 AA20 AF30 AG31 AK34 AJ33 D28 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
VREF Group
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
I/O
I VDD33 I I Vss VDD33 I I I I I VssA_4 VDD33A_4 Vss Vss VDD15 VDD33A_5 VDD33 VssA_5 I Vss VDD33 VDD15 I I I I Vss I I I I VDD15
Pin Description
RX_DAT_IN_11_N/ RX_DAT_IN_1_N VDD33 RX_DAT_IN_12_P/ RX_DAT_IN_2_P RX_DAT_IN_12_N/ RX_DAT_IN_2_N Vss VDD33 RX_DAT_IN_13_P/ RX_DAT_IN_3_P RX_DAT_IN_13_N/ RX_DAT_IN_3_N RX_CLK_IN_0_P RX_CLK_IN_0_N LVCTAP_1 VssA_4 VDD33A_4 Vss Vss VDD15 VDD33A_5 VDD33 VssA_5 LVCTAP_2 Vss VDD33 VDD15 RX_DAT_IN_20_P/ RX_DAT_IN_4_P RX_DAT_IN_20_N/ RX_DAT_IN_4_N RX_DAT_IN_21_P/ RX_DAT_IN_5_P RX_DAT_IN_21_N/ RX_DAT_IN_5_N Vss RX_DAT_IN_22_P/ RX_DAT_IN_6_P RX_DAT_IN_22_N/ RX_DAT_IN_6_N RX_DAT_IN_23_P/ RX_DAT_IN_7_P RX_DAT_IN_23_N/ RX_DAT_IN_7_N VDD15
Additional Function
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
BM416 Pair
L2_D0 -- L3_D0 L3_D0 -- -- L4_D0 L4_D0 L5_D0 L5_D0 -- -- -- -- -- -- -- -- -- -- -- -- -- L6_A0 L6_A0 L7_D0 L7_D0 -- L8_D0 L8_D0 L9_A0 L9_A0 --
BM680 Pair
L2_A0 -- L3_A0 L3_A0 -- -- L4_A0 L4_A0 L5_A0 L5_A0 -- -- -- -- -- -- -- -- -- -- -- -- -- L6_A0 L6_A0 L7_A0 L7_A0 -- L8_A0 L8_A0 L9_A0 L9_A0 --
Note: The pin description for RX_DAT_IN* shows both the naming conventions, 2.5 Gbit/10 Gbit, where only one is valid depending on the mode of operation.
Agere Systems Inc.
55
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Pin Information (continued)
Table 20. PBGA Pinout Table (continued) BM416 BM680 VDDIO Bank
M11 Y24 W23 M12 N16 AA25 AA26 -- M15 Y23 W24 N17 Y25 Y26 M16 -- W25 V24 P10 W26 V23 U23 -- M17 V25 U24 V26 P11 U26 N13 U25 T24 R23 T23 N14 AA21 AH32 AE30 AA22 D32 AG32 AF31 AF32 AB13 AC30 AD30 D34 AE31 AE32 AB14 AF33 AD31 AD32 F34 AB30 AC31 AC32 AC33 AB15 AB31 AB32 AA30 G33 AB33 AB20 AA31 Y30 AA32 AA33 AB21 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
VREF Group
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
I/O
Vss VDD33 I Vss VDD15 I I VDD33 Vss I I VDD15 I I Vss VDD33 I I VDD15 I I I VDD33 Vss I I I VDD15 VDD33 Vss I I I I Vss
Pin Description
Vss VDD33 LVCTAP_3 Vss VDD15 RX_CLK_IN_1_P RX_CLK_IN_1_N VDD33 Vss RX_DAT_IN_30_P/ RX_DAT_IN_8_P RX_DAT_IN_30_N/ RX_DAT_IN_8_N VDD15 RX_DAT_IN_31_P/ RX_DAT_IN_9_P RX_DAT_IN_31_N/ RX_DAT_IN_9_N Vss VDD33 RX_DAT_IN_32_P/ RX_DAT_IN_10_P RX_DAT_IN_32_N/ RX_DAT_IN_10_N VDD15 LVCTAP_4 RX_DAT_IN_33_P/ RX_DAT_IN_11_P RX_DAT_IN_33_N/ RX_DAT_IN_11_N VDD33 Vss RX_CLK_IN_2_P RX_CLK_IN_2_N LVCTAP_5 VDD15 VDD33 Vss RX_CLK_IN_3_P RX_CLK_IN_3_N RX_DAT_IN_40_P/ RX_DAT_IN_12_P RX_DAT_IN_40_N/ RX_DAT_IN_12_N Vss
Additional Function
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
BM416 Pair
-- -- -- -- -- L10_A0 L10_A0 -- -- L11_D0 L11_D0 -- L12_A0 L12_A0 -- -- L13_D0 L13_D0 -- -- L14_A0 L14_A0 -- -- L15_D0 L15_D0 -- -- -- -- L16_D0 L16_D0 L17_A0 L17_A0 --
BM680 Pair
-- -- -- -- -- L10_A0 L10_A0 -- -- L11_A0 L11_A0 -- L12_A0 L12_A0 -- -- L13_A0 L13_A0 -- -- L14_A0 L14_A0 -- -- L15_A0 L15_A0 -- -- -- -- L16_A0 L16_A0 L17_A0 L17_A0 --
Note: The pin description for RX_DAT_IN* shows both the naming conventions, 2.5 Gbit/10 Gbit, where only one is valid depending on the mode of operation.
56
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Pin Information (continued)
Table 20. PBGA Pinout Table (continued) BM416 BM680 VDDIO Bank
P12 T25 T26 -- P13 -- -- R24 R25 P14 P15 R26 P25 P24 R10 P26 N26 N23 P23 R11 -- -- N25 N24 R12 -- M26 M25 R15 M24 M23 -- L26 L25 G34 Y31 Y32 W30 AB22 Y33 J34 W31 W32 AC34 K33 V30 V31 W33 AE33 V32 V33 U33 U31 AF34 U30 K34 U32 T33 AH33 T32 T31 T30 AJ34 R33 R32 M34 R31 R30 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
VREF Group
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
I/O
VDD15 I I VDD33 Vss VDD33 VDD15 I I Vss VDD15 I I VDD33 Vss I I I I Vss VDD33 VDD15 O O Vss VDD33 O O Vss O O VDD15 O O
Pin Description
VDD15 RX_DAT_IN_41_P/ RX_DAT_IN_13_P RX_DAT_IN_41_N/ RX_DAT_IN_13_N VDD33 Vss VDD33 VDD15 RX_DAT_IN_42_P/ RX_DAT_IN_14_P RX_DAT_IN_42_N/ RX_DAT_IN_14_N Vss VDD15 RX_DAT_IN_43_P/ RX_DAT_IN_15_P RX_DAT_IN_43_N/ RX_DAT_IN_15_N VDD33 Vss LV_REF10 LV_REF14 LV_RESHI LV_RESLO Vss VDD33 VDD15 TX_CLK_OUT_0_P TX_CLK_OUT_0_N Vss VDD33 TX_DAT_OUT_10_P/ TX_DAT_OUT_0_P TX_DAT_OUT_10_N/ TX_DAT_OUT_0_N Vss TX_DAT_OUT_11_P/ TX_DAT_OUT_1_P TX_DAT_OUT_11_N/ TX_DAT_OUT_1_N VDD15 TX_DAT_OUT_12_P/ TX_DAT_OUT_2_P TX_DAT_OUT_12_N/ TX_DAT_OUT_2_N
Additional Function
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
BM416 Pair
-- L18_A0 L18_A0 -- -- -- -- L19_A0 L19_A0 -- -- L20_D0 L20_D0 -- -- -- -- -- -- -- -- -- L21_A0 L21_A0 -- -- L22_A0 L22_A0 -- L23_A0 L23_A0 -- L24_A0 L24_A0
BM680 Pair
-- L18_A0 L18_A0 -- -- -- -- L19_A0 L19_A0 -- -- L20_A0 L20_A0 -- -- -- -- -- -- -- -- -- L21_A0 L21_A0 -- -- L22_A0 L22_A0 -- L23_A0 L23_A0 -- L24_A0 L24_A0
Note: The pin descriptions for RX_DAT_IN* and TX_DAT_OUT* shows both the naming conventions, 2.5 Gbit/10 Gbit, where only one is valid depending on the mode of operation.
Agere Systems Inc.
57
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Pin Information (continued)
Table 20. PBGA Pinout Table (continued) BM416 BM680 VDDIO Bank
-- K26 -- L24 L23 J26 K25 -- J25 K24 -- -- H26 G26 -- K23 J23 -- -- J24 H25 -- H24 G25 -- E26 F26 -- -- G24 H23 G23 AL2 -- P33 N33 P32 P30 P31 AL4 N32 N31 N16 N30 M33 M32 AL30 M31 M30 L33 N17 L32 K32 AL31 L30 L31 N18 J31 K31 K30 AM3 H33 J32 H32 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
VREF Group
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
I/O
Vss VDD33 VDD33 O O O O Vss O O VDD15 VDD33 O O Vss O O VDD33 VDD15 O O Vss O O VDD15 O O VDD33 Vss O O VDD33
Pin Description
Vss VDD33 VDD33 TX_DAT_OUT_13_P/ TX_DAT_OUT_3_P TX_DAT_OUT_13_N/ TX_DAT_OUT_3_N TX_CLK_OUT_1_P TX_CLK_OUT_1_N Vss TX_DAT_OUT_20_P/ TX_DAT_OUT_4_P TX_DAT_OUT_20_N/ TX_DAT_OUT_4_N VDD15 VDD33 TX_DAT_OUT_21_P/ TX_DAT_OUT_5_P TX_DAT_OUT_21_N/ TX_DAT_OUT_5_N Vss TX_DAT_OUT_22_P/ TX_DAT_OUT_6_P TX_DAT_OUT_22_N/ TX_DAT_OUT_6_N VDD33 VDD15 TX_DAT_OUT_23_P/ TX_DAT_OUT_7_P TX_DAT_OUT_23_N/ TX_DAT_OUT_7_N Vss TX_CLK_OUT_2_P TX_CLK_OUT_2_N VDD15 TX_DAT_OUT_30_P/ TX_DAT_OUT_8_P TX_DAT_OUT_30_N/ TX_DAT_OUT_8_N VDD33 Vss TX_DAT_OUT_31_P/ TX_DAT_OUT_9_P TX_DAT_OUT_31_N/ TX_DAT_OUT_9_N VDD33
Additional Function
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
BM416 Pair
-- -- -- L25_A0 L25_A0 L26_D0 L26_D0 -- L27_D0 L27_D0 -- -- L28_A0 L28_A0 -- L29_A0 L29_A0 -- -- L30_D0 L30_D0 -- L31_D0 L31_D0 -- L32_A0 L32_A0 -- -- L33_D0 L33_D0 --
BM680 Pair
-- -- -- L25_A0 L25_A0 L26_A0 L26_A0 -- L27_A0 L27_A0 -- -- L28_A0 L28_A0 -- L29_A0 L29_A0 -- -- L30_A0 L30_A0 -- L31_A0 L31_A0 -- L32_A0 L32_A0 -- -- L33_A0 L33_A0 --
Note: The pin description for TX_DAT_OUT* shows both the naming conventions, 2.5 Gbit/10 Gbit, where only one is valid depending on the mode of operation.
58
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Pin Information (continued)
Table 20. PBGA Pinout Table (continued) BM416 BM680 VDDIO Bank
F25 E25 -- F24 -- D26 D25 -- -- C25 D24 -- F23 E24 -- -- C26 B25 E23 C24 -- -- D23 B24 D22 C23 A24 B23 C22 -- D21 C21 -- A23 H31 J30 N19 G32 AM13 G31 F32 N34 H30 E33 E32 AM22 F31 E31 G30 P16 F30 E30 B32 C31 AM32 AN2 E29 E28 A32 B31 E27 E26 B30 P17 D29 C29 AN33 C28 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
VREF Group
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
I/O
I I VDD15 I Vss O O VDD15 VDD33 O O Vss O O VDD33 VDD15 VDD33 VssA_6 VDD33 VDD33A_6 Vss Vss VDD33A_7 VssA_7 O O O O VDD33 VDD15 O O Vss O
Pin Description
TX_CLK_IN_P TX_CLK_IN_N VDD15 LVCTAP_6 Vss TX_DAT_OUT_32_P/ TX_DAT_OUT_10_P TX_DAT_OUT_32_N/ TX_DAT_OUT_10_N VDD15 VDD33 TX_DAT_OUT_33_P/ TX_DAT_OUT_11_P TX_DAT_OUT_33_N/ TX_DAT_OUT_11_N Vss TX_CLK_OUT_3_P TX_CLK_OUT_3_N VDD33 VDD15 VDD33 VssA_6 VDD33 VDD33A_6 Vss Vss VDD33A_7 VssA_7 TX_DAT_OUT_40_N/ TX_DAT_OUT_12_N TX_DAT_OUT_40_P/ TX_DAT_OUT_12_P TX_DAT_OUT_41_N/ TX_DAT_OUT_13_N TX_DAT_OUT_41_P/ TX_DAT_OUT_13_P VDD33 VDD15 TX_DAT_OUT_42_N/ TX_DAT_OUT_14_N TX_DAT_OUT_42_P/ TX_DAT_OUT_14_P Vss TX_DAT_OUT_43_N/ TX_DAT_OUT_15_N
Additional Function
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
BM416 Pair
L34_A0 L34_A0 -- -- -- L35_A0 L35_A0 -- -- L36_D0 L36_D0 -- L37_D0 L37_D0 -- -- -- -- -- -- -- -- -- -- L38_D0 L38_D0 L39_D0 L39_D0 -- -- L40_A0 L40_A0 -- L41_D0
BM680 Pair
L34_A0 L34_A0 -- -- -- L35_A0 L35_A0 -- -- L36_A0 L36_A0 -- L37_A0 L37_A0 -- -- -- -- -- -- -- -- -- -- L38_A0 L38_A0 L39_A0 L39_A0 -- -- L40_A0 L40_A0 -- L41_A0
Note: The pin description for TX_DAT_OUT* shows both the naming conventions, 2.5 Gbit/10 Gbit, where only one is valid depending on the mode of operation.
Agere Systems Inc.
59
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Pin Information (continued)
Table 20. PBGA Pinout Table (continued) BM416 BM680 VDDIO Bank
B22 A22 B21 D20 D19 K12 K15 -- K16 -- -- C20 K17 B20 C19 -- -- L10 -- A21 A20 L13 -- -- B19 C18 L11 -- -- D18 D17 A19 B18 C17 A18 B17 -- -- -- A17 B16 D15 D16 D27 A30 E25 B29 A29 T18 T19 A11 U16 A17 C27 D26 U17 B28 A28 A19 B27 U18 C26 B26 A27 -- E24 D25 D24 C25 U19 B25 A26 E23 D23 A24 C24 A25 E22 E21 U34 B24 D22 B23 A23 C12 D21 -- -- -- -- -- -- -- 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC)
VREF Group
-- -- -- -- -- -- -- -- -- -- 9 9 -- 10 10 -- 10 -- 10 10 10 -- 10 10 1 1 -- 1 1 1 1 -- 1 1 2 2 -- 2 2 2 2 -- 3
I/O
O I I I I Vss Vss VDDIO1 Vss VDDIO1 I/O I/O Vss I/O I/O VDDIO1 I/O Vss I/O I/O I/O VDD15 I/O I/O I/O I/O Vss I/O I/O I/O I/O VDDIO1 I/O I/O I/O I/O Vss I/O I/O I/O I/O VDDIO1 I/O
Pin Description
TX_DAT_OUT_43_P/ TX_DAT_OUT_15_P PWRDN RESET_RX RESET_TX PLL_BYPASS Vss Vss VDDIO1 Vss VDDIO1 PT32D PT32C Vss PT31D PT31C VDDIO1 PT30D Vss PT30A PT29D PT29C VDD15 PT29B PT29A PT28D PT28C Vss PT28B PT28A PT27D PT27C VDDIO1 PT27B PT27A PT26D PT26C Vss PT26B PT26A PT25D PT25C VDDIO1 PT24D
Additional Function
-- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_1_10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_1_01 -- -- -- -- -- VREF_1_02 -- -- -- -- -- -- --
BM416 Pair
L41_D0 -- -- -- -- -- -- -- -- -- -- -- -- L1C_D0 L1T_D0 -- -- -- -- L2C_A0 L2T_A0 -- -- -- L3C_D0 L3T_D0 -- -- -- L4C_A0 L4T_A0 -- L5C_D0 L5T_D0 L6C_D0 L6T_D0 -- -- -- L7C_D0 L7T_D0 -- L8C_A0
BM680 Pair
L41_A0 -- -- -- -- -- -- -- -- -- -- -- -- L1C_A0 L1T_A0 -- -- -- -- L2C_A0 L2T_A0 -- L3C_A0 L3T_A0 L4C_A0 L4T_A0 -- L5C_A0 L5T_A0 L6C_A0 L6T_A0 -- L7C_D1 L7T_D1 L8C_A0 L8T_A0 -- L9C_D1 L9T_D1 L10C_A0 L10T_A0 -- L11C_D1
Note: The pin description for TX_DAT_OUT* shows both the naming conventions, 2.5 Gbit/10 Gbit, where only one is valid depending on the mode of operation.
60
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Pin Information (continued)
Table 20. PBGA Pinout Table (continued) BM416 BM680 VDDIO Bank
C16 -- -- A16 A15 B15 -- -- -- -- -- C15 C14 L14 -- -- -- B14 A14 D14 -- -- -- M13 D13 C13 -- -- -- B13 A13 -- A12 B12 -- -- C12 D12 -- -- B11 A11 -- -- D11 B22 V16 A22 D20 E20 C15 C21 B21 A21 V17 B20 C19 A20 -- D19 E19 V18 B19 B18 C20 D18 E18 V19 -- B17 C17 W16 D17 C18 A16 B16 E17 C16 D16 W17 A15 B15 D15 C23 A14 E16 C14 W18 B14 E15 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- -- 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) 1 (TC) -- 1 (TC) 0 (TL)
VREF Group
3 -- 3 3 3 -- 3 3 3 -- 3 4 4 -- 4 4 -- 4 4 -- 4 4 -- -- 5 5 -- 5 5 5 5 5 5 5 -- 5 6 6 -- 6 6 6 -- 6 1
I/O
I/O Vss I/O I/O I/O VDDIO1 I/O I/O I/O Vss I/O I/O I/O VDD15 I/O I/O Vss I/O I/O VDDIO1 I/O I/O Vss VDD15 I/O I/O Vss I/O I/O I/O I/O I/O I/O I/O Vss I/O I/O I/O VDDIO1 I/O I/O I/O Vss I/O I/O
Pin Description
PT24C Vss PT24A PT23D PT23C VDDIO1 PT23A PT22D PT22C Vss PT22A PT21D PT21C VDD15 PT20D PT20C Vss PT19D PT19C VDDIO1 PT19B PT19A Vss VDD15 PT18D PT18C Vss PT18B PT18A PT17D PT17C PT17A PT16D PT16C Vss PT16A PT15D PT15C VDDIO1 PT15A PT14D PT14C Vss PT14A PT13D
Additional Function
VREF_1_03 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- VREF_1_04 -- -- -- -- -- PTCK1C PTCK1T -- -- -- PTCK0C PTCK0T -- VREF_1_05 -- -- -- -- -- -- -- -- VREF_1_06 -- -- MPI_RTRY_N
BM416 Pair
L8T_A0 -- -- L9C_A0 L9T_A0 -- -- -- -- -- -- L10C_A0 L10T_A0 -- -- -- -- L11C_A0 L11T_A0 -- -- -- -- -- L12C_A0 L12T_A0 -- -- -- L13C_A0 L13T_A0 -- L14C_A0 L14T_A0 -- -- L15C_A0 L15T_A0 -- -- L16C_A0 L16T_A0 -- -- L1C_A0
BM680 Pair
L11T_D1 -- -- L12C_A0 L12T_A0 -- -- L13C_A0 L13T_A0 -- -- L14C_D1 L14T_D1 -- L15C_A0 L15T_A0 -- L16C_A0 L16T_A0 -- L17C_A0 L17T_A0 -- -- L18C_A0 L18T_A0 -- L19C_A0 L19T_A0 L20C_A0 L20T_A0 -- L21C_A0 L21T_A0 -- -- L22C_A1 L22T_A1 -- -- L23C_D1 L23T_D1 -- -- L1C_A0
Agere Systems Inc.
61
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Pin Information (continued)
Table 20. PBGA Pinout Table (continued) BM416 BM680 VDDIO Bank
C11 A10 -- C10 B10 A9 -- B9 C9 D10 D9 -- A8 B8 -- -- K13 -- A7 A6 -- -- C8 B7 -- C7 B6 -- D7 D8 A5 -- -- C6 B5 B26 -- -- A4 C5 -- -- -- B3 A3 K10 D14 C4 A13 B13 A12 B12 W19 D13 E14 B11 A10 D2 E13 D12 C11 B10 -- A9 D11 B9 Y13 A8 E12 C10 D3 D10 C9 Y14 E11 D9 E1 A7 B8 E10 C8 Y15 B7 A6 D8 B6 E3 C7 A5 C6 B5 Y20 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) --
VREF Group
1 -- 1 1 1 1 -- 2 2 2 2 -- 2 2 3 3 -- 3 3 3 -- 3 3 3 -- 4 4 -- 4 4 -- 4 4 5 5 -- 5 5 5 5 -- 5 5 6 6 --
I/O
I/O VDDIO0 I/O I/O I/O I/O Vss I/O I/O I/O I/O VDDIO0 I/O I/O I/O I/O VDD15 I/O I/O I/O Vss I/O I/O I/O VDDIO0 I/O I/O Vss I/O I/O VDDIO0 I/O I/O I/O I/O Vss I/O I/O I/O I/O VDDIO0 I/O I/O I/O I/O Vss
Pin Description
PT13C VDDIO0 PT13B PT13A PT12D PT12C Vss PT12B PT12A PT11D PT11C VDDIO0 PT11B PT11A PT10D PT10C VDD15 PT10A PT9D PT9C Vss PT9A PT8D PT8C VDDIO0 PT7D PT7C Vss PT6D PT6C VDDIO0 PT6B PT6A PT5D PT5C Vss PT5B PT5A PT4D PT4C VDDIO0 PT4B PT4A PT3D PT3C Vss
Additional Function
MPI_ACK_N -- -- VREF_0_01 M0 M1 -- MPI_CLK A21/MPI_BURST_N M2 M3 -- VREF_0_02 MPI_TEA_N -- -- -- -- VREF_0_03 -- -- -- D0 TMS -- A20/MPI_BDIP_N A19/MPI_TSZ1 -- A18/MPI_TSZ0 D3 -- VREF_0_04 -- D1 D2 -- -- VREF_0_05 TDI TCK -- -- -- -- VREF_0_06 --
BM416 Pair
L1T_A0 -- -- -- L2C_D0 L2T_D0 -- L3C_A0 L3T_A0 L4C_A0 L4T_A0 -- L5C_A0 L5T_A0 -- -- -- -- L6C_A0 L6T_A0 -- -- L7C_D0 L7T_D0 -- L8C_D0 L8T_D0 -- L9C_A0 L9T_A0 -- -- -- L10C_D0 L10T_D0 -- -- -- L11C_D1 L11T_D1 -- -- -- L12C_A0 L12T_A0 --
BM680 Pair
L1T_A0 -- L2C_A0 L2T_A0 L3C_A0 L3T_A0 -- L4C_A0 L4T_A0 L5C_A0 L5T_A0 -- L6C_A0 L6T_A0 L7C_A0 L7T_A0 -- -- L8C_D1 L8T_D1 -- -- L9C_D1 L9T_D1 -- L10C_A0 L10T_A0 -- L11C_D1 L11T_D1 -- L12C_A0 L12T_A0 L13C_D1 L13T_D1 -- L14C_A0 L14T_A0 L15C_D1 L15T_D1 -- L16C_D1 L16T_D1 L17C_A0 L17T_A0 --
62
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Pin Information (continued)
Table 20. PBGA Pinout Table (continued) BM416 BM680 VDDIO Bank
-- -- D5 D6 -- -- B4 B2 K14 C4 C3 K11 -- -- U13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- E9 D7 C5 D6 E8 E7 A4 B4 -- E6 D5 Y21 AK26 P18 -- P19 R16 R17 R18 R19 R34 T13 T14 T15 T20 T21 T22 T34 U13 U14 U15 U20 U21 U22 V13 V14 V15 V20 V21 V22 V34 W13 W14 W15 W20 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) 0 (TL) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
VREF Group
6 6 6 6 6 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
I/O
I/O I/O I/O I/O I/O I/O O I/O VDD15 I/O VDD33 Vss VDD33 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15
Pin Description
PT3B PT3A PT2D PT2C PT2B PT2A PCFG_MPI_IRQ PCCLK VDD15 PDONE VDD33 Vss VDD33 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15
Additional Function
-- -- PLL_CK1C/PPLL PLL_CK1T/PPLL -- --
CFG_IRQ_N/ MPI_IRQ_N
BM416 Pair
-- -- L13C_A0 L13T_A0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
BM680 Pair
L18C_D1 L18T_D1 L19C_A0 L19T_A0 L20C_A0 L20T_A0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
CCLK -- DONE -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Agere Systems Inc.
63
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Pin Information (continued)
Table 20. PBGA Pinout Table (continued) BM416 BM680 VDDIO Bank
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W21 W22 W34 Y16 Y17 Y18 Y19 AA16 AA17 AA18 AA19 AA34 AB16 AB17 AB18 AB19 AB34 AD33 AD34 AE34 AG33 AG34 AH34 AK29 AL32 AL33 AL34 AM31 AM33 AM34 AN32 AP31 AN34 AP1 AP4 AP33 AP34 Y22 AP24 AD1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 (BC) 7 (CL)
VREF Group
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
I/O
VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 Vss Vss Vss Vss Vss Vss VDDIO5 VDDIO7
Pin Description
VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 VDD15 Vss Vss Vss Vss Vss Vss VDDIO5 VDDIO7
Additional Function
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
BM416 Pair
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
BM680 Pair
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
64
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
JC
This is the thermal resistance from junction to case. It is most often used when attaching a heat sink to the top of the package. It is defined by:
TJ - TC JC = ------------------Q
Package Thermal Characteristics Summary
There are three thermal parameters that are in common use: JA, JC, and JC. It should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow.
JA
This is the thermal resistance from junction to ambient (theta-JA, R-theta, etc.):
TJ - TA JA = ------------------Q
The parameters in this equation have been defined above. However, the measurements are performed with the case of the part pressed against a watercooled heat sink to draw most of the heat generated by the chip out the top of the package. It is this difference in the measurement process that differentiates JC from JC. JC is a true thermal resistance and is expressed in units of C/W.
where TJ is the junction temperature, TA, is the ambient air temperature, and Q is the chip power. Experimentally, JA is determined when a special thermal test die is assembled into the package of interest, and the part is mounted on the thermal test board. The diodes on the test chip are separately calibrated in an oven. The package/board is placed either in a JEDEC natural convection box or in the wind tunnel, the latter for forced convection measurements. A controlled amount of power (Q) is dissipated in the test chip's heater resistor, the chip's temperature (TJ) is determined by the forward drop on the diodes, and the ambient temperature (TA) is noted. Note that JA is expressed in units of C/watt.
JB
This is the thermal resistance from junction to board (JL). It is defined by:
TJ - TB JB = ------------------Q
where TB is the temperature of the board adjacent to a lead measured with a thermocouple. The other parameters on the right-hand side have been defined above. This is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. Note that JB is expressed in units of C/W, and that this parameter and the way it is measured are still in JEDEC committee.
JC
This JEDEC designated parameter correlates the junction temperature to the case temperature. It is generally used to infer the junction temperature while the device is operating in the system. It is not considered a true thermal resistance, and it is defined by:
TJ - TC JC = ------------------Q
FPSC Maximum Junction Temperature
Once the power dissipated by the FPSC has been determined (see the Estimating Power Dissipation section), the maximum junction temperature of the FPSC can be found. This is needed to determine if speed derating of the device from the 85 C junction temperature used in all of the delay tables is needed. Using the maximum ambient temperature, TAmax, and the power dissipated by the device, Q (expressed in C), the maximum junction temperature is approximated by: TJmax = TAmax + (Q * JA) Figure 21 lists the thermal characteristics for all packages used with the ORCA ORLI10G FPSC.
where TC is the case temperature at top dead center, TJ is the junction temperature, and Q is the chip power. During the JA measurements described above, besides the other parameters measured, an additional temperature reading, TC, is made with a thermocouple attached at top-dead-center of the case. JC is also expressed in units of C/W.
Agere Systems Inc.
65
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Package Thermal Characteristics
Table 21. ORCA ORLI10G Plastic Package Thermal Guidelines Package 0 fpm
JA (C/W)
200 fpm 500 fpm
Max Power T = 70 C Max TJ = 125 C Max 0 fpm (W) 3.05 4.10
416-Pin PBGAM 680-Pin PBGAM
18.0 13.4
16.5 11.5
13.5 10.5
Note: The 416-Pin PBGAM and the 680-Pin PBGAM packages include 2 oz. copper plates.
Heat Sink Vendors for BGA Packages
The estimated worst-case power requirements for the ORLI10G with a programmable XGMII to XSBI interface for 10 Gbits/s Ethernet applications is 4 W to 5 W. Consequently, for most applications an external heat sink will be required. Below, in alphabetical order, is a list of heat sink vendors who advertise heat sinks aimed at the BGA market. Table 22. Heat Sink Vendors Vendor Aavid Thermal Technology Chip Coolers IERC R-Theta Sanyo Denki Thermalloy Wafefield Engineering Location Laconia, NH Warwick, RI Burbank, CA Buffalo, NY Torrance, CA Dallas, TX Wakefield, MA Phone (603) 527-2152 (800) 227-0254 (818) 842-7277 (800) 388-5428 (310) 783-5400 (214) 243-4321 (617) 246-0874
Package Coplanarity
The coplanarity limits of the Agere packages are as follows:
s
PBGAM: 8.0 mils
66
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Package Parasitics
The electrical performance of an IC package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. Table 23 lists eight parasitics associated with the ORCA packages. These parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. Four inductances in nH are listed: LSW and LSL, the self-inductance of the lead; and LMW and LML, the mutual inductance to the nearest neighbor lead. These parameters are important in determining ground bounce noise and inductive crosstalk noise. Three capacitances in pF are listed: CM, the mutual capacitance of the lead to the nearest neighbor lead; and C1 and C2, the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). These parameters are important in determining capacitive crosstalk and the capacitive loading effect of the lead. Resistance values are in m. The parasitic values in Table 23 are for the circuit model of bond wire and package lead parasitics. If the mutual capacitance value is not used in the designer's model, then the value listed as mutual capacitance should be added to each of the C1 and C2 capacitors. Table 23. ORCA ORLI10G Package Parasitics Package Type 416-Pin PBGAM 680-Pin PBGAM LSW 3.52 3.80 LMW 0.80 1.30 RW 235 250 C1 0.40 0.50 C2 1.0 1.0 CM 0.25 0.30 LSL 1.5--5.0 2.8--5.0 LML 0.5--1.30 0.5--1.50
LSW PAD N
RW
LSL
CIRCUIT BOARD PAD
C1 LMW CM LML
C2
PAD N + 1 LSW RW C1 LSL C2
5-3862(C)r2
Figure 26. Package Parasitics
Agere Systems Inc.
67
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Package Outline Diagrams
Terms and Definitions
Basic Size (BSC): The basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. Design Size: The design size of a dimension is the actual size of the design, including an allowance for fit and tolerance. Typical (TYP): When specified after a dimension, this indicates the repeated design size if a tolerance is specified or repeated basic size if a tolerance is not specified. Reference (REF): The reference dimension is an untoleranced dimension used for informational purposes only. It is a repeated dimension or one that can be derived from other values in the drawing. Minimum (MIN) or Maximum (MAX): Indicates the minimum or maximum allowable size of a dimension.
68
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Package Outline Diagrams (continued)
416-Pin PBGAM
Dimensions are in millimeters.
27.00 PIN A1 CORNER 24.00
24.00 27.00
0.61 0.08
1.17 0.05
2.28 0.10 SEATING PLANE 0.20
0.50 0.10
SOLDER BALL 25 SPACES @ 1.00 = 25.00 CORNER A1 BALL
25 23 21 19 17 15 13 11 26 24 22 20 18 16 14 12 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
0.63 0.15
25 SPACES @ 1.00 = 25.00
CENTER ARRAY FOR THERMAL ENHANCEMENT
1139(F)
Agere Systems Inc.
69
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Data Sheet October 2001
Package Outline Diagrams (continued)
680-Pin PBGAM
Dimensions are in millimeters.
35.00 A1 BALL IDENTIFIER ZONE 30.00 - 0.00
+ 0.70
35.00
30.00 - 0.00
+ 0.70
1.170 0.61 0.08 SEATING PLANE 0.20 SOLDER BALL 0.50 0.10 33 SPACES @ 1.00 = 33.00 2.51 MAX
AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 27 29 31 33 10 12 14 16 18 20 22 24 26 28 30 32 34
0.64 0.15
33 SPACES @ 1.00 = 33.00
A1 BALL CORNER
5-4406(F)
70
Agere Systems Inc.
Data Sheet October 2001
ORCA ORLI10G Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC
Hardware Ordering Information
ORLI10G -1 BM 680 DEVICE TYPE SPEED GRADE TEMPERATURE RANGE NUMBER OF PINS PACKAGE TYPE
5-6435 (F).Q
ORLI10G, -1 speed grade, 680-pin plastic ball grid array multilayer (PBGAM). Table 24. Device Type Options Device ORLI10G Table 25. Temperature Options Symbol (Blank) Description Industrial Temperature -40 C to +85 C Voltage 1.5 V internal
Table 26. Package Options Symbol BM Description Plastic Ball Grid Array, Multilayer (PBGAM)
Table 27. Package Matrix (Speed Grade) Devices ORLI10G 416-Pin PBGAM -1, -2, -3 680-Pin PBGAM -1, -2, -3
Software Ordering Information
Implementing a design in an ORLI10G FPSC requires the ORCA Foundry development system and an ORLI10G design kit. For ordering information please visit: http://www.agere.com/micro/netcom/ipkits
Agere Systems Inc.
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IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. EIA is a registered trademark of Electronic Industries Association. PAL is a trademark of Advanced Micro Devices, Inc. PowerPC is a registered trademark of International Business Machines, Inc. AMBA is a trademark and ARM is a registered trademark of Advanced RISC Machines Limited. Synopsys Smart Model is a registered trademark of Synopsys, Inc. Motorola is a registered trademark of Motorola, Inc.
For additional information, contact your Agere Systems Account Manager or the following: http://www.agere.com or for FPGAs/FPSCs http://www.agere.com/orca INTERNET: docmaster@agere.com E-MAIL: N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) Tel. (44) 7000 624624, FAX (44) 1344 488 045 EUROPE:
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. ORCA is a registered trademark of Agere Systems Inc. Foundry is a trademark of Xilinx.
Copyright (c) 2001 Agere Systems Inc. All Rights Reserved
October 2001 DS01-277NCIP (Replaces DS01-269NCIP)

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