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NCV8509 Series Sequenced Linear Dual-Voltage Regulator
The NCV8509 Series are dual voltage regulators whose output voltages power up in such a manner as to protect the integrity of modern day microcontroller I/O and ESD input structures. Newer generation microcontrollers require two power supplies. One voltage is used for powering the core, while the other powers the I/O.
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SOIC 16 LEAD WIDE BODY EXPOSED PAD PDW SUFFIX CASE 751AG
* Power-Up Sequence * Output Voltage Options:
VOUT1 5 V (2%) 115 mA, VOUT2 2.6 V (2%) 100 mA VOUT1 5 V (2%) 115 mA, VOUT2 2.5 V (2%) 100 mA VOUT1 3.3 V (2%) 115 mA, VOUT2 1.8 V (2%) 100 mA Low 175 mA Quiescent Current Power Shunt Programmable RESET Time Dual Drive RESET Valid Programmable SLEW Rate Control Thermal Shutdown 16 Lead SOW Exposed Pad NCV Prefix, for Automotive and Other Applications Requiring Site and Change Control Pb-Free Packages are Available
16 1
* * * * * * * * *
MARKING DIAGRAM
16 NCV8509xx AWLYYWWG
1 = Voltage Ratings as Indicated Below: 26 = 5 V/2.6 V 25 = 5 V/2.5 V 18 = 3.3 V/1.8 V A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Device xx
Typical Applications
* Automotive Powertrain * Telematics
MRA4004T3 VIN1 CIN1 10 F VBAT REX 138 CIN2 0.1 F VIN2 VOUT1 CVOUT1 10 F Microprocessor CVOUT2 10 F RRESET 10 k CSLEW 33 nF
PIN CONNECTIONS
1 SLEW Delay GND NC NC RESET NC NC 16 NC VOUT1 NC VIN1 VIN2 NC VOUT2 NC
VOUT2
NCV8509
SLEW
RESET Delay GND CDelay 33 nF
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet.
Figure 1. Application Diagram
(c) Semiconductor Components Industries, LLC, 2006
1
February, 2006 - Rev. 22
Publication Order Number: NCV8509/D
NCV8509 Series
MAXIMUM RATINGS
Rating VIN1 (dc) VIN1 Peak Transient Voltage VIN2 (dc) VIN2 (Current out of pin) Operating Voltage Input Voltage Range (SLEW, RESET, Delay) VOUT1 VOUT2 Electrostatic Discharge (Human Body Model) (Machine Model) Package Thermal Resistance, SOW-16 E Pad: Lead Temperature Soldering: Junction-to-Case, RJC Junction-to-Ambient, RJA Reflow: (SMD styles only) (Note 1) Value -0.3 to 50 50 50 10 50 -0.3 to 10 10 10 4.0 400 16 57 240 peak (Note 2) Unit V V V mA V V V V kV V C/W C/W C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. 60 second maximum above 183C. 2. -5C/+0C allowable conditions.
ELECTRICAL CHARACTERISTICS (6.0 V < VIN1 < 18 V, IVOUT1 = 5.0 mA, IVOUT2 = 5.0 mA, -40C < TJ < 125C,
CVOUT1 = CVOUT2 = 10 mF; unless otherwise noted.) Characteristic VOUT1 Output Voltage 5 V Option 3.3 V Option Dropout Voltage (VIN1 - VOUT1) Load Regulation Line Regulation Current Limit VOUT2 Output Voltage 2.6 V Option 2.5 V Option 1.8 V Option Load Regulation Line Regulation Current Limit General Quiescent Current Thermal Shutdown (Note 3) 3. Both outputs will turn off. IOUT1 = IOUT2 = 100 A, VIN1 = 12 V IOUT1 = IOUT2 = 50 mA, VIN1 = 14 V (Guaranteed by Design) - - 150 125 5.0 180 175 10 210 A mA C 1.0 mA < IVOUT2 < 100 mA 1.0 mA < IVOUT2 < 100 mA 1.0 mA < IVOUT2 < 100 mA 1.0 mA < IVOUT2 < 100 mA 6.0 V < VIN1 = VIN2 < 18 V VOUT2 = VOUT2 (typ) - 500 mV VOUT2 = 0 V 2.548 2.450 1.764 - - 105 - 2.6 2.5 1.8 5.0 10 305 105 2.652 2.550 1.836 50 50 610 300 V V V mV mV mA mA 1.0 mA < IVOUT1 < 100 mA 1.0 mA < IVOUT1 < 100 mA IOUT = 100 mA IOUT = 100 A 1.0 mA < IVOUT1 < 100 mA 6.0 V < VIN1 < 18 V VOUT1 = VOUT1 (typ) - 500 mV VOUT1 = 0 V 4.9 3.234 - - - - 115 - 5.0 3.3 400 100 10 10 305 105 5.1 3.366 600 200 50 50 610 300 V V mV mV mV mV mA mA Test Conditions Min Typ Max Unit
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NCV8509 Series
ELECTRICAL CHARACTERISTICS (continued) (6.0 V < VIN1 < 18 V, IVOUT1 = 5.0 mA, IVOUT2 = 5.0 mA, -40C < TJ < 125C, CVOUT1 = CVOUT2 = 10 mF; unless otherwise noted.)
Characteristic SLEW SLEW Charging Current VOUT1 SLEW Rate (Note 4) 5 V Option 3.3 V Option VOUT2 SLEW Rate 2.6 V Option 2.5 V Option 1.8 V Option SLEW Control Threshold RESET RESET Threshold Increasing (Note 5) RESET Threshold Decreasing 5 V Option 3.3 V Option 2.6 V Option 2.5 V Option 1.8 V Option RESET Output Low RESET Output Peak RESET Threshold Hysteresis 5 V Option 3.3 V Option 2.6 V Option 2.5 V Option 1.8 V Option Delay Delay Switching Threshold Delay Charge Current Delay Saturation Voltage Delay Discharge Current Output Tracking Delta 1 [VOUT1 - VOUT2] 5 V Option 3.3 V Option Delta 2 [VOUT2 - VOUT1] Power Shunt Shunt Voltage 1 (VIN2) Shunt Voltage 2 (VIN2) VIN1 = 6.0 V, IOUT2 = 100 mA, No REX VIN1 = 12 V, 1.0 mA < IOUT2 < 100 mA, No REX 3.3 3.25 - 4.5 4.6 5.75 V V COUT1 = COUT2 , IOUT1 = IOUT2 COUT1 = COUT2 , IOUT1 = IOUT2 COUT1 = COUT2 , IOUT1 = IOUT2 - - - - - - 3.2 2.8 100 V V mV Delay = 1.0 V VOUT1 Out of Regulation Delay = 5.0 V VOUT1 out of Regulation - 1.125 4.0 - 10 1.5 6.0 - - 1.875 8.0 0.1 - V A V mA IRESET = 1.0 mA Power Down (See Figure 41) - 50 33 26 25 18 100 66 52 50 36 150 99 78 75 54 mV mV mV mV mV - - 4.5 2.97 2.34 2.25 1.62 - - 4.73 3.12 2.46 2.36 1.70 0.1 0.6 0.965 x VOUT 0.965 x VOUT 0.965 x VOUT 0.965 x VOUT 0.965 x VOUT 0.4 1.0 V V V V V V V 94.5 96.5 98.5 % SLEW = 1.0 V CSLEW = 33 nF - - CSLEW = 33 nF - - - (See Figure 53) 1.5 370 355 256 1.8 - - - 2.1 V/s V/s V/s V 710 469 - - V/s V/s 4.0 6.0 8.0 A Test Conditions Min Typ Max Unit
4. Not a tested parameter. 5. RESET signal sensitive to VOUT1 and VOUT2.
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NCV8509 Series
PIN DESCRIPTION
Pin No. 1 2 3 Symbol SLEW Delay GND NC Description Control for output rise time during power up. Requires capacitor to ground. Timing capacitor for RESET function. Ground.
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4, 5, 7-9, 11, 14, 16 6 No connection. RESET VOUT2 VIN2 VIN1 Active reset (accurate to VOUT > 1.0 V). 10 12 13 15 100 mA output (2% output voltage) for powering microprocessor core. Input voltage for VOUT2. Input voltage for VOUT1, and internal circuitry. VOUT1 100 mA output (2% output voltage) for powering microprocessor I/O. VIN1 CIN1 VREF REX SLEW Control VIN2 CIN2 Power Shunt VBG VREF + + + - VIN1 SLEW CSLEW Bandgap & Bias VOUT1 Error Amp VREF COUT1 Start-Up Current + - GND + + + - - + VOUT1 VIN1 RESET VOUT1 VBG - + Delay Discharge Latch VREF RESET Comp Delay CDelay VIN2 Thermal Shutdown VOUT2 Error Amp VREF COUT2 Start-Up Current
Figure 2. Block Diagram http://onsemi.com
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NCV8509 Series
TYPICAL PERFORMANCE CHARACTERISTICS
2.65 2.64 2.63 2.62 Voltage (V) 2.61 2.60 2.59 2.58 2.57 2.56 2.55 -40 -20 0 20 40 60 80 Temperature (C) 100 120 140 IVOUT1 = 5 mA IVOUT2 = 5 mA Voltage (V) 3.37 3.36 3.35 3.34 3.33 3.32 3.31 3.30 3.29 3.28 3.27 3.26 3.25 3.24 3.23 -40 -20
IVOUT1 = 5 mA IVOUT2 = 5 mA 0 20 40 60 80 Temperature (C) 100 120 140
Figure 3. 2.6 V Output Voltage
2.55 2.54 2.53 2.52 Voltage (V) 2.51 2.50 2.49 2.48 2.47 2.46 2.45 -40 -20 0 20 40 60 80 Temperature (C) 100 120 140 IVOUT1 = 5 mA IVOUT2 = 5 mA Voltage (V) 1.81 1.80 1.79 1.78 1.77 1.84 1.83 1.82
Figure 4. 3.3 V Output Voltage
IVOUT1 = 5 mA IVOUT2 = 5 mA 0 20 40 60 80 Temperature (C) 100 120 140
1.76 -40 -20
Figure 5. 2.5 V Output Voltage
Figure 6. 1.8 V Output Voltage
5.10 5.08 5.06 VIN2 (VOLTS) 5.04 Voltage (V) 5.02 5.00 4.98 4.96 4.94 4.92 4.90 -40 -20 0 20 40 60 80 Temperature (C) 100 120 140 IVOUT1 = 5 mA IVOUT2 = 5 mA
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 1.8 V 0.5 0 0 2 4 6 8 10 VIN1 (VOLTS) 12 2.6 V Rex = 14 16 2.5 V
Figure 7. 5.0 V Output Voltage
Figure 8. VIN2 versus VIN1
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NCV8509 Series
TYPICAL PERFORMANCE CHARACTERISTICS
1.8 1.6 125C 1.4 1.2 IQ (mA) 1.0 0.8 0.6 0.4 0.2 0 0 5 10 15 IOUT1 (mA) 20 25 2 0 0 10 20 30 40 50 60 IOUT1 (mA) 70 80 90 100 IQ (mA) -40C 25C 8 6 4 -40C 10 25C 12 125C
Figure 9. IQ versus IOUT1
Figure 10. IQ versus IOUT1
1.2 1.0 25C 0.8 IQ (mA) IQ (mA) 125C 0.6 0.4 0.2 0 0 5 10 15 IOUT2 (mA) 20 25 -40C
3.0 -40C 2.5 2.0 1.5 1.0 0.5 0 0 10 20 30 40 50 60 IOUT2 (mA) 70 80 90 100 25C 125C
Figure 11. IQ versus IOUT2
Figure 12. IQ versus IOUT2
2.5
14 12 125C 25C
2.0 10 IQ (mA) IQ (mA) 1.5 8 6 4 25C 5 15 IOUT1, IOUT2 (mA) 10 20 25 2 0 0 0 10 20 30 40 50 60 70 IOUT1, IOUT2 (mA)
-40C
1.0 -40C 0.5 125C 0
80
90 100
Figure 13. IQ versus IOUT (VOUT1 & VOUT2)
Figure 14. IQ versus IOUT (VOUT1 & VOUT2)
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NCV8509 Series
TYPICAL PERFORMANCE CHARACTERISTICS
6 5 4 VOUT1 (V) 3 2 1 0 0 1 2 3 4 5 VIN1 (V) 6 7 8 9 10 125C 25C -40C VOUT1 (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 125C 1 2 25C 3 4 -40C 5 6 VIN1 (V) 7 8 9 10
Figure 15. VOUT1 (5 V) versus VIN1
Figure 16. VOUT1 (3.3 V) versus VIN1
3.0 2.5 2.0 VOUT2 (V) 1.5 1.0 0.5 0 0 125C 1 2 25C 3 4 -40C 5 VIN1 (V) 6 7 8 9 10 VOUT2 (V)
3.0 2.5 2.0 1.5 1.0 0.5 0 0 125C 1 2 25C 3 4 -40C 5 6 VIN1 (V) 7 8 9 10
Figure 17. VOUT2 (2.6 V) versus VIN1
Figure 18. VOUT2 (2.5 V) versus VIN1
2.0 1.8 1.6 1.4 VOUT2 (V) 1.2 1.0 0.8 0.6 0.4 0.2 0 0 125C 1 2 25C 3 4 -40C 6 5 VIN1 (V) 7 8 9 10
Figure 19. VOUT2 (1.8 V) versus VIN1
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NCV8509 Series
TYPICAL PERFORMANCE CHARACTERISTICS
10 RESET DELAY TIME (mS) 40 35 9.5 TIME (mS) 0 20 40 60 80 TEMPERATURE (C) 100 120 30 25 20 15 10 5 7.5 -40 -20 0 0 20 40 60 80 100 CDelay (nF) 120 140 160
9.0
8.5
8.0
Figure 20. Reset Delay Time versus Temperature
2500 5V 2000 600 VOLTS/SEC VOLTS/SEC 3.3 V 1500 2.6 V 1000 2.5 V 1.8 V 500 0 0 500 400 800 700
Figure 21. Reset Delay Time versus CDelay
5V
3.3 V 2.6 V
300 2.5 V 200 1.8 V 100 0
10
20
30
40 50 60 CSLEW (nF)
70
80
90
100
30
40
50
60 70 CSlew (nF)
80
90
100
Figure 22. Slew Rate versus CSlew
Figure 23. Slew Rate versus CSlew
450 400 DROPOUT VOLTAGE (mV) 350 300 250 200 150 100 50 0 0 25 3.3 V/1.8 V
5 V/2.5 V QUIESCENT CURRENT (mA)
16 14 12 10 8 6 4 2 0 Iout1 = Iout2 = 50 mA 0 2 4 6 8 10 12 14 OUTPUT CURRENT (mA) 16 18 3.3 V/1.8 V 5 V/2.5 V 5 V/2.6 V
5 V/2.6 V
50 75 100 OUTPUT CURRENT (mA)
125
Figure 24. VOUT1 Dropout Voltage
Figure 25. Quiescent Current vs. VIN1
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NCV8509 Series
TYPICAL PERFORMANCE CHARACTERISTICS
1000 UNSTABLE REGION 3.3 V 5.0 V 10 ESR (W) ESR (W) 10 STABLE REGION 1.8 V 1 STABLE REGION 100 UNSTABLE REGION 2.5 V
100
2.6 V
1
0.1 CVOUT1 = 10 mF 0.01
0.1 CVOUT2 = 10 mF 0 10 20 30 40 50 60 70 OUTPUT CURRENT (mA) 80 90 100
0.01 0 10 20 30 40 50 60 70 OUTPUT CURRENT (mA) 80 90 100
Figure 26. VOUT1 Output Capacitor ESR (10 mF)
Figure 27. VOUT2 Output Capacitor ESR (10 mF)
1000
3.3 V, 0.1 mF
100 5.0 V, 0.1 mF 5.0 V, 1.0 mF ESR (W) 10
UNSTABLE REGION STABLE REGION 0.1 mF
1 mF
100 3.3 V, 1.0 mF UNSTABLE REGION 1 STABLE REGION
ESR (W)
10
1 1 mF 0.1 UNSTABLE REGION
0.1
0.01
0.01 0 10 20 30 40 50 60 70 OUTPUT CURRENT (mA) 80 90 100 0 10 20 30 40 50 60 70 OUTPUT CURRENT (mA) 80 90 100
Figure 28. VOUT1 Output Capacitor ESR (0.1 mF / 1 mF)
Figure 29. VOUT2 (2.6 V) Output Capacitor ESR (0.1 mF / 1 mF)
100
UNSTABLE REGION STABLE REGION
100 1 mF 10 ESR (W) 0.1 mF UNSTABLE REGION 1 mF
10 ESR (W)
0.1 mF 1 1 mF 0.1 UNSTABLE REGION
0.1 mF 1 STABLE REGION 0.1 UNSTABLE REGION 1 mF
0.01 0 10 20 30 40 50 60 70 OUTPUT CURRENT (mA) 80 90 100
0.01 0 10 20 30 40 50 60 70 OUTPUT CURRENT (mA) 80 90 100
Figure 30. VOUT2 (2.5 V) Output Capacitor ESR (0.1 mF / 1 mF)
Figure 31. VOUT2 (1.8 V) Output Capacitor ESR (0.1 mF / 1 mF)
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NCV8509 Series
TYPICAL PERFORMANCE CHARACTERISTICS
(Load Transient waveforms shown were measured on the 5 V/2.6 V device)
Figure 32. VOUT1 Load Transient Response 100 mA to No Load & No Load to 100 mA
Figure 33. VOUT2 Load Transient Response 100 mA to No Load & No Load to 100 mA
Figure 34. VOUT1 Load Transient Response 100 mA to No Load
Figure 35. VOUT2 Load Transient Response 100 mA to No Load
Figure 36. VOUT1 Load Transient Response No Load to 100 mA
Figure 37. VOUT2 Load Transient Response No Load to 100 mA
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NCV8509 Series
TIMING DIAGRAMS
VIN1
VOUT1 VOUT2
Outputs are not actively discharged.
Figure 38. Response to Impulse
VIN1 VOUT1
VIN1 VOUT1 Z(VOUT1) << Z(VOUT2)
VIN1 VOUT1 Z(VOUT1) >> Z(VOUT2) VOUT2
VOUT2
VOUT2
Figure 39. Output Decay vs. Load Impedance
Max VIN Delta I(VIN2) x REX Power Shunt Off 4.5 V Power Shunt On VIN1 VIN2
Figure 40. VIN Power Shunt
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NCV8509 Series
CIRCUIT DESCRIPTION
VIN
VOUT1
RESET Reset Delay Power Up Reset Delay Short on VOUT1 Reset Delay RESET Output Peak
VIN1 Fast Turn Off
Figure 41. Dual Drive RESET Valid
RESET
The RESET function gets its drive from both the input (VIN1) and the output (VOUT1). Because of this, it is able to maintain a more reliable reset valid signal. Most regulators maintain a valid reset signal down to 1 V on the output voltage. The reset on the NCV8509 is valid down to 0 V on the output voltage VOUT1 (power is provided via VIN1) and the reset on the NCV8509 is valid down to 0 V on the input voltage VIN1 (power is provided via VOUT1). Refer to Figure 41 for operation timing diagrams.
Delay Function
The delay capacitor is discharged when the regulation (RESET threshold) has been violated. This is a latched incident. The capacitor will fully discharge and wait for the device to regulate before going through the delay time event again.
Power Shunt
The reset delay circuit provides a programmable (by external capacitor) delay on the RESET output lead. The delay lead provides source current (typically 6.0 A) to the external delay capacitor during the following proceedings: 1. During power up (once the regulation threshold has been verified); 2. After a reset event has occurred and the device is back in regulation.
REX routes some of the current used in the VOUT2 to a second input pin (VIN2). This is accomplished by using an internal shunt. A simplified version of this shunt is shown in Figure 42. This has the effect of reducing the amount of power dissipated on chip. The effects of choosing the external resistor value are shown in Figure 43. Selection of the optimum Rex resistor value can be done using the following equation:
(Vin(max) * 4.5) Iout2(max)
When not using the power shunt, short VIN1 to VIN2.
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NCV8509 Series
VIN1 1.8 1.6 1.4 REX Watts REX > 138 1.2 1.0 0.8 0.6 0.4 0.2 VOUT2 0 0 5 10 VIN 15 REX < 138 REX = 138
VIN2 Voltage Regulator
IOUT2 = 100 mA 20 25
Figure 42. Power Shunt
Figure 43. Power On Chip
VIN1 18 V 135 100 mA VIN2 4.5 V VOUT2 2.5 V 100 mA RLOAD + 600 mV - 135
VIN1 6.0 V 135 21.5 mA VIN2 3.1 V VOUT2 2.5 V 21.5 mA RLOAD 78.5 mA
VIN1 6.0 V
21.5 mA VIN2 4.5 V VOUT2 2.5 V 100 mA
RLOAD
Figure 44.
Figure 45.
Figure 46.
Why Use a Power Shunt?
The power shunt circuitry helps manage and optimize power dissipation on the integrated circuit. Figure 44 shows a 100 mA load. A 135 resistor dissipates 1.35 W as shown. Without the power shunt, the 135 resistor would run into head room issues at 6.0 V and would only be able to drive 21.5 mA as shown in Figure 45 before causing the 2.5 V output to collapse. Figure 46 shows the power shunt circuitry adding the current back in at low voltage operation. So the power is moved off chip at high voltage where it is needed most. To further clarify, Figure 47 shows the maximum allowed resistor value (29 ) without the power shunt for 6.0 V operation. Figure 48 shows the scenario at high voltage. Only 290 mW of power is dissipated off chip compared to Figure 44 with 1.35 W.
VIN1 6.0 V 29 100 mA VIN2 3.1 V + 600 mV - VOUT2 2.5 V 100 mA RLOAD 29
VIN1 18 V
100 mA VIN2 15.1 V VOUT2 2.5 V 100 mA
RLOAD
Figure 47.
Figure 48.
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NCV8509 Series
NCV8509
Power Dissipation
VIN1
Shunt
NCV8509 has a power shunt circuit which reduces the power on chip by utilizing an external resistor, REX. Thus the power on chip, PIC, is equal to the total power, PT, minus the power dissipated in the resistor PREX. Refer to Figure 49.
PIC + PTOTAL * PREX
(1)
Iq REX + VSAT Q1 -
where
PTOTAL + (VIN1 * VOUT1) IOUT1 ) (VIN1 * VOUT2) IOUT2 ) (VIN1
(2) VIN2
VZ
Iq)
Q2 (3) VOUT2
and
PREX + (VIN1 * VIN2) IOUT2
Control Circuitry
Q3 VOUT1
IOUT2
GND
IOUT1
Figure 49. VIN1 * VSAT VREF VIN1 * (IOUT2 REX) for VIN1 t (VREF ) VSAT) for (VREF ) VSAT) t VIN1 t (VREF ) (IOUT2 for (VREF ) (IOUT2 IOUT)) t VIN1
(4)
VIN2 +
REX))
where VREF = VZ - VBE when Q1 is normally conducting. Based on equation 3, the power in REX is dependent on VIN2. (Increasing REX may require an increase in CIN2. A careful system validation should be performed for stability). The voltage on VIN2 is controlled by the shunt circuit, which has three modes of operation, as seen in Figure 50. Mode 1. At low battery VIN2 is equal to VIN1 minus the saturation voltage of the shunt output NPN. Mode 2. Once VIN1 rises above the reference voltage of the shunt circuit, VIN2 will regulate at the VREF. Mode 3. VIN2 would continue to regulate at VREF, but since IOUT2 is not infinite, when VIN1 rises higher than the reference voltage plus the voltage drop across the external resistor REX, it will force VIN2 to be VIN1 - (IOUT2 x REX). Equation 4 provides a summary for VIN2. Combining equations 3 and 4 gives three different equations for power across REX.
PMODE1 + (VSAT IOUT2) IOUT2 REX
(5) (6) (7)
PMODE2 + (VIN1 * VREF) PMODE3 + IOUT22
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NCV8509 Series
Max VIN Delta I(VIN2) x REX Shunt Off 4.5 V Shunt On VIN1 Mode 1 VIN1 t VREF ) VSAT VIN2 + VIN1 * VSAT Mode 2 VREF ) VSAT t VIN1 t VREF ) (IOUT2 VIN2 + VREF REX) VIN2 Mode 3 VIN1 u VREF ) (IOUT2 VIN2 + VIN1 * (IOUT2 REX) REX)
Figure 50. VIN Shunt
100 Thermal Resistance, Junction to Ambient, RqJA, (C/W) 90 80 70 60 50 40 0 200 600 400 Copper Area (mm2) 800
RqJA's less than the calculated value in equation 2 will keep the die temperature below 150C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.
Heat Sinks
A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA:
RqJA + RqJC ) RqCS ) RqSA
(9)
Figure 51. 16 Lead SOW (Exposed Pad), qJA as a Function of the Pad Copper Area (2 oz. Cu Thickness), Board Material = 0.0625, G-10/R-4
Once the value of PIC(max) is known, the maximum permissible value of RqJA can be calculated:
T RqJA + 150C * A PIC
(8)
The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with
where: RqJC = the junction-to-case thermal resistance, RqCS = the case-to-heatsink thermal resistance, and RqSA = the heatsink-to-ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.
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NCV8509 Series
10 s VOUT1
10 s VOUT2
Fast SLEW Rate >> Soft Start
Fast SLEW Rate >> Soft Start
Disable Time
Disable Time Decay Time Dependent on External Load Short On VOUT1 Short On VOUT2
Decay Time Dependent on External Load
Figure 52. Fault Response. Note the High SLEW Rate Coming Out of Fault Conditions. Soft Start Only Applies to a Power Up Sequence. Slew Rate Control
Figure 53 shows the circuitry associated with Slew Rate Control. The diagram highlights the control of one output for simplicity. VOUT1 and VOUT2 are both controlled on the IC. The slew rate capacitor (CSLEW) is charged with an on-chip current source runing at 6.0 mA (typ.). Charging a capacitor with a current source creates a linear voltage ramp as shown in Figure 54. The lowest voltage to the positive terminals of the comparator (Error Amp) dominates the output voltage (VOUT). Consequently, when CSLEW is fully discharged on power up, it is the dominant factor on the positive terminal and disables the output. The output (VOUT) follows the linear ramp on the SLEW pin (after being gained up with R1 and R2) until VBG becomes the dominant voltage. This occurs when SLEW = VBG + VD1 or approximately 1.8 V.
Internal Voltage Rail 3.8 V VIN1 6.0 A SLEW VBG D2 D1 VOUT
Slew time can be calculated using the standard capacitor equation.
I + C dv , t + dt C(DV) I
Using a 33 nF capacitor, the slew time is:
t+ (33 nF)(1.8 V) + 9.9 ms 6 mA
The corresponding slew rate for this is 1.8 V/9.9 ms = 182 V/s ON THE SLEW PIN. To calculate the slew rate on outputs, you must multiply by the gain set up by R1 and R2.
V Av + OUT 1.28 V
For a 5 V output, the gain would be:
Av + 5 V + 3.9 V V 1.28 V
assuming VBG = 1.28 V. The resultant slew rate on the output is the slew rate on the SLEW pin multiplied by the gain, or:
(182 V s) (3.9 V V) + 710 V s
SLEW Pin Voltage (V)
CSLEW
+ + - Error Amp
3.8
R1
Outputs in Regulation 1.8
R2
Figure 53. Slew Control Circuitry
tSLEW Time (ms)
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NCV8509 Series
ORDERING INFORMATION
Device NCV8509PDW18 NCV8509PDW18G NCV8509PDW18R2 NCV8509PDW18R2G NCV8509PDW25 NCV8509PDW25G NCV8509PDW25R2 NCV8509PDW25R2G NCV8509PDW26 NCV8509PDW26G NCV8509PDW26R2 NCV8509PDW26R2G 5 V/2.6 V 5 V/2.5 V 3.3 V/1.8 V Output Voltage Package SOIC 16 Lead SOIC 16 Lead (Pb-Free) SOIC 16 Lead SOIC 16 Lead (Pb-Free) SOIC 16 Lead SOIC 16 Lead (Pb-Free) SOIC 16 Lead SOIC 16 Lead (Pb-Free) SOIC 16 Lead SOIC 16 Lead (Pb-Free) SOIC 16 Lead SOIC 16 Lead (Pb-Free) 1000 Tape & Reel 47 Units/Rail 1000 Tape & Reel 47 Units/Rail 1000 Tape & Reel Shipping 47 Units/Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NCV8509 Series
PACKAGE DIMENSIONS
SOIC 16 LEAD WIDE BODY EXPOSED PAD PDW SUFFIX CASE 751AG-01 ISSUE O
-U- A M
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751R-01 OBSOLETE, NEW STANDARD 751R-02. MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 3.31 3.51 0.25 0.32 0.00 0.10 4.58 4.78 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.130 0.138 0.010 0.012 0.000 0.004 0.180 0.188 0_ 7_ 0.395 0.415 0.010 0.029
P 0.25 (0.010)
M
W
M
1 8
B R x 45_ -W-
PIN 1 I.D.
G TOP SIDE
14 PL
DETAIL E
C -T- 0.10 (0.004) T D 16 PL 0.25 (0.010) H
M
F
K TU
S
SEATING PLANE
W
S
J DETAIL E
EXPOSED PAD
1
8
DIM A B C D F G H J K L M P R
L
16 9
BACK SIDE
SOLDERING FOOTPRINT*
0.350 0.175 0.050 Exposed Pad
C L 0.200 0.074
0.188 C L 0.376
0.024
0.145
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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18
NCV8509 Series
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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19
NCV8509/D

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