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| E2F0009-18-62 Semiconductor MSM7661B Semiconductor NTSC/PAL Digital Video Decoder This version: MSM7661B Jun. 1998 Pr el im in ar y GENERAL DESCRIPTION The MSM7661B is an LSI device which converts digitally sampled NTSC or PAL video signals to 8-bit format based on ITU-RBT601. The input video signals available are composite video signals and S video signals. The composite video signals are converted to YUV data via a 2-dimensional Y/C separation circuit. The A-to-D converted data is data sampled at pixel clock frequency or double pixel clock frequency (the built-in decimation filter is used). Input signal synchronization can lock synchronization and color burst at high speed through internal digital processing. The MSM7661B is upward compatible with the MSM7661. It provides additional features which are added to the MSM7661 indicated by the mark n and is superior to the MSM7661 in picture quality and synchronization stability. The device, which includes an additional register added to the MSM7661, has electrical characteristics which are nearly equal to those of the MSM7661. The MSM7661B allows a pin-for-pin replacement with the MSM7661. FEATURES (* indicates a new feature compared with MSM7660. n indicates a new feature compared with MSM7661.) * Input video signals include the following two types of digital data that are A-to-D converted at pixel frequency or double pixel frequency : NTSC/PAL composite video signal NTSC/PAL S video signal 8-bit Y/8-bit C (CbCr) output (conforms to ITU-RBT601) YCbCr 4:2:2 YCbC 4 : 1 : 1 nYCbCr 8-bit multiplex output (27 MHz) (not including SAV and EAV) * 2-dimensional Y/C separation using adaptive comb filter (this filter is bypassed for S video signal input) NTSC: 3 lines/2 lines PAL: 2 lines (3 virtual lines) * Input signal synchronization can lock synchronization and color burst at high speed through internal digital processing. Sampling frequency 13.5 MHz (ITU-R601) 12.27 MHz (NTSC Square Pixel) 14.31818 MHz (NTSC 4Fsc) 14.75 MHz (PAL Square Pixel) * Internal AGC/ACC circuit Switchable between AGC and MGC (fixed gain) nSwitchable between ACC and MCC (fixed gain) * Built-in decimation filter located in the input stage allows easy configuration of an external filter circuit (located ahead of A/D converter). * Automatic NTSC/PAL recognition (only for ITU-RBT.601) * Sleep mode 1/42 Semiconductor * Multiplex signal recognition (Teletext) Data during vertical blanking is output in 8 bits in Through mode. I2C-bus interface * 3.3 V single power supply (each I/O pin is 5 V tolerable) * Package: 64-pin plastic QFP (QFP64-P-1414-0.80-BK) (Product name: MSM7661B GS-BK) MSM7661B 2/42 BLOCK DIAGRAM Semiconductor SYNC (CSYNC_L) PLLSEL CLKX2O CLKSEL SYSSEL HSY VSYNC_L HSYNC_L VVALID ODD CLKX2 CLKXO HVALID VCO_CP Synchronization Block 8 bits (YCbCr) Luminance Block (AGC + LPF) Y[7:0] YD[7:0] Decimation Filter lum. Prologue Block Epilogue Block (Output Formatter) (2Dim. Y/C separate) CD[7:0] Decimation Filter Line Memory (1kbyte) 2 chr. Chrominance Block (ACC + LPF) MODE[3:0] C[7:0] I2C-bus Control Logic Test Control Logic MSM7661B SCL SDA RESET_L TE TEST1 TEST2 (SLEEP) 3/42 Semiconductor MSM7661B PIN CONFIGURATION (TOP VIEW) 56 CLKXO 55 HSYNC_L 54 VSYNC_L 53 HVALID 60 SYNC 59 VCO_CP 58 CLKX2O 57 SYSSEL 52 VVALID 51 ODD 62 CLKX2 61 HSY 64 VDD 63 GND CD[0] 1 CD[1] 2 CD[2] 3 CD[3] 4 CD[4] 5 CD[5] 6 CD[6] 7 CD[7] 8 CVBS[0] 9 CVBS[1] 10 CVBS[2] 11 CVBS[3] 12 CVBS[4] 13 CVBS[5] 14 CVBS[6] 15 CVBS[7] 16 VDD 17 GND 18 SCL 19 SDA 20 MODE[0] 21 MODE[1] 22 MODE[2] 23 MODE[3] 24 50 GND 49 VDD 48 C[0] 47 C[1] 46 C[2] 45 C[3] 44 C[4] 43 C[5] 42 C[6] 41 C[7] 40 Y[0] 39 Y[1] 38 Y[2] 37 Y[3] 36 Y[4] 35 Y[5] 34 Y[6] 33 Y[7] RESET_L 25 PLLSEL 26 CLKSEL 27 TEST1 28 SLEEP 29 TE 30 64-Pin Plastic QFP GND 31 VDD 32 4/42 Semiconductor MSM7661B PIN DESCRIPTIONS Pin 1 to 8 9 to 16 17 18 19 20 21 to 24 Symbol CD[0 to 7] CVBS[0 to 7] VDD GND SCL SDA MODE[0 to 3] I I/O I I2C-bus clock pin I2C-bus data pin Mode input pins. These pins are internally pulled-down. MODE[3] MODE[1:0] 0: composite 1: S video 00: ITU-R601 01: Square Pixel 10: 4Fsc (only for NTSC) 11: none If ITU-R signals are input when registers are set to automatic NTSC/PAL recognition mode, NTSC/PAL is automatically recognized irrespective of MODE2 setting. 25 26 27 28 29 30 31 32 RESET_L PLLSEL CLKSEL TEST1 SLEEP TE GND VDD I I I I I I System reset pin (active at "L") Unused. Fixed to "H" externally. Clock select input pin. "L" AE double-speed 27 MHz, "H" AE ordinary 13.5 MHz Input pin for testing. Normally "L". Internally pulled down. Sleep mode setting pin. Normally "L". Internally pulled down. Input pin for testing. Normally "L". Internally pulled down. MODE[2] 0: NTSC 1: PAL Type I I Description Chrominance signal input pin (valid only for S video input) Set each pin to "L" level at composite signal input. Composite signal input pin Luminance signal is input for S video input. 5/42 Semiconductor MSM7661B Pin 33 to 40 41 to 48 49 50 51 52 53 54 55 56 57 Symbol Y[7 to 0] C[7 to 0] VDD GND ODD VVALID HVALID VSYNC_L HSYNC_L CLKXO SYSSEL Type O O Description Chrominance signal output pins YCbCr 8-bit multiplex output pins Luminance signal output pins O O O O O O O Field display output pin Outputs "H" for odd field. Vertical valid line timing output pin Horizontal valid pixel timing output pin V sync output pin H sync output pin Internal operation clock output pin Display select output pin for NTSC-PAL detect / multiplex signal detect / HLOCK sync detect. Selection by register. (Default : NTSC-PAL detect) NTSC mode : "L", PAL mode : "H" Multiplex signal detect : "H" HLOCK sync detect : "H" 58 59 60 61 62 63 64 CLKX2O VCO_CP SYNC HSY CLKX2 GND VDD O O I/O O I Clock output pin Unused. Open normally. Composite sync output. Unused as input pin. Clamp signal timing output pin for A/D converter Clock input pin 6/42 Semiconductor MSM7661B ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Input Voltage Power Consumption Storage Temperature Symbol VDD VI PW TSTG Condition -- -- -- -- Rating -0.3 to +4.5 -0.3 to +5.5 800 -55 to +150 Unit V V mW C RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Power Supply Voltage "H" Level Input Voltage "L" Level Input Voltage Operating Temperature Symbol VDD GND VIH VIL Ta Condition -- -- -- -- -- Min. 3.0 -- 2.2 0 0 Typ. 3.3 0 -- -- 25 Max. 3.6 -- VDD 0.8 70 Unit V V V V C 7/42 Semiconductor MSM7661B ELECTRICAL CHARACTERISTICS DC Characteristics (Ta = 0 to 70C, VDD = 3.3 V 0.3 V) Parameter "H" Level Output Voltage Symbol VOH Condition IOH = -4 mA (*1) IOH = -6 mA (*2) IOH = -8 mA (*3) IOL = 4 mA (*1) "L" Level Output Voltage VOL IOL = 6 mA (*2) IOL = 8 mA (*3) VI = GND to VDD Input Leak Current Output Leak Current Power Supply Current (operating) Power Supply Current (operating) Power Supply Current (SLEEP) SDA Output Voltage SDA Output Current II IO IDDO IDDO2 IDDS SDAVL SDAIO Rpull-down = 50 kW (*4) VI = GND to VDD CLK = 27 MHz VDD = 3.3 V CLK = 13.5 MHz VDD = 3.3 V SLEEP ON -- -- -10 20 -10 -- -- -- 0 3 -- -- -- 155 125 1 -- -- +10 250 +10 190 160 5 0.4 -- mA mA mA mA mA V mA -- -- 0.4 V 0.7 VDD -- -- V Min. Typ. Max. Unit *1: *2: *3: *4: HSYNC_L, VSYNC_L, SYSSEL Y[7:0], C[7:0], HSY, HVALID, VVALID, ODD, CLKXO CLKX2O MODE[3:0], SLEEP, TEST1, TE 8/42 Semiconductor AC Characteristics (Single Speed Mode) Parameter Symbol Condition ITU-R601 CLKX2 Cycle Time tCLKX1 NTSC 4Fsc NTSC Square Pixel PAL Square Pixel CLKX2 Duty Input Data Setup Time Input Data Hold Time Output Data Delay Time 1 (*) Output Data Delay Time 2 (*) Output Data Delay Time 3 (*) Output Clock Delay Time (*) (External) Output Clock Delay Time (*) (Internal) SCL Clock Cycle Time Low Level Cycle tD_D1 tIS1 tIH1 tODX1 tOD2X1 tOD1 tCXD1 tCD1 tC_SCL tL_SCL -- CLKSEL : H CLKSEL : H CLKSEL : H CLKSEL : H CLKSEL : H CLKSEL : H CLKSEL : H Rpull_up = 4.7 kW Rpull_up = 4.7 kW MSM7661B (Ta = 0 to 70C, VDD = 3.3 V 0.3 V) Min. -- -- -- -- 40 0 30 2 2 9 7 7 200 100 Typ. Max. 74.07 69.84 81.5 67.8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60 -- -- 8 7 25 17 18 -- -- Unit ns ns ns ns % ns ns ns ns ns ns ns ns ns (*output load 40 pF) AC Characteristics (Double Speed Mode) (Ta = 0 to 70C, VDD = 3.3 V 0.3 V) Parameter Symbol Condition ITU-R601 CLKX2 Cycle Time tCLKX2 NTSC 4Fsc NTSC Square Pixel PAL Square Pixel CLKX2 Duty Input Data Setup Time Input Data Hold Time Output Data Delay Time 1 (*) Output Data Delay Time 2 (*) Output Data Delay Time 3 (*) Output Clock Delay Time (*) (External) Output Clock Delay Time (*) (Internal) SCL Clock Cycle Time Low Level Cycle tD_D2 tIS2 tIH2 tODX2 tOD2X2 tOD2 tCXD2 tCD2 tC_SCL tL_SCL -- CLKSEL : L CLKSEL : L CLKSEL : L CLKSEL : L CLKSEL : L CLKSEL : L CLKSEL : L Rpull_up = 4.7 kW Rpull_up = 4.7 kW Min. -- -- -- -- 40 5 15 2 2 9 7 7 200 100 Typ. Max. 37.05 34.9 40.75 33.9 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60 -- -- 7 6 24 17 18 -- -- Unit ns ns ns ns % ns ns ns ns ns ns ns ns ns (*output load 40 pF) 9/42 Semiconductor Input and Output Timing CLKSEL:H tCLKX1 CLKSEL:L tCLKX2 MSM7661B , ,, , , CLKX2 tCXD1 tCXD2 CLKX2O tCD1 tCD2 CLKXO tIS1 tIH1 tIS2 tIH2 not valid not valid not valid not valid CVBS CD RESET_L tOD2X1 tOD2X2 HSY, HVALID, VVALID, ODD, SYSSEL, Y,C, HSYNC_L, VSYNC_L tOD1 tODX1 tOD2 tODX2 I2C-bus Interface Input/Output Timing The basic input/output timing of the I2C-bus interface is as follows. SDA SCL MSB S Start Condition 1 2 7 8 9 ACK 1 tC_SCL 2 3-8 9 ACK P Stop Condition Data Line Stable: Data Valid Change of Data Allowed I2C-bus Basic Input/Output Timing 10/42 Semiconductor MSM7661B BLOCK DESCRIPTION 1. Prologue Block The prologue block performs Y/C separation by inputting data. Data can be input either at ordinary pixel frequency (ITU-R : 13.5 MHz) or at double pixel frequency (ITU-R: 27 MHz). When the double pixel frequency is used, data is processed after changing to the ordinary pixel frequency via a decimeter circuit. By changing the register setting, the decimeter circuit can be bypassed irrespective of whether data is input at ordinary pixel frequency or at double pixel frequency. The prologue block performs Y/C separation using a 2-dimensional adaptive comb filter when composite signals (CVBS) are input. The following operation modes can be changed via the I2C-bus. The * mark indicates a default. The default is a state that is selected when reset. 1) Video input mode select Composite video input * S video input 2) Video input mode select Auto NTSC/PAL select* (Only for ITU-R601) Dependent on Operation mode selected When ITU-R601 is selected, the video input mode is automatically determined by the number of lines per field. 3) Operation mode select NTSC CCIR601 MTSC Square Pixel NTSC 4Fsc PAL CCIR601 PAL Square Pixel 4) Decimeter circuit pass/bypass select Decimeter circuit is passed. * Decimeter circuit is bypassed. 5) Y/C separation mode select Adaptive comb filter is used. * Unadaptive comb filter is used. Trap filter is used. The adaptive comb filter detects the correlation up to 3 lines between continuous lines. The Y/ C is separated by the comb filter according to the way of correlation if theses lines are correlated. The Y/C is separated by the trap filter if these lines are not correlated (only 2 lines in the case of PAL). In the unadaptive comb filter, the Y/C is always separated by removing the luminance component based on the average of preceding and following lines (when there is the correlation between 3 lines). 13.5 MHz* 12.27 MHz 14.31818 MHz 13.5 MHz 14.75 MHz 11/42 Semiconductor MSM7661B If the comb filter is not used, the Y/C is separated by the trap filter. The Y/C separation circuit is bypassed by S video signal input. In adittion, the functions of this block work only when lines are valid as image information. The processing of CVBS signals is not made during V-blanking. 2. Luminance Block The luminance block removes synchronous signals from the signals containing luminance components after Y/C separation. The signals are corrected and output as luminance signals. The luminance signal output level gain control functions include three selectable modes such as AGC (Auto Gain Control), MGC (manual Gain Control) + No Clamp, and MGC + Pedestal Clamp. In the AGC mode, the luminance level amplification is determined by comparing the depth of SYNC with the reference value. The default is 40IRE which can be changed by the register. The input is a sync chip clamp type. In the MGC + No Clamp mode, the luminance signal output level is not affected by the input, and the amplification and black level are controlled by setting the register. In the MGC + Pedestal Clamp mode, the signal output level is clamped to the pedestal level of the input. The signal amplification and black level are controllable from the clamped point by setting the register. This block can select the follwing operation modes. 1) Use of prefilter and sharp filter Used* Not used These filters are used for enhancing the edges of luminance component signals. 2) Selection of aperture bandpass filter coefficient Middle range* High range 3) Coring range select off* 4LBS 5LBS 7LBS 4) Aperture weighting factor select 0* 0.25 0.75 1.5 The profile of these signals can be corrected by coring and aperture correction. 5) Use of pixel position correction circuit Used* Not used 6) AGC loop filter time constant select Slow Factor value 1/1024n 12/42 Semiconductor Medium Fast Fixed 1/64n* 1/n 0 MSM7661B 7) Parameter for AGC reference level fine adjustment 8) Parameter for sync separation level fine adjustment The black level is controlled. When the default is specified, the depestal position is output as a black level (=16). 9) Pedestral clamp selecton Pedestral clamp is not used.* Pedestral clamp is used. (AGC will not operate) 3. Chrominance Block This is a chroma signal processing block. The following modes can be selected. 1) Use of color bandpass filter Used* Not used 2) ACC loop filter time constant select Slow Medium Fast Fixed 3) ACC reference level fine adjustment 4) Parameter for burst level fine adjustment The threshold level for valid chroma amplitude is selected based on a color burst ratio. 0.5 0.25* 0.125 off 5) Color killer mode select Auto color killer mode* Forcible color killer 6) Parameter for color subcarrier phase fine adjustment In this block, chroma signals pass through the chroma bandpass filter to cut an unnecessary band. To maintain a constant chroma level, UV demodulation is performed on these signals via the ACC correction circuit. (This filter can be bypassed.) If the demodulation result does not reach a specified level, color killer signals are generated to fix the ACC gain. This functions as an auto color killer control circuit. The UV demodulation result is output as chrominance signals via a low pass filter. Factor value 1/1024n 1/64n* 1/n 0 13/42 Semiconductor 4. Synchronization Block MSM7661B This is a synchronizing signal processing block. Chip output synchronizing signals and synchronizing signals for internal use are generated by this block. Various signals are output in this block and the following operation modes can be selected. 1) SYNC threshold level adjustment 2-1) Fine adjustment of HSY signal (start side) 2-2) Fine adjustment of HSY signal (stop side) 3) HSY signal enable select High Level Active* These signal are used to sync chip and clamp timing to the A/D converter 4) Fine adjustment of HSYNC_L signal 5-1) Fine adjustment of HVALID signal (start side) 5-2) Fine adjustment of HVALID signal (stop side) 6-1) Fine adjustment of VVALID signal (start side) 6-2) Fine adjustment of VVALID signal (stop side) The data signals are transmitted or received at the rising edge of the HVALID signal. 7) TV, VTR mode select TV mode VTR mode* The TV mode outputs a fixed pixel number per one line and absorbs a jitter that does not appear on the TV receiver normally. The VTR mode outputs the results of decoding in accordance with the HSYNC signal regardless of whether a jitter exists or not. 14/42 Semiconductor 5. Epilogue Block MSM7661B The Epilogue Block outputs UV signals from the chrominance block and Y signals from the luminance block in the format based on the signal obtained by setting of the control register. In this block, the following modes can be selected. 1) Display of blue back when synchronization fails. OFF ON* 2) Output modes 2.1) ITUR 601 mode Output signal Y/CbCr format select YCbCr 4 : 2 : 2* YCbCr 4:1:1 The chrominance signal (U, V component) outputs Cb and Cr data to the C pin in an output format described later. 2.2) YCbCr 8-bit multiplex output mode This mode does not include SAV and EAV. 3) Selection of 8-bit chroma signal output format Offset binary* 2's Complement 4) Output pin enable select High impedance Output enable* 5) Multiplex signal detect level adjustment The levels to detect multiplexed signals sent during the vertical blanking period are configured to be variable. The binary values after input signals are A-to-D converted are employed as the levels to detect multiplexed signals, and the levels are set in eight steps with respect to the SYNC tip level. Detect level OMR [5:3] 80 to 136 video in 6) Various modes detection NTSC/PAL detect mode* Multiplex signal detect mode HSYNC synchronization detect mode 7) Output signal phase control 15/42 Semiconductor I2C Control Block MSM7661B 6. This is the serial interface block based on the I2C standard of Phillips Corporation. This block functions only as a Slave-Receiver. The external control can set the internal registers (MRA, MRB, HSYT, etc.). 7. Test Control Block This block is used to test this LSI. Normally it is not used. 16/42 Semiconductor MSM7661B Register Description Registers controlled by I2C bus are shown below. A register setting value with an "*" indicates the default. Enter "0" to the undefined register when setting registers. Mode Register A (MRA) MRA[6] Synchronization mode MRA[5] Chroma format MRA[4] Override MRA[3] Video Input mode MRA[2:0] Video Input mode Mode Register B (MRB) MRB[6] Color killer mode *1: MRB[5] MRB[4] Pixel Sampling Ratio Blue Back *0: 0: *1: OFF (Video signal is demodulated and output regardless of synchronization detection .) AUTO (Blue Back is output when synchronization is not detected.) 17/42 Semiconductor MRB[3] Sync enable, clamping pulse 0: *1: Data-pass control *0: 1: HSY outputs "HIGH" level. HSY outputs active. MSM7661B MRB[2] DECIMETER is used at 2X sampling. No DECIMETER is used. (Note) This register becomes valid at doube-speed clock input(27 MHz). MRB[1:0] Y/C separation mode *00: Adaptive comb filter (Operation mode is selected monitoring the correlation of 3 lines.) Nonadaptive comb filter (Operation mode is always fixed.) Comb filter is not used. (Trap filter is used.) Undefined 01: 10: 11: (Note) Adaptive comb filter: Non-adaptive comb filter: 2/3-line comb filter at NTSC Comb filter/trap filter at PAL 3-line comb filter at NTSC 2-line cosine comb filter at PAL Horizontal Sync Trimmer (HSYT) Sync Threshold level adjust (STHR) (Note) The sync signal detect threshold level is adjusted. Horizontal Sync Delay (HSDL) Horizontal Valid Trimmer (HVALT) 18/42 Semiconductor Vertical Valid Trimmer (VVALT) MSM7661B Luminance Control (LUMC) (Note) The limit range is from 16 to 235 at limiter ON. LUMC[6] Use of Pre-filter 0: *1: *00: 01: 10: 11: *00: 01: 10: 11: Prefilter is not used. Prefilter is used. middle range LUMC[5:4] Aperture bandpass select high range coring off +/-4LSB +/-5LSB +/-7LSB LUMC[3:2] Coring range select LUMC[1:0] Aperture filter weighting factor *00: 01: 10: 11: 0 0.25 0.75 1.5 AGC/Pedestral Loop filter control (AGCLF) slow medium fast fixed to 0x1F: +31 AGCLF[5:0] 0x20: -32 19/42 Semiconductor Sync separation level (SSEPL) MSM7661B SSEPL[6:0] Sync separation level 0x40: -64 Chrominance Control (CHRC) (Note) The limit range is from16 to 224 at limiter ON. CHRC[2] CHRC[1:0] Chroma bandpass filter Color kill threshold factor 0: 00: *01: 10: 11: OFF *1: ON 0.5 color burst level 0.25 color burst level 0.125 color burst level 0 (Color killer off) ACC Loop filter control (ACCLF) slow medium fast fixed to 0x0F: +15 ACCLF[4:0] 0x10: -16 Hue control (HUE) 20/42 Semiconductor Optional Mode Register (OMR) MSM7661B 136 Active Hi-Z NTSC/PAL SOUT (Multiplex signal detect) HDET (H-Sync detect) Undefined OMR[2] Hi-Z on Sleep for Out-pin OMR[1:0] Signal Indicate mode Output phase control for data Y (OPCY) OPCY[1:0] Output phase control for data Y Output phase control for data C (OPCC) 21/42 Semiconductor MSM7661B FUNCTIONAL DESCRIPTION Input Signal Level Input signal is 8 bits in a straight binary format. The recommended input range is shown below. 255 reserved 246 200 Iuminance chrominance +DC NTSC:60 (PAL:63) sync 4 0 input black level 13 input sync-tip level CVBS[7:0] input range 22/42 Semiconductor Output format The YCbCr 4:2:2 format and 4:1:1 format are shown below. The output format can be changed by register settings. OUTPUT Y7(MSB) Y6 Y5 Y4 Y3 Y2 Y1 Y0(LSB) C7(MSB) C6 C5 C4 C3 C2 C1 C0(LSB) Y point C point PIXEL BYTE SEQUENCE Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 0 0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 2 2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 3 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 4 4 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cr0 5 OUTPUT Y7(MSB) Y6 Y5 Y4 Y3 Y2 Y1 Y0(LSB) C7(MSB) C6 C5 C4 C3 C2 C1 C0(LSB) Y point C point Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cr7 Cr6 0 0 0 0 0 MSM7661B PIXEL BYTE SEQUENCE Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb5 Cb4 Cr5 Cr4 0 0 0 0 1 0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb3 Cb2 Cr3 Cr2 0 0 0 0 2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb1 Cb0 Cr1 Cr0 0 0 0 0 3 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb7 Cb6 Cr7 Cr6 0 0 0 0 4 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb5 Cb4 Cr5 Cr4 0 0 0 0 5 4 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb3 Cb2 Cr3 Cr2 0 0 0 0 6 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cb1 Cb0 Cr1 Cr0 0 0 0 0 7 YCbCr 4:2:2 format YCbCr 4:1:1 format YCbCr 8-bit multiplex output mode format 1T CLKX2 HVALID Y (7:0) INVALID Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Y717 Cb718 Y718 Cr718 Y719 INVALID 23/42 Semiconductor MSM7661B TIMING DESCRIPTION A/D Converter Support Signal The timing wave form of HSY/HCL signals, which measure the sync chip and clamp timing for the A/D converter, is as follows. CVBS COLOR BURST HSY A/D Converter Support Signal Line control signal The line control signal timing is as follows. CLK CLKO HVALID Y[7:0] C[7:0] Y0 Cb0 Y1 Cr0 Y2 Cb2 Y3 Cr2 Y(n) Cb(n) Y(n+1) Cr(n) Line Control Timing 24/42 Semiconductor Total Number of Pixels MSM7661B The total number of pixels vary depending on the mode and frequency used, as shown below (default values when typical signals are input). Video and Sampling Mode Video Mode Sampling Rate 13.5 MHz NTSC 12.27 MHz (SQ) 14.32 MHz (4FSC) -- 13.5 MHz PAL 14.75 MHz (SQ) -- -- Total Pixels 858 780 910 864 944 Active Pixels 720 640 768 720 768 Front-porch 16 28 8 14 34 HBLK Pixels Hsync.Back-porch 122 112 134 130 142 Total 138 140 142 144 176 25/42 Semiconductor Vertical Synchronizing Signal The vertical synchronizing signal timing is as follows. 524 CVBS HVALID HSYNC_L VSYNC_L SYNC (CSYNC_L) VVALID ODD 262 CVBS HVALID HSYNC_L VSYNC_L SYNC (CSYNC_L) VVALID ODD 263 264 265 266 267 268 269 270 271 283 284 525 1 2 3 4 5 6 7 8 9 21 MSM7661B 22 285 Vertical Synchronizing Signal (NTSC 60 Hz) 26/42 Semiconductor MSM7661B 621 CVBS HVALID HSYNC_L SYNC (CSYNC_L) VSYNC_L VVALID ODD 309 CVBS HVALID HSYNC_L SYNC (CSYNC_L) VSYNC_L VVALID ODD 622 623 624 625 1 2 3 4 5 6 23 24 310 311 312 313 314 315 316 317 318 336 337 338 Vertical Synchronizing Signal (PAL 50 Hz) 27/42 Semiconductor Horizontal Synchronizing Signal The horizontal synchronizing signal timing is as follows. MSM7661B Y[7:0] HVALID HSYNC_L 60 pixels Horizontal Timing 28/42 Semiconductor MSM7661B I2C BUS FORMAT The I2C-bus interface input format is shown below. S Slave Address Symbol S Slave Address A Subaddress Data n P Start condition Slave address 1000001X, 8th bit is write signal. Acknowledge. Generated by slave Subaddress byte Data to write to address designated by subaddress. Stop condition A Subaddress A Data 0 A ...... Data n A P Description As mentioned above, the write operation can be executed from subaddress to subaddress continuously. When the write operation is executed at subaddresses discontinuously, the Acknowledge and Stop condition formats are input repeatedly after Data 0. If one of the following matters occurs, the decoder will not return "A" (Acknowledge). * The slave address does not match. * A non-existent subaddress is specified. * The write attribute of a register does not match "X" (read/write control bit). The input timing is shown below. SDA SCL MSB S Start Condition 1 2 7 8 9 ACK 1 tC_SCL 2 3-8 9 ACK P Stop Condition Data Line Stable: Data Valid Change of Data Allowed I2C-bus Basic Input/Output Timing 29/42 Semiconductor MSM7661B OPERATION MODE SETTING The video mode includes ; 1. Internal terminal mode to be directly set by a dedicated terminal 2. Register setting mode to be specified by setting the internal registers These modes can be changed by the mode register MRA [4]. The reset state (default) is the external terminal mode. The following registers can be set in the external terminal mode. MRA[3] input signal mode *0: 1: *000: 001: 010: 100: 101: Composite video input S-video input NTSC ITU-R601 NTSC Square Pixel MTSC 4Fsc PAL ITU-R601 PAL Square Pixel 13.5 MHz 12.27 MHz 14.31818 MHz 13.5 MHz 14.75 MHz MRA[2 : 0] input mode OPERATION CLOCK SETTING The operation clock settings at ITU-R601 are shown below. Input clock 27.0 MHz 27.0 MHz 13.5 MHz Input data 27.0 MHz 13.5 MHz 13.5 MHz CLKSEL Pin "L" "L" "H" Register (MRB2) "0" (decimation filter used) "1" (Unused) "1" (Unused) Clock for A/D converter CLKX2O (27 MHz) CLKXO (13.5 MHz) CLKX2O or CLKXO (13.5 MHz) When the double speed clock is used, data can be input at a double speed or at an ordinary speed by setting the internal register (MRB2) and the clock for the A/D converter. The internal processing after decimation filter is performed at an ordinary speed. 30/42 Semiconductor MSM7661B INTERNAL REGISTERS Register List Register Function Mode Register A (MRA) Mode Register B (MRB) Horizontal Sync Trimmer (HSYT) Sync Threshold level adjust (STHR) Horizontal Sync Delay (HSDL) Horizontal Valid Trimmer (HVALID) Vertical Valid Trimmer (VVALID) Luminance Control (LUMC) AGC/Pedestal Loop Filter Control (AGCLF) Subaddress 0 1 2 3 4 5 6 7 8 9 A B C D E F Data byte D7 MRA7 MRB7 HSYT7 STHR7 HSDL7 D6 MRA6 MRB6 HSYT6 STHR6 HSDL6 D5 MRA5 MRB5 HSYT5 STHR5 HSDL5 D4 MRA4 MRB4 HSYT4 STHR4 HSDL4 D3 MRA3 MRB3 HSYT3 STHR3 HSDL3 D2 MRA2 MRB2 HSYT2 STHR2 HSDL2 D1 MRA1 MRB1 HSYT1 STHR1 HSDL1 D0 MRA0 MRB0 HSYT0 STHR0 HSDL0 HVALID7 HVALID6 HVALID5 HVALID4 HVALID3 HVALID2 HVALID1 HVALID0 VVALID7 VVALID6 VVALID5 VVALID4 VVALID3 VVALID2 VVALID1 VVALID0 LUMC7 LUMC6 LUMC5 LUMC4 LUMC3 LUMC2 LUMC1 LUMC0 AGCLF7 AGCLF6 AGCLF5 AGCLF4 AGCLF3 AGCLF2 AGCLF1 AGCLF0 SSEPL7 SSEPL6 SSEPL5 SSEPL4 SSEPL3 SSEPL2 SSEPL1 SSEPL0 CHRC7 HUE7 OMR7 OPCY7 OPCC7 CHRC6 HUE6 OMR6 OPCY6 OPCC6 CHRC5 HUE5 OMR5 OPCY5 OPCC5 CHRC4 HUE4 OMR4 OPCY4 OPCC4 CHRC3 HUE3 OMR3 OPCY3 OPCC3 CHRC2 HUE2 OMR2 OPCY2 OPCC2 CHRC1 HUE1 OMR1 OPCY1 OPCC1 CHRC0 HUE0 OMR0 OPCY0 OPCC0 ACCLF7 ACCLF6 ACCLF5 ACCLF4 ACCLF3 ACCLF2 ACCLF1 ACCLF0 Sync separation level (SSEPL) Chrominance Control (CHRC) ACC Loop Filter Control (ACCLF) Hue Control (HUE) Optional Mode Register (OMR) Output Phase Control for Data Y (OPCY) Output Phase Control for Data C (OPCC) 31/42 Semiconductor Relationship between Register Setting Value and Adjusted Value Horizontal Sync Trimmer Position adjustment of sync chip clamp timing signal HSYT [7:4] :Adjusting the starting position D E F 0 0 1 2 3 4 5 6 7 8 9 MSM7661B Register Setting Value (Ox) C A B Adjusted Value (Pixel) -32 -24 -16 -8 +8 +16 +24 +32 +40 +48 +56 +64 +72 +80 +88 HSYT [3:0] :Adjusting the end position D E F 0 0 1 2 3 4 5 6 7 8 9 A B +8 +16 +24 +32 +40 +48 +56 +64 +72 +80 +88 Register Setting Value (Ox) C Adjusted Value (Pixel) -32 -24 -16 -8 Horizontal Sync Delay Adjustment of the starting position of horizontal sync signal HSDL [7:0] MSB[7 : 4] 8 0 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F 9 A B C D E F 0 0 +4 +8 +12 +16 +20 +24 +28 +32 1 2 3 4 5 6 7 -512 -448 -384 -320 -256 -192 -128 -64 -508 -444 -380 -316 -252 -188 -124 -60 -504 -440 -376 -312 -248 -184 -120 -56 -500 -436 -372 -308 -244 -180 -116 -52 -496 -432 -368 -304 -240 -176 -112 -48 -492 -428 -364 -300 -236 -172 -108 -44 -488 -424 -360 -296 -232 -168 -104 -40 -484 -420 -356 -292 -228 -164 -100 -36 -480 -416 -352 -288 -224 -160 -96 -476 -412 -348 -284 -220 -156 -92 -472 -408 -344 -280 -216 -152 -88 -468 -404 -340 -276 -212 -148 -84 -464 -400 -336 -272 -208 -144 -80 -460 -396 -332 -268 -204 -140 -76 -456 -392 -328 -264 -200 -136 -72 -452 -388 -324 -260 -196 -132 -68 -32 -28 -24 -20 -16 -12 -8 -4 +64 +128 +192 +256 +320 +384 +448 +68 +132 +196 +260 +324 +388 +452 +72 +136 +200 +264 +328 +392 +456 +76 +140 +204 +268 +332 +396 +460 +80 +144 +208 +272 +336 +400 +464 +84 +148 +212 +276 +340 +404 +468 +88 +152 +216 +280 +344 +408 +472 +92 +156 +220 +284 +348 +412 +476 +96 +160 +224 +288 +352 +416 +480 +36 +100 +164 +228 +292 +356 +420 +484 +40 +104 +168 +232 +296 +360 +424 +488 +44 +108 +172 +236 +300 +364 +428 +492 +48 +112 +176 +240 +304 +368 +432 +496 +52 +116 +180 +244 +308 +372 +436 +500 +56 +120 +184 +248 +312 +376 +440 +504 +60 +124 +188 +252 +316 +380 +444 +508 32/42 Semiconductor Horizontal Valid Trimmer Position adjustment of horizontal valid pixel timing signal HVALT [7:4] Register Setting Value (Ox) MSM7661B :Adjusting the starting position 8 9 -7 A -6 B -5 C -4 D -3 E -2 F -1 0 0 1 +1 2 +2 3 +3 4 +4 5 +5 6 +6 7 +7 Adjusted Value (Pixel) -8 HVALT [3:0] Register Setting Value (Ox) :Adjusting the end position 8 9 -7 A -6 B -5 C -4 D -3 E -2 F -1 0 0 1 +1 2 +2 3 +3 4 +4 5 +5 6 +6 7 +7 Adjusted Value (Pixel) -8 Vertical Valid Trimmer Position adjustment of vertical valid line timing signal VVALT [7:4] Register Setting Value (Ox) :Adjusting the starting position 8 -8 9 -7 A -6 B -5 C -4 D -3 E -2 F -1 0 0 1 +1 2 +2 3 +3 4 +4 5 +5 6 +6 7 +7 Adjusted Value (Line) VVALT [3:0] Register Setting Value (Ox) :Adjusting the end position 8 -8 9 -7 A -6 B -5 C -4 D -3 E -2 F -1 0 0 1 +1 2 +2 3 +3 4 +4 5 +5 6 +6 7 +7 Adjusted Value (Line) AGC Loop filter control AGCLF [5:0] Register Setting Value (Ox) :Adjusting sync level MSB [5 : 4] 3 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 1 +16 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31 2 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 0 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F 33/42 Semiconductor Sync separation level SSEPL [6:0] Register Setting Value (Ox) MSM7661B :Adjusting the blanking level MSB [6 : 4] 4 5 -48 -47 -46 -45 -44 -43 -42 -41 -40 -39 -38 -37 -36 -35 -34 -33 6 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 7 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 1 +16 +17 +18 +19 +20 +21 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31 2 +32 +33 +34 +35 +36 +37 +38 +39 +40 +41 +42 +43 +44 +45 +46 +47 3 +48 +49 +50 +51 +52 +53 +54 +55 +56 +57 +58 +59 +60 +61 +62 +63 0 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F -64 -63 -62 -61 -60 -59 -58 -57 -56 -55 -54 -53 -52 -51 -50 -49 ACC Loop filter control ACCLF [4:0] Register Setting Value (Ox) :Adjusting the color burst level MSB [4] 1 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 0 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F 34/42 Semiconductor Hue control Adjustment of color subcarrier phase HUE [7:0] Register Setting Value (Ox) MSM7661B MSB [7 : 4] 8 9 A B C -90.0 -88.6 -87.2 -85.8 -84.4 -83.0 -81.6 -80.2 -78.8 -77.3 -75.9 -74.5 -73.1 -71.7 -70.3 -68.9 D -67.5 -66.1 -64.7 -63.3 -61.9 -60.5 -59.1 -57.7 -56.3 -54.8 -53.4 -52.0 -50.6 -49.2 -47.8 -46.4 E -45.0 -43.6 -42.2 -40.8 -39.4 -38.0 -36.6 -35.2 -33.8 -32.3 -30.9 -29.5 -28.1 -26.7 -25.3 -23.9 F -22.5 -21.1 -19.7 -18.3 -16.9 -15.5 -14.1 -12.7 -11.3 -9.8 -8.4 -7.0 -5.6 -4.2 -2.8 -1.4 0 +0.0 +1.4 +2.8 +4.2 +5.6 +7.0 +8.4 +9.8 +11.3 +12.7 +14.1 +15.5 +16.9 +18.3 +19.7 +21.1 1 +22.5 +23.9 +25.3 +26.7 +28.1 +29.5 +30.9 +32.3 +33.8 +35.2 +36.6 +38.0 +39.4 +40.8 +42.2 +43.6 2 +45.0 +46.4 +47.8 +49.2 +50.6 +52.0 +53.4 +54.8 +56.3 +57.7 +59.1 +60.5 +61.9 +63.3 +64.7 +66.1 3 +67.5 +68.9 +70.3 +71.7 +73.1 +74.5 +75.9 +77.3 +78.8 +80.2 +81.6 +83.0 +84.4 +85.8 +87.2 +88.6 4 +90.0 +91.4 +92.8 +94.2 +95.6 +97.0 +98.4 +99.8 5 6 7 0 1 2 3 4 5 6 LSB [3 : 0] 7 8 9 A B C D E F -180.0 -157.5 -135.0 -112.5 -178.6 -156.1 -133.6 -111.1 -177.2 -154.7 -132.2 -109.7 -175.8 -153.3 -130.8 -108.3 -174.4 -151.9 -129.4 -106.9 -173.0 -150.5 -128.0 -105.5 -171.6 -149.1 -126.6 -104.1 -170.2 -147.7 -125.2 -102.7 -168.8 -146.3 -123.8 -101.3 -167.3 -144.8 -122.3 -165.9 -143.4 -120.9 -164.5 -142.0 -119.5 -163.1 -140.6 -118.1 -161.7. -139.2 -116.7 -160.3 -137.8 -115.3 -158.9 -136.4 -113.9 -99.8 -98.4 -97.0 -95.6 -94.2 -92.8 -91.4 +112.5 +135.0 +157.5 +113.9 +136.4 +158.9 +115.3 +137.8 +160.3 +116.7 +139.2 +161.7 +118.1 +140.6 +163.1 +119.5 +142.0 +164.5 +120.9 +143.4 +165.9 +122.3 +144.8 +167.3 +101.3 +123.8 +146.3 +168.8 +102.7 +125.2 +147.7 +170.2 +104.1 +126.6 +149.1 +171.6 +105.5 +128.0 +150.5 +173.0 +106.9 +129.4 +151.9 +174.4 +108.3 +130.8 +153.3 +175.8 +109.7 +132.2 +154.7 +177.2 +111.1 +133.6 +156.1 +178.6 35/42 Semiconductor MSM7661B Filter Characteristics Band Pass Filter (NTSC ITU-R601) 0 -20 Level [dB] -40 -60 -80 -100 0 1 2 3 4 5 6 Frequency [MHz] Band Pass Filter (PAL ITU-R601) 0 -20 Level [dB] -40 -60 -80 -100 0 1 2 3 4 5 6 Frequency [MHz] 36/42 Semiconductor MSM7661B Trap Filter (NTSC ITU-R601) 0 -20 Level [dB] -40 -60 -80 -100 0 1 2 3 4 5 6 Frequency [MHz] Trap Filter (PAL ITU-R601) 0 -20 Level [dB] -40 -60 -80 -100 0 1 2 3 4 5 6 Frequency [MHz] 37/42 Semiconductor MSM7661B Pre Filter 0 -20 Level [dB] -40 -60 -80 -100 0 1 2 3 4 5 6 Frequency [MHz] Sharp Filter 0 -20 Level [dB] -40 -60 -80 -100 0 1 2 3 4 5 6 Frequency [MHz] 38/42 Semiconductor MSM7661B Decimation Filter 0 -20 Level [dB] -40 -60 -80 -100 0 2 4 6 8 10 12 Frequency [MHz] * The characteristics of the various filters shown above are based on design data. 39/42 Semiconductor BASIC APPLICATION CIRCUIT EXAMPLE Application 1 Mode setting Video signal: NTSC-composite CLKX2: 27 MHz 3.3 V MSM7661B I2C Controller HSY SDA RESET_L TEST2 (SLEEP) SCL VDD 8 LPF1 Input circuit A/D C 8 CVBS0 CVBS7 CD0 CD7 C0...C7 Y0...Y7 Video in 8 8 Frame memory or image LSI MSM7661B VSYNC_L HSYNC_L SYSSEL CLKSEL PLLSEL MODE0 MODE1 MODE2 MODE3 CLKXO2 SYNC VC0_CP CLKX2 HVALID VVALID ODD CLKXO OSC GND LLLL Dip SW A/D C: CXD1179Q (SONY) LPF1: 628LJN-1471 (TOKO) 3.3 V 40/42 Semiconductor Application 2 Mode setting Video signal: NTSC-composite CLKX2: 13.5 MHz 3.3 V MSM7661B I2C Controller TEST2 (SLEEP) HSY SDA RESET_L SCL VDD 8 LPF1 Input circuit A/D C 8 CVBS0 CVBS7 CD0 CD7 C0...C7 Y0...Y7 Video in 8 8 Frame memory or image LSI MSM7661B VSYNC_L HSYNC_L SYSSEL CLKSEL PLLSEL MODE0 MODE1 MODE2 MODE3 CLKXO2 SYNC VC0_CP CLKX2 HVALID VVALID ODD CLKXO OSC GND LLLL Dip SW A/D C: upc659 (NEC) LPF1: 628LJN-1471 (TOKO) 3.3 V 41/42 Semiconductor MSM7661B PACKAGE OUTLINES AND DIMENSIONS (Unit : mm) 64-Pin Plastic QFP 42/42 |
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