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| MITSUMI Wide Discriminator MM1327 Wide Discriminator Monolithic IC MM1327 Outline This IC identifies the letter box portion of wide broadcast, etc. video signals. The luminance and chroma signals are used so that the rate of identification on dark screens is increased. Output is the total of 6bit ADC data and character signal, etc. white peak signal discriminator bit, for 7bit data output. In addition, an EDTV2 simple discrimination function is built-in. Features 1. Signal level discrimination using composite luminance and chroma signal 2. Discrimination of video signal within horizontal scanning interval can be done every scan due to integrated output 3. Built-in white peak detection circuit for subtitles 4. Built-in EDTV2 simple discrimination function 5. 22H discrimination output (COMB-THROUGH) circuit built-in 6. Built-in window limiter circuit 7. Data output is 7bit serial output format : 6bit ADC + peak detection 8. Operates on +5V single power supply Package SDIP-30 Applications Wide TV MITSUMI Wide Discriminator MM1327 Block Diagram Pin Assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I Q Y AGND MAX VCOM ZR INT IN INT OUT S/H DA DGND HD VD GP 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 ADCLK NRZCLK DATA EDTV2 VDO COMB-TH LIMIT-SW COMB-SW NTSC/PAL IR DELAY SEPA-LEVEL LIMIT-LEVEL GC VCC 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SDIP-30 MITSUMI Wide Discriminator MM1327 Pin Description Pin no. 1 2 3 Pin name I Q Y Function Video signal input pin Internal equivalent circuit diagram 4 12 5 AGND DGND MAX Composite output of input video signal maximum value 6 VCOM Internal reference voltage output Connect 1F between this pin and GND. 7 ZR Connection pin for MAX output clamp capacitor 8 INT IN Integrated circuit input pin Integrated reset done at GP timing. MITSUMI Wide Discriminator MM1327 Pin no. 9 10 Pin name INT OUT S/H Function Integrated output pin and sample and hold pins S/H of integration results at HD timing Internal equivalent circuit diagram 11 DA DAC output for consecutive comparison ADC ------------------------------------- 13 15 HD IN GP IN Timing pulse input pins GP operates even on SCP input (5VP-P). 14 VD IN Timing pulse input pin VD operates even on SCP input (5VP-P). 16 ADCLK Clock input pin for consecutive ADC MITSUMI Wide Discriminator MM1327 Pin no. 17 25 26 Pin name NRZCLK IR DELAY Function Clock input pins for NRZ discrimination Input CLK is integrated by resistor connected between Pin 25 and GND and internal 20pF, and delay is set by Pin 26 voltage. Data output pins Internal equivalent circuit diagram 18 19 20 21 22 23 24 DATA EDTV2 VDO COMB-TH LIMIT-SW COMB-SW NTSC/PAL Switching pins 27 SEPA LEVEL NRZ discrimination luminance signal SEPA level adjustment pin 28 LIMIT LEVEL MAX composite output limit level adjustment pin Limit area: NTSC : 42~241H PAL : 46~291H 29 GAIN I, Q gain adjustment pin 30 VCC MITSUMI Wide Discriminator MM1327 Absolute Maximum Ratings Item Operating temperature Storage temperature Power supply voltage Input voltage Allowable loss Symbol TOPR TSTG VCC max. VIN max. Pd Ratings -20~+75 -40~+125 7.0 < VIN < VCC GND = = 800 Units C C V V mW Recommended Operating Conditions Item Operating temperature Operating voltage Symbol TOPR VOPR Ratings -20~+75 4.5~5.5 Units C V MITSUMI Wide Discriminator MM1327 Electrical Characteristics Item Consumption current MAX amp (Except where noted otherwise, Ta=25C, VCC=5.0V) Symbol ICC VYIN VIIN VQIN V max. Y V max.Y V max.I V max.Q GY I Q I Q G max.I G max.Q G min.I G min.Q GIQ VYSL VYSH VCSL VCSH INRZCL INRZCH VIR VNL VTHD VTVD VTGP IHDL IHDH IVDL IVDH IGPL IGPH VTCOSL VTCOSH VOCOMB VOVDO ICOMB=1mA IVDO=1mA 2.1 0.4 0.4 INL=1mA HD VD or SCP GP or SCP VHD=0.4V VHD=4.5V VVD=0.4V VVD=4.5V VGP=0.4V VGP=4.5V 2.30 0.63 3.69 2.50 0.83 3.89 VNRZCLK=0.4V VNRZCLK=4.5V 2.2 2.4 1.5 27 Measurement conditions Min. Typ. Max. Units 20 30 2.4 2.4 2.4 2.4 V VP-P 0.0 0.5 dB dB dB dB V mA Y Clamping level I Q MAX output pin voltage *1 *1 *1 *1 2.0 2.0 2.0 2.0 1.0 0.6 0.6 2.2 2.2 2.2 2.2 Maximum input level I Q Y input voltage gain Maximum gain VCA *2 VGC=1.2V VGC=1.2V VGC=3.6V VGC=3.6V -0.5 Minimum gain I, Q gain difference *3 *3 *3 *3 +11.5 +12.0 +12.5 +11.5 +12.0 +12.5 -0.5 -0.5 -0.5 0.0 0.0 0.0 5 30 0.4 1.8 1 1 2.6 0.4 2.70 1.03 4.09 1 1 1 1 1 1 0.7 0.7 0.5 0.5 0.5 7 GIQ=GI-GQ EDTV II discrimination NRZ detection level L H L H L H IRE S A V V NRZ detection readout timing NRZCLK pin input current IR pin voltage EDTV II output voltage L Trigger signal HDIN Sync signal separation level VDIN GPIN HD pin input current L H L H L H L H V A A A V V V VD pin input current GP pin input current COMB-SW switching voltage COMB-TH output voltage L VDO output voltage L MITSUMI Wide Discriminator MM1327 Note 1 : 1 Clamp level and MAX output pin voltage Measure voltage on each pin when GPIN and HDIN are connected to VCC. * * * Note 2 : 2 Y input voltage gain Input a sweep signal to Y input, input a clamp pulse synchronized to HSYNC to GPIN pin, and measure voltage gain at MAX pin for 100kHz. Note 3 : 3 I, Q max/min gain Input a square wave signal as shown below and a GPIN signal to I input (or Q input) and GPIN pin, and measure voltage gain at MAX pin. 0.3V I or Q signal 0V 5V GP pin 0V 2S 63.5S Note 4 : 4 MAX amp limit level Measure limit level at MAX pin when LIMIT-SW pin is high. However, the limit range is as follows for the NTSC/PAL pin. * * * Note 5 : 5 Offset voltage for reset Connect GPIN pin to VCC and measure potential difference between INT IN pin and INT OUT pin. Note 6 : 6 Integrated limit voltage Input a 100% white signal to Y input and a clamp pulse synchronized to HSYNC to GPIN pin. Measure INT OUT pin voltage at integration end at this time. Y input 100IRE INT OUT output VINTL MITSUMI Wide Discriminator MM1327 Timing Chart 1 1st field 259H 260H 261H 262H 1H 2H 2nd field 3H 4H 5H 6H 7H 8H 9H 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 20H 21H 22H 23H 24H 25H Composite SCP -5V -2.8V -1.7V -0V -5V GP -0V -5V VB -0V -5V RB -0V VDO COMB-TB 1st field 260H 261H 262H 263H 1H 2H 2nd field 3H 4H 5H 6H 7H 8H 9H 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 20H 21H 22H 23H 24H 25H Composite SCP -5V -2.8V -1.7V -0V -5V GP -0V -5V VB -0V -5V RB -0V VDO COMB-TB MITSUMI Wide Discriminator MM1327 Timing Chart 2 100IRE 50IRE Y input 0IRE 50IRE +0.15V I (Q) input -0.15 MAX output tegrated output 3FM S/H 00M GP HD ADCLX DATA PEAK 05 00 1. The largest of Y, I and Q video input signals is output on MAX output pin. 2. MAX output date is integrated during horizontal scanning. 3. Integration results are sampled and held at HD pulse timing. 4. Consecutive comparison ADC outputs data as serial data. (Serial data is 1H delayed from video signal input.) 5. Output data configuration is as shown in the table below. Data configuration Y input Peak of more than 50IRE No peak of more than 50IRE PEAK 1 0 Video White scanning Black scanning DATA 00 3F Timing Chart 3 1 0 1 1 0 YIN (22H) NRZCLK Integrated NRZCLK (Internal circuit) DELAY NRZ discrimination timing 1. When YIN input signal matches "10110" at NRZ discrimination timing, it is identified as an EDTV2 signal. EDTV2 pin is high for EDTV2 identification. MITSUMI Wide Discriminator MM1327 Measuring Circuit |
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