 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM DESCRIPTION The MH32V7245BST is 33554432-word x 72-bit dynamic ram stacked structural module. This consist of thirty-six industry standard 16M x 4 dynamic RAMs in TSOP and two industry standard input buffer in TSSOP. The stacked structure of TSOP on a card edge dual in-line package provides any application where high densities and large of quantities memory are required. This is a socket-type memory module ,suitable for easy interchange or addition of module. PIN CONFIGURATION 85pin 94pin 1pin 10pin 11pin FEATURES Type name MH32V7245BST-5 MH32V7245BST-6 /RAS /CAS Address /OE access access access access time time time time Cycle time Power dissipation (typ.W) (max.ns) (max.ns) (max.ns) (max.ns) (min.ns) 95pin 50 60 18 20 30 35 18 20 84 110 7.03 5.87 Utilizes industry standard 16M x 4 RAMs TSOP and industry standard input buffer in TSSOP 168-pin (84-pin dual dual in-line package) stacked structure Single 3.3V(+/- 0.3V) supply operation Low stand-by power dissipation . . . . . . . . . . 64.9mW(Max) Low operation power dissipation MH32V7245BST -5 . . . . . . . . . . . . . . . . . . 8.44W(Max) MH32V7245BST -6 . . . . . . . . . . . . . . . . . . 7.79W(Max) All input are directly LVTTL compatible All output are three-state and directry LVTTL compatible Includes(0.22 uF x 38) decoupling capacitors 4096 refresh cycle every 64ms (A0 - A11) Hyper-page mpde,Read-modify-write,/CAS before /RAS refresh, Hidden refresh capabilities JEDEC standard pin configration & Buffered PD pin Buffered input except /RAS and DQ Gold plating contact pads 124pin BACK SIDE 125pin 40pin FRONT SIDE 41pin APPLICATION Main memory unit for computers , Microcomputer memory 168pin 84pin PD&ID TABLE -5 -6 -7 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 = NC , 0 = drive to VOL PD pin . . . buffered. When /PDE is low, PD information can be read ID pin . . . non-buffered 1 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM PIN CONFIGURATION Pin No. Pin Name Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 DQ16 DQ17 Vss Reserved Reserved Vcc /WE0 /CAS0 Reserved /RAS0 /OE0 Vss A0 A2 A4 A6 A8 A10 Reserved Vcc RFU RFU Pin No. Pin Name Vss /OE2 /RAS2 /CAS4 Reserved /WE2 Vcc Reserved Reserved DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 Vcc DQ24 RFU RFU RFU RFU DQ25 DQ26 DQ27 Vss DQ28 DQ29 DQ30 DQ31 Vcc DQ32 DQ33 DQ34 DQ35 Vss PD1 PD3 PD5 PD7 ID0 Vcc Pin No. Pin Name Vss DQ36 DQ37 DQ38 DQ39 Vcc DQ40 DQ41 DQ42 DQ43 DQ44 Vss DQ45 DQ46 DQ47 DQ48 DQ49 Vcc DQ50 DQ51 DQ52 DQ53 Vss Reserved Reserved Vcc RFU /CAS1 Reserved /RAS1 RFU Vss A1 A3 A5 A7 A9 A11 Reserved Vcc RFU B0 Pin No. Pin Name Vss RFU /RAS3 /CAS5 Reserved /PDE Vcc Reserved Reserved DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 RFU RFU RFU RFU DQ61 DQ62 DQ63 Vss DQ64 DQ65 DQ66 DQ67 Vcc DQ68 DQ69 DQ70 DQ71 Vss PD2 PD4 PD6 PD8 ID1 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Reserved: Reserved use RFU: Reserved for future use 2 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM BLOCK DIAGRAM /RAS0 /CAS0 /RAS1 /CAS1 /WE0 /OE0 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 /RAS2 /CAS4 /RAS3 /CAS5 /WE2 /OE2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 D0 D18 D9 D27 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 D1 D19 D10 D28 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 D2 D20 D11 D29 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 D3 D21 D12 D30 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 D4 D22 D13 D31 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 D5 D23 D14 D32 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 D6 D24 D15 D33 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 D7 D25 D16 D34 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 /OE /W /CAS /RAS DQ1 ~DQ4 D8 D26 D17 D35 D : M5M465405BTP A0 B0 A1 - A11 D0 - D8 D18 - D26 D9 - D17 D27 - D35 D0 - D35 Vcc Vss Stacked Unit PIN NAME /RAS /CAS /WE /OE A, B DQ Vcc Vss FUNCTION ROW ADDRESS STROBE INPUT COLUMN ADDRESS STROBE INPUT WRITE CONTROL INPUT OUTPUT ENABLE INPUT ADDRESS INPUT DATA I/O POWER SUPPLY GROUND C1. - C20 .. D0 - D35 & INPUT BUFFER 3 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM FUNCTION The MH32V7245BST provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., hyper page mode, /CAS before /RAS refresh, and delayed-write. The input conditions for each are shown in Table 1. Table 1 Input conditions for each mode Inputs Operation /RAS Read Write (Early write) Write (Delayed write) Read-modify-write Hidden refresh /CAS before /RAS refresh Standby ACT ACT ACT ACT ACT ACT NAC /CAS ACT ACT ACT ACT ACT ACT DNC /W NAC ACT ACT ACT DNC NAC DNC /OE ACT DNC DNC ACT ACT DNC DNC Row address APD APD APD APD DNC DNC DNC Column address APD APD APD APD DNC DNC DNC Input/Output Refresh Input OPN VLD VLD VLD OPN DNC DNC Output VLD OPN IVD VLD VLD OPN OPN NO NO NO NO YES YES NO Hyper page mode identical Remark Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open 4 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc IO Pd Topr Tstg Parameter Supply voltage Output current Power dissipation Operating temperature Storage temperature Conditions With respect to Vss Ta=25C Ratings -0.5~4.6 50 20 0~70 -40~100 Unit V mA W C C RECOMMENDED OPERATING CONDITIONS Symbol Vcc Vss VIH VIL Parameter Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage Min 3.0 0 2.0 -0.3 (Ta=0~70C, unless otherwise noted) (Note 1) Limits Nom 3.3 0 Max 3.6 0 Vcc+0.3 Unit V V V V 0.8 Note 1 : All voltage values are with respect to Vss ELECTRICAL CHARACTERISTICS Symbol VOH VOL IOZ II I I (RAS) ICC1 (AV) Parameter High-level output voltage Low-level output voltage Off-state output current Input current (except /RAS) Input current (/RAS) Average supply current from Vcc operating (Ta=0~70C, Vcc=3.3V 0.3V, Vss=0V, unless otherwise noted) (Note 2) Test conditions IOH=-2.0mA IOL=2.0mA Q floating 0V 0V 0V VOUT Vcc VIN VIN Vcc+0.3V, Other input pins=0V Vcc+0.3V, Other input pins=0V Min 2.4 0 -20 -10 -90 Limits Typ Max Vcc 0.4 20 10 90 2378 2198 56 38 1838 1658 2378 2198 Unit V V A A A mA VII VII -5 -6 (Note 3,4,5) /RAS, /CAS cycling tRC=tWC=min. output open /RAS=/CAS =VIH, output open /RAS=/CAS Vcc -0.2, output open /RAS=VIL,/CAS cycling tPC=min. output open IIV /CAS before /RAS refresh cycling tRC=min. output open VII VII VII VII ICC2 Supply current from Vcc , stand-by Average supply current from Vcc Hyper-Page-Mode mA mA -5 (Note 3,4,5) ICC4(AV) -6 -5 -6 ICC6(AV) Average supply current from Vcc /CAS before /RAS refresh mode mA (Note 3,5) Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc3 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Under condition of colmun address being changed once or less while /RAS=VIL and /CAS=VIH CAPACITANCE Symbol (Ta = 0~70C, Vcc = 3.3V 0.3V, Vss = 0V, unless otherwise noted) Parameter Test conditions VI=Vss f=1MHZ Vi=25mVrms Min Limits Typ CI (/RAS) Input capacitance, /RAS input CI Input capacitance, except /RAS input C(DQ) Input/Output capacitance,DATA Max 80 15 25 Unit pF pF pF 5 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM SWITCHING CHARACTERISTICS Symbol tCAC tRAC tAA tCPA tOEA tOHC tOHR tCLZ tOEZ tWEZ tOFF tREZ (Ta=0~70C, Vcc=3.3V 0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15) Limits Parameter Min Access time from /CAS (Note 7,8) Access time from /RAS (Note 7,9) Columu address access time (Note 7,10) Access time from /CAS precharge (Note 7,11) Access time from /OE (Note 7) Output hold time from /CAS Output hold time from /RAS (Note 13) Output low impedance time from /CAS low (Note 7) Output disable time after /OE high (Note 12) Output disable time after /WE high (Note 12) Output disable time after /CAS high (Note 12,13) Output disable time after /RAS high (Note 12,13) -5 Max 18 50 30 33 18 Min -6 Max 20 60 35 38 20 10 5 10 18 18 18 13 20 20 20 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns 10 5 10 Note 6: An initial pause of 500 us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing a /CAS before /RAS refresh). Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods (greater than 64 ms) of /RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 1TTL loads and 50pF,VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=-2mA). The reference levels for measuring of output signals are 2.0V(VOH) and 0.8V(VOL). 8: Assumes that tRCD tRCD(max), tASC tASC(max) and tCP tCP(max). 9: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD tRAD(max) and tASC tASC(max). 11: Assumes that tCP tCP(max) and tASC tASC(max). 12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT I +/- 10 uAI) and is not reference to VOH(min) or VOL(max). 13: Output is disable after both /RAS and /CAS go to high. IIV IIV IIV IIV IIV VII VII VII VII VII TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Hyper-Page Mode Cycles) (Ta=0~70C, Vcc=3.3V 0.3V, Vss=0V, unless otherwise noted ,see notes 14,15) Limits Symbol tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tRDD tCDD tODD tT Parameter Min Refresh cycle time /RAS high pulse width Delay time, /RAS low to /CAS low Delay time, /CAS high to /RAS low Delay time, /RAS high to /CAS low /CAS high pulse width Column address delay time from /RAS low Row address setup time before /RAS low Column address setup time before /CAS low Row address hold time after /RAS low Column address hold time after /CAS low Delay time, data to /CAS low Delay time, data to /OE low Delay time, /RAS high to data Delay time, /CAS high to data Delay time, /OE high to data Transition time 30 9 10 0 8 5 5 0 3 8 0 0 13 18 18 1 -5 Max 64 32 Min 40 9 10 0 10 7 5 0 5 10 0 0 15 20 20 1 -6 Max 64 40 Unit ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note16) (Note17) (Note18) 20 10 25 13 (Note19) (Note19) (Note20) (Note20) (Note20) (Note21) 50 50 Note 14: The timing requirements are assumed tT =2ns. 15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. . 17: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA. 18: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC. 19: Either tDZC or tDZO must be satisfied. 20: Either tRDD or tCDD or tODD must be satisfied. 21: tT is measured between VIH(min) and VIL(max). IIV IIV IIV VII 6 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Read and Refresh Cycles Limits Symbol tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tCAL tORH tOCH Parameter Min Read cycle time /RAS iow pulse width /CAS iow pulse width /CAS hold time after /RAS iow /RAS hold time after /CAS iow Read Setup time after /CAS high Read hold time after /CAS iow Read hold time after /RAS iow Column address to /RAS hold time Column address to /CAS hold time /RAS hold time after /OE iow /CAS hold time after /OE iow 84 50 8 30 18 0 0 0 30 13 18 13 -5 Max 10000 10000 Min 104 60 10 43 20 0 0 0 35 18 20 15 -6 Max 10000 10000 ns ns ns ns ns ns ns ns ns ns ns ns Unit (Note 22) (Note 22) Note 22: Either tRCH or tRRH must be satisfied for a read cycle. Write Cycle (Early Write and Delayed Write) Limits Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH Parameter Write cycle time /RAS iow pulse width /CAS iow pulse width /CAS hold time after /RAS iow /RAS hold time after /CAS low Write setup time before /CAS low Write hold time after /CAS low /CAS hold time after /W low /RAS hold time after W low Write pulse width Data setup time before /CAS low or W low Data hold time after /CAS low or W low Min 84 50 8 30 18 0 8 8 13 8 -5 13 -5 Max 10000 10000 Min 104 60 10 35 20 0 10 10 15 10 -5 15 -6 Max 10000 10000 ns ns ns ns ns ns ns ns ns ns ns ns Unit (Note 24) Read-Write and Read-Modify-Write Cycles Limits Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tOEH Parameter Read write/read modify write cycle time /RAS low pulse width /CAS low pulse width /CAS hold time after /RAS low /RAS hold time after /CAS low Read setup time before /CAS low Delay time, /CAS low to /W low Delay time, /RAS low to /W low Delay time, address to /W low OE hold time after W low IIV IIV -5 (Note23) -6 Max Min 133 89 44 77 49 0 32 72 47 15 IIV IIV Unit Max ns ns ns ns ns ns ns ns ns ns (Note24) (Note24) (Note24) Min 109 75 38 65 43 0 28 60 40 13 IIV 10000 10000 10000 10000 Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD (min), tAWD tAWD(min) and tCPWD tCPWD(min) (for Fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until /CAS or /OE goes back to VIH) is indeteminate. 7 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle, Read Write Mix Cycle,Hi-Z control by /OE or /W) (Note 25) Limits Symbol tHPC tHPRWC tDOH tRAS tCP tCPRH tCPWD tCHOL tOEPE tWPE tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD Parameter Hyper page mode read/write cycle time Hyper page mode read write/read modify write cycle time -5 Min 20 55 10 65 8 33 43 7 7 7 28 40 43 13 25 28 Max Min 25 66 10 77 10 38 50 7 7 7 32 47 50 15 30 33 -6 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Output hold time from /CAS low /RAS low pulse width for read write cycle /CAS high pulse width /RAS hold time after /CAS precharge Delay time,/CAS precharge to /W low (Note26) (Note27) (Note24) 100000 15 100000 16 Hold time to maintain the data Hi-Z until /CAS access /OE Pulse width(Hi-Z control) /W Pulse width(Hi-Z control) Delay time,/CAS low to /W low after read Delay time, Address to /W low after read Delay time,/CAS precharge to /W low after read Delay time,/CAS low to /OE high after read Delay time,Address to /OE high after read Delay time, /CAS precharge to /OE high after read Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle. 26: tRAS(min) is specified as two cycles of /CAS input are performed. 27: tCP(max) is specified as a reference point only. /CAS before /RAS Refresh Cycle (Note 28) Limits Symbol tCSR tCHR tRSR tRHR Parameter /CAS setup time before /RAS low /CAS hold time after /RAS low Read setup time before /RAS low Read hold time after /RAS low Min 10 5 15 5 -5 Max Min 10 5 15 5 -6 Max ns ns ns ns Unit Note 28: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh mode. 8 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Timing Diagrams Read Cycle (Note 29) tRC tRAS VIH /RAS VIL tCSH tCRP VIH / CAS VIL tRAD tASR A0,B0~A11 VIH VIL tRAH tASC tCAH ROW ADDRESS tRP tRCD tRSH tCAS tCRP tRAL tCAL tASR ROW ADDRESS COLUMN ADDRESS tRCS VIH /W VIL tDZC VIH Hi-Z VIL tCAC tAA tCLZ DQ (OUTPUTS) tRRH tRCH tCDD tRDD DQ (INPUTS) tREZ tOHR DATA VALID tWEZ tOFF tOHC VOH Hi-Z VOL tRAC tDZO VIH tOEA tOCH tOEZ tODD Hi-Z /OE VIL tORH Note 29 Indicates the don't care input. VIH(min) VIN VIH(max) or VIL(min) Indicates the invalid output. VII VII VII VII VIN VIL(max) 9 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Early Write Cycle tWC tRAS VIH VIL tCSH tCRP VIH /CAS VIL tASR VIH VIL tASR tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRP /RAS tRCD tRSH tCAS tCRP A0,B0~A11 ROW ADDRESS tWCS /W VIH VIL tDS VIH tWCH tDH DQ (INPUTS) DATA VALID VIL DQ (OUTPUTS) VOH Hi-Z VOL VIH /OE VIL 10 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Delayed Write Cycle tWC tRAS VIH VIL tCSH tCRP VIH / CAS VIL tASR tRAH tASC tCAH tASR COLUMN ADDRESS ROW ADDRESS tRP /RAS tCRP tRSH tCAS tRCD VIH A0,B0~A11 VIL ROW ADDRESS tCWL tRCS /W VIH VIL tWCH tDZC DQ (INPUTS) tRWL tWP tDS Hi-Z tCLZ tDH DATA VALID VIH VIL DQ (OUTPUTS) VOH Hi-Z VOL tDZO tOEZ tODD tOEH Hi-Z /OE VIH VIL 11 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Read-Write, Read-Modify-Write Cycle tRWC tRAS VIH /RAS VIL tCSH tCRP VIH / CAS VIL tASR tRAH tRAD tASC tCAH tASR tRCD tRSH tCAS tCRP tRP VIH A0,B0~A11 VIL ROW ADDRESS COLUMN ADDRESS ROW ADDRESS tRCS VIH VIL tAWD tCWD tRWD tCWL tRWL tWP /W tDS tDZC DQ (INPUTS) tDH VIH VIL tCAC tAA tCLZ Hi-Z DATA VALID DQ (OUTPUTS) VOH Hi-Z VOL tRAC tDZO VIH VIL tOEA DATA VALID Hi-Z tODD tOEH tOEZ /OE 12 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Read Cycle tRAS VIH /RAS VIL tCSH tCRP VIH / CAS VIL tRAD tASR VIH A0,B0~A11 VIL tRAH tASC tCAH tASC tCAH tASC tCPRH tCAH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS tRP tASR ROW ADDRESS COLUMN-1 COLUMN-2 COLUMN-3 ROW ADDRESS tRCS tCAL VIH /W VIL tDZC tCAL tCAL tRRH tRCH tWEZ tRDD tCDD tCAC tAA tCLZ Hi-Z tCAC tAA tDOH DATA VALID-1 DATA VALID-2 DQ (INPUTS) VIH VIL tCAC tAA tDOH tREZ tOHR tOFF tOHC DATA VALID-3 DQ (OUTPUTS) VOH Hi-Z VOL tRAC tDZO VIL tCPA tOEA tOCH tCPA tOEZ /OE VIH tODD 13 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Early Write Cycle tRAS VIH /RAS VIL tCSH tCRP VIH / CAS VIL tCAL tASR VIH A0,B0~A11 VIL tRAH tASC tCAH tASC tCAH tASC tCAL tCAH tRCD tCAS tCP tHPC tCAS tRSH tCP tCAS tRP tCRP tASR ROW ADDRESS COLUMN-1 COLUMN-2 COLUMN-3 ROW ADDRESS tWCS VIH /W VIL tDS tWCH tWCS tWCH tWCS tWCH tDH tDS tDH tDS tDH DQ (INPUTS) VIH VIL DATA VALID-1 DATA VALID-2 DATA VALID-3 DQ (OUTPUTS) VOH Hi-Z VOL VIL /OE VIH 14 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Read-Write,Read-Modify-Write Cycle tRAS VIH /RAS VIL tCSH tCRP VIH / CAS VIL tASR tRAD tRAH tASC tCAH tASC tCAH tCWL tRCD tCAS tCP tHPRWC tCAS tRP tRWL tCRP tASR ROW ADDRESS VIH A0,B0~A11 VIL ROW ADDRESS COLUMN-1 COLUMN-2 tAWD tRCS VIH /W VIL tRWD tDZC DQ (INPUTS) tAWD tCWL tWP tRCS tCWD tWP tCWD tCPWD tDS tDH DATA VALID-1 tDZC tDS Hi-Z tCAC tAA tCLZ tDH DATA VALID-2 VIH VIL Hi-Z tCAC tAA tCLZ DQ (OUTPUTS) VOH Hi-Z VOL tRAC tDZO VIH tOEA DATA VALID-1 Hi-Z tODD tOEZ tCPA tDZO tOEA DATA VALID-2 Hi-Z tODD tOEH tOEZ /OE VIL 15 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Mix Cycle (1) tRAS VIH VIL tCSH tCRP tRCD VIH / CAS VIL tRAD tASR VIH A0,B0~A11 VIL tRAH tASC tCAH tASC tCAH tASC tCAH tCAS tCP tHPC tCAS tCP tHPRWC tCAS tCWL tRWL tRP /RAS tCRP tASR ROW ADDRESS COLUMN-1 COLUMN-2 COLUMN-3 ROW ADDRESS tRCS tCAL /W VIH VIL tDZC tWCS tWCH tCAL tCPWD tAWD tCWD tWP tDS tDH tDZ C tDS tDH DQ (INPUTS) VIH VIL tCAC tAA tCLZ DATA VALID-2 DATA VALID-3 tAA tCAC tWEZ DATA VALID-1 tCLZ DATA VALID-3 DQ (OUTPUTS) VOH Hi-Z VOL tRAC tDZO VIL tCPA tOEA tOEZ tOCH tDZO tOEA tOEZ tOEH /OE VIH tODD tODD 16 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Mix Cycle (2) VIH /RAS VIL tHPC VIH / CAS VIL tCP tASC A0,B0~A11 VIH COLUMN-1 COLUMN-2 COLUMN-3 tCAS tCAH tASC tCAS tCAH tASC tCAH VIL tCAL tRCH tWCS VIH /W VIL tHAWD tHPWD DQ (INPUTS) tCAL tWCH tHCWD tDH tDS DATA VALID-2 tDZC VIH Hi-Z VIL tCAC tAA tCPA tWEZ tCAC tAA tCPA tCLZ Hi-Z DQ (OUTPUTS) VOH VOL tHCOD tHAOD VIL tHPOD DATA VALID-1 Hi-Z tOEA DATA VALID-3 tOEZ tODD tDZC /OE VIH 17 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Read Cycle ( Hi-Z control by OE ) tRAS VIH /RAS VIL tCSH tCRP VIH / CAS VIL tRAD tASR VIH VIL tRAH tASC tCAH tASC tCAH tASC tCPRH tCAH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS tRP tCRP tASR A0,B0~A11 ROW ADDRESS COLUMN-1 COLUMN-2 COLUMN-3 ROW ADDRESS tRAL tRCS tRRH tRCH VIH /W VIL tWEZ tDZC tRDD tCDD tCAC tAA tCLZ DQ (OUTPUTS) DQ (INPUTS) VIH VIL tCAC tAA tDOH DATA VALID-1 DATA VALID-1 DATA VALID-2 Hi-Z tCAC tAA tCLZ Hi-Z tCPA tREZ tOHR tOFF tOHC DATA VALID-3 VOH Hi-Z VOL tRAC tDZO VIL tOEA tOEZ tOCH tOEA tCPA tCHOL tOEZ tOEZ /OE VIH tOEPE tOEPE tODD 18 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hyper Page Mode Read Cycle ( Hi-Z control by W ) tRAS VIH VIL tCSH tCRP VIH / CAS VIL tRAD tASR VIH A0,B0~A11 VIL tRAH tASC tCAH tASC tCAH tASC tCPRH tCAH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS tRP /RAS tCRP tASR ROW ADDRESS COLUMN-1 COLUMN-2 COLUMN-3 ROW ADDRESS tRAL tRCS VIH VIL tDZC tWPE tRCH tRCS /W tRRH tRCH tRDD tCDD tCAC tAA DQ (INPUTS) VIH VIL tCAC tAA tCLZ tCAC tAA tDOH DATA VALID-1 Hi-Z tWEZ DATA VALID-2 tCLZ Hi-Z tREZ tOHR tOFF tOHC DATA VALID-3 DQ (OUTPUTS) VOH Hi-Z VOL tRAC tDZO VIL tOEA tOCH tCPA tCPA tOEZ /OE VIH tODD 19 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM /CAS before /RAS Refresh Cycle tRC /RAS VIH VIL tRPC tCSR VIH VIL tCPN tCHR tRP tRAS tRAS tRC tRP / CAS tRPC tCSR tCHR tRPC tCRP tASR A0,B0~A11 VIH VIL tRRH /W VIH VIL tRCH tRCS ROW ADDRESS COLUMN ADDRESS DQ (INPUTS) VIH VIL tREZ tOHR tOFF tOHC Hi-Z DQ (OUTPUTS) VOH VOL tOEZ VIH /OE VIL 20 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Hidden Refresh Cycle (Read) (Note 31) tRC tRAS /RAS VIH VIL tCRP VIH / CAS VIL tRAD tASR A0,B0~A11 VIH VIL tRCS tRAL tRAH ROW ADDRESS tRC tRP tRAS tRP tRCD tRSH tCHR tASC tCAH COLUMN ADDRESS tASR ROW ADDRESS tRRH tRCH /W VIH VIL tDZC tCDD tRDD DQ (INPUTS) VIH Hi-Z VIL tCAC tAA tCLZ Hi-Z VOL tRAC tDZO VIH tOEA tORH tOEZ tODD DATA VALID tREZ tOHR tOFF tOHC Hi-Z DQ (OUTPUTS) VOH /OE VIL Note 31: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above. 21 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 Preliminary Spec. MITSUBISHI LSIs MH32V7245BST -5, -6 HYPER PAGE MODE 2415919104 - BIT ( 33554432 - WORD BY 72 - BIT ) DYNAMIC RAM Package outline 133.350.13 6.77Max 30.13 10.13 127.350.13 38.10.13 17.780.13 30.13 R20.13 5.1Min 1.270.1 23.4950.13 43.180.13 MIT - DS - 0218-0.0 MITSUBISHI ELECTRIC 13/JUL./1998 5.1Min |
Price & Availability of MH32V7245BST-6
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |