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E2G0135-18-11
Semiconductor MD51V64400
Semiconductor
This version: Mar. 1998 MD51V64400
16,777,216-Word 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
The MD51V64400 is a 16,777,216-word 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MD51V64400 achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MD51V64400 is available in a 32-pin plastic SOJ or 32-pin plastic TSOP.
FEATURES
* 16,777,216-word 4-bit configuration * Single 3.3 V power supply, 0.3 V tolerance * Input : LVTTL compatible, low input capacitance * Output : LVTTL compatible, 3-state * Refresh : RAS-only refresh : 8192 cycles/64 ms CAS before RAS refresh, hidden refresh : 4096 cycles/64 ms * Fast page mode, read modify write capability * CAS before RAS refresh, hidden refresh, RAS-only refresh capability * Package options: 32-pin 400 mil plastic SOJ (SOJ32-P-400-1.27) (Product : MD51V64400-xxJA) 32-pin 400 mil plastic TSOP (TSOPII32-P-400-1.27-K) (Product : MD51V64400-xxTA) xx indicates speed rank.
PRODUCT FAMILY
Family MD51V64400-50 MD51V64400-60 Access Time (Max.) tRAC tAA tCAC tOEA 50 ns 25 ns 13 ns 13 ns 60 ns 30 ns 15 ns 15 ns Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) 90 ns 110 ns 504 mW 432 mW 1.8 mW
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Semiconductor
PIN CONFIGURATION (TOP VIEW)

VCC 1 32 VSS VCC 1 32 VSS DQ1 2 31 DQ4 DQ1 2 DQ2 3 NC 4 NC 5 31 DQ4 30 DQ3 29 NC 28 NC DQ2 3 NC 4 NC 5 NC 6 NC 7 30 DQ3 29 NC 28 NC 27 NC 25 OE NC 6 NC 7 27 NC 25 OE 26 CAS 26 CAS WE 8 WE 8 RAS 9 24 A12R 23 A11R 22 A10 21 A9 20 A8 19 A7 RAS 9 24 A12R 23 A11R 22 A10 21 A9 20 A8 19 A7 A0 10 A1 11 A2 12 A3 13 A4 14 A0 10 A1 11 A2 12 A3 13 A4 14 A5 15 VCC 16
MD51V64400
A5 15 VCC 16
32-Pin Plastic SOJ
18 A6
17 VSS
18 A6
17 VSS
32-Pin Plastic TSOP (K Type)
Pin Name A0 - A10, A11R, A12R RAS CAS DQ1 - DQ4 OE WE VCC VSS NC
Function Address Input Row Address Strobe Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (3.3 V) Ground (0 V) No Connection
Note :
The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin.
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Semiconductor
MD51V64400
BLOCK DIAGRAM
WE RAS CAS
11
OE
I/O Controller Output Buffers
4
Timing Generator
4
DQ1 - DQ4
Column Address Buffers Internal Address Counter
11 11
Column Decoders
4
Input Buffers
4
A0 - A10
Refresh Control Clock
Sense Amplifiers
4
I/O Selector
4
A11R, A12R
2
Row Row Address 13 DecoBuffers ders
Word Drivers
Memory Cells
VCC
On Chip VBB Generator On Chip IVCC Generator
VSS
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Semiconductor
MD51V64400
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD* Topr Tstg Rating -0.5 to 4.6 50 1 0 to 70 -55 to 150 Unit V mA W C C
*: Ta = 25C Recommended Operating Conditions
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 3.0 0 2.0 -0.3 Typ. 3.3 0 -- -- Max. 3.6 0 VCC + 0.3 0.8 (Ta = 0C to 70C) Unit V V V V
Capacitance
(VCC = 3.3 V 0.3 V, Ta = 25C, f = 1 MHz) Parameter Input Capacitance (A0 - A10, A11R, A12R) Input Capacitance (RAS, CAS, WE, OE) Output Capacitance (DQ1 - DQ4) Symbol CIN1 CIN2 CI/O Typ. -- -- -- Max. 5 7 7 Unit pF pF pF
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Semiconductor DC Characteristics
Parameter Output High Voltage Output Low Voltage Input Leakage Current
Symbol
MD51V64400
(VCC = 3.3 V 0.3 V, Ta = 0C to 70C) Condition MD51V64400 -50 Min. VOH IOH = -2.0 mA VOL IOL = 2.0 mA 0 V VI VCC + 0.3 V; ILI All other pins not under test = 0 V DQ disable 0 V VO VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS VCC -0.2 V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable ICC6 RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. -- 80 -- 70 mA 1, 3 -- 140 -- 120 mA 1, 2 -- 5 -- 5 mA 1 -- 100 -- 90 mA 1, 2 -10 10 -10 10 mA 2.4 0 Max. VCC 0.4 MD51V64400 -60 Min. 2.4 0 Max. VCC 0.4 V V Unit Note
Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode)
ILO
-10
10
-10
10
mA
ICC1
-- -- --
100 1 0.5
-- -- --
90 1 0.5
mA 1, 2
mA
1
Notes : 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH.
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Semiconductor AC Characteristics (1/2)
MD51V64400
(VCC = 3.3 V 0.3 V, Ta = 0C to 70C) Note 1, 2, 3 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS CAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address to RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS
Symbol
MD51V64400 -50 Min. Max. -- -- -- -- 50 13 25 30 13 -- 13 13 50 64 -- 10,000
100,000
MD51V64400 -60 Min. 110 155 40 85 -- -- -- -- -- 0 0 0 3 -- 40 60 60 15 15 10 15 60 5 35 20 15 0 10 0 10 30 0 0 0 Max. -- -- -- -- 60 15 30 35 15 -- 15 15 50 64 -- 10,000
100,000
Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 8 5 6 4, 5, 6 4, 5 4, 6 4 4 4 7 7 3
tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tOEA tCLZ tOFF tOEZ tT tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH
90 131 35 76 -- -- -- -- -- 0 0 0 3 -- 30 50 50 13 13 7 13 50 5 30 17 12 0 7 0 7 25 0 0 0
-- -- -- 10,000 -- -- -- 37 25 -- -- -- -- -- -- -- --
-- -- -- 10,000 -- -- -- 45 30 -- -- -- -- -- -- -- --
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Semiconductor AC Characteristics (2/2)
MD51V64400
(VCC = 3.3 V 0.3 V, Ta = 0C to 70C) Note 1, 2, 3 Parameter Write Command Set-up Time Write Command Hold Time Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS)
Symbol
MD51V64400 -50 Min. Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 7 7 13 13 13 0 7 13 36 48 73 53 5 10 10 10 10
MD51V64400 -60 Min. 0 10 10 15 15 15 0 10 15 40 55 85 60 5 10 10 10 10 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unit Note ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 9 9 9 9 9
tWCS tWCH tWP tOEH tRWL tCWL tDS tDH tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR tWRP tWRH
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Semiconductor Notes:
MD51V64400
1. A start-up delay of 200 s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100 pF. The output timing reference levels are VOH = 2.0 V and VOL = 0.8 V. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.) , tRWD tRWD (Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle.
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E2G0114-17-41R Semiconductor MD51V64400
,,, , ,,,
TIMING WAVEFORM
Read Cycle
tRC tRAS tRP VIH - RAS VIL - tCRP tCRP tCSH tRCD CAS VIH - VIL - tRAD tRSH tCAS tRAL tASR tRAH tASC tCAH Address VIH - VIL - VIH - VIL - VIH - VIL - VOH - Row Column tRCS tRRH tRCH WE OE tAA tROH tOEA tRAC tCAC tOEZ tOFF DQ VOL - Open Valid Data-out tCLZ "H" or "L"
Write Cycle (Early Write)
tRC
tRAS
tRP
RAS
VIH - VIL - VIH - VIL -
tCRP
tCRP
tCSH
tRCD
tRSH
CAS
tRAD tRAH
tCAS
tASR
tASC
tCAH
tRAL
Address
VIH - VIL -
Row
Column
tWCS
tWCH tWP
tCWL
VIH - WE VIL - VIH - VIL - VIH -
tRWL
OE
tDS
tDH
DQ
VIL -
Valid Data-in
Open
"H" or "L"
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,,,
Semiconductor MD51V64400 Read Modify Write Cycle
tRWC tRAS tRP RAS VIH - VIL - tCSH tCRP tCRP tRCD tRSH VIH - CAS VIL - tCAS tASR tRAH tASC tCAH VIH - Address VIL - WE OE VIH - VIL - VIH - VIL - VI/OH- Row Column tRAD tRWD tCWD tAA tAWD tCWL tRWL tWP tRCS tOEA tOED tOEH tCAC tRAC tOEZ tDS tDH DQ VI/OL- tCLZ Valid Data-out Valid Data-in "H" or "L"
10/15
Semiconductor
Fast Page Mode Read Cycle
Fast Page Mode Write Cycle (Early Write)
, ,, , , ,,
MD51V64400
tRASP tRP VIH - RAS V - IL VIH - CAS VIL - VIH - VIL - VIH - VIL - tRHCP tCRP tRCD tPC tRSH tCRP tCP tCP tRAD tCAS tCAS tCAS tASR tRAH tASC tCSH tCAH tASC tCAH tASC tRAL tCAH Address Row Column Column Column tRCS tRCH tRCS tAA tRCH tRCS tAA tRCH WE tAA tRRH VIH - OE VIL - tOEA tCPA tCPA tOEA tOEA tCAC tRAC tOFF tOEZ tCAC tOFF tCAC tOFF tCLZ tOEZ tCLZ tOEZ VOH - DQ VOL - tCLZ
Valid Data-out Valid Data-out Valid Data-out
"H" or "L"
tRASP tPC
tRP
VIH - RAS V - IL VIH - CAS VIL - VIH - VIL -
tRHCP
tCRP
tRCD
tRSH
tCRP
tCAS
tCP
tCP
tCAS
tCAS
tASR
tRAH tASC tRAD
tCSH tCAH
tASC
tCAH
tASC
tCAH
tRAL
Address
Row
tWCS
WE
VIH - VIL -
Column tCWL tWCH tWP
Column tCWL tWCS tWCH tWP
Column tRWL tCWL tWCS tWCH tWP tDS tDH
tDS
tDH
tDS
tDH
VIH - DQ VIL -
Valid Data-in
Valid Data-in
Valid Data-in
Note: OE = "H" or "L"
"H" or "L"
11/15
Semiconductor
Fast Page Mode Read Modify Write Cycle
VIH - RAS VIL -
VIH - CAS VIL -
Address
VIH - VIL -
V WE IH - VIL -
VIH - OE V - IL VI/OH- VI/OL -
DQ
RAS-Only Refresh Cycle
RAS
VIH - VIL -
CAS
VIH - VIL -
Address
VIH - VIL -
DQ
VOH - VOL -
,,,, , , ,
tRASP tRP tCSH tPRWC tRCD tCAS tCP tCAS tCP tRSH tCAS tCRP tRAD tRAH tCAH tASC tASC tASR tASC tCAH tCAH tRAL Row Column tRWD tRCS Column Column tCWD tCWL tRCS tCPWD tCWD tAWD tCWL tRCS tCPWD tCWD tAWD tRWL tCWL tAWD tRAC tDS tWP tDH tDS tWP tDH tROH tDS tWP tDH tAA tCPA tAA tCPA tAA tOEA tOEA tOEA tOED tOED tOED tCAC tOEZ tCAC tOEZ
In
MD51V64400
tCAC
tOEZ
Out
In
Out
Out
In
tCLZ
tCLZ
tCLZ
"H" or "L"
tRC
tRAS
tRP
tCRP
tRPC
tASR
tRAH
Row
tOFF
Open
Note: WE, OE = "H" or "L"
"H" or "L"
12/15
Semiconductor CAS before RAS Refresh Cycle
tRC t RP RAS VIH - VIL - tRPC tCP CAS VIH - VIL - tCSR tCHR tRAS t RPC
MD51V64400
tRP
WE
DQ
Hidden Refresh Read Cycle
RAS
CAS
Address
VIH - WE V IL - VIH - OE V IL -
DQ
,, , ,,
tWRP tWRH tWRP VIH - VIL - t OFF VOH - VOL - Open Note: OE, Address = "H" or "L" "H" or "L"
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH - VIL - VIH - VIL -
tCRP
tRCD
tRSH
tCHR
tASR
tRAD tASC tRAH
tCAH
VIH - VIL -
Row
Column
tRCS
tRAL
tRRH
tAA
tROH
tOEA
tWRP
tWRH
tRAC
tCAC tCLZ
tOFF
tOEZ
VOH -
VOL -
Valid Data-out
"H" or "L"
13/15
,,, ,
Semiconductor MD51V64400 Hidden Refresh Write Cycle
tRC tRC tRAS tRP tRAS tRP RAS VIH - VIL - VIH - tCRP tRCD tRSH tCHR CAS VIL - tASR tRAD tASC tRAH tCAH t RAL Address VIH - VIL - Row Column tWCS tWCH VIH - WE V IL - VIH - OE V IL - tWP tWRP tWRH tDS tDH V- DQ IH VIL - Valid Data-in "H" or "L"
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Semiconductor
MD51V64400
PACKAGE DIMENSIONS
(Unit : mm)
SOJ32-P-400-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.42 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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