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19-2697; Rev 0; 12/02
Low-Jitter 155MHz/622MHz Clock Generator
General Description
The MAX3672 is a low-jitter 155MHz/622MHz reference clock generator IC designed for system clock distribution and frequency synchronization in OC-48 and OC-192 SONET/SDH and WDM transmission systems. The MAX3672 integrates a phase/frequency detector, an operational amplifier (op amp), prescaler dividers, and input/output buffers. Using an external VCO, the MAX3672 can be configured easily as a phase-lock loop with bandwidth programmable from 30Hz to 10kHz. The MAX3672 operates from a single +3.3V or +5.0V supply and dissipates 150mW (typ) at 3.3V. The operating temperature range is -40C to +85C.
Features
o Single +3.3V or +5.0V Supply o Power Dissipation: 150mW at +3.3V Supply o External VCO Center Frequencies (fVCO): 155MHz to 700MHz o Reference Clock Frequencies: fVCO, fVCO/2, fVCO/4, fVCO/8, fVCO/32 o Main Clock Output Frequency: fVCO o Optional Output Clock Frequencies: fVCO, fVCO/2, fVCO/4, fVCO/8 o Low Intrinsic Jitter: <0.4psRMS o Loss-of-Lock Indicator o PECL Clock Output Interface
MAX3672
Applications
OC-12 to OC-192 SONET/WDM Transport Systems Clock Jitter Clean-Up and Frequency Synchronization Frequency Conversion System Clock Distribution
Ordering Information
PART MAX3672E/D TEMP RANGE -40C to +85C PIN-PACKAGE Dice*
*Dice are designed to operate from -40 to +85C, but are tested and guaranteed at TA = +25 only.
Typical Application Circuit
+3.3V 142 155MHz REFCLK+ +3.3V 142 REFCLKVCOIN+ VCO KVCO = 25kHz/V 155MHz 100 VCOIN142 VCCD MOUT+ MOUT142
MAX3892 16:1 SERIALIZER
MAX3672
RSEL VSEL NSEL1 N.C. N.C.
332 VC 0.01F 4700pF 500k OPAMPOPAMP+ 4700pF REPRESENTS A CONTROLLED-IMPEDANCE TRANSMISSION LINE. 500k VFILTER 1000pF POLAR GND 3.3V SETUP FOR 10kHz LOOP BANDWIDTH GSEL NSEL2
________________________________________________________________ Maxim Integrated Products
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Low-Jitter 155MHz/622MHz Clock Generator MAX3672
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ......................................................-0.5V to +7.0V Voltage at C2+, C2-, THADJ, CTH, NSEL1, NSEL2, GSEL, LOL, RSEL, REFCLK-, REFCLK+, VSEL, VCOIN+, VCOIN-, VC, POLAR, PSEL1, PSEL2, COMP, OPAMP+, OPAMP- ..................................-0.5V to (VCC + 0.5V) Voltage at VFILTER .................................................-0.5V to +3.0V PECL Output Current (MOUT+, MOUT-, POUT+, POUT-).................................................56mA Operating Temperature Range ...........................-40C to +85C Storage Temperature Range. ............................-65C to +160C Die-Attach Process Temperature.....................................+400C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.3V 10% or VCC = +5.0V 10%, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Supply Current SYMBOL ICC (Note 2) CONDITIONS MIN TYP 50 MAX 72 UNITS mA
INPUT SPECIFICATIONS (REFCLK, VCOIN) Input High Voltage Input Low Voltage VIH VIL VCC 1.16 VCC 1.81 VCC 1.3 7.2 12.0 AC-coupled 300 VCC 1.025 VCC 1.085 VCC 1.81 VCC 1.83 2.4 11.5 21.0 17.5 32.5 1900 VCC 0.88 V -40C to 0C 0C to +85C Output Low Voltage VOL -40C to 0C TTL SPECIFICATIONS Output High Voltage Output Low Voltage VOH VOL Sourcing 20A Sinking 2mA VCC 0.4 V V VCC 0.88 VCC 1.62 VCC 1.556 V VCC 0.88 VCC 1.48 V V
Input Bias Voltage Common-Mode Input Resistance Differential Input Resistance Differential Input Voltage Swing PECL OUTPUT SPECIFICATIONS 0C to +85C Output High Voltage VOH
V k k mVP-P
2
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Low-Jitter 155MHz/622MHz Clock Generator
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.3V 10% or VCC = +5.0V 10%, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX VCC 0.3 VCC 0.5 3 90 High gain Low gain High gain Low gain 16.0 4.0 20 5 24.4 6.2 0.80 1.08 V UNITS
MAX3672
OPERATIONAL AMPLIFIER SPECIFICATIONS (Note 3) VCC = +3.3V 10% Op Amp Output Voltage Range VO VCC = +5.0V 10% Op Amp Input Offset Voltage Op Amp Open-Loop Gain Full-Scale PFD/CP Output Current PFD/CP Offset Current | VOS | AOL 0.5 0.3
mV dB
PHASE FREQUENCY DETECTOR (PFD)/CHARGE-PUMP (CP) SPECIFICATIONS (Note 4) | IPD | A % | IPD |
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.3V 10% or VCC = +5.0V 10%, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Note 5)
PARAMETER Clock Output Frequency Optional Clock Output Frequency Clock Output Rise/Fall Time Clock Output Duty Cycle NOISE SPECIFICATIONS Random Noise Voltage at LoopFilter Output Spurious Noise Voltage at LoopFilter Output Power-Supply Rejection at LoopFilter Output PSR VNOISE Freq > 1kHz (Note 7) (Note 8) (Note 9) 30 50 1.14 VRMS /Hz VRMS dB fVCO = 622MHz fVCO = 155MHz Measured from 20% to 80% (Note 6) 45 622/311/ 155/78 155/78/ 38/19 280 55 SYMBOL CONDITIONS MIN TYP MAX 700 UNITS MHz
CLOCK OUTPUT SPECIFICATIONS
MHz
ps %
REFERENCE CLOCK INPUT SPECIFICATIONS Reference Clock Frequency Reference Clock Duty Cycle 30 622/ 155/78/ 19 700 70 MHz %
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Low-Jitter 155MHz/622MHz Clock Generator MAX3672
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.3V 10% or VCC = +5.0V 10%, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Note 5)
PARAMETER PLL SPECIFICATIONS PLL Jitter Transfer Bandwidth Jitter Transfer Peaking OPAMP SPECIFICATION Unity-Gain Bandwidth VCO INPUT SPECIFICATIONS VCO Input Frequency VCO Input Slew Rate fVCO 0.5 622/155 700 MHz V/ns 7 MHz BW (Note 10) FJITTER BW (Note 11) 30 10,000 0.1 Hz dB SYMBOL CONDITIONS MIN TYP MAX UNITS
Specifications at -40C are guaranteed by design and characterization. Measured with PECL outputs unterminated. OPAMP specifications met with 10k load to ground or 5k load to VCC (POLAR = 0 and POLAR = VCC). PFD/CP currents are measured from pins OPAMP+ to OPAMP-. See Table 4 for gain settings. AC characteristics are guaranteed by design and characterization. Measured with 50% VCO input duty cycle. Random noise voltage at op amp output with 800k resistor connected between VC and OPAMP-, PFD/CP gain (KPD) = 5A/UI, and POLAR = 0. Measured with the PLL open loop and no REFCLK or VCO input. Note 8: Spurious noise voltage due to PFD/CP output pulses measured at op amp output with R1 = 800k, KPD = 5A/UI, and compare frequency 400 times greater than the higher-order pole frequency (see the Design Procedure section). Note 9: PSR measured with a 100mVP-P sine wave on VCC in a frequency range from 100Hz to 2MHz. External resistors R1 matched to within 1%, external capacitors C1 matched to within 10%. Measured closed loop with PLL bandwidth set to 200Hz. Note 10: The PLL 3dB bandwidth is adjusted from 30Hz to 10kHz by changing external components R1 and C1, by selecting the internal programmable divider ratio and phase-detector gain. Measured with VCO gain of 150ppm/V and C1 limited to 2.2F. Note 11: When input jitter frequency is above PLL transfer bandwidth (BW), the jitter transfer function rolls off at -20dB/decade. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7:
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Low-Jitter 155MHz/622MHz Clock Generator
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
MAX3672
SUPPLY CURRENT vs. TEMPERATURE
MAX3672 toc01
OUTPUT CLOCK EDGE SPEED vs. TEMPERATURE
270 260 250 240 230 220 210 200 190 180 170 160 150 140 -40
MAX3672 toc02
POWER-SUPPLY REJECTION vs. FREQUENCY
BW = 1kHz -10 SUPPLY REJECTION (dB) -20 -30 -40 -50 -60 LOOP FILTER OUTPUT
MAX3672 toc03
70
0
5.0V 50 3.3V
EDGE SPEED 20% TO 80% (ps)
60 SUPPLY CURRENT (mA)
40
155.52 667
30
20 -40 -20 0 20 40 60 80 TEMPERATURE (C)
-20
0
20
40
60
80
1k
10k
100k FREQUENCY (Hz)
1M
10M
TEMPERATURE (C)
667MHz CLOCK OUTPUT
MAX3672 toc04
155MHz CLOCK OUTPUT
MAX3672 toc05
200mV/div
200mV/div
500ps/div
2ns/div
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Low-Jitter 155MHz/622MHz Clock Generator MAX3672
Pad Description
PAD 1 2 3, 10, 16 4 5, 12, 18, 27, 33 6 7 8 9 11 13 14 15 17 19 20 21, 24 22 23 25 26 28 29 30 31 32 34 35 36 37 NAME C2+ C2VCCD THADJ GND CTH NSEL1 NSEL2 GSEL LOL RSEL REFCLK+ REFCLKVSEL POUTPOUT+ VCCO MOUTMOUT+ VCOINVCOIN+ VFILTER VC POLAR PSEL1 PSEL2 VCCA COMP OPAMPOPAMP+ FUNCTION Positive Filter Input. External capacitor connected between C2+ and C2- used for setting the higher order pole frequency (see the Setting the Higher-Order Poles section). Negative Filter Input. External capacitor connected between C2+ and C2- used for setting the higher order pole frequency (see the Setting the Higher-Order Poles section). Positive Digital Supply Voltage Threshold Adjust Input. Used to adjust the loss-of-lock threshold (see the LOL Setup section). Ground Threshold Capacitor Input. Connect capacitor connected between CTH and ground to control the loss-of-lock conditions (see the LOL Setup section). Divide Selector 1 Input. Three-level pin used to set the frequency divider ratio (N2) (Table 3). Divide Selector 2 Input. Three-level pin used to set the frequency divider ratio (N2) (Table 3). Gain Selector Input. Three-level pin used to set the phase-detector gain (Kpd) (Table 4). Loss of Lock. LOL signals a TTL low when the reference frequency differs from the VCO frequency. LOL signals a TTL high when the reference frequency equals the VCO frequency. Reference Clock Selector Input. Three-level pin used to set the pre-divider ratio (N3) for the input reference clock (Table 1). Positive Reference Clock Input, PECL Negative Reference Clock Input, PECL VCO Clock Selector Input. Three-level pin used to set the pre-divider ratio (N1) for the input VCO clock (Table 2). Negative Optional Clock Output, PECL Positive Optional Clock Output, PECL Positive Supply Voltage for PECL Outputs Negative Main Clock Output, PECL Positive Main Clock Output, PECL Negative VCO Clock Input, PECL Positive VCO Clock Input, PECL Optional Noise Filter. Connect an external capacitor to reduce PECL output noise (see the Typical Application Circuit). Control Voltage Output. The voltage output from the op amp that controls the VCO. Polarity Control of Op Amp Input. POLAR = GND for VCOs with positive-gain transfer. POLAR = VCC for VCOs with negative-gain transfer. Optional Clock Selector 1 Input. Sets the divider ratio for the optional clock output (Table 5). Optional Clock Selector 2 Input. Sets the divider ratio for the optional clock output (Table 5). Positive Analog Supply Voltage for the Charge Pump and Op Amp Compensation Control Input. Op Amp Compensation Reference Control Input. COMP = GND for VCOs whose control pin is VCC referenced. COMP = VCC for VCOs whose control pin is GND referenced. Negative Op Amp Input, POLAR = GND Positive Op Amp Input, POLAR = GND
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Low-Jitter 155MHz/622MHz Clock Generator
Functional Diagram
C1 R1
MAX3672
VCO KVCO
R3 C3 C1 R1
LOL
THADJ
CTH
VC
COMP
POLAR
OPAMP-
OPAMP+
LOL
OPAMP
REFCLK+ PECL REFCLKRSEL
DIV (N3) 1/2/8
DIV (N2)
PFD/CP Kpd
GSEL C2-
VSEL DIV (N1) 4/8/32 VCOIN+ VCOINPECL PECL MOUTDIVIDER CONTROL LOGIC DIV 1/2/4/8 POUT+ PECL POUTDIV (N2)
C2+ MOUT+
MAX3672
NSEL1
NSEL2
PSEL1
PSEL2
VFILTER
Detailed Description
The MAX3672 contains all the blocks needed to form a PLL except for the VCO, which must be supplied separately. The MAX3672 consists of input buffers for the reference clock and VCO, input and output clock-divider circuitry, LOL detection circuitry phase detector, gaincontrol logic, a phase-frequency detector and charge pump, an op amp, and PECL output buffers. This device is designed to clean up the noise on the reference clock input and provide a low-jitter system clock output. This device also supports frequency conversion.
that they can be AC-coupled (Figure 1 in the Interface Schematic section). A single-ended VCO or reference clock can also be applied.
Input and Output Clock-Divider Circuitry
The pre-dividers scale the input frequencies of the VCO and reference clock. Clock-divider ratios N1 and N3 must be chosen so that the output frequencies of the pre-dividers are equal. The maximum allowable predivider output frequency is 77.76MHz (Table 1). The main dividers (N2) facilitate tuning the loop bandwidth by setting the frequency divider ratio. The divider control logic can be programmed to divide from 1 to 256 in binary multiples (Table 3). The POUT output buffer is preceded by a clock divider that scales the main clock output by 1, 2, 4, or 8 to provide an optional clock.
Input Buffer for Reference Clock and VCO
The MAX3672 contains differential inputs for the reference clock and the VCO. These high impedance inputs can be DC-coupled and are internally biased with so
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Low-Jitter 155MHz/622MHz Clock Generator MAX3672
LOL Detection Circuitry
The MAX3672 incorporates a loss-of-lock (LOL) monitor that consists of an XOR gate, filter, and comparator with adjustable threshold (see the LOL Setup section). A loss-of-lock condition is signaled with a TTL low when the reference clock frequency differs from the VCO frequency. clock and VCO pre-dividers are equal. Table 1 shows the divider ratios and pre-divider output frequencies for various reference clock and VCO frequencies.
Setting the Loop Bandwidth
To eliminate jitter present on the reference clock, the proper selection of loop bandwidth is critical. If the total output jitter is dominated by the noise at the reference clock input, then lowering the loop bandwidth will reduce system jitter. The loop bandwidth (K) is a function of the VCO gain (KVCO), the gain of the phase detector (KPD), the loop filter resistor (R1), and the total feedback-divider ratio (N = N1 N2). The loop bandwidth of the MAX3672 can be approximated by: K= KPDR1K VCO 2N
Phase-Frequency Detector and Charge Pump
The phase-frequency detector incorporated into the MAX3672 produces pulses proportional to the phase difference between the reference clock and the VCO input. The charge pump converts this pulse train to a current signal that is fed to the op amp. The phase detector gain can be set to either 5A/UI or 20A/UI with the GSEL input (Table 4).
Op Amp
The op amp is used to form an active PLL loop filter capable of driving the VCO control voltage input. Using the POLAR input, the op amp input polarity can be selected to work with VCOs having positive or negative gaintransfer functions. The COMP pin selects the op amp internal compensation. Connect COMP to ground if the VCO control voltage is VCC referenced. Connect COMP to VCC if the VCO control voltage is ground referenced.
For stability, a zero must be added to the loop in the form of resistor R 1 in series with capacitor C 1 (see the Functional Diagram). The location of the zero can be approximated as: fZ = 1 2R1C1
Design Procedure
Setting Up the VCO and Reference Clock
The MAX3672 accepts a range of reference clock and VCO frequencies. The RSEL and VSEL inputs must be set so that the output frequencies of the reference
Because of the second-order nature of the PLL jitter transfer, peaking will occur and is proportional to fZ/K. For certain applications, it may be desirable to limit jitter peaking in the PLL passband region to less than 0.1dB. This can be achieved by setting fZ K/100. A more detailed analysis of the loop filter is located in application note HFDN-13.0 on www.maxim-ic.com.
Table 1. VCO and Reference Clock Setup
FVOC (MHz) 622.08 622.08 622.08 622.08 155.52 155.52 155.52 155.52 FREF (MHz) 622.08 155.52 77.76 19.44 622.08 155.52 77.76 19.44 VSEL INPUT OPEN OPEN OPEN GND -- OPEN VCC OPEN VCO DIVIDER N1 8 8 8 32 -- 8 4 8 RSEL INPUT GND OPEN VCC VCC -- GND OPEN VCC REFERENCECLOCK DIVIDER N3 8 2 1 1 -- 8 2 1 PRE-DIVIDER OUTPUT FREQUENCY (MHz) 77.76 77.76 77.76 19.44 -- 19.44 38.88 19.44
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Low-Jitter 155MHz/622MHz Clock Generator
Table 2. RSEL and VSEL Settings
INPUT PIN VSEL VCC OPEN GND VCO DIVIDER N1 4 8 32 INPUT PIN RSEL VCC OPEN GND REFERENCECLOCK DIVIDER N3 1 2 8
The HOP can be implemented either by providing a compensation capacitor C2, which produces a pole at: f HOP = 1 2(20k)(C2 )
MAX3672
or by adding a lowpass filter, consisting of R3 and C3, directly on the VCO tuning port, which produces a pole at: f HOP = 1 2R3 C3
Table 3. Divider Logic Setup
INPUT PIN NSEL1 INPUT PIN NSEL2 VCC OPEN GND VCC OPEN GND VCC OPEN GND VCC VCC VCC OPEN OPEN OPEN GND GND GND DIVIDER RATIO N2 1 2 4 8 16 32 64 128 256
Using R3 and C3 might be preferable for filtering more noise in the PLL, but it might still be necessary to provide filtering through C2 when using large values of R1 and N1 N2, to prevent clipping in the op amp.
Setting the Optional Output
The MAX3672 optional clock output can be set to binary subdivisions of the main clock frequency. The PSEL1 and PSEL2 pins control the binary divisions. Table 5 shows the pin configuration and possible divider ratios.
Applications Information
PECL Interfacing
The MAX3672 outputs (MOUT+, MOUT-, POUT+, POUT-) are designed to interface with PECL signal levels and should be biased appropriately. Proper termination requires an external circuit that provides a Thevenin equivalent of 50 to VCC - 2.0V and controlled-impedance transmission lines. To ensure best performance, the differential outputs must have balanced loads. If the optional clock output is not used, the output can be left floating to save power.
Table 4. Phase Detector Gain Setup
INPUT PIN GSEL OPEN or VCC GND Kpd (A/UI) 20 5
Table 5. Optional Clock Setup
INPUT PIN PSEL1 VCC GND VCC GND INPUT PIN PSEL2 VCC VCC GND GND VCO TO POUT DIVIDER RATIO 1 2 4 8
Layout
The MAX3672 performance can be significantly affected by circuit board layout and design. Use good highfrequency design techniques, including minimizing ground inductance and using fixed-impedance transmission lines on the reference and VCO clock signals. Power-supply decoupling should be placed as close to the die as possible. Take care to isolate the input from the output signals to reduce feedthrough.
Setting the Higher-Order Poles
Spurious noise is generated by the phase detector switching at the compare frequency, where fCOMPARE = fVCO/(N1 N2). Reduce the spurious noise from the digital phase detector by placing a higher-order pole (HOP) at a frequency much less than the compare frequency. The HOP should, however, be placed high enough in frequency that it does not decrease the overall loop-phase margin and impact jitter peaking. These two conditions can be met by selecting the HOP frequency to be (K 4) < fHOP < fCOMPARE, where K is the loop bandwidth.
VCO Selection
The MAX3672 is designed to accommodate a wide range of VCO gains, positive or negative transfer slopes, and VCC-referenced or ground-referenced control voltages. These features allow the user a wide range of options in VCO selection; however, the proper VCO must be selected to allow the clock generator circuitry to operate at the optimum levels. When selecting
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Low-Jitter 155MHz/622MHz Clock Generator MAX3672
Interface Schematics
VCC
VCC
VCC - 1.3V
10.5k
10.5k
OUT+
REFLCK+
OUT-
REFLCK-
MAX3672
MAX3672
Figure 1. Input Interface
Figure 2. Output Interface
LOL
a VCO, the user needs to take into account the VCO's phase noise and modulation bandwidth. Phase noise is important because the phase noise above the PLL bandwidth is dominated by the VCO noise performance. The modulation bandwidth of the VCO contributes an additional higher-order pole (HOP) to the system and should be greater than the HOP set with the external filter components.
60k
Noise Performance Optimization
THADJ
0.6V CTH 60k REFCLK VCO MAX3672
Depending on the application, there are many different ways to optimize the PLL performance. The following are general guidelines to improve the noise on the system output clock. 1) If the reference clock noise dominates the total system-clock output jitter, then decreasing the loop bandwidth (K) reduces the output jitter. 2) If the VCO noise dominates the total system clock output jitter, then increasing the loop bandwidth (K) reduces the output jitter. 3) Smaller total divider ratio (N1 N2), lower HOP, and smaller R1 reduce the spurious output jitter. 4) Smaller R1 reduces the random noise due to the op amp.
Figure 3. Loss-of-Lock Indicator
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Low-Jitter 155MHz/622MHz Clock Generator
Bond Pad Coordinates
PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 PAD COORDINATES (m) X 50.8 50.8 50.8 50.8 50.8 50.8 50.8 50.8 50.8 266.8 420.7 574.6 728.5 882.4 1036.2 1190.1 1344 1549.2 1792.2 1792.2 1792.2 1792.2 1792.2 1792.2 1792.2 1792.2 1792.2 1792.2 1565.4 1411.5 1257.6 1103.7 893.2 685.3 531.4 377.5 223.6 Y 1557.3 1408.8 1179.3 1028.1 874.2 720.4 566.5 412.6 258.7 50.8 50.8 50.8 50.8 50.8 50.8 50.8 50.8 50.8 256 409.9 563.8 717.7 871.6 1025.4 1179.3 1333.2 1530.3 1692.3 1692.3 1692.3 1692.3 1692.3 1692.3 1692.3 1692.3 1692.3 1692.3
The LOL output indicates if the PLL has locked onto the reference clock using an XOR gate and comparator. The comparator threshold can be adjusted with THADJ, and the XOR gate output can be filtered with a capacitor between CTH and ground (Figure 3). When the voltage at pin CTH exceeds the voltage at pin THADJ, then the LOL output goes low and indicates that the PLL is not locked. Note that excessive jitter on the reference clock input at frequencies above the loop bandwidth may degrade LOL functionality. The user can set the amount of frequency or phase difference between VCO and reference clock at which LOL indicates an out-of-lock condition. The frequency difference is called the beat frequency. The CTH pin can be connected to an external capacitor, which sets the lowpass filter frequency to approximately fL = 1 2C TH 60k
LOL Setup
MAX3672
This lowpass filter frequency should be set about 10 times lower then the beat frequency to ensure that the filtered signal at CTH does not drop below the THADJ threshold voltage. Internal comparisons occur at the pre-divider output frequency (see Table 1 for VCO and reference clock setup). For example, assume the predivider output frequency is 19.44MHz. For a 1ppm sensitivity, the minimum beat frequency is 19Hz, and the filter should be set to 1.9Hz. Set CTH to 1.36uF. The voltage at THADJ will determine the level at which the LOL output flags. THADJ is set to a default value of 0.6V which corresponds to a 45 phase difference. This value can be overridden by applying the desired threshold voltage to the THADJ input. The range of THADJ is 0V (0) to 2.4V (180).
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11
Low-Jitter 155MHz/622MHz Clock Generator MAX3672
Chip Topography
OPAMP+ VCCA PSEL2 GND VFILTER OPAMPPOLAR PSEL1 COMP
Chip Information
PROCESS: GST2 SUBSTRATE CONNECTED TO GND DIE THICKNESS: 14 mils
37 C2+ C2VCCD THADJ GND CTH NSEL1 NSEL2 GSEL 1 2
36
35
34
33
32
31
30
VC
29
28 27 26 GND VCOIN+ VCOINVCCD MOUT+
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages.
0.076"
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
25 24 23 22 21 20 19
MOUT- (1.930mm) VCCD POUT+ POUT-
RSEL
VSEL
REFCLK+
REFCLK-
VCCD
GND
0.080" (2.032mm)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
VCCD
GND
LOL

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