View KK74LV640N_1260540.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TECHNICAL DATA
KK74LV640
Octal 3-State Inverting Bus Transceiver
The 74LV640 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT640. The 74LV640 provides six inverting buffers with Schmitt-trigger action. * * * * Wide Operating Voltage: 1.2 to 3.6 V Optimized for Low Voltage applications: 1.0 to 3.6 V Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V Low input current
ORDERING INFORMATION KK74LV640N Plastic KK74LV640D SOIC TA = -40 to 125 C for all packages
PIN ASSIGNMENT
DIR 01
20
19
VCC OE
A1 02
A2 03
LOGIC DIAGRAM
DIR 01 OE
A1
18 B1
17 B2
A3 04
A4 05
19
A5 06
A6 07
640
16 B3
15 B4
02
B1 03
A2
B2 04
14 B5
13 B6
12 B7
11 B8
18
A7 08
17
A8 09
GND 10
A3
B3
16
05
A4
B4
15
06
A5
B5 07
A6
14
FUNCTION TABLE
Inputs
OE DIR
L
H
X
B6 08
13
Inputs/Outputs
A=B
input
Z
A7
B7
input
B=A
Z
A8
09
B8
12
L
L
H
11
PIN 20=VCC PIN 10 = GND
1
KK74LV640
MAXIMUM RATINGS*
Symbol VCC IIK* Io*
1 2
Parameter DC supply voltage (Referenced to GND) DC input diode current DC output diode current DC output source or sink current -bus driver outputs DC GND current for types with - bus driver outputs DC VCC current for types with - bus driver outputs Power dissipation per paskade, plastic DIP+ SOIC package+ Storage temperature Lead temperature, 1.5 mm from Case for 10 seconds (Plastic DIP ), 0.3 mm (SOIC Package)
Value -0.5 / +5.0 20 50 35 70 70 750 500 -65 / +150 260
Unit V mA mA mA mA mA mW C C
IOK*
3
IGND ICC PD Tstg TL
*
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/C from 65 to 125C SOIC Package: : - 8 mW/C from 65 to 125C *1: VI < -0.5V or VI > VCC+0.5V *2: Vo < -0.5V or Vo > VCC+0.5V *3: -0.5V < Vo < VCC+0.5V
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA tLH, tHL Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V Min 1.2 0 -40 0 Max 3.6 VCC +125 1000 700 500 400 Unit V V C ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
2
KK74LV640
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit Symbol Parameter Test Conditions VO = VCC0.1 V VCC V 1.2 2.0 3.0 3.6 1.2 2.0 3.0 3.6 VI = VIH - or VIL IO = -50 A VI = VIH - or VIL IO = -8.0 mA VOL Low-Level Output Voltage VI = VIH - or VIL IO = 50 A VI = VIH - or VIL IO = 8.0 mA IIL Low-Level Input Leakage Current High-Level Input Leakage Current Maximum Three-State Leakage Current Quiescent Supply Current (per Package) VI=0 V * -0.1 -1.0 -1.0 A 1.2 2.0 3.0 3.6 3.0 0.09 0.09 0.09 0.09 0.33 0.1 0.1 0.1 0.09 0.40 0.1 0.1 0.1 0.09 0.50 V 1.2 2.0 3.0 3.6 3.0 25C min 0.9 1.4 2.1 2.5 1.1 1.92 2.92 3.52 2.48 max 0.3 0.6 0.9 1.1 -40C / 85C min 0.9 1.4 2.1 2.5 1.0 1.9 2.9 3.5 2.34 max 0.3 0.6 0.9 1.1 -40C / 125C min max 0.9 1.4 2.1 2.5 1.0 1.9 2.9 3.5 2.20 0.3 0.6 0.9 1.1 Unit
VIH
High-Level Input Voltage
V
VIL
Low -Level Input Voltage
V
VOH
High-Level Output Voltage
V
IIH
VI= V
*
-
0.1
-
1.0
-
1.0
A
IOZ
VI= VIL or VIH VO=VCC or GND VI=0 V or V IO = 0 A
1.2 *
-
0.5
-
5.0
-
10
A
ICC
*
-
8.0
-
80.0
-
180.0
A
.
3
KK74LV640
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tLH =tHL = 6.0 ns, RL=1 k)
Guaranteed Limit Symbol tPLH, tPHL Parameter Propagation Delay, A to B , B to A Propagation Delay , Direction or Output Enable to A or B Propagation Delay , Direction or Output Enable to A or B Output Transition Time, Any Output Input Capacitance (Pin 1 or Pin 19) Input Capacitance (Pin 2-9 or Pin 11-18) VI=0 V or V Test Conditions VIL=0 V VIH=VCC tLH = tHL =6.0 ns L = 50 pF VIL=0 V VIH=VCC tLH = tHL =6.0 ns L = 50 pF VIL=0 V VIH=VCC tLH = tHL =6.0 ns L = 50 pF VIL=0 V VIH=VCC tLH = tHL =6.0 ns L = 50 pF VCC V 1.2 2.0 * 1.2 2.0 * 25C min max 100 23 14 120 30 20 -40C / 85C min max 125 28 18 140 37 24 -40C / 125C min max 140 34 21 160 43 28 Unit ns
tPLZ, tPHZ
ns
tPZL, tPZH
1.2 2.0 *
-
120 28 17
-
140 35 21
-
160 43 26
ns
tTLH, tTHL
1.2 2.0 * 3.0
-
60 16 10 7.0
-
75 20 13 -
-
90 24 15 -
ns
CI
pF
CI/O
3.0
-
20.0
-
-
-
-
pF
CPD * - VCC=3.30.3V
-
50
-
-
-
-
pF
tHL
0.9 V1 0.1 0.9 V1
tLH
VCC
0.1
PULSE GENERATOR VI
VCC
VO DEVICE UNDER TEST
tPHL
GND
RT
CL
RL
tPLH
VCC
0.9
0.9 V1 0.1 V1 0.1
B (A)
Termination resistance RT - should be equal to ZOUT of pulse generators
tTHL
tTLH
Figure 1. Switching Waveforms
Figure 2. Test Circuit
4
KK74LV640
N SUFFIX PLASTIC DIP (MS - 001AD)
A
Dimension, mm
20 11 B 1 10
Symbol A B C
MIN 24.89 6.1
MAX 26.92 7.11 5.33
F
L
D F
0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38
0.56 1.78
C -T- SEATING N G D 0.25 (0.010) M T K
PLANE
G H
H J
M
J K L M N
10 3.81 8.26 0.36
NOTES:
1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side.
D SUFFIX SOIC (MS - 013AC)
A 20 11
Dimension, mm Symbol MIN 12.6 7.4 2.35 0.33 0.4 1.27 9.53 0 0.1 0.23 10 0.25 8 0.3 0.32 10.65 0.75 MAX 13 7.6 2.65 0.51 1.27
H
B
P
A B
1
G
10 C R x 45
C D F
-TD 0.25 (0.010) M T C M K
SEATING PLANE
J
F
M
G H J K M P R
NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B 0.25 mm (0.010) per side.
5

▲Up To Search▲

Price & Availability of KK74LV640N

	To Download KK74LV640N Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .