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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844246
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
FEATURES
* Six LVDS outputs * Crystal oscillator interface * Output frequency range: 53.125MHz to 333.3333MHz * Crystal input frequency range: 25MHz to 33.333MHz * RMS phase jitter at 125MHz, using a 25MHz crystal (1.875MHz to 20MHz): 0.39ps (typical) * Full 3.3V or 3.3V core, 2.5V output supply mode * 0C to 70C ambient operating temperature * Industrial temperature information available upon request * Available in both standard and lead-free RoHS-compliant packages
Function
GENERAL DESCRIPTION
The ICS844246 is a Crystal-to-LVDS Clock Synthesizer/Fanout Buffer designed for Fibre HiPerClockSTM Channel and Gigabit Ethernet applications and is a member of the HiperClockSTM family of High Performance Clock Solutions from ICS. The output frequency can be set using the frequency select pins and a 25MHz crystal for Ethernet frequencies, or a 26.5625MHz crystal for a Fibre Channel. The low phase noise characteristics of the ICS844246 make it an ideal clock for these demanding applications.
IC S
SELECT FUNCTION TABLE
Inputs FB_SEL 0 0 0 0 1 1 1 1 N_SEL1 0 0 1 1 0 0 1 1 N_SEL0 0 1 0 1 0 1 0 1 M Divide 20 20 20 20 24 24 24 24 N Divide 2 4 5 8 3 4 6 12
M/N 10 5 4 2.5 8 6 4 2
BLOCK DIAGRAM
Q0 nQ0 PLL_BYPASS
Pullup
PIN ASSIGNMENT
VDDO VDDO nQ2 Q2 nQ1 Q1 nQ0 Q0 PLL_BYPASS VDDA VDD FB_SEL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q3 nQ3 Q4 nQ4 Q5 nQ5 N_SEL1 GND GND N_SEL0 XTAL_OUT XTAL_IN
Q1
1
XTAL_IN XTAL_OUT
nQ1
OSC
PLL
0
Output Divider
Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5
Feedback Divider
FB_SEL N_SEL1 N_SEL0
Pulldown Pullup Pullup
ICS843246
24-Lead, 300-MIL SOIC 7.5mm x 15.33mm x 2.3mm body package M Package Top View 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm body package G Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844246AM
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1
REV. A SEPTEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844246
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
Type Power Output Output Output Input Power Power Input Input Input Pullup Description Output supply pins. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Selects between the PLL and cr ystal inputs as the input to the dividers. When LOW, selects PLL. When HIGH, selects XTAL_IN, XTAL_OUT. LVCMOS / LVTTL interface levels. Analog supply pin. Core supply pin. Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels. Cr ystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Pullup Output frequency select pin. LVCMOS/LVTTL interface levels. Power supply ground. Output Output Output Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 8 9 10 11 12 13, 14 15, 18 16, 17 19, 20 21, 22 23, 24 Name VDDO nQ2, Q2 nQ1, Q1 nQ0, Q0 PLL_BYPASS VDDA VDD FB_SEL XTAL_IN, XTAL_OUT N_SEL0 N_SEL1 GND nQ5, Q5 nQ4, Q4 nQ3, Q3
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
844246AM
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REV. A SEPTEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844246
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
Function
CRYSTAL FUNCTION TABLE
Inputs XTAL (MHz) 25 25 25 25 25 25 25 25 26.5625 26.5625 26.5625 26.5625 26.5625 30 30 30 30 31.25 31.25 31.25 31.25 33.3333 33.3333 33.3333 33.3333 FB_SEL 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 N_SEL1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 N_SEL0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 M 20 20 20 20 24 24 24 24 20 24 24 24 24 20 20 20 20 20 20 20 20 20 20 20 20 500 500 500 500 600 600 600 600 531.25 637.5 637.5 637.5 637.5 600 600 600 600 625 62 5 62 5 625 666.6667 666.6667 666.6667 666.6667 VCO (MHz) N 2 4 5 8 3 4 6 12 5 3 4 6 12 2 4 5 8 2 4 5 8 2 4 5 8 Output (MHz) 250 125 10 0 62.5 200 150 100 50 106.25 212.5 159.375 106.25 53.125 300 150 12 0 75 312.5 156.25 12 5 78.125 333.3333 166.6667 133.3333 83.3333
844246AM
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3
REV. A SEPTEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844246
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
4.6V -0.5V to VDD + 0.5V 10mA 15mA 50C/W (0 lfpm) 70C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA 24 Lead SOIC 24 Lead TSSOP Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3. 3 3. 3 3.3 125 7 127 Maximum 3.465 3.465 3.465 Units V V V mA mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 2.375 Typical 3. 3 3. 3 2. 5 125 7 115 Maximum 3.465 3.465 2.625 Units V V V mA mA mA
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current FB_SEL PLL_BYPASS, N_SEL0, N_SEL1 FB_SEL PLL_BYPASS, N_SEL0, N_SEL1 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0. 8 150 5 Units V V A A A A
IIL
Input Low Current
844246AM
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4
REV. A SEPTEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844246
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
Test Conditions Minimum Typical 387 40 1.29 50 Maximum Units mV mV V mV
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5% TA = 0C TO 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change
NOTE: Please refer to Parameter Measurement Information for output information.
TABLE 4E. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Test Conditions Minimum Typical 379 40 1.24 50 Maximum Units mV mV V mV
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pf parallel resonant crystal. 25 Test Conditions Minimum Typical Maximum 33.333 50 7 1 Units MHz pF mW Fundamental
844246AM
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5
REV. A SEPTEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844246
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
Test Conditions 125MHz, Integration Range: 1.875MHz - 20MHz 20% to 80% Minimum 53.125 0.39 TBD 355 50 1 Typical Maximum 333.33 Units MHz ps ps ps % ms
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter FOUT t jit(O) t sk(o) tR / tF odc Output Frequency RMS Phase Jitter (Random) Output Skew; NOTE 1, 2 Output Rise/Fall Time Output Duty Cycle
PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter FOUT t jit(O) t sk(o) tR / tF odc Output Frequency RMS Phase Jitter (Random) Output Skew; NOTE 1, 2 Output Rise/Fall Time Output Duty Cycle 20% to 80% 125MHz, Integration Range: 1.875MHz - 20MHz Test Conditions Minimum 53.125 0.38 TBD 380 50 1 Typical Maximum 333.33 Units MHz ps ps ps % ms
PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
844246AM
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6
REV. A SEPTEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844246
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
TYPICAL PHASE NOISE
AT
125MHZ @ 3.3V
-10 -20 -30 -40 -50 -60
Gb Ethernet Filter 125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.39ps (typical)
0
NOISE POWER dBc Hz
-70 -80 -90 -100 -110 -120 -130 -140 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
Raw Phase Noise Data
Phase Noise Result by adding Gb Ethernet Filter to raw data OFFSET FREQUENCY (HZ)
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-150
844246AM
REV. A SEPTEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844246
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
3.3V 2.5V
PARAMETER MEASUREMENT INFORMATION
Qx
3.3V5% POWER SUPPLY + Float GND -
SCOPE
LVDS
Qx
SCOPE
++ -
LVDS
nQx
nQx
POWER SUPPLY Float GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx Qx
nQ0:nQ5 Q0:Q5
t PW
nQy Qy
t
PERIOD
tsk(o)
odc =
t PW t PERIOD
x 100%
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD out
80% Clock Outputs
80% VSW I N G
DC Input
LVDS
out
20% tR tF
20%
VOS/ VOS
OUTPUT RISE/FALL TIME
OFFSET VOLTAGE SETUP
VDD out
DC Input
LVDS
100
VOD/ VOD out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
844246AM
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7
REV. A SEPTEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844246
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844246 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each V DDA pin. The 10 resistor can also be replaced by a ferrite bead.
3.3V VDD .01F V DDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844246 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p
Figure 2. CRYSTAL INPUt INTERFACE
844246AM
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8
REV. A SEPTEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844246
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVDS All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached.
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input.
2.5V or 3.3V VDD LVDS_Driv er + R1 100
-
100 Ohm Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
844246AM
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9
REV. A SEPTEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844246
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7A. JAVS. AIR FLOW TABLE
FOR
24 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 50C/W
200
43C/W
500
38C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7B. JAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
TRANSISTOR COUNT
The transistor count for ICS844246 is: 3887
844246AM
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10
REV. A SEPTEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844246
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
24 LEAD SOIC PACKAGE OUTLINE - G SUFFIX
FOR
PACKAGE OUTLINE - M SUFFIX
FOR
24 LEAD TSSOP
TABLE 8A. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 15.20 7.40 1.27 BASIC 10.65 0.75 1.27 8 Millimeters Minimum 24 2.65 -2.55 0.51 0.32 15.85 7.60 Maximum
TABLE 8B. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MS-013, MO-119
Reference Document: JEDEC Publication 95, MO-153
844246AM
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11
REV. A SEPTEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844246
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
Marking TBD TB D TBD TBD Package 24 Lead SOIC 24 Lead SOIC 24 Lead "Lead-Free" SOIC 24 Lead "Lead-Free" SOIC 24 Lead TSSOP 24 Lead TSSOP 24 Lead "Lead-Free" TSSOP 24 Lead "Lead-Free" TSSOP Shipping Packaging tube 1000 tape & reel tube 1000 tape & reel tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS844246AM ICS844246AMT ICS844246AMLF ICS844246AMLFT ICS844246AG ICS844246AGT ICS844246AGLF ICS844246AGLFT
ICS844246AG ICS844246AG TBD TBD
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 844246AM
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REV. A SEPTEMBER 29, 2005

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