View ICS8343I-01_1252906.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8343I-01
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
FEATURES
* 16 LVCMOS/LVTTL outputs * 1 LVCMOS/LVTTL clock input * CLK can accept the following input levels: LVCMOS, LVTTL * Maximum output frequency: 200MHz * Dual output enable inputs facilitates 1-to-16 or 1-to-8 input to output modes * All inputs are 5V tolerant * Output skew: 250ps (typical) * Part-to-part skew: 700ps (typical) * Full 3.3V and 2.5V or mixed 3.3V core/2.5V operating supply * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS8343I-01 is a low skew, 1-to-16 LVCMOS/LVTTL Fanout Buffer and a member of HiPerClockSTM the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8343I-01 single ended clock input accepts LVCMOS or LVTTL input levels. The ICS8343I-01 operates at 3.3V, 2.5V and mixed 3.3V input and 2.5V supply modes over the commercial temperature range. Guaranteed output and partto-part skew characteristics make the ICS8343I-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
ICS
BLOCK DIAGRAM
VDD1 V
DD1
PIN ASSIGNMENT
OE1 OE2 Q15 Q14 Q13
DD
VDD V
VDD2 V
DD2
Q2
CLK CLK Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q15 Q15 Q14 Q14 Q13 Q13 Q12 Q12 Q11 Q11 Q10 Q10 Q9 Q9 Q8 Q8
32 31 30 29 28 27 26 25 VDD1 VDD1 VDD1 Q3 Q4 GND GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Q5 Q6 Q7 CLK VDD Q8 Q9 Q10
ICS8343I-01
OE1 OE1
GND GND
OE2 OE2
32-Lead LQFP 7mm x 7mm x 1.4mm body package Y Package (Top View)
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8343AYI-01
Q1
Q0
24 23 22 21 20 19 18 17
VDD2 VDD2 VDD2 Q12 Q11 GND GND GND
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 22, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8343I-01
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
Type Power Output Power Output Input Power Output Output Power Output Description Q0 thru Q7 output supply pins. LVCMOS/LVTTL clock outputs. 7 typical output impedance. Power supply ground. LVCMOS/LVTTL clock outputs. 7 typical output impedance. Pulldown LVCMOS/LVTTL clock input / 5V tolerant. Core supply pin. LVCMOS/LVTTL clock outputs. 7 typical output impedance. LVCMOS/LVTTL clock outputs. 7 typical output impedance.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2, 3 4, 5 6, 7, 8, 17, 18, 19 9, 10, 11 12 13 14, 15, 16 20, 21 22, 23, 24 25, 26, 27 Name VDD1 Q3, Q4 GND Q5, Q6, Q7 CLK VDD Q8, Q9, Q10 Q11, Q12 VDD2 Q13, Q14, Q15
Q8 thru Q15 output supply pins. LVCMOS/LVTTL clock outputs. 7 typical output impedance. Output enable. When low forces outputs Q8 thru Q15 to HiZ state. 28 OE2 Input Pullup 5V tolerant. LVCMOS/LVTTL interface levels. Output enable. When low forces outputs Q0 thru Q7 to HiZ state. 29 OE1 Input Pullup 5V tolerant. LVCMOS/LVTTL interface levels. 30, 31, 32 Q0, Q1, Q2 Output LVCMOS/LVTTL clock outputs. 7 typical output impedance. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN C PD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance VDD, VDD1, VDD2 = 3.3V 5 VDD, VDD1, VDD2 = 3.465V VDD1, VDD2 = 2.63V Test Conditions Minimum Typical 4 11 9 51 51 7 12 Maximum Units pF pF pF K K
TABLE 3. FUNCTION TABLE
Inputs OE1 0 1 0 1 OE2 0 0 1 1 HiZ Active HiZ Active Outputs Q0:Q7 Q8:Q15 HiZ HiZ Active Active
NOTE: OE1 and OE2 are 5V tolerant.
8343AYI-01
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 22, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8343I-01
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDx + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDD1 = VDD2 = 3.3V5%, TA = -40 TO 85C
Symbol VDD VDDx IDD Parameter Core Supply Voltage Output Supply Voltage; NOTE 1 Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 35 14 Units V V mA mA
IDDx Output Supply Current; NOTE 2 NOTE 1: VDDx denotes VDD1 and VDD2. NOTE 2: IDDx denotes the sum of IDD1 and IDD2.
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDD1 = VDD2 = 3.3V5%, TA = -40 TO 85C
Symbol Parameter VIH VIL IIH IIL VOH VOL IOZL IOZH Input High Voltage Input Low Voltage Input High Current Input Low Current OE1, OE2 CLK OE1, OE2 CLK OE1, OE2 CLK OE1, OE2 CLK VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 2.6 0.5 5 5 Test Conditions Minimum 2 2 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 5 150 Units V V V V A A A A V V A A
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Tristate Current Low Output Tristate Current High
NOTE 1: Outputs terminated with 50 to VDDx/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit.
8343AYI-01
www.icst.com/products/hiperclocks.html
3
REV. A JUNE 22, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8343I-01
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 35 14 Units V V mA mA
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDD1 = VDD2 = 2.5V5%, TA = -40 TO 85C
Symbol VDD VDDx IDD Parameter Core Supply Voltage Output Supply Voltage; NOTE 1 Power Supply Current
IDDx Output Supply Current; NOTE 2 NOTE 1: VDDx denotes VDD1 and VDD2. NOTE 2: IDDx denotes the sum of IDD1 and IDD2.
TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDD1 = VDD2 = 2.5V5%, TA = -40 TO 85C
Symbol Parameter VIH VIL IIH IIL VOH VOL IOZL Input High Voltage Input Low Voltage Input High Current Input Low Current OE1, OE2 CLK OE1, OE2 CLK OE1, OE2 CLK OE1, OE2 CLK VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 1.8 0.5 5 5 Test Conditions Minimum 2 2 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 5 150 Units V V V V A A A A V V A A
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Tristate Current Low
Output Tristate Current High IOZH NOTE 1: Outputs terminated with 50 to VDDx/2. See Parameter Measurement Information, 3.3V/2.5 Output Load Test Circuit.
8343AYI-01
www.icst.com/products/hiperclocks.html
4
REV. A JUNE 22, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8343I-01
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 Maximum 2.625 2.625 34 13 Units V V mA mA
TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = VDD1 = VDD2 = 2.5V5%, TA = -40 TO 85C
Symbol VDD VDDx IDD Parameter Core Supply Voltage Output Supply Voltage; NOTE 1 Power Supply Current
IDDx Output Supply Current; NOTE 2 NOTE 1: VDDx denotes VDD1 and VDD2. NOTE 2: IDDx denotes the sum of IDD1 and IDD2.
TABLE 4F. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDD1 = VDD2 = 2.5V5%, TA = -40 TO 85C
Symbol Parameter VIH VIL IIH IIL VOH VOL IOZL IOZH Input High Voltage Input Low Voltage Input High Current Input Low Current OE1, OE2 CLK OE1, OE2 CLK OE1, OE2 CLK OE1, OE2 CLK VDD = VIN = 2.625V VDD = VIN = 2.625V VDD = 2.625V, VIN = 0V VDD = 2.625V, VIN = 0V -150 -5 1.8 0.5 5 5 Test Conditions Minimum 2 2 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 5 150 Units V V V V A A A A V V A A
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Tristate Current Low Output Tristate Current High
NOTE 1: Outputs terminated with 50 to VDDx/2. See Parameter Measurement Information, 2.5V Output Load Test Circuit.
8343AYI-01
www.icst.com/products/hiperclocks.html
5
REV. A JUNE 22, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8343I-01
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
Test Conditions Minimum Typical Maximum 200 200MHz Measured on rising edge @VDDx/2 Measured on rising edge @VDDx/2 20% to 80% 133MHz > 133MHz 0.4 50 tPERIOD/2 3 250 700 1.5 Units MHz ns ps ps ns % ns
TABLE 5A. AC CHARACTERISTICS, VDD = VDD1 = VDD2 = 3.3V5%, TA = -40 TO 85C
Symbol fMAX tpLH Parameter Onput Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time Output Duty Cycle Output Pulse Width
t sk(o) t sk(pp)
tR / tF odc tPW
All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDx/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%, VDD1 = VDD2 = 2.5V5%, TA = -40 TO 85C
Symbol fMAX Parameter Onput Frequency Test Conditions Minimum Typical Maximum 200 Units MHz
tpLH Propagation Delay; NOTE 1 200MHz 3.25 ns t sk(o) Output Skew; NOTE 2, 4 Measured on rising edge @VDDx/2 250 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 Measured on rising edge @VDDx/2 700 ps Output Rise/Fall Time 20% to 80% 0.4 1.0 ns tR / tF odc Output Duty Cycle 133MHz 50 % All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDx/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, VDD = VDD1 = VDD2 = 2.5V5%, TA = -40 TO 85C
Symbol fMAX tpLH Parameter Onput Frequency Propagation Delay; NOTE 1 Test Conditions 200MHz Minimum Typical 3 Maximum 133 Units MHz ns
t sk(o) Output Skew; NOTE 2, 4 Measured on rising edge @VDDx/2 250 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 Measured on rising edge @VDDx/2 1 ns Output Rise/Fall Time 20% to 80% 0.4 1.0 ns tR / tF odc Output Duty Cycle 133MHz 50 % All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDx/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8343AYI-01
www.icst.com/products/hiperclocks.html
6
REV. A JUNE 22, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8343I-01
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5%
2.05V5% 1.25V5%
VDD, V DDx
SCOPE
Qx
VDD V DDx
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V CORE/ 3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V5%
VDD, V DDx
SCOPE
Qx
V
Qx
DDx
2
LVCMOS
GND
V
Qy
DDx
2 tsk(o)
-1.25V5%
2.5V CORE/ 2.5V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Part 1
Qx
V
DDx
80% 20% tR
80% 20% tF
2
Part 2
Qy
V
DDx
Clock Outputs
2 tsk(pp)
PART-TO-PART SKEW
8343AYI-01
OUTPUT RISE/FALL TIME
www.icst.com/products/hiperclocks.html
7
REV. A JUNE 22, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8343I-01
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
CLK
VDDx 2
V Q0:Q15 Pulse Width t
DDx
2
Q0:Q15
VDDx 2 t
PD
PERIOD
odc =
t PW t PERIOD
PROPAGATION DELAY
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
8343AYI-01
www.icst.com/products/hiperclocks.html
8
REV. A JUNE 22, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8343I-01
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6.
JAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0 200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
67.8C/W 47.9C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8343I-01 is: 985
8343AYI-01
www.icst.com/products/hiperclocks.html
9
REV. A JUNE 22, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8343I-01
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
8343AYI-01
www.icst.com/products/hiperclocks.html
10
REV. A JUNE 22, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8343I-01
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS8343AYI-01 ICS8343AYI-01T Marking ICS8343AYI-01 ICS8343AYI-01
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8343AYI-01
www.icst.com/products/hiperclocks.html
11
REV. A JUNE 22, 2004

▲Up To Search▲

Price & Availability of ICS8343I-01

	To Download ICS8343I-01 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .