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HYS 64/72V16300/32220GU SDRAM-Modules
3.3 V 16M x 64/72-Bit 1 Bank 128MByte SDRAM Module 3.3 V 32M x 64/72-Bit 2 Bank 256MByte SDRAM Module 168-Pin Unbuffered DIMM Modules
* 168-Pin unbuffered 8-Byte Dual-In-Line SDRAM Modules for PC main memory applications * PC100-222, PC133-333 and PC133-222 versions * 1 bank 16M x 64, 16M x 72 and 2 bank 32M x 64, 32M x 72 organzation * Optimized for byte-write non-parity (x64) or ECC (x72) applications * JEDEC standard Synchronous DRAMs (SDRAM) * Fully PC board layout compatible to INTEL's Rev. 1.0 Module Specification * SDRAM Performance: -7 /-7.5 PC133
fCK Max. Clock
* Programmed Latencies: Product Speed -7 -7.5 -8 PC133-222 PC133-333 PC100-222 CL 2 3 2
tRCD tRP
2 3 2
2 3 2
* Single +3.3 V(0.3 V) Power Supply * Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential and Interleave) * Auto-Refresh (CBR) and Self-Refresh * Decoupling capacitors mounted on substrate * All inputs and outputs are LVTTL compatible * Serial Presence Detect with E2PROM
-8 PC100 100 6
Unit MHz ns
133 5.4
* Utilizes 16M x 8 SDRAMs in TSOPII-54 packages with 4096 refresh cycles every 64 ms * 133.35 mm x 31.75 mm x 4,00 mm card size with gold-contact pads (JEDEC MO-161-BA)
Frequency
tAC Clock Access
Time
Description The HYS 64(72)V16300GU and HYS 64(72)V32220GU are industry-standard 168-pin 8-byte Dual In-line Memory Modules (DIMMs) which are organized as 16M x 64, 16M x 72 in 1 bank and 32M x 64 and 32M x 72 in two banks of high-speed memory arrays designed with 128Mbit Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use -7 speed sorted 16M x 8 SDRAM devices in TSOP54 packages to meet the PC133-222 requirements, -7.5 speed sorted for PC133-333 and use -8 components for the standard PC100-222 applications. Decoupling capacitors are mounted on the PC board. The PC board design is in accordance with INTEL's Module Specification. The DIMMs have Serial Presence Detect, implemented with a serial E 2PROM using the two-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All INFINEON 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25" (31.75 mm) height.
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Ordering Information Type 128 MByte DIMMs HYS 64V16300GU-7-C2 PC133-222-520 L-DIM-168-33 133 Mhz 16M x 64 1 bank SDRAM module 1.25" 1.25" 1.25" 1.25" 1.25" 1.25" Code Package Descriptions Module Height
HYS 64V16300GU-7.5-C2 PC133-333-520 L-DIM-168-33 133 Mhz 16M x 64 1 bank SDRAM module HYS 64V16300GU-8-C2 HYS 72V16300GU-7-C2 PC100-222-620 L-DIM-168-33 100 MHz 16M x 64 1 bank SDRAM module PC133-222-520 L-DIM-168-33 133 Mhz 16M x 72 1 bank SDRAM module
HYS 72V16300GU-7.5-C2 PC133-333-520 L-DIM-168-33 133 Mhz 16M x 72 1 bank SDRAM module HYS 72V16300GU-8-C2 256 MByte DIMMs HYS 64V32220GU-7-C2 PC133-222-520 L-DIM-168-30 133 MHz 32M x 64 2 bank SDRAM module PC100-222-620 L-DIM-168-33 100 MHz 16M x 72 1 bank SDRAM module
1.25" 1.25" 1.25" 1.25" 1.25" 1.25"
HYS 64V32220GU-7.5-C2 PC133-333-520 L-DIM-168-30 133 MHz 32M x 64 2 bank SDRAM module HYS 64V32220GU-8-C2 HYS 72V32220GU-7-C2 PC100-222-620 L-DIM-168-30 100 MHz 32M x 64 2 bank SDRAM module PC133-222-520 L-DIM-168-30 133 Mhz 32M x 72 2 bank SDRAM module
HYS 72V32220GU-7.5-C2 PC133-333-520 L-DIM-168-30 133 Mhz 32M x 72 2 bank SDRAM module HYS 72V32220GU-8-C2 PC100-222-620 L-DIM-168-30 100 Mhz 32M x 72 2 bank SDRAM module
Note: All part numbers end with a place code, designating the die revision. Consult factory for current revision. Example: HYS 64V16300GU-8-C2, indicates that Rev.C2 dies are used for SDRAM components.
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Pin Definitions and Functions A0-A11 BA0, BA1 CB0-CB7 RAS CAS Address Inputs Bank Selects Check Bits (x72 modules only) Column Address Strobe WE CKE0, CKE1 *) CLK0 - CLK3 Read/Write Input V SS Clock Enable Clock Input Ground
SCL Clock for SPD SDA Serial Data Out N.C. No Connection - - - -
DQ0 - DQ63 Data Input/Output
DQMB0 - DQMB7 Data Mask Chip Select Power (+3.3 V)
Row Address Strobe CS0 - CS3 *)
VDD
*) CKE1, CS1 and CS3 on two bank modules only
Address Format Part Number 16M x 64 HYS 64V16300GU 16M x 72 HYS 72V16300GU 32M x 64 HYS 64V32220GU 32M x 72 HYS 72V32220GU Rows 12 12 12 12 Columns 10 10 10 10 Bank Select 2 2 2 2 Refresh Period Interval 4k 4k 4k 4k 64 ms 64 ms 64 ms 64 ms 15,6 s 15,6 s 15,6 s 15,6 s
Pin Configuration PIN# Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PIN# 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 Symbol PIN# 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Symbol PIN# 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 Symbol
VSS
DQ0 DQ1 DQ2 DQ3
VSS
DU CS2 DQMB2 DQMB3 DU
VSS
DQ32 DQ33 DQ34 DQ35
VSS
CKE0 CS3 DQMB6 DQMB7 N.C.
VDD
DQ4 DQ5 DQ6 DQ7 DQ8
VDD
DQ36 DQ37 DQ38 DQ39 DQ40
VDD
N.C. N.C. N.C. (CB2) N.C. (CB3)
VDD
N.C. N.C. CB6 CB7
VSS
DQ9 DQ10 DQ11
VSS
DQ16 DQ17 DQ18
VSS
DQ41 DQ42 DQ43
VSS
DQ48 DQ49 DQ50
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Pin Configuration (cont'd) PIN# Symbol 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 DQ12 DQ13 PIN# 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol DQ19 PIN# 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Symbol DQ44 DQ45 PIN# 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol DQ51
VDD
DQ20 N.C. DU CKE1
VDD
DQ52 N.C. DU N.C.
VDD
DQ14 DQ15 N.C. (CB0) N.C. (CB1)
VDD
DQ46 DQ47 N.C. (CB4) N.C. (CB5)
VSS
DQ21 DQ22 DQ23
VSS
DQ53 DQ54 DQ55
VSS
N.C. N.C.
VSS
N.C. N.C.
VDD
WE DQMB0 DQMB1 CS0 DU
VSS
DQ24 DQ25 DQ26 DQ27
VDD
CAS DQMB4 DQMB5 CS1 RAS
VSS
DQ56 DQ57 DQ58 DQ59
VDD
DQ28 DQ29 DQ30 DQ31
VDD
DQ60 DQ61 DQ62 DQ63
VSS
A0 A2 A4 A6 A8 A10 BA1
VSS
A1 A3 A5 A7 A9 BA0 A11
VSS
CLK2 N.C. WP SDA SCL
VSS
CLK3 N.C. SA0 SA1 SA2
VDD VDD
CLK0
VDD
CLK1 N.C.
VDD
VDD
Note: Pin names in parentheses are for the x72 ECC versions; example: Pin 106 = (CB5).
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WE CS0 DQMB0 DQ(7:0) CS WE DQM DQ0-DQ7 D0 CS WE DQM DQ0-DQ7 D1 CS WE DQM DQ0-DQ7 D8 DQMB4 DQ(39:32) CS WE DQM DQ0-DQ7 D4 CS WE DQM DQ0-DQ7 D5
DQMB1 DQ(15:8)
DQMB5 DQ(47:40)
CB(7:0)
CS2 DQMB2 DQ(23:16) CS WE DQM DQ0-DQ7 D2 CS WE DQM DQ0-DQ7 D3 D0-D7, (D8) DQMB6 DQ(55:48) WE CS DQM DQ0-DQ7 D6 CS WE DQM DQ0-DQ7 D7 E PROM (256 word x 8 Bit) SA0 SA1 SA2 SCL SA0 SA1 SA2 SCL SDA WP 47 k
2
DQMB3 DQ(31:24)
DQMB7 DQ(63:56)
A0-A11, BA0, BA1 VCC VSS RAS CAS CKE0
D0-D7, (D8) C0-C15, (C16, C17) D0-D7, (D8) D0-D7, (D8) D0-D7, (D8) D0-D7, (D8)
Clock Wiring 16 M x 64 16 M x 72
5 SDRAM Termination 4 SDRAM + 3.3 pF Termination
Note: D8 is only used in the x72 ECC version and all resistor values are 10 Ohm except otherwise noted.
CLK0 CLK1 CLK2 CLK3
4 SDRAM + 3.3 pF Termination 4 SDRAM + 3.3 pF Termination
Block Diagram for 16M x 64/72 SDRAM DIMM Modules (HYS 64/72V16300GU)
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CS1 CS0 DQMB0 DQ(7:0) CS DQM DQ0-DQ7 D0 CS DQM DQ0-DQ7 D1 CS DQM DQ0-DQ7 D16 CS DQM DQ0-DQ7 D8 CS DQM DQ0-DQ7 D9 CS DQM DQ0-DQ7 D17 DQMB4 DQ(39:32) CS DQM DQ0-DQ7 D4 CS DQM DQ0-DQ7 D5 CS DQM DQ0-DQ7 D12 CS DQM DQ0-DQ7 D13
DQMB1 DQ(15:8)
DQMB5 DQ(47:40)
CB(7:0)
CS3 CS2 DQMB2 DQ(23:16) CS DQM DQ0-DQ7 D2 CS DQM DQ0-DQ7 D3 CS DQM DQ0-DQ7 D10 CS DQM DQ0-DQ7 D11 DQMB6 DQ(55:48) CS DQM DQ0-DQ7 D6 CS DQM DQ0-DQ7 D7
2
CS DQM DQ0-DQ7 D14 CS DQM DQ0-DQ7 D15
DQMB3 DQ(31:24)
DQMB7 DQ(63:56)
A0-A11, BA0, BA1 VDD VSS
D0-D15, (D16, D17)
E PROM (256 Word x 8 Bit) SA0 SA1 SA2 SCL SA0 SA1 SA2 SCL SDA WP
D0-D15, (D16, D17) C0-C31, (C32...C35) D0-D7, (D8) D0-D15, (D16, D17) D0-D7, (D16) VDD
47 k
RAS, CAS, WE CKE0
Clock Wiring 32 M x 64 CLK0 CLK1 CLK2 CLK3 4 SDRAM 4 SDRAM 4 SDRAM 4 SDRAM + 3.3 pF + 3.3 pF + 3.3 pF + 3.3 pF 32 M x 72 5 SDRAM 5 SDRAM 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF
10 k
CKE1 D9-D15, (D17)
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 except otherwise noted.
BL01
Block Diagram for 32M x 64/72 SDRAM DIMM Modules (HYS 64/72V32220GU)
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Absolute Maximum Ratings
Parameter Symbol min. Input / Output voltage relative to VSS Power supply voltage on VDD Storage temperature range Power dissipation per SDRAM component Data out current (short circuit) VIN, VOUT VDD T STG PD IOS - 1.0 - 1.0 -55 - - Limit Values max. 4.6 4.6 +150 1 50 V V
o
Unit
C
W mA
Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability
DC Characteristics TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V
Parameter Symbol min. Input High Voltage Input Low Voltage Output High Voltage (IOUT = - 4.0 mA) Output Low Voltage (IOUT = 4.0 mA) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) Output Leakage Current (DQ is disabled, 0 V < VOUT < VDD) VIH VIL VOH VOL II(L) IO(L) 2.0 -0.5 2.4 - -40 -40 Limit Values max. VDD + 0.3 0.8 - 0.4 40 40 V V V V Unit
A A
Capacitance TA = 0 to 70 C; VDD = 3.3 V 0.3 V, f = 1 MHz Parameter Symbol Limit Values max. max. max. 16Mx64 16Mx72 32Mx64
Input Capacitance (A0 to A11, BA0, BA1, RAS, CAS, WE) Input Capacitance (CS0 - CS3) Input Capacitance (CLK0 - CLK3) Input Capacitance (CKE0, CKE1) Input Capacitance (DQMB0 - DQMB7) Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7) Input Capacitance (SCL, SA0-2) Input/Output Capacitance CI1 CCS CCLK CCKE CI4 CIO CSC CSD 65 32 38 65 13 10 8 8 72 40 40 72 13 10 8 8 105 35 42 65 20 17 8 8
Unit max. 32Mx72
144 43 45 72 20 17 8 8 pF pF pF pF pF pF pF pF
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Operating Currents per SDRAM Component
TA = 0 to 70 oC, VDD = 3.3 V 0.3 V
Parameter Operating Current Test Condition - Symbol -7 /7.5 -8 max. 160 150 Unit Note mA
1)
ICC1
tRC = tRCMIN., tCK = tCKMIN.
Outputs open, Burst Length = 4, CL = 3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access Precharge Standby Current in Power Down Mode CS = V IH (min.), CKE VIL(MAX) Precharge Stand-by Current in Non-Power Down Mode CS = V IH (MIN.), CKE V IH(MIN) No Operating Current CKE V IH(MIN.) ICC3N CKE V IL(MAX.) ICC3P 50 10 45 10 mA mA
1) 1)
tCK = min.
ICC2P
1.5
1.5
mA
1)
tCK = min.
ICC2N
40
35
mA
1)
tCK = min., CS = VIH(MIN),
active state (max. 4 banks) Burst Operating Current tCK = min., Read command cycling Auto-Refresh Current tCK = min., Auto-Refresh command cycling Self-Refresh Current Self-Refresh Mode, CKE = 0.2 V
-
ICC4
100
90
mA
1), 2)
-
ICC5
230
210
mA
1)
-
ICC6
1.5
1.5
mA
1)
1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7 and 7.5 modules and at 100 Mhz for -8 modules. Input signals are changed once during tCK, except for ICC6 and for standby currents when tCK = infinity. All values are shown per memory component. 2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3 and BL = 4 assumed and the data-out current is excluded
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AC Characteristics
3), 4)
TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V, tT = 1 ns
Parameter Symbol -7 PC133-222 min. Clock and Access Time Clock Cycle Time CAS Latency = 3 CAS Latency = 2 System Frequency CAS Latency = 3 CAS Latency = 2 Clock Access Time CAS Latency = 3 CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Setup & Hold Parameters Input Setup Time Input Hold Time Power Down Mode Entry Time Power Down Mode Exit Setup Time Mode Register Setup Time Limit Values -7.5 PC133-333 -8 PC100-222 max. Unit Note
max. min.
max. min.
tCK
7.5 7.5 - - 133 133 5.4 5.4 - - 7.5 10 - - - - 2.5 2.5 - - 133 100 5.4 6 - - 10 10 - - - - 3 3 - - 100 100 6 6 - - ns ns
-
fCK
- - MHz MHz
-
tAC
- - ns ns ns ns
4), 5)
tCH tCL
2.5 2.5
6) 6)
tIS tIH tSB tPDE tRSC
1.5 0.8 - 1 2 1
- - 1 - - -
1.5 0.8 - 1 2 1
- - 1 - - -
2 1 - 1 2 1
- - 1 - - -
ns ns CLK CLK CLK ns
7) 7) 8)
9)
Transition Time (rise and fall) tT Common Parameters RAS to CAS Delay Precharge Time Active Command Period Cycle Time Bank-to-Bank Delay Time
-
tRCD tRP tRAS tRC tRRD
15 15 42 60 14
- - 100k - -
20 20 45 67.5 15
- - 100k - -
20 20 50 70 16
- - 100k - -
ns ns ns ns ns
- - - - -
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AC Characteristics (cont'd) 3), 4)
TA = 0 to 70 C; VSS = 0 V; VDD = 3.3 V 0.3 V, tT = 1 ns
Parameter Symbol -7 PC133-222 min. CAS to CAS Delay Time (same bank) Refresh Cycle Refresh Period (4096 cycles) tREF Self-Refresh Exit Time Read Cycle Data Out Hold Time Data Out to Low Impedance Data Out to High Impedance DQM Data Out Disable Latency Write Cycle Data Input to Precharge (write recovery) DQM Write Mask Latency - 1 64 - - 1 64 - - 1 64 - ms CLK
10)
Limit Values -7.5 PC133-333 1 - -8 PC100-222 max. - 1
Unit
Note
max. min. -
max. min.
tCCD
1
CLK
-
tSREX
tOH tLZ tHZ tDQZ
3 0 3 -
- - 7 2
3 0 3 -
- - 7 2
3 0 3 -
- - 8 2
ns ns ns CLK
4)
-
11
-
tWR tDQW
2 0
- -
2 0
- -
2 0
- -
CLK CLK
- -
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Notes 3. All AC characteristics are shown on SDRAM component level. An initial pause of 100 s is required after power-up, then a Precharge All Banks command must be given followed by eight Auto-Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between V IH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate between 0.8 V and 2.0 V. 5. If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns must be added to this parameter. 6. Rated at 1.4 V 7. If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter. 8. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR) commands must be given to "wake-up" the device. 9. Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal is assumed latched on the next cycle. 10.Self-Refresh Exit is a synchronous operation and begins on the second positive clock edge after CKE returns high. Self-Refresh Exit is not complete until a time period equal to tRC is satisfied after the Self Refresh Exit command is registered. 11.This is referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
t CH CLOCK 1.4 V t CL t IH tT 2.4 V 0.4 V
t IS
INPUT tAC t LZ OUTPUT
1.4 V t AC t OH 1.4 V t HZ
IO.vsd
I/O 50 pF
Measurement conditions for tAC and tOH
A Serial Presence Detect storage device--E2PROM--is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a Serial Presence Detect protocol (I2C synchronous 2-wire bus).
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SPD-Table for PC133-222 Modules:
Byte# Description SPD Entry Value Hex 16Mx64 16Mx72 32Mx64 32Mx72 -7 -7 -7 -7 80 08 04 0C 0A 01 40 48 00 01 75 54 00 02 80 08 00 08 01 00 08 00 02 40 02 48
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General Min. Clock Cycle Time at CAS Latency = 2 Max. data access time from Clock for CL=2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL=1 Minimum Row Precharge Time Minimum Row Active to Row Active delay tRRD
128 256 SDRAM 12 10 1/2 64 / 72 0 LVTTL 7.5 ns 5.4 ns none / ECC Self-Refresh, 15.6 s x8 n/a / x8 t ccd = 1 CLK
16 17 18 19 20 21 22 23 24 25 26 27 28
1, 2, 4 & 8 4 CAS latency = 2 &3 CS latency = 0 Write latency = 0 non buffered/non reg. Vcc tol +/- 10% 7.5 ns 5.4 ns not supported not supported 15 ns 14 ns
0F 04 06 01 01 00 0E 75 54 FF FF 0F 0E
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Byte#
Description
SPD Entry Value
Hex 16Mx64 16Mx72 32Mx64 32Mx72 -7 -7 -7 -7 0F 2A 20 15 08 15 08 FF
Minimum RAS to CAS delay tRCD 30 Minimum RAS pulse width tRAS 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input hold time 35 SDRAM data input setup time 62-61 Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufacturers information 125 126 Frequency Specification 127 Support Details 128+ Unused storage locations
29
15 ns 42 ns 128 MByte 1.5 0.8 1.5 0.8 ns ns ns ns
Revision 1.2 CE XX E0 XX
12 tbd XX 64 AF FF FF tbd XX
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SPD-Table for PC133-333 Modules:
Byte# Description SPD Entry Value Hex 16Mx64 16Mx72 32Mx64 32Mx72 -7.5 -7.5 -7.5 -7.5 80 08 04 0C 0A 01 40 48 00 01 75 54 00 02 80 08 00 08 01 00 08 00 02 40 02 48
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General Min. Clock Cycle Time at CAS Latency = 2 Max. data access time from Clock for CL=2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL=1 Minimum Row Precharge Time Minimum Row Active to Row Active delay tRRD
128 256 SDRAM 12 10 1/2 64 / 72 0 LVTTL 7.5 ns 5.4 ns none / ECC Self-Refresh, 15.6 s x8 n/a / x8 t ccd = 1 CLK
16 17 18 19 20 21 22 23 24 25 26 27 28
1, 2, 4 & 8 4 CAS latency = 2 &3 CS latency = 0 Write latency = 0 non buffered/non reg. Vcc tol +/- 10% 10.0 ns 6.0 ns not supported not supported 20 ns 15 ns
0F 04 06 01 01 00 0E A0 60 FF FF 14 0F
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Byte#
Description
SPD Entry Value
Hex 16Mx64 16Mx72 32Mx64 32Mx72 -7.5 -7.5 -7.5 -7.5 14 2D 20 15 08 15 08 FF
Minimum RAS to CAS delay tRCD 30 Minimum RAS pulse width tRAS 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input hold time 35 SDRAM data input setup time 62-61 Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufacturers information 125 126 Frequency Specification 127 Support Details 128+ Unused storage locations
29
20 ns 45 ns 128 MByte 1.5 0.8 1.5 0.8 ns ns ns ns
Revision 1.2 13 XX 25 XX
12 14 XX 64 AF FF FF 26 XX
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SPD-Table for PC100 Modules:
Byte# Description SPD Entry Value Hex 16Mx64 16Mx72 32Mx64 32Mx72 -8 -8 -8 -8 80 08 04 0C 0A 01 40 48 00 01 A0 60 00 02 80 08 00 08 01 00 08 00 02 40 02 48
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont'd) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General Min. Clock Cycle Time at CAS Latency = 2 Max. data access time from Clock for CL=2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL=1 Minimum Row Precharge Time Minimum Row Active to Row Active delay tRRD
128 256 SDRAM 12 10 1/2 64 / 72 0 LVTTL 10.0 ns 6.0 ns none / ECC Self-Refresh, 15.6 s x8 n/a / x8 t ccd = 1 CLK
16 17 18 19 20 21 22 23 24 25 26 27 28
1, 2, 4 & 8 4 CAS latency = 2 &3 CS latency = 0 Write latency = 0 non buffered/non reg. Vcc tol +/- 10% 10.0 ns 6.0 ns not supported not supported 20 ns 16 ns
0F 04 06 01 01 00 0E A0 60 FF FF 14 10
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Byte#
Description
SPD Entry Value
Hex 16Mx64 16Mx72 32Mx64 32Mx72 -8 -8 -8 -8 14 2D 20 20 10 20 10 FF
Minimum RAS to CAS delay tRCD 30 Minimum RAS pulse width tRAS 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input hold time 35 SDRAM data input setup time 62-61 Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufacturers information 125 126 Frequency Specification 127 Support Details 128+ Unused storage locations
29
20 ns 45 ns 128 MByte 2 ns 1 ns 2 ns 1 ns
Revision 1.2 71 XX 100 MHz AF 83 XX
12 72 XX 64 FF FF 84 XX
INFINEON Technologies
17
9.01
HYS 64/72V16300/32220GU SDRAM-Modules
Package Outlines L-DIM-168-30 (JEDEC MO-161-BA) SDRAM DIMM Module Package
133.35 + 0.15
127.35
31.75 + 0.13
4 max.
4
*)
3 1 3 1.27 10 11 6.35 42.18 91 x 1.27 = 115.57 3.125 40 41 6.35 84
1.27 + 0.1
85
94
2 95
124
125
168
17.78
*)
3 min.
3
Detail of Contacts
*) on ECC modules only
0.25
1 1.27
L-DIM-168-30
2.55
Note: All tolerances according to JEDEC standard
INFINEON Technologies
18
9.01
HYS 64/72V16300/32220GU SDRAM-Modules
Package Outlines L-DIM-168-33 (JEDEC MO-161-BA) SDRAM DIMM Module Package HYS 64/72V16300GU
133.35 + 0.15
127.35
3 max.
+ 0.13 -
4
*)
31.75 3 1 3 1.27 10 11 6.35 42.18 91 x 1.27 = 115.57 3.125 40 41 6.35 84
1.27 + 0.1
2 85 94 95 124 125 168
17.78
3 min.
3
Detail of Contacts
*) on ECC modules only
0.25
1 1.27
L-DIM-168-33
2.55
Note: All tolerances according to JEDEC standard
INFINEON Technologies
19
9.01
HYS 64/72V16300/32220GU SDRAM-Modules
Update Releases:
June 1, 1999 June 17, 1999 August 3, 1999 August 5, 1999 August 23, 1999 Sept.30, 1999 Dec. 2, 1999 Feb. 23, 2000
10.5.2000 21.8.2000 06.09.2001
Explanation for factory specific code in part numbers added Byte 22 for PC100 modules changed from 06 to 0E PC133 spec incorpoated SPD tables added Byte 126 changed to 64h for PC133 modules Some errors corrected, checksums added Some timing parameters adjusted according to INTELs PC133 specification -8A speedsort removed ICC currents updated in accordance to 128Mbit component datasheets Capacitance values updated according to module C-measurements Block Diagrams corrected, R&L template Reference to JEDEC MO-161-BA added PC133-222 modules "-7 speed sort" added SCR : Absolute Maximum Ratings table added
INFINEON Technologies
20
9.01

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