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TM
HD-15531/883
CMOS Manchester Encoder-Decoder
Description
The Intersil HD-15531/883 is a high performance CMOS device intended to service the requirements of MIL-STD1553 and similar Manchester II encoded, time division multiplexed serial data protocols. This LSI chip is divided into two sections, an Encoder and a Decoder. These sections operate independently of each other, except for the master reset and word length functions. This circuit provides many of the requirements of MIL-STD-1553. The Encoder produces the sync pulse and the parity bit as well as the encoding of the data bits. The Decoder recognizes the sync pulse and identifies it as well as decoding the data bits and checking parity. The HD-15531/883 also surpasses the requirements of MILSTD-1553 by allowing the word length to be programmable (from 2 to 28 data bits). A frame consists of three bits for sync followed by the data word (2 to 28 data bits) followed by one bit of parity, thus, the frame length will vary from 6 to 32 bit periods. This chip also allows selection of either even or odd parity for the Encoder and Decoder separately. This integrated circuit is fully guaranteed to support the 1MHz data rate of MIL-STD-1553 over both temperature and voltage. For high speed applications the 15531B will support a 2.5 Megabit/sec data rate. The HD-15531/883 can also be used in many party line digital data communications applications, such as a local area network or an environmental control system driven from a single twisted pair or fiber optic cable throughout a building.
March 1997
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * Support of MIL-STD-1553 * Data Rate (15531B) . . . . . . . . . . . . . . . .2.5 Megabit/Sec * Data Rate (15531) . . . . . . . . . . . . . . . . .1.25 Megabit/Sec * Variable Frame Length to 32-Bits * Sync Identification and Lock-In * Separate Manchester II Encode, Decode * Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
PACKAGE CERDIP TEMPERATURE RANGE -55oC to +125oC 1.25MBIT/SEC HD1-15531/883 2.5MBIT/SEC HD1-15531B/883 PKG. NO. F40.6
FN2962.1
170
HD-15531/883 Pinout
HD-15531/883 (CERDIP) TOP VIEW
VCC VALID WORD TAKE DATA' TAKE DATA SERIAL DATA OUT SYNCHR DATA SYNCHR DATA SEL SYNCHR CLK DECODER CLK 1 2 3 4 5 6 7 8 9 40 COUNT C1 39 COUNT C4 38 DATA SYNC 37 ENCODER CLK 36 COUNT C3 35 NC 34 ENCODER SHIFT CLK 33 SEND CLK IN 32 31 30 29 SEND DATA ENCODER PARITY SEL SYNC SEL ENCODER ENABLE
SYNCHR CLK SEL 10 BIPOLAR ZERO IN 11 BIPOLAR ONE IN 12 UNIPOLAR DATA IN 13 DECODER SHIFT CLK 14 TRANSITION SEL 15 NC 16 COMMAND SYNC 17 DECODER PARITY SEL 18 DECODER RESET 19 COUNT C0 20
28 SERIAL DATA IN 27 BIPOLAR ONE OUT 26 OUTPUT INHIBIT 25 24 BIPOLAR ZERO OUT
/ 6 OUT
23 COUNT 2 22 MASTER RESET 21 GND
Block Diagrams
ENCODER
21 22 33 24
GND MASTER RESET SEND CLK IN 6 OUT
VCC OUTPUT INHIBIT
1
26
/2 /6
CHARACTER FORMER
27
BIPOLAR ONE OUT BIPOLAR ZERO OUT
25
37
ENCODER CLK
BIT COUNTER 32 20 C0 40 C1 23 C2 36 C3 39 C4 34 28 29 30 31
SEND DATA
SERIAL DATA IN
SYNC SELECT ENCODER PARITY SELECT
ENCODER SHIFT CLK
ENCODER ENABLE
171
HD-15531/883 Block Diagrams
(Continued) DECODER
7 8
SYNCHRONOUS DATA SELECT UNIPOLAR DATA IN BIPOLAR ONE IN BIPOLAR ZERO IN 13 12 11 TRANSITION FINDER
SYNCHRONOUS DATA 4 TAKE DATA COMMAND DATA SYNC 5 SERIAL DATA OUT VALID WORD PARITY SELECT DECODER SHIFT CLK
DATA SELECT GATE
CHARACTER IDENTIFIER
17 38
DECODER CLK DECODER CLK SELECT SYNCHRONOUS CLK SYNCHRONOUS CLK SELECT MASTER RESET
9 15 SYNCHRONIZER 8
CLOCK SELECT DATA
BIT RATE CLK
2 PARITY 16 CHECK
14 10 22
DECODER RESET
19
BIT COUNTER 23 36 39 C3 C4
3
TAKE DATA
20 40 C0
C1 C2
172
HD-15531/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance JA JC CERDIP Package . . . . . . . . . . . . . . . . . . 35oC/W 9oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range (TA). . . . . . . . . . . . -55oC to +125oC Encoder/Decoder Clock Rise Time (TECR, TDCR) . . . . . . . 8ns Max Encoder/Decoder Clock Fall Time (TECF, TDCF) . . . . . . . . 8ns Max Sync. Transition Span (TD2). . . . . . . . . . . 18 TDC Typical, (Note 1) Short Data Transition Span (TD4). . . . . . . . 6 TDC Typical, (Note 1) Long Data Transition Span (TD5) . . . . . . . 12 TDC Typical, (Note 1)
TABLE 1. HD-15531/883, HD-15531B/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS SYMBOL VIL VIH VILC VIHC VOL GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE -55oC TA +125oC MIN MAX 0.2 VCC GND +0.5 0.4 UNITS V V V V V
PARAMETER Input LOW Voltage Input HIGH Voltage Input LOW Clock Voltage Input HIGH Clock Voltage Output LOW Voltage
TEST CONDITIONS VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V IOL = +1.8mA, VCC = 4.5V (Note 2) IOH = -3.0mA, VCC = 4.5V (Note 2) VI = VCC or GND, VCC = 5.5V VIN = VCC = 5.5V, Outputs Open (Note 3)
-55oC TA +125oC 0.7 VCC -55oC TA +125oC -
-55oC TA +125oC VCC -0.5 -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -
Output HIGH Voltage
VOH
1, 2, 3
2.4
-
V
Input Leakage Current
II
1, 2, 3
-1.0
+1.0
A
Standby Supply Current
ICCSB
1, 2, 3
-
2
mA
Functional Test NOTES:
FT
7, 8
-
-
-
1. TDC = Decoder clock period = 1/FDC. 2. Interchanging of force and sense conditions is permitted. 3. Tested as follows: f = 15MHz, VIH = 70% VCC, VIL = 20% VCC, CL = 50pF, VOH VCC/2 and VOL VCC/2.
TABLE 2. HD-15531/883, HD-15531B/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (NOTE 2) CONDI-TIONS GROUP A SUBGROUPS HD-15531/883 TEMPERATURE MIN MAX HD-15531B/883 MIN MAX UNITS
PARAMETER
SYMBOL
ENCODER TIMING Encoder Clock Frequency Send Clock Frequency FEC VCC = 4.5V and 5.5V 9, 10, 11 -55oC TA +125oC 15 30 MHz
FESC
VCC = 4.5V and 5.5V
9, 10, 11
-55oC TA +125oC
-
2.5
-
5.0
MHz
173
HD-15531/883
TABLE 2. HD-15531/883, HD-15531B/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) (NOTE 2) CONDI-TIONS VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 HD-15531/883 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 150 75 75 90 100 55 150 0 10 95 MAX 1.25 125 50 130 HD-15531B/883 MIN 150 50 50 90 100 55 150 0 10 95 MAX 2.5 80 50 130 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns
PARAMETER Encoder Data Rate Master Reset Pulse Width Shift Clock Delay Serial Data Setup Serial Data Hold Enable Setup Enable Pulse Width Sync Setup Sync Pulse Width Send Data Delay Bipolar Output Delay Enable Hold Sync Hold
SYMBOL FED TMR TE1 TE2 TE3 TE4 TE5 TE6 TE7 TE8 TE9 TE10 TE11
DECODER TIMING Decoder Clock Frequency Decoder Sync Clock Decoder Data Rate Decoder Reset Pulse Width Decoder Reset Setup Time Decoder Reset Hold Time Master Reset Pulse Bipolar Data Pulse Width One Zero Overlap Sync Delay (ON) FDC VCC = 4.5V and 5.5V 9, 10, 11 -55oC TA +125oC 15 30 MHz
FDS FDD TDR
VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V
9, 10, 11 9, 10, 11 9, 10, 11
-55oC TA +125oC -55oC TA +125oC -55oC TA +125oC
150
2.5 1.25 -
150
5.0 2.5 -
MHz MHz ns
TDRS
VCC = 4.5V and 5.5V
9, 10, 11
-55oC TA +125oC
75
-
75
-
ns
TDRH TMR TD1 TD3 TD6
VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V
9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
-55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC
10 150 TDC +10 (Note 1) -20
TDC-10 (Note 1) 110
10 150 TDC +10 (Note 1) -20
TDC-10 (Note 1) 110
ns ns ns ns ns
174
HD-15531/883
TABLE 2. HD-15531/883, HD-15531B/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) (NOTE 2) CONDI-TIONS VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 HD-15531/883 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 0 0 0 0 MAX 110 80 110 110 110 75 HD-15531B/883 MIN 0 0 0 0 MAX 110 80 110 110 110 75 UNITS ns ns ns ns ns ns
PARAMETER Take Data Delay (ON) Serial Data Out Delay Sync Delay (OFF) Take Data Delay (OFF) Valid Word Delay Sync Clock to Shift Clock Delay Sync Data Setup NOTES:
SYMBOL TD7 TD8 TD9 TD10 TD11 TD12
TD13
VCC = 4.5V and 5.5V
9, 10, 11
-55oC TA +125oC
75
-
75
-
ns
1. TDC = Decoder Clock Period = 1/FDC. 2. AC Testing as follows: VIH = 70% VCC, VIL = 20% VCC; Input rise/fall times driven at 1ns/V; Timing reference levels: VCC/2; Output load: CL = 50pF. TABLE 3. HD-15531/883, HD-15531B/883 ELECTRICAL PERFORMANCE SPECIFICATIONS LIMITS PARAMETER Input Capacitance Input/Output Capacitance Operating Power Supply Current NOTES: 1. The parameters listed in Table 3 are controlled via design or process parameters are characterized upon initial design and after major process and/or design changes. 2. Guaranteed but not 100% tested. SYMBOL CI CIO ICCOP CONDITIONS VCC = OPEN, f = 1MHz, All measurements referenced to device GND VCC = OPEN, f = 1MHz, All measurements referenced to device GND VCC = 5.5V, f = 1MHz NOTES 1 1 1, 2 TEMPERATURE TA = +25oC TA = +25oC -55oC TA +125oC MIN MAX 25 25 10 UNITS pF pF mA
TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C & D METHOD 100%/5004 100%/5004 100%/5004 100%/5004 Samples/5005 Samples/5005 SUBGROUPS 1, 7, 9 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9
175
HD-15531/883 Burn-In Circuit
HD1-15531/883 CERDIP
R VCC A A A A VCC GND VCC FO GND R R R R R 1 2 3 4 5 6 7 8 9 10 11 R GND A VCC NC A GND GND VCC R R R R 12 13 14 15 16 17 18 19 20 R R VCC 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 R R A VCC GND GND R R R R VCC R A VCC GND VCC GND R R VCC VCC R A FO GND NC A
R A R
GND
NOTES: 1. VCC = 5.5V 0.5V. 2. VIH = 4.5V 10%. 3. VIL = -0.2V to +0.4V. 4. R = 47k 5%. 5. F0 = 100kHz 10%.
176
HD-15531/883 Die Characteristics
DIE DIMENSIONS: 155 x 195 x 19 1mils METALLIZATION: Type: Si-Al Thickness: 11kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 2.0 x 105 A/cm2
Metallization Mask Layout
HD-15531/883
VALID WORD TAKE DATA' TAKE DATA VCC
COUNT C1 COUNT C4
DATA SYNC ENCODER CLK COUNT C3
SERIAL DATA OUT
ENCODER SHIFT CLK SYNCHR DATA SEND CLK IN SYNCHR DATA SEL
SYNCHR CLK
SEND DATA
DECODER CLK
ENCODER PARITY SEL
SYNCHR CLK SEL
SYNC SEL
BIPOLAR ZERO IN BIPOLAR ONE IN
ENCODER ENABLE
SERIAL DATA IN UNIPOLAR DATA IN BIPOLAR ONE OUT
DECODER SHIFT CLK OUTPUT INHIBIT TRANSITION SEL
COMMAND SYNC DECODER PARITY SEL COUNT C0 MASTER COUNT RESET 2
BIPOLAR ZERO OUT
DECODER RESET
GND
/ 6 OUT
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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