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| GMS81C3004 Table of Contents 1. OVERVIEW............................................1 Description .........................................................1 Features .............................................................1 Development Tools ............................................1 13. INTERRUPTS ....................................46 Interrupt Sequence .......................................... 48 Multi Interrupt .................................................. 50 External Interrupt ............................................. 51 2. BLOCK DIAGRAM .................................2 3. PIN ASSIGNMENT ................................3 4. PACKAGE DIAGRAM ............................4 5. PIN FUNCTION......................................5 6. PORT STRUCTURES............................7 7. ELECTRICAL CHARACTERISTICS ....10 Absolute Maximum Ratings .............................10 Recommended Operating Conditions ..............10 DC Electrical Characteristics ...........................10 A/D Comparator Characteristics ......................12 AC Characteristics ...........................................12 Typical Characteristics .....................................14 14. KEY SCAN.........................................53 15. LCD DRIVER .....................................55 Configuration of LCD driver ............................. 55 Control of LCD Driver Circuit ........................... 56 Bias Resistor ................................................... 57 LCD Display Memory ...................................... 59 LCD Port Selection .......................................... 60 Control Method of LCD Driver ......................... 60 LCD Waveform ................................................ 62 16. WATCHDOG TIMER .........................64 17. BUZZER DRIVER ..............................66 18. POWER DOWN OPERATION...........68 SLEEP Mode ................................................... 68 STOP Mode .................................................... 69 8. MEMORY ORGANIZATION.................16 Registers ..........................................................16 Program Memory .............................................19 Data Memory ...................................................22 Addressing Mode .............................................25 19. OSCILLATOR CIRCUIT.....................73 20. RESET ...............................................74 External Reset Input ........................................ 74 Watchdog Timer Reset ................................... 74 9. I/O PORTS ...........................................29 Registers for Port .............................................29 I/O Ports Configuration ....................................30 21. POWER FAIL PROCESSOR.............75 A. CONTROL REGISTER LIST .................. i B. PAD COORDINATION .......................... ii Pad Layout ......................................................... ii Bonding Pad Coordination ................................ iii 10. CLOCK GENERATOR .......................33 Operation Mode ...............................................35 Operation Mode Switching ...............................36 11. TIMER ................................................38 Basic Interval Timer .........................................38 Timer/Event Counter 1 .....................................39 Watch Timer .....................................................43 C. INSTRUCTION..................................... iv Terminology List ................................................iv Instruction Map ...................................................v Instruction Set ...................................................vi 12. COMPARATOR .................................44 D. MASK ORDER SHEET ....................... xii MAR. 1999 Ver 1.01 GMS81C3004 GMS81C3004 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH LCD DRIVER 1. OVERVIEW 1.1 Description The GMS81C3004 is an advanced CMOS 8-bit microcontroller with 4K bytes of ROM. The device is one of GMS800 family. The LG Semicon GMS81C3004 is a powerful microcontroller which provides a highly flexible and cost effective solution to many LCD applications such as controller with LCD and toys. The GMS81C3004 provides the following standard features: 4K bytes of ROM, 256 bytes of RAM, 8-bit timer/counter, on-chip oscillator and clock circuitry. In addition, the GMS81C3004 supports power saving modes to reduce power consumption. Device name GMS81C3004 ROM Size 4K bytes RAM Size 256 bytes Package 80QFP or DIE 1.2 Features * 4K Bytes On-chip Program Memory * 256 Bytes of On-chip Data RAM (Included 64 bytes stack memory) * Dot Matrix LCD Driver - Max. 320 dots (40 seg. x 8 com.) - 40 bytes of Display RAM * Instruction Cycle Time: - 0.5us, 1.9us, 3.8us, 15.2us at 4.19MHz - 61us, 244us, 488us, 1.95ms at 32.768KHz * 51 Programmable I/O pins (Included 32 LCD pins) * 2.2V to 5.5V Wide Operating Range * Dual Clock Operation (4.19MHz, 32kHz) * One 8-bit Basic Interval Timer * Key Scan * One 8-bit Timer/ Counter * Watch Timer * Watchdog timer * Eight Interrupt sources - External input: 3 - Keyscan input: 1 - Timer: 4 * Buzzer Driving port - 500Hz ~ 130kHz * 4-channel 5-bit On-chip Comparator * Power Down Mode - STOP mode - SLEEP mode 1.3 Development Tools The GMS81C3004 is supported by a full-featured macro assembler, an in-circuit emulator CHOICE-DrTM. In Circuit Emulators LCD Simulator Assembler CHOICE-Dr. (with EVA81C) Under development LGS Macro Assembler MAR. 1999 Ver 1.01 1 GMS81C3004 2. BLOCK DIAGRAM Common Drive Output COM0 ~ COM7 Segment Drive Output SEG0 ~ SEG39 (R4, R5, R6, R7) LCD Power Supply VCL1 VCL2 VCL3 VCL4 VCL5 LCD CONTROLLER R7 R6 R5 R4 PSW ALU Accumulator Stack Pointer Data Memory LCD Display Memory PC RESET TEST Interrupt Controller System controller System Clock Controller Timing generator 8-bit Basic Interval Tim er Watchdog Timer Watch Timer 8-bit Timer/ Counter Program Memory Data Table XIN XOUT SXIN SXOUT High freq. Low freq. Clock Generator 5-bit C om parator PC VDD VSS Power Supply R20~R22 R00 R01 R02 R03 R04 R05 R06 R07 / INT0 / INT1 / INT2 / EC1 / LCDCK R2 R0 R1 Buzzer Driver R10/ KS0 R11 / KS1 R12 / KS2 R13 / BUZ / KS3 R14 / CMP0 / KS4 R15 / CMP1 / KS5 R16 / CMP2 / KS6 R17 / CMP3 / KS7 2 MAR. 1999 Ver 1.01 GMS81C3004 3. PIN ASSIGNMENT SEG13 / R55 SEG12 / R54 SEG11 / R53 SEG10 / R52 SEG9 / R51 SEG8 / R50 SEG7 / R47 SEG6 / R46 SEG5 / R45 SEG4 / R44 SEG3 / R43 SEG2 / R42 SEG1 / R41 SEG0 / R40 SXOUT RESET XOUT TEST SXIN VDD R22 43 R21 42 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 SEG14 / R56 SEG15 / R57 SEG16 / R60 SEG17 / R61 SEG18 / R62 SEG19 / R63 SEG20 / R64 SEG21 / R65 SEG22 / R66 SEG23 / R67 SEG24 / R70 SEG25 / R71 SEG26 / R72 SEG27 / R73 SEG28 / R74 SEG29 / R75 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 41 R20 XIN 40 39 38 37 36 35 34 R07 R06 / LCDCK R05 R04 R03 / EC1 R02 / INT2 R01 / INT1 R00 / INT0 R17 / CMP3 / KS7 R16 / CMP2 / KS6 R15 / CMP1 / KS5 R14 / CMP0 / KS4 R13 / BUZ / KS3 R12 / KS2 R11 / KS1 R10 / KS0 GMS81C3004 33 32 31 30 29 28 27 26 25 VSS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 VCL1 VCL2 VCL3 VCL4 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG30 / R76 MAR. 1999 Ver 1.01 SEG31 / R77 SEG39 VCL5 3 GMS81C3004 4. PACKAGE DIAGRAM 24.15 23.65 20.10 19.90 UNIT: mm 18.15 17.65 14.10 13.90 SEE DETAIL "A" 0-7 3.10 max. 0.8 BSC 1.03 0.73 1.95 REF 0.45 0.30 0.36 0.10 DETAIL "A" Figure 4-1 Package Diagram 4 MAR. 1999 Ver 1.01 0.23 0.13 GMS81C3004 5. PIN FUNCTION VDD: Supply voltage. VSS: Circuit ground. TEST: Used for shipping inspection of the IC. For normal operation, it should be connected to VSS. RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. SXIN: Input to the internal sub system clock operating circuit. SXOUT: Output from the inverting subsystem oscillator amplifier. R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R0 serves the functions of the various following special features. Port pin R00 R01 R02 R03 R06 Alternate function INT0 (External interrupt 0) INT1 (External interrupt 1) INT2 (External interrupt 2) Event counter input LCD clock output R20~R22: R2 is a 3-bit CMOS bidirectional I/O port. Each pins 1 or 0 written to the their Port Direction Register can be used as outputs or inputs. R40~R47, R50~57, R60~R67, R70~R77: R4, R5, R6, R7 are four 8-bit CMOS bidirectional I/O port. Each pins 1 or 0 written to the their Port Direction Register can be used as outputs or inputs. Ports is multiplexed with SEG0~SEG31 respectively. Port pin SEG0~SEG7 SEG8~SEG15 SEG16~SEG23 SEG24~SEG31 Alternate function R40~R47 R50~R57 R60~R67 R70~R77 After the reset of the MCU, port is initialized as a segment output port. SEG0~SEG39: Segment signal output pins for the LCD display. See "15. LCD DRIVER" on page 55 for details. COM0~COM7: Common signal output pins for the LCD display. See "15. LCD DRIVER" on page 55 for details. VCL1~VCL5: Power supply pins for the LCD driver. Since the LCD driving resistors are provided internally, no lines should be connected to these pins. The voltage on each pin is VDD> V CL1> VCL2> VCL3> VCL4> VCL5 > V SS. For details, Refer to Section "15.". R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R1 serves the functions of the various following special features. Port pin R10 R11 R12 R13 R14 R15 R16 R17 Alternate function KS0 (Key scan input 0) KS1 (Key scan input 1) KS2 (Key scan input 2) BUZ / KS3 (Buzzer output or Key scan input 3) CMP0 / KS4 (Comparator input or Key scan input 4) CMP1 / KS5 (Comparator input or Key scan input 5) CMP2 / KS6 (Comparator input or Key scan input 6) CMP3 / KS7 (Comparator input or Key scan input 7) MAR. 1999 Ver 1.01 5 GMS81C3004 PIN NAME VDD VSS TEST RESET VCL1~VCL5 XIN XOUT SXIN SXOUT R00 (INT0) R01 (INT1) R02 (INT2) R03 (EC1) R04 R05 R06 (LCDCK) R07 R10 (KS0) R11 (KS1) R12 (KS2) R13 (BUZ/KS3) R14~R17 (CMP0~CMP3/ KS4~KS7) R20~R22 SEG0~SEG7 (R40~R47) SEG8~SEG15 (R50~R57) SEG16~SEG23 (R60~R67) SEG24~SEG31 (R70~R77) SEG32~SEG39 COM0~COM7 Pin No. 46 11 45 44 20~24 48 47 50 49 33 34 35 36 37 38 39 40 25 26 27 28 29~32 41,42, 43 51~58 59~66 67~74 1,2, 75~80 3~10 12~19 In/Out I I I O I O I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O I/O I/O (Output) I/O I/O (Input) I/O (Input) I/O (Input) I/O (Output/Input) I/O (Input/Input) I/O Output (I/O) Output (I/O) Segment signal output ports Output (I/O) Output (I/O) O O Segment signal output ports Common signal output ports Table 5-1 Port Function Description 3-bit general I/O ports 8-bit general I/O ports 8-bit general I/O ports Supply voltage Circuit ground Function For test purposes. Should connect it to GND for normal operation. Reset signal input LCD power supply Main oscillation input Main oscillation output Sub oscillation input Sub oscillation output External interrupt 0 input External interrupt 1 input External interrupt 2 input External counter input LCD clock output - Key scan input Buzzer output or key scan input Comparator input 0~3 or key scan input 4~7 8-bit general I/O ports 8-bit general I/O ports 8-bit general I/O ports 8-bit general I/O ports 6 MAR. 1999 Ver 1.01 GMS81C3004 6. PORT STRUCTURES R00~R03 / INT0~INT2, EC1 Pull up Reg. VDD DB Data Reg. DB Data Reg. R10~R12 / KS0~KS2 Pull up Reg. DB Pull-up Tr. DB Pull-up Tr. VDD DB Dir. Reg. VSS Pin DB Dir. Reg. VSS Pin DB RD INT EC1 Noise Canceler MUX DB RD Key Scan MUX Key Scan Enable R04, R05, R07, R20~R23 R13 / BUZ, KS3 DB Pull up Reg. Data Reg. BUZZER DB Dir. Reg. VSS DB RD DB RD MUX MU X Pull-up Tr. VDD DB Pull up Reg. Buzzer Enable VDD MU X Pull-up Tr. DB Pin DB D ata R eg. DB Dir. Reg. VSS Pin R06/LCDCK Key Scan DB Pull up Reg. LCR[2] LCDCK MU X Pull-up Tr. VDD Key Scan Enable DB D ata R eg. Pin DB Dir. Reg. VSS DB RD MUX MAR. 1999 Ver 1.01 7 GMS81C3004 R14~R17 / CIN0~CIN3, KS4~KS7 Pull up Reg. Data Reg. SEG32 ~ SEG39 LCVDD DB LCD Data Reg. LCD Control DB Pull-up Tr. VDD DB DB Dir. Reg. VSS Pin LCD Control LCVSS SEGn Pin n=32 to 39 DB RD Comparator MUX COM0 ~ COM7 Channel Selection Frame Counter Key Scan Enable LCVDD Key Scan LCD Control LCVSS COMn Pin n=0 to 7 SEG0~SEG31 / R4, R5, R6, R7 VDD DB Data Reg. VCL1 ~ VCL5 DB Dir. Reg. VSS Pin LCDEN LCR.4 DB RD MU X VCL1 LCVDD DB LCD Data Reg. LCD Control DB Port / SEG Selection Reg. VCL2 VCL3 VCL4 LCVSS VCL5 LCDEN LCR.5 8 MAR. 1999 Ver 1.01 GMS81C3004 XIN, XOUT ( Crystal or Ceramic resonator Option) VDD Main frequency clock RESET VDD RESET XOUT VDD VSS VDD Noise Canceler VSS XIN VSS STOP TEST XIN, XOUT (RC Option) VDD Main frequency clock XOUT VDD VSS VDD TEST VDD Noise Canceler VSS RC Oscillator XIN VSS STOP SXIN, SXOUT VDD SXIN VDD VSS VSS SXOUT VDD Sub frequency clock Noise Canceler VSS MAR. 1999 Ver 1.01 9 GMS81C3004 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Supply voltage ........................................... -0.3 to +6.0 V Storage Temperature ................................-40 to +125 C Voltage on any pin with respect to Ground (VSS) ............................................................... -0.3 to VDD+0.3 Maximum current out of VSS pin ........................100 mA Maximum current into VDD pin ............................80 mA Maximum current sunk by (IOL per I/O Pin) ........20 mA Maximum output current sourced by (IOH per I/O Pin) .................................................................................8 mA Maximum current (IOL) ...................................... 80 mA Maximum current (IOH)...................................... 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7.2 Recommended Operating Conditions Specifications Parameter Symbol Condition Min. Supply Voltage Operating Frequency Sub Operating Frequency Operating Temperature VDD fXIN fSXIN TOPR fXIN=4.19MHz fSXIN=32.768kHz VDD=2.2~5.5V VDD=2.2~5.5V 2.2 1 32 -20 Max. 5.5 4.5 35 85 V MHz kHz C Unit 7.3 DC Electrical Characteristics (TA=-20~85C, V DD=2.2~5.5V), Specifications Parameter Symbol VIH1 VIH2 VIL1 VIL2 VOH VOL IIH1 IIH2 IIL1 IIL2 Condition Min. Input High Voltage All input pins except XIN and SXIN XIN and SXIN All input pins except XIN and SXIN XIN and SXIN VDD=2.2 ~ 5.5V, IOH1=-500A R0,R1,R2,R4,R5,R6,R7 VDD=2.2 ~ 5.5V, IOL1=500A R0,R1,R2,R4,R5,R6,R7 VIN=VDD , All input pins except XIN, SX IN VIN=VDD, XIN, SXIN VIN=VDD , All input pins except XIN, SX IN VIN=VDD, XIN, SXIN 0.8 VDD VDD-0.5 0.8 VDD - Unit Typ. Max. VDD VDD 0.2 VDD 0.4 0.1 VDD 3 20 -3 -20 V V V V V V A A A A Input Low Voltage Output High Voltage Output Low Voltage Input High Leakage Current Input Low Leakage Current - 10 MAR. 1999 Ver 1.01 GMS81C3004 Specifications Parameter Output High Leakage Current Output Low Leakage Current Pull-up Resistor1 LCD Voltage Dividing Resistor Voltage Drop |VDD -COMn| , n=0~7 Voltage Drop |VDD -SEGn| , n=0~39 VCL1 Output Voltage VCL2 Output Voltage VCL3 Output Voltage VCL4 Output Voltage VCL5 Output Voltage Symbol Condition Min. IOHL IOLL RPORT RRESET RLCD VDC VDS VCL1 VCL2 VCL3 VCL4 VCL5 IDD1 Main clock mode2 VDD=3V10% 4.19M H z C rystal O scillator, C L1 =C L2 =30pF Sleep mode3 V D D =3V10% 4.19M H z C rystal O scillator, C L1 =C L2 =30pF Sub clock mode4 V D D =3V10% SXIN=32kH z Sleep mode VDD=3V10% SXIN=32kH z Stop mode5 VDD=5V10% SXIN=0V VDD=2.7 ~ 5.5V 1/4 bias ( VCL2=VCL3) VO= VDD, All output pins VO=0V , All output pins VIN=0V, VDD=3V10%, R0, R1, R2 VIN=0V, VDD=3V10%, RESET VDD=2.7 ~ 5.5V VDD=2.7 ~ 5.5V -15A per common pin VDD=2.7 ~ 5.5V -15A per segment pin 50 30 50 0.75VDD -0.2 0.5VDD0.2 0.5VDD0.2 0.25VDD -0.2 -0.2 Typ. 100 60 70 0.75VDD 0.5VDD 0.5VDD 0.25VDD 0 1.4 Max. 3 -3 200 k 120 90 120 120 0.75VDD +0.2 0.5VDD+ 0.2 0.5VDD+ 0.2 0.25VDD +0.2 +0.2 3.0 mA V k mV mV A A Unit IDD2 - 0.6 1.0 mA Supply Current1 IDD3 - 10 30 A IDD4 - 6 10 A IDD5 1. 2. 3. 4. - 1.3 10 A The Data for 5V operation, refer to "7.6. Typical Characteristics" on page 14. This mode set System Clock Mode Register(SCMR) to xxxx0000 that is fXIN /2 This mode set SCMR to xxxx0000 (fXIN /2) Main-frequency clock stops and the sub-frequency clock is operates. Supply current in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, comparator voltage divide resistor, LVD circuit and output port drive currents. 5. Main-frequency clock stops and sub-frequency clock in not used MAR. 1999 Ver 1.01 11 GMS81C3004 7.4 A/D Comparator Characteristics (TA=-20~85C, V DD=5.0V) Specifications Parameter Analog Input Voltage Range Accuracy Symbol VAIN NFS CMP0~CMP3 Pins Min. VSS Typ. Max. VDD 1 V LSB Unit 7.5 AC Characteristics (TA=-20~+85C, VDD=5V10%, VSS=0V) Specifications Parameter Symbol fMAIN fSUB tMCPW tSCPW tMRCP,tMFCP tSRCP,tSFCP tST tIW tRST tECW tREC,tFEC Pins Min. Operating Frequency XIN SXIN XIN SXIN XIN SXIN XIN, XOUT INT0, INT1, INT2 RESET EC1 EC1 1 32 80 5 2 8 2 Typ. Max. 4.5 35 500 15 20 20 20 20 MHz kHz nS S nS nS mS tSYS1 tSYS1 tSYS1 nS Unit External Clock Pulse Width External Clock Transition Time Oscillation Stabilizing Time Interrupt Pulse Width RESET Input Width Event Counter Input Pulse Width Event Counter Transition Time 1. tSYS is one of 2/fMAIN or 8/fMAIN or 16/fMAIN or 64/fMAIN in main clock operation mode, tSYS is one of 2/fSUB or 8/fSUB or 16/fSUB or 64/fSUB in sub clock operation mode. 12 MAR. 1999 Ver 1.01 GMS81C3004 1/fMAIN tMCPW tMCPW VDD-0.5V XIN tMRCP tSCPW tMFCP tSCPW 0.5V tSYS 1/f SUB VDD-0.5V SXIN tSRCP tSFCP 0.5V tIW tIW INT0, INT1 INT2 0.8VDD 0.2VDD tRST RESET 0.2VDD tECW tECW 0.8VDD 0.2VDD EC1 tREC tFEC Figure 7-1 Timing Chart MAR. 1999 Ver 1.01 13 GMS81C3004 7.6 Typical Characteristics This graphs and tables provided in this section are for design guidance only and are not tested or guranteed. In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for imformation only and divices are guranteed to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3) and (mean - 3) respectively where is standard deviation IOH-VOH, VDD=3.0V IOH (mA) -8 -25C 25C -6 85C -15 IOH-VOH, VDD=5.5V IOH (mA) -25C -20 25C 85C R (k) 100 R-Ta - R0,R1,R2 pin VDD=3.0V -4 -10 VDD=5.5V 50 -2 0 0.5 1.0 1.5 2.0 2.5 VOH (V) -5 0 0 2 3 4 5 VOH 6 (V) -20 0 40 80 Ta (C) IOL-VOL, VDD=3.0V IOL (mA) 16 IOL (mA) -25C 25C 85C 12 30 40 IOL-VOL, VDD=5.5V R-Ta - R (k) 100 -25C 25C 85C RESET pin VDD=3.0V 8 20 50 VDD=5.5V 4 VOL (V) 10 0 0 1 2 3 4 0.5 1.0 1.5 2.0 2.5 VOL 5 (V) -20 0 40 80 Ta (C) VIH1 (V) 4 3 2 1 0 VDD-VIH1 R0,R1,R2 pin fXIN=4MHz Ta=25C VIH2 (V) 4 3 2 1 VDD 6 (V) 0 VDD-VIH2 fSXIN=32kHz Ta=25C RESET pin 1 2 3 4 5 2 3 4 5 VDD 6 (V) 14 MAR. 1999 Ver 1.01 GMS81C3004 VDD-VIL1 VIL1 (V) 4 3 2 1 0 1 2 3 4 5 VDD 6 (V) f XIN=4MHz Ta=25C VIL2 (V) 4 3 2 1 0 VDD-VIL2 fSXIN=32kHz Ta=25C 2 fXIN 3 4 5 VDD 6 (V) fXIN-VDD fXIN (MHz) 4 R = 30k 3 R = 51k Ta=25C R = 20k fXIN-T REXT = 82k VDD=3.0V Operating Area fXIN (MHz) Ta= -20~85C (Main-clock mode) 4 3 fXIN(25C) 1.05 1.00 2 0.95 2 R = 100k VDD 6 (V) 1 0.90 1 T 75 (C) 0 2 3 4 5 0.85 -20 0 25 50 0 2 3 4 5 VDD 6 (V) Normal Operation IDD1-VDD IDD (mA) 4 3 2 2MHz 1 0 2 3 4 5 1MHz VDD 6 (V) 5 0 fXIN = 4MHz Ta=25C I DD (A) 20 Normal Operation IDD3-VDD Ta=25C fSXIN=32kHz 15 10 2 3 4 5 VDD 6 (V) Sleep Mode ISLEEP(IDD2)-VDD IDD (A) 800 600 400 2MHz 200 0 2 3 4 5 1MHz VDD 6 (V) fXIN = 4MHz Ta=25C IDD (A) 8 6 4 2 0 Sleep Mode ISLEEP(IDD4)-VDD fSXIN=32kHz Ta=25C IDD (A) 4 3 2 1 VDD 6 (V) 0 Stop Mode ISTOP(IDD5)-VDD fSXIN=32kHz Ta=25C 2 3 4 5 2 3 4 5 VDD 6 (V) MAR. 1999 Ver 1.01 15 GMS81C3004 8. MEMORY ORGANIZATION The GMS81C3004 has separate address spaces for Program memory, Data Memory and Display memory. Program memory can only be read, not written to. It can be up to 4K bytes of Program memory. Data memory can be read and written to up to 256 bytes including the stack area. Display memory has prepared 40 bytes for LCD. 8.1 Registers This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register. A X Y SP PCH PCL PSW ACCUMULATOR X REGISTER Y REGISTER STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD Stack Address ( 1C0H ~ 1FFH ) 15 1 8 7 SP 0 Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 1C0H to 1FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "FFH" is used. Figure 8-1 Configuration of Registers Hardware fixed Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below. Y Y A Caution: The Stack Pointer must be initialized by software because its value is undefined after RESET. Example: To initialize the SP LDX TXSP #0FFH ; SP FFH A Two 8-bit Registers can be used as a "YA" 16-bit Register Figure 8-2 Configuration of YA 16-bit Register Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3 . It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed (save or restore). 16 MAR. 1999 Ver 1.01 GMS81C3004 [Zero flag Z] This flag is set when the result of an arithmetic operation MSB PSW NEGATIVE FLAG OVERFLOW FLAG SELECT DIRECT PAGE when g=1, page is addressed by RPR BRK FLAG or data transfer is "0" and is cleared by any other result. LSB N V G B H I Z C RESET VALUE : 00 H CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS Figure 8-3 PSW (Program Status Word) Register [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address. [Direct page flag G] This flag assigns RAM page for direct addressing mode. In the direct addressing mode, addressing area is from zero page 00H to 0FFH when this flag is "0". If it is set to "1", addressing area is assigned by RPR register (address 0F8H). It is set by SETG instruction and cleared by CLRG. [Overflow flag V] This flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH) or -128(80 H ). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag. MAR. 1999 Ver 1.01 17 GMS81C3004 At execution of a CALL/TCALL/PCALL At acceptance of interrupt At execution of RET instruction At execution of RET instruction 01FC 01FD 01FE 01FF PCL PCH Push down 01FC 01FD 01FE 01FF PSW PCL PCH Push down 01FC 01FD 01FE 01FF PCL PCH Pop up 01FC 01FD 01FE 01FF PSW PCL PCH Pop up SP before execution SP after execution 01FF 01FD 01FF 01FC 01FD 01FF 01FC 01FF At execution of PUSH instruction PUSH A (X,Y,PSW) 01FC 01FD 01FE 01FF A Push down At execution of POP instruction POP A (X,Y,PSW) 01FC 01FD 01FE 01FF A Pop up 01FFH 01C0H Stack depth SP before execution SP after execution 01FF 01FE 01FE 01FF Figure 8-4 Stack Operation 18 MAR. 1999 Ver 1.01 GMS81C3004 8.2 Program Memory A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 4K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 8-5 , shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 8-6 . As shown in Figure 8-5 , each area is assigned a fixed location in Program Memory. Program Memory area contains the user program. Example: Usage of TCALL LDA #5 TCALL 0FH : : ;1B Y TE INS T RU CT IO N ;IN S TE A D O F 2 B Y TE S ;N O R M A L CA LL F000H ; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0 RET ; FUNC_B: LDA LRG1 2 RET ; ;TABLE CALL ADD. AREA ; ORG 0FFC0H DW FUNC_A DW FUNC_B 1 ;TC A LL A DD R E SS A RE A PROGRAM MEMORY FEFFH FF00H FFC0H FFDFH FFE0H FFFFH TCALL AREA INTERRUPT VECTOR AREA PCALL AREA The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte interval: 0FFF8H and 0FFF9 H for External Interrupt 1, 0FFFAH and 0FFFBH for External Interrupt 0, etc. Any area from 0FF00H to 0FFFFH, if it is not going to be used, its service location is available as general purpose Program Memory. Address 0FFE0H Vector Area Memory Key Scan Interrupt Vector Area Watch Timer Interrupt Vector Area Watchdog Timer Interrupt Vector Area External Interrupt 2 Vector Area Timer/Counter 1 Interrupt Vector Area External Interrupt 1 Vector Area External Interrupt 0 Vector Area Basic Interval Timer Interrupt Vector Area RESET Vector Area Figure 8-5 Program Memory Map Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2 H for TCALL14, etc., as shown in Figure 8-7 . E2 E4 E6 E8 EA EC EE F0 F2 F4 F6 F8 FA FC FE NOTE: "-" means reserved area. Figure 8-6 Interrupt Vector Area MAR. 1999 Ver 1.01 19 GMS81C3004 Address 0FFC0H C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF Program Memory TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK * Address 0FF00H PCALL Area Memory PCALL Area (192 Bytes) 0FFBFH NOTE: * means that the BRK software interrupt is using same address with TCALL0. Figure 8-7 PCALL and TCALL Memory Area PCALL rel 4F35 PCALL 35H TCALL n 4A TCALL 4 4F 35 4A 01001010 ~ ~ ~ ~ 0D125H NEXT ~ ~ Reverse ~ ~ 0FF00H 0FF35H NEXT PC: 11111111 11010110 FH FH DH 6 H 0FF00H 0FFD6H 25 D1 0FFFFH 0FFD7H 0FFFFH 20 MAR. 1999 Ver 1.01 GMS81C3004 Example: The usage software example of Vector address and the initialize part. ORG DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW ORG 0FFE0H NOT_USED NOT_USED NOT_USED KEY_INT WT_INT NOT_USED NOT_USED NOT_USED WDT_INT INT2 TMR1_INT NOT_USED INT1 INT0 BIT_INT RESET 0F000H ; Key Scan ; Watch Timer ; Watch Dog Timer ; Int.2 ; Timer-1 ; ; ; ; Int.1 Int.0 BIT Reset ;******************************************** ; MAIN PROGRAM * ;******************************************* ; RESET: DI ;Disable All Interrupts CLRG LDX #0 RAM_CLR: LDA #0 ;RAM Clear(!0000H->!00BFH) STA {X}+ CMPX #0C0H BNE RAM_CLR ; LDX #0FFH ;Stack Pointer Initialize TXSP ; CALL LCD_CLR ;Clear LCD display memory ; LDM R0, #0 ;Normal Port 0 LDM R0DD,#1000_0010B ;Normal Port Direction LDM PUR0,#1000_0010B ;Pull Up Selection Set LDM PMR0,#0000_0001B ;R0 port / int : : LDM PCOR,#1 ;Enable Peripheral clock : : MAR. 1999 Ver 1.01 21 GMS81C3004 8.3 Data Memory Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into four groups, a user RAM, control registers, Stack, and LCD memory. 0000H Address 0C0H 0C1H 0C2H 0C4H 0C5H 0C6H 0C7H 0C8H 0C9H 0CAH 0CCH 0CDH 0CEH 0CFH 0D4H 0D5H 0D6H 0D8H 0D9H 0DAH 0DBH 0DCH 0DDH 0DEH 0DFH 0E4H 0E5H 0E5H 0ECH 0EDH 0F0H 0F1H 0F3H 0F4H 0F5H 0F6H 0F7H 0F8H 0F9H 0F9H 0FAH 0FBH 0FEH Symbol R0 R1 R2 R4 R5 R6 R7 R0DD R1DD R2DD R4DD R5DD R6DD R7DD PUR0 PUR1 PUR2 IESR PMR0 IENL IENH IRQL IRQH SLMR WDTR TM1 T1 TDR1 CMR CSR WTMR LCR LPMR KSCR KDTR PMR1 BUR RPR BITR CKCTLR SCMR PCOR LVDR R/W R/W R/W R/W R/W R/W R/W R/W W W W W W W W W W W W W R/W R/W R/W R/W W W R/W R W W W W R/W R/W R/W R R/W W R/W R W R/W W R/W RESET Value Undefined Undefined Undefined Undefined Undefined Undefined Undefined 00000000 00000000 -----000 00000000 00000000 00000000 00000000 00000000 00000000 -----000 --000000 ----0000 --00---0 --00-000 --00---0 --00-000 -------0 00111111 ---00000 00000000 Undefined 00-00000 0-----00 ----0000 0-00-000 00000000 00000000 00000000 -------0 11111111 ----0000 Undefined ----0111 ----0000 -------0 ---10000 Addressing mode byte, bit1 byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte2 byte byte byte byte byte byte byte byte byte byte byte byte, bit byte, bit byte, bit byte, bit byte byte byte, bit byte, bit byte byte byte byte byte, bit byte, bit byte, bit byte, bit byte, bit byte byte, bit byte, bit byte byte, bit byte byte, bit USER MEMORY PAGE0 00BFH 00C0H 00FFH 01C0H 01FFH CONTROL REGISTERS USER MEMORY OR STACK AREA UNIMPLEMENTED AREA PAGE1 0C00H 0C4FH LCD DISPLAY MEMORY PAGE12 Figure 8-8 Data Memory Map User Memory The GMS81C3004 has 256 x 8 bits for the user memory (RAM). Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0H to 0FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section. Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction. Table 8-1 Control Registers 1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit. Example; To write at CKCTLR LDM CKCTLR,#09H ;Divide ratio /8 22 MAR. 1999 Ver 1.01 GMS81C3004 Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. Address 0C0H 0C1H 0C2H 0C4H 0C5H 0C6H 0C7H 0C8H 0C9H 0CAH 0CCH 0CDH 0CEH 0CFH 0D4H 0D5H 0D6H 0D8H 0D9H 0DAH 0DBH Symbol R0 R1 R2 R4 R5 R6 R7 R0DD R1DD R2DD R4DD R5DD R6DD R7DD PUR0 PUR1 PUR2 IESR PMR0 IENL IENH KSEN INT2EN WTEN T1EN Bit 7 Bit 6 Bit 5 Bit 4 The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-4 on page 18. LCD Display Memory LCD display data area is handled in LCD section. See "15.4 LCD Display Memory" on page 59. Bit 3 Bit 2 Bit 1 Bit 0 Power-on Reset value xxxx xxxx xxxx xxxx - ---- -xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 - ---- -000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 - ---- -000 --00 0000 ---- 0000 - INT1EN INT0EN WDTEN BITEN --00 ---0 --00 -000 MAR. 1999 Ver 1.01 23 GMS81C3004 Address 0DCH 0DDH 0DEH 0DFH 0E4H 0E5H 1 0E5H 1 0ECH 0EDH 0F0H 0F1H 0F3H 0F4H 0F5H 0F6H 0F7H 0F8H 0F9H 2 0F9H 2 0FAH 0FBH 0FEH Symbol IRQL IRQH SLMR WDTR TM1 T1 TDR1 CMR CSR WTMR LCR LPMR KSCR KDTR PMR1 BUR RPR BITR CKCTLR SCMR PCOR LVDR Bit 7 - Bit 6 - Bit 5 KSIF INT2IF - Bit 4 WTIF T1IF - Bit 3 - Bit 2 INT1IF - Bit 1 INT0IF - Bit 0 WDTIF BITIF Power-on Reset value --00 ---0 --00 -000 ---- ---0 0011 1111 - - - ---0 0000 0000 0000 Undefined - 00-0 0000 0--- --00 ---- 0000 0-00 -000 0000 0000 0000 0000 0000 0000 - - - - - - - R13/BUZ ---- ---0 1111 1111 - - - - ---- 0000 Undefined - - - - ---- 0111 ---- 0000 ---- ---0 ---1 0000 1. The register T1 and TMR1 are located at same address. Address 0E5H is read as T1, and written to TMR1. 2. The register BITR and CKCTLR are located at same address. Address 0F9H is read as BITR, and written to CKCTLR. SFR bit and byte addressable SFR not bit addressable - : this bit location is reserved 24 MAR. 1999 Ver 1.01 GMS81C3004 8.4 Addressing Mode The GMS81C3004 uses six addressing modes; * Register addressing * Immediate addressing * Direct page addressing * Absolute addressing * Indexed addressing * Register-indirect addressing 35H data (3) Direct Page Addressing dp In this mode, a address is specified within direct page. Example; G=0 C535 LDA 35H ;A RAM[35H] ~ ~ ~ ~ data A (1) Register Addressing Register addressing accesses the A, X, Y, C and PSW. (2) Immediate Addressing #imm In this mode, second byte (operand) is accessed as a data immediately. Example: 0435 ADC #35H MEMORY 0E550H 0E551H C5 35 (4) Absolute Addressing !abs Absolute addressing sets corresponding memory data to Data , i.e. second byte(Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example; 0735F0 ADC !0F035H ;A ROM[0F035H] 04 35 A+35H+C A When G-flag is 1, then RAM address is difined by 16-bit address which is composed of 8-bit RAM paging register (RPR) and 8-bit immediate data. Example: G=1, RPR=0CH E45535 LDM 35H,#55H ~ ~ 0F100H 0F101H 0C35H data data 55H 0F102H 07 35 F0 address: 0F035 0F035H data ~ ~ A+data+C A 0F100H 0F101H 0F102H ~ ~ E4 55 35 ~ ~ MAR. 1999 Ver 1.01 25 GMS81C3004 The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H regardless of G-flag and RPR. 983501 INC !0135H ;A ROM[135H] X indexed direct page, auto increment {X}+ In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; G=0, X=35H DB LDA {X}+ 135H data ~ ~ ~ ~ 0F100H 0F101H 0F102H 98 35 01 data+1 data 35H data ~ ~ data A ~ ~ DB address: 0135 36H X (5) Indexed Addressing X indexed direct page (no offset) {X} In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H, G=1, RPR=01H D4 LDA {X} ;ACCRAM[X]. X indexed direct page (8 bit offset) dp+X This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; G=0, X=0F5H C645 LDA 45H+X 115H data ~ ~ data A ~ ~ 0E550H D4 3AH data ~ ~ 0E550H 0E551H C6 45 ~ ~ data A 45H+0F5H=13AH 26 MAR. 1999 Ver 1.01 GMS81C3004 Y indexed direct page (8 bit offset) dp+Y This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. Y indexed absolute !abs+Y Sets the value of 16-bit absolute address plus Y-register data as Memory. This addressing mode can specify memory in whole area. Example; Y=55H D500FA LDA !0FA00H+Y 3F35 JMP [35H] 35H 36H 0A E3 ~ ~ 0E30AH NEXT ~ ~ jump to address 0E30AH ~ ~ 0FA00H 3F 35 ~ ~ 0F100H 0F101H 0F102H D5 00 FA 0FA00H+55H=0FA55H X indexed indirect [dp+X] Processes memory data as Data, assigned by 16-bit pair m em ory w hich is deter mined by pair data [dp+X+1][dp+X] Operand plus X-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, X=10H 1625 ADC [25H+X] ~ ~ 0FA55H data ~ ~ data A (6) Indirect Addressing Direct page indirect [dp] Assigns data address to use for accomplishing command which sets memory data(or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL Example; G=0 0FA00H 35H 36H 05 E0 ~ ~ 0E005H data ~ 0E005H ~ 25 + X(10) = 35H ~ ~ ~ ~ 16 25 A + data + C A MAR. 1999 Ver 1.01 27 GMS81C3004 Y indexed indirect [dp]+Y Processes momory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct page plus Y-register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, Y=10H 1725 ADC [25H]+Y Absolute indirect [!abs] The program jumps to address specified by 16-bit absolute address. JMP Example; G=0 1F25E0 JMP [!0C025H] PROGRAM MEMORY 25H 26H 05 E0 0E025H 0E026H 25 E7 ~ ~ 0E015H data ~ ~ 0E005 H + Y(10) = 0E015H ~ ~ ~ ~ NEXT jump to address 0E30AH ~ ~ 0E725 H ~ ~ 0FA00H 17 25 ~ ~ 0FA00H 1F 25 A + data + C A E0 ~ ~ 28 MAR. 1999 Ver 1.01 GMS81C3004 9. I/O PORTS The GMS81C3004 has seven ports (R0, R1, R2, R4, R5, R6, and R7), and LCD segment port (SEG0~SEG39), and LCD common port (COM0~COM7). These ports pins may be multiplexed with an alternate function for the peripheral features on the device. In general, in a initial reset state, R0,R1,R2 ports are used as a general purpose input port and R4, R5, R6 and R7 ports are used as LCD segment drive output port. 9.1 Registers for Port Port Data Registers The Port Data Registers in I/O buffer in each seven ports (R0,R1,R2,R4,R5,R6,R7) are represented as a Type D flipflop, which will clock in a value from the internal bus in response to a "write to data register" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read data register" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to "read data register" signal from the CPU. Some instructions that read a port activating the "read register" signal, and others activating the "read pin" signal Port Direction Registers All pins have data direction registers which can define these ports as output or input. A "1" in the port direction register configure the corresponding port pin as output. Conversely, write "0" to the corresponding bit to specify it as input pin. For example, to use the even numbered bit of R0 as output ports and the odd numbered bits as input ports, write "55H" to address 0C8H (R0 port direction register) during initial setting as shown in Figure 9-1 . All the port direction registers in the GMS81C3004 have 0 written to them by reset function. On the other hand, its initial status is input. Pull-up Control Registers The R0, R1, and R2 ports have internal pull-up resistors. Figure 9-2 shows a functional diagram of a typical pull-up port. It is connected or disconnected by Pull-up Control register (PURn). The value of that resistor is typically 100k. Refer to DC characteristics for more details. When a port is used as key input, input logic is firmly either low or high, therefore external pull-down or pull-up resisters are required practically. The GMS81C3004 has internal pull-up, it can be logic high by pull-up that can be able to configure either connect or disconnect individually by pull-up control registers PURn. When ports are configured as inputs and pull-up resistor is selected by software, they are pulled to high. If port is configured as an output, pull-up is disabled automatically regardless of setting of PURn. VDD VDD PULL-UP RESISTOR PORT PIN WRITE "55H" TO PORT R0 DIRECTION REGISTER 0C0H 0C1H R0 DATA R1 DATA 01010101 76543210 BIT GND Pull-up control bit 0: Disconnect 1: Connect ~ ~ 0C8H 0C9H R0 DIRECTION R1 DIRECTION ~ ~ IOIO I O I O PORT 76543210 I : INPUT PORT O : OUTPUT PORT Figure 9-2 Pull-up Port Structure Figure 9-1 Example of port I/O assignment MAR. 1999 Ver 1.01 29 GMS81C3004 9.2 I/O Ports Configuration R0 Ports R0 is an 8-bit CMOS bidirectional I/O port (address 0C0H). Each I/O pin can independently used as an input or an output through the R0DD register (address 0C8H). R0 has internal pull-ups that is independently connected or disconnected by PUR0. The control registers for R0 are shown below. R1 has internal pull-ups that is independently connected or disconnected by register PUR1. If the key scan function is used, these pin can input the key switch signal without external pull-up registers. For more details refer to "14.. KEY SCAN" on page 53. The control registers for R1 are shown below. R1 Data Register ADDRESS : 0C0H RESET VALUE : Undefined R1 ADDRESS : 0C1H RESET VALUE : Undefined R17 R16 R15 R14 R13 R12 R11 R10 R0 Data Register R0 R07 R06 R05 R04 R03 R02 R01 R00 R1 Direction Register R1DD ADDRESS : 0C9H RESET VALUE : 00H R0 Direction Register R0DD ADDRESS : 0C8H RESET VALUE : 00H Port Direction 0: Input 1: Output ADDRESS : 0D5 H RESET VALUE : 00 H Port Direction 0: Input 1: Output ADDRESS :0D4H RESET VALUE : 00H R1 Pull-up Selection Register PUR1 R0 Pull-up Selection Register PUR0 Pull-up select 0: Without pull-up 1: With pull-up Pull-up select 0: Without pull-up 1: With pull-up In addition, Port R0 is multiplexed with various special features. The control register PMR0 (address 0D9H) controls the selection of alternate function. After reset, this value is "0", port may be used as normal I/O port. To use alternate function such as External Interrupt rather than normal I/O, write "1" in the corresponding bit of PMR0. Port Pin R00 R01 R02 R03 R06 Alternate Function INT0 (External Interrupt 0) INT1 (External Interrupt 1) INT2 (External Interrupt 2) EC1 (External count input to Timer/Counter 1) LCDCK (LCD clock output) Port R1 is multiplexed with various special features.The control registers controls the selection of alternate function. After reset, this value is "0", port may be used as normal I/O port. The way to select alternate function such as comparator input or buzzer will be shown in each peripheral section. In addition, R1 port is used as key scan function which operate with normal input port. Port Pin R10 R11 R12 R13 R14 R15 R16 R17 Alternate Function KS0 KS1 KS2 KS3/BUZ (Buzzer frequency output) KS4/CMP0 (Comparator input 0) KS5/CMP1 (Comparator input 1) KS6/CMP2 (Comparator input 2) KS7/CMP3 (Comparator input 3) R1 Ports R1 is an 8-bit CMOS bidirectional I/O port (address 0C1H). Each I/O pin can independently used as an input or an output through the R1DD register (address 0C9H). Input or output is configured automatically by each function register (CSR, PMR1, KSCR) regardless of R1DD. 30 MAR. 1999 Ver 1.01 GMS81C3004 R2 Port R2 is an 3-bit CMOS bidirectional I/O port (address 0C2H). Each I/O pin can independently used as an input or an output through the R2DD register (address 0CAH). R2 has internal pull-ups that is independently connected or disconnected by PUR2 (address 0D6H). The control registers for R2 are shown as below. On the initial reset, R4 is configured as LCD segment output ports regardless of Direction Register R4DD. The LCD Port Mode Register (LPMR) should be properly set to be used as normal I/O. Example: To use as I/O ports : : LDM : : : LPMR,#xxxx_xx11B R2 Data Register R2 - ADDRESS: 0C2H RESET VALUE: Undefined R22 R21 R20 x: Don't care R2 Direction Register R2DD - ADDRESS : 0CAH RESET VALUE : 00H R5 Port / SEG8 ~ SEG15 R5 is an 8-bit CMOS bidirectional I/O port (address 0C5H). Each I/O pin can independently used as an input or an output through the R5DD register (address 0CDH). R5 is shared with LCD segment ports. Port Direction 0: Input 1: Output ADDRESS : 0D6 H RESET VALUE : 00 H - R2 Pull-up Selection Register PUR2 - R5 Data Register Pull-up select 0: Without pull-up 1: With pull-up R5 ADDRESS: 0C5H RESET VALUE : Undefined R57 R56 R55 R54 R53 R52 R51 R50 R5 Direction Register ADDRESS :0CDH RESET VALUE : 00H R4 Port / SEG0 ~ SEG7 R4 is an 8-bit CMOS bidirectional I/O port (address 0C4H). Each I/O pin can independently used as an input or an output through the R4DD register (address 0CCH). R4 has difference that it doesn't have internal pull-ups and is shared with LCD segment ports. R5DD Port Direction 0: Input 1: Output On the initial reset, R5 is configured as LCD segment output port regardless of Direction Register R5DD. The LCD Port Mode Register (LPMR) should be set properly to be used as normal I/O. Refer to example below. Example: To use as an I/O port : : LDM : : : R4 Data Register R4 ADDRESS : 0C4H RESET VALUE : Undefined R17 R16 R15 R14 R13 R12 R11 R10 R4 Direction Register R4DD ADDRESS : 0CCH RESET VALUE : 00H LPMR,#xxxx_11xxB Port Direction 0: Input 1: Output x: Don't care MAR. 1999 Ver 1.01 31 GMS81C3004 R6 Port / SEG16 ~ SEG23 R6 is an 8-bit CMOS bidirectional I/O port (address 0C6H). Each I/O pin can independently used as an input or an output through the R6DD register (address 0CEH). R6 is shared with LCD segment ports. R7 Port / SEG24 ~ SEG31 R7 is an 8-bit CMOS bidirectional I/O port (address 0C7H). Each I/O pin can independently used as an input or an output through the R7DD register (address 0CFH). R7 is shared with LCD segment ports. R6 Data Register R6 ADDRESS : 0C6H RESET VALUE : Undefined R7 Data Register R7 ADDRESS : 0C7H RESET VALUE : Undefined R67 R66 R65 R64 R63 R62 R61 R60 R77 R76 R75 R74 R73 R72 R71 R70 R6 Direction Register R6DD ADDRESS : 0CEH RESET VALUE : 00H R7 Direction Register R7DD ADDRESS : 0CFH RESET VALUE : 00H Port Direction 0: Input 1: Output Port Direction 0: Input 1: Output After reset, R6 is initialized as LCD segment output ports regardless of Direction Register R6DD. The LCD Port Mode Register (LPMR) should be set properly to use as normal I/O. Refer to example below. Example: To use as an I/O port LDM LPMR,#xx11_xxxxB After reset, R7 is initialized as LCD segment output ports regardless of Direction Register R7DD. The LCD Port Mode Register (LPMR) should be set properly to use as normal I/O. Refer to example below. Example: To use as an I/O port LDM LPMR,#11xx_xxxxB x: Don't care x: Don't care SEG0~SEG39 Segment signal output pins for the LCD display. COM0~COM7 Common signal output pins for the LCD display. 32 MAR. 1999 Ver 1.01 GMS81C3004 10. CLOCK GENERATOR As shown in Figure 10-1 , the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains two oscillators: a main-frequency clock oscillator and a sub-frequency clock oscillator. Power consumption can be reduced by switching them to the low power operation frequency clock can be easily obtained by attaching a resonator between the XIN and X OUT pin and the SX IN and SXOUT pin, respectively. The system clock can also be obtained from the external oscillator. The clock generator produces the system clocks forming clock pulse, which are supplied to the CPU and the peripheral hardware. The internal system clock can be selected by bit2, and bit3 of the system clock mode register, SCMR. Instruction cycle time CPU clock /2 /8 / 16 / 64 fMAIN = 4.19MHz 0.48 us 1.90 us 3.80 us 15.30 us fSUB = 32.768kHz 61 us 244 us 488 us 1953 us The registers are shown in Figure 10-2 . To the peripheral block, the clock among the not-divided original clocks, divided by 2, 4,..., up to 1024 can be provided. Peripheral clock is enabled or disabled by bit 0 of the peripheral clock enable register (ENPCK). select clock PRESCALER MPX /2 /8 /16 /64 MPX SX IN PIN XIN PIN 1X 0X fEX Internal system clock PRESCALER 2 [0FAH] 2 ENPCK [0FBH] SCMR System clock mode register PCOR Peripheral clock enable register /1 /2 /4 /8 /16 /32 /64 /256 /1024 /128 /512 Peripheral clock Figure 10-1 Block Diagram of Clock Generator Example; PCOR setting and Basic Interval Timer Note: On the initial reset, all peripherals are stopped because peripheral clock is not supplied to each function block. Therefore, Peripheral Clock Enable Register, PCOR must be written to "1" in software initial part. Then, timer and other functions may be operated by provided clock. PCOR CKCTLR IENL IENH BITEN EQU EQU EQU EQU EQU LDM LDM SET1 EI 0FBH 0F9H 0DAH 0DBH 0,IENH PCOR,#1 CKCTLR,#0CH BITEN MAR. 1999 Ver 1.01 33 GMS81C3004 MSB R/W R/W R/W LSB R/W SCMR - - - - ADDRESS: 0FAH INITIAL VALUE: ---- 0000 System clock control 00: main clock on 01: main clock on 10: sub clock on (main clock on) 11: sub clock on (main clock off) System clock source select 00: fM/2 or f S/2 01: fM/8 or fS/8 10: fM/16 or fS/16 11: fM/64 or fS/64 fM: fMAIN fS: fSUB MSB LSB W ENPCK PCOR - ADDRESS: 0FBH INITIAL VALUE: ---- ---0 Peripheral clock control 0: Off (All function block are disabled except CPU) 1: On Figure 10-2 SCMR, PCOR: System Clock Control Registers 34 MAR. 1999 Ver 1.01 GMS81C3004 10.1 Operation Mode The system clock controller starts or stops the main-frequency clock oscillator and switches between the sub frequency clock. The operating mode is generally divided into the main-clock mode and the sub-clock mode, which are controlled by System clock mode register (SCMR). Figure 10-3 shows the operating mode transition diagram. System clock control is performed by the system clock mode register, SCMR. During reset, this register is initialized to "0" so that the main-clock operating mode is selected. Main-clock operating mode This mode is fast-frequency operating mode. The CPU and the peripheral hardwares are operated on the high-frequency clock. At reset release, this mode is invoked. Sub-clock operating mode This mode is low-frequency operating mode In this mode, the high-frequency clock oscillation is stops to operate the CPU and the peripheral hardware on the low-frequency clock, thereby reducing power consumption SLEEP mode In this mode, the CPU clock stops while peripherals and the oscillation source continue to operate normally. STOP mode In this mode, the system operations are all stopped, holding the internal states valid immediately before the stop at the low power consumption level. Main - Oscillating Sub - Oscillating Main - According to SCMR Sub - Oscillating NOTE1: RESET Key Scan Interrupt Watch Timer Interrupt Timer interrupt (EC1) External Interrupt RESET All Interrupts Instruction Main-clock Mode Instruction Release (Main clock) Sub-clock Mode NOTE2: tru Reset c ti o n In s te 1 Re ns tru ST OP I no fe r ctio to to n fe r no Re te 2 RESET Operation t se Re Re Main: Oscillating Sub: Oscillating se t Main: Stopped Sub: Oscillating STOP Mode SLEEP Mode Main: According to SCMR Sub: Oscillating Figure 10-3 Operating Mode MAR. 1999 Ver 1.01 35 GMS81C3004 10.2 Operation Mode Switching In the Main-clock operation mode, only the high-frequency clock oscillator is used. In the Sub-clock operation mode, the high-frequency clock oscillation stops, enabling the low power voltage operation or the low power consumption operation. Instruction execution does not stop when the operation speed switching is performed. However, some peripheral hardware capabilities may be affected. For details, refer to the description of the relevant operation. The following describes the switching between the Mainclock and the Sub-clock operations. During reset, the system clock mode register is initialized at the Main-clock mode. It must be set to the Sub-clock operation for the lowpower consumption mode. Switching from main clock operation to subclock operation First, write "10B" into lower 2 bits of SCMR to switch the main system clock to the sub-frequency clock. Next, write "11B" to turn off main frequency oscillation. Example: : : : MOV MOV : : : : ;20ms software delay DLY: LDY #0 DLP0: LDA #0 DLP1: NOP INC A BCC DLP1 INC Y CMPY #20 BCC DLP0 RET Shifting from the Normal operation to the SLEEP mode By setting bit 0 of SMR, the CPU clock stops and the SLEEP mode is invoked. The CPU stops while other peripherals are operate normally. The way of release from this mode is RESET and all available interrupts. For more detail, See "18.1 SLEEP Mode" on page 68 SCMR,#2 SCMR,#3 ;Switch to sub mode ;Turn off main clock Shifting from the Normal operation to the STOP mode By executing STOP instruction, the main-frequency clock oscillation stops and the STOP mode is invoked. But subfrequency clock oscillation is operated continuously. After the STOP operation is released by reset, the operation mode is changed to Main-clock mode. The methods of release are RESET, Key scan interrupt, Watch Timer interrupt, Timer/Event counter1 (EC1 pin), and External Interrupt. For more details, see "18.2. STOP Mode" on page 69. Note: In the STOP and SLOW operating modes, the power consumed by the oscillator and the internal hardware is reduced. However, the power for the pin interface (depending on external circuitry and program) is not directly associated with the low-power consumption operation. This must be considered in system design as well as interface circuit design. Returning from Sub clock operation to main clock operation First, write "10B" into lower 2 bits of the SCMR to turn on the main-frequency oscillation, when the stabilization (warm-up) has been taken by the software delay routine. Sub clock operation mode can also be released by setting the RESET pin to low, which immediately performs the reset operation. After reset, the GMS81C3004 is placed in main frequency operation mode. Example: : : : MOV CALL MOV : SCMR,#2 DLY SCMR,#0 ;Turn on main-clock ;Wait until stable ;Move to main mode 36 MAR. 1999 Ver 1.01 GMS81C3004 ~ ~ Main freq. clock (XIN pin) Sub freq. clock (SX IN pin) ~ ~ ~ ~ ~ ~ Operation clock ~ ~ Main-clock operation Changed to the Sub-clock Sub-clock operation SCMR XXXX XX10B Turn off main clock SCMR XXXX XX11B (a) Main clock mode Sub clock mode ~ ~ Main freq. clock (XIN pin) Stabilizing Time > 20ms ~ ~ ~ ~ Sub freq. clock (SX IN pin) Operation clock ~ ~ Sub-clock operation Main-clock operation Changed to the Transition SCMR XXXX XX10B Changed to the Main-clock SCMR XXXX XX00B or 01B (b) Sub clock Main clock Figure 10-4 System Clock Switching Timing MAR. 1999 Ver 1.01 37 GMS81C3004 11. TIMER 11.1 Basic Interval Timer The GMS81C3004 has one 8-bit Basic Interval Timer that is free-run and can not stop. Block diagram is shown in Figure 11-1 . The Basic Interval Timer generates the time base for key scanning, watchdog timer counting, and etc. It also provides a Basic interval timer interrupt (BITIF). As the count overflow from FFH to 00H, this overflow causes the interrupt to be generated. The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 11-2 . Source clock can be selected by lower 3 bits of CKCTLR. BITR and CKCTLR are located at same address, and address 0F9H is read as a BITR, and written to CKCTLR.. f M/2 9 or fS/29 fM/210 or fS/210 fM/23 or fS/23 fM/24 or fS/24 f M/2 5 or fS/25 f M/2 6 or fS/26 f M/2 7 or fS/27 fM/28 or fS/28 MUX source clock 8-bit up-counter overflow BITR [0F9 H] BITIF Basic Interval Timer Interrupt Watchdog timer clock (WDTCK) clear Select Input clock 3 BITCK [0F9H] Basic Interval Timer clock control register Internal bus line BTCL CKCTLR Figure 11-1 Block Diagram of Basic Interval Timer Source clock CKCTLR [2:0] 000 001 010 011 100 101 110 111 S C M R [1:0]= 00 or 01 fM/23 fM/24 fM/25 fM/26 fM/27 fM/28 fM/29 fM/210 S C M R[1:0]= 10 or 11 fS/23 fS/24 fS/25 fS/26 fS/27 fS/28 fS/29 fS/210 Interrupt (overflow) Period At fMAIN=4.19MHz 0.488 ms 0.976 1.953 3.906 7.812 15.625 31.250 62.500 At fSUB=32.768kHz 62.5 ms 125.0 250.0 500.0 1000.0 2000.0 4000.0 5000.0 Table 11-1 Basic Interval Timer Interrupt Time fMAIN : main clock frequency (ex: 4.19MHz) fSUB: sub clock frequency (ex: 32.768kHz) 38 MAR. 1999 Ver 1.01 GMS81C3004 CKCTLR 7 - 6 - 5 - 4 - 3 BTCL 2 1 BITCK 0 ADDRESS: 0F9H INITIAL VALUE: ----0111 Basic Interval Timer source clock select 000: f M/2 3 or fS/23 001: f M/2 4 or fS/24 f M: main-clock frequency 010: f M/2 5 or fS/25 011: f M/2 6 or fS/26 fS: sub-clock frequency 100: f M/2 7 or fS/27 101: f M/2 8 or fS/28 110: f M/2 9 or fS/29 111: f M/2 10 or fS/210 Clear bit 0: Normal operation (free-run) 1: Clear 8-bit counter (BITR) to "0". This bit becomes 0 automatically after one machine cycle. Caution: Both register are in same address, when write, to be a CKCTLR, when read, to be a BITR. 7 6 5 4 3 2 1 0 BITR 8-BIT BINARY COUNTER ADDRESS: 0F9H INITIAL VALUE: 00000000 Figure 11-2 BITR: Basic Interval Timer Mode Register 11.2 Timer/Event Counter 1 Timer/Event Counter 1 consists of prescaler, multiplexer, 8-bit compare data register, 8-bit count register, Control register, and Comparator as shown in Figure 11-3 . The timer/counter 1 has two operating modes. One is the timer mode which is operated by internal clock, other is event counter mode which is operated by external clock [0FAH] from pin EC1. The contents of TDR1 are compared with the contents of up-counter T1. If a match is found, a timer/counter 1 interrupt (T1IF) is generated, and the counter is cleared. Counting up is resumed after the counter is cleared. SCMR[1:0] MPX same address 8-bit Timer 1 compare data register PRESCALER [0E5 H] XIN PIN SX IN PIN EC1 PIN 0X 1X TDR1 Comparator Timer 1 Interrupt Match /2 /8 /32 /128 /512 MUX source clock T1 8-bit up-counter Clear T1ST 3 T1CK Select Input clock [0E4 H] T1CN [0E5H] TM1 Timer/Counter 1 control register Caution: Both register are in same address, when write, to be a TDR1, when read, to be a T1. Figure 11-3 Block Diagram of Timer/Event Counter MAR. 1999 Ver 1.01 39 GMS81C3004 Note: The content of TDR1 must be initialized (by software) with the value between 1H and 0FFH,not to 0. R/W 4 R/W 3 R/W 2 R/W 1 T1CKS R/W 0 TM1 7 - 6 - 5 - T1ST T1CN ADDRESS: E4 H INITIAL VALUE:---0 0000 Timer/Counter 1 source clock select 000: EC1 (External clock from EC1 pin) 001: /2 010: /8 011: /32 100: /128 101: /512 110: reserved 111: reserved Timer/Counter 1 enable flag 0: Disable count 1: Enable count Timer/Counter 1 start/stop control flag 0: stop count 1: clearing the T1 counter and start count again Reserved TDR1 or T1 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 KDTR ADDRESS: E5H INITIAL VALUE: Undefined STATUS When read When write SYMBOL T1 TDR1 DESCRIPTION 8-bit Timer count register 8-bit comparing data register Figure 11-4 Timer Mode Register and TDR1, T1 Registers Timer Mode In the timer mode, the internal clock is used for counting up. Thus, you can think of it as counting internal clock input. The contents of TDR1 are compared with the contents of up-counter, T1. If match is found, a timer 1 interrupt Start count (T1IF) is generated and the up-counter is cleared to 0. Counting up is resumed after the up-counter is cleared. As the value of TDR1 is changeable by software, time interval is set as you want Source clock ~ ~ ~~ ~~ n-2 n-1 n 0 1 3 4 Up-counter 0 1 2 3 2 ~~ ~~ TDR1 T1IF interrupt n Match Detect Counter Clear Figure 11-5 Timer Mode Timing Chart ~ ~ 40 MAR. 1999 Ver 1.01 GMS81C3004 Clock Source Value of TM[2:0] 000 001 010 011 100 101 110 111 S C M R[1:0]= 00 or 01 fEC1 fM/2 fM/23 fM/25 fM/27 fM/29 Invalid Invalid S CM R [1:0]= 10 or 11 fEC1 fS/2 fS/23 fS/25 fS/27 fS/29 - Resolution A t f MAIN=4.19M Hz 1/fEC1 s 0.476 us 1.907 us 7.629 us 30.517 us 122.070 us A t f SUB = 32.768kH z 1/fEC1 s 61.03 us 244.14 us 976.56 us 3906.25 us 15625.00 us - Maximum Time Setting A t f MAIN = 4.19M H z 1/fEC1 x 256 s 122.1 us 488.3 us 1953.1 us 7812.5 us 31250.0 us A t fSUB = 32.768kH z 1/fEC1 x 256 s 15.6 ms 62.5 ms 250.0 ms 1000.0 ms 4000.0 ms - Table 11-2 Timer/Counter 1 Source clock Interrupt Time fM : main-clock frequency, fS: sub-clock frequency, fEC1: external event from EC1 pin frequency Event counter Mode In this mode, counting up is started by an external trigger. This trigger means falling edge of the EC1 pin input. Source clock is used as an internal clock selected with TM1. The contents of TDR1 are compared with the contents of the up-counter. If a match is found, an T1IF interrupt is generated, and the counter is cleared to "0". The counter is restarted by the falling edge of the EC1 pin input. The maximum frequency applied to the EC1 pin is fMAIN/ 2 [Hz] in main clock mode, and fSUB/2[Hz] is sub clock mode. In order to use event counter function, the bit EC1S of the Port Mode Register PMR0(address 0D9H) is required to be set to "1". After reset, the value of TDR1 is undefined, it should be initialized to between 1H~FFH not to "0" Start count EC1 pin input ~ ~ ~~ ~~ Up-counter 0 1 2 n-1 n 0 1 2 ~~ ~~ TDR1 T1IF interrupt n Figure 11-6 Event Counter Mode Timing Chart ~ ~ Example: Every 1ms interrupt request flag is generated at 4MHz : LDM LDM LDM SET1 EI PCOR,#1 TM1,#1BH TDR1,#125 T1E ; Enable Peri. Clock ; divide by 8 ; 8us x 125= 1ms ; Enable Timer 1 Int. ; Enable Master Int. The interval period of Timer is calculated as below equation. 1Period = --------- x Prescaler ratio x TDR f XIN MAR. 1999 Ver 1.01 41 GMS81C3004 TDR1 TDR1=n n n-1 n-2 PCP ~ ~ up -c ou nt ~ ~ 8 7 6 ~ ~ 2 1 0 5 4 3 TIME Interrupt period = PCP x n Timer 1 (T1IF) Interrupt Occur interrupt Occur interrupt Occur interrupt Figure 11-7 Count Example of Timer / Event counter TDR1 disable enable clear & start stop up -c ou nt ~ ~ ~ ~ TIME Timer 1 (T1IF) Interrupt Occur interrupt Occur interrupt T1ST Start & Stop T1CN Control count T1ST = 0 T1ST = 1 T1CN = 1 T1CN = 0 Figure 11-8 Count Operation of Timer / Event counter 42 MAR. 1999 Ver 1.01 GMS81C3004 11.3 Watch Timer The watch timer consists of the clock selector, 14-bit binary counter and Watch timer mode register. It is a multi-purpose timer. It is generally used for watch design. Since Sub-frequency keeps running in spite of Stop mode, Watch Timer continues its operation. Bit 3 of WTMR enables or stops counter, and bit 2 and bit 1 determine the clock source between main or sub frequency. Because in Stop Mode, main-frequency clock stops, clock source should be sub-frequency clock. In case that circuit uses 4.19MHz and Sub-frequency is 32.768kHz, bit 0 of WTMR may choose either 2Hz or 256Hz. Watch Timer Mode Register W WTMR - ADDRESS : 0F0 H RESET VALUE : ----0000 W W W Reserved Interrupt interval 0: /26 (2 Hz) 1: /214 (256 Hz) Source clock selection 00: fSUB (sub clock) 01: fMAIN /128 (main clock) 10: inhibit 11: inhibit Watch Timer control bit 0: Disable (count stop) 1: Enable Figure 11-9 Watch Timer Mode Register MUX fSUB fMAIN/2 7 00 01 14 BIT COUNTER Key Scan & LCD clock source /26 select source clock 2 select MUX /214 Watch Timer Interrupt EXAMPLE: WHEN f SUB = 32.768 kHz AND f MAIN=4.19 MHz, INTERVAL OF TIMER = 2Hz OR 256Hz WTMR [0F0H] Figure 11-10 Watch Timer Block Diagram Usage of Watch Timer in STOP mode When system is off and watch should keep working, follow the steps below. 1. It determines the mode to perform between main mode and sub mode when released from Stop mode. and is set to Sub-frequency operation mode. 2. Enters in STOP mode. 3. After released by 0.5 second watch timer interrupt, count up 1 second and refreshes LCD Display. When the performing count up and refresh the LCD, the CPU operates either in main frequency mode or sub frequency mode. 4. Enters in STOP mode again. 5. Repeats 3 and 4. As mentioned above, by releasing every 0.5 sec., power consumption can be reduced consideravably. MAR. 1999 Ver 1.01 43 GMS81C3004 12. COMPARATOR The A/D comparator circuit is shown in Figure 12-1 . The A/D comparator circuit consists of the switch tree, ladder resistor, comparator and control register CMR, CSR (address 0ECH, 0EDH). The CSR register select normal port or analog input. The bit 7 of CSR has 1's written to them, port can be configured as comparator ports, and in that state can be used as analog input. The lower 2 bits of CMR control which port applied into comparator input. As analog inputs, unselected port can be used digital input (normal input) as shown in Table 12-2. Comparator Channel Selection Register [0EDH] CSR Comparator Mode Register [0ECH] voltage select CMR 5-bit DAC VDD port select channel select DAC MUX 5 enable enable result R14/CMP0 R15/CMP1 R16/CMP2 R17/CMP3 CIN0 digital or analog select CIN1 CIN2 CIN3 reference voltage - + OUTPUT LATCH Comparator Figure 12-1 Block Diagram of Comparator circuit Control The comparator module has four analog inputs for the GMS81C3004. The Comparator Register, that is the comparator register CMR and CSR are shown in Figure 12-2 . Lower 5 bits of CMR can select voltage as 1/64 VDD step internal reference voltage, based on the setting of bits 0 to bit 5. The comparator result between the analog input voltage and the internal reference voltage is stored in bit 6 of CMR. Bit 6 of CMR 0 1 Description input voltage < reference voltage input voltage > reference voltage struction, not bit manipulation. Example: : LDA BBC : : GOTO3: : : : CMR A.6,GOTO3 The CMR can be read or tested by byte manipulation in- 16 machine cycle (8s at 4MHz) is required for comparison the result of comparison is stored in the bit 6 of Comparator Mode Register CMR (address 0ECH). The bit 7 is comparator enable bit. When comparator is enabled, the current consumption of comparator is typically 0.95mA (to be defined after). 44 MAR. 1999 Ver 1.01 GMS81C3004 00000: VDD/64 00001: 3VDD/64 00010: 5VDD/64 00011: 7VDD/64 00100: 9VDD/64 00101: 11VDD/64 00110: 13VDD/64 00111: 15VDD/64 : : : : 11000: 49VDD/64 11001: 51VDD/64 11010: 53VDD/64 11011: 55VDD/64 11100: 57VDD/64 11101: 59VDD/64 11110: 61VDD/64 11111: 63VDD/64 Table 12-1 Setting the Reference voltage Comparator Mode Register W CMR R W W ADDRESS : 0EC H RESET VALUE : 00-00000 W W W Reference voltage selection See left Table. Reserved Conversion result store bit 0: input < reference 1: input > reference A/D comparator enable bit 0: Disable 1: Enable Comparator Selection Register W CSR MSB LSB Analog input selection 00: CIN0 01: CIN1 10: CIN2 11: CIN3 Port Selection 0: R14,R15,R16,R17 1: Comparator analog input ADDRESS : 0EDH RESET VALUE : 0-----00 W W Select analog input pin by using bit 1 and bit 0 of the Channel Selection Register CSR (address 0EDH). The port pins can be configured as analog inputs or as digital I/O by setting the CSR. Refer to Table 12-2. Figure 12-2 Comparator Registers CSR[7] 0 1 1 1 1 CSR[1:0] XX 00 01 10 11 CHANNEL CIN0 CIN1 CIN2 CIN3 R14,R15,R16,R17 R15,R16,R17 can be used as digital input R14,R16,R17 can be used as digital input R14,R15,R17 can be used as digital input R14,R15,R16 can be used as digital input Remarks Table 12-2 Pin Configuration of Analog input MAR. 1999 Ver 1.01 45 GMS81C3004 13. INTERRUPTS The GMS81C3004 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circuit, and Master enable flag ("I" flag of PSW). 9 interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 13-1 . Below table shows the Interrupt priority Reset/Interrupt Hardware Reset Basic Interval Timer External Interrupt 0 External Interrupt 1 Timer/Counter 1 External Interrupt 2 Watchdog Timer Watch Timer Key Scan interrupt Symbol RESET BIT INT0 INT1 Timer 1 INT2 WDT WT KS Priority 1 2 3 4 5 6 7 8 The External Interrupts INT0, INT1, INT2 each can be transition-activated (1-to-0 or 0-to-1 transition). The flags that actually generate these interrupts are bit INT0F, INT1F and INT2F in register IRQH. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. The Timer 1 Interrupts are generated by T1IF which is set by a match in their respective timer/counter register. The Basic Interval Timer Interrupt is generated by BITIF which is set by an overflow in the timer register. The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL), and the interrupt request flags (in IRQH and IRQL) except Power-on reset and software BRK interrupt. Internal bus line I-flag is in PSW, it is cleared by "DI", set by "EI" instruction. When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by "RETI" instruction, I-flag is set to "1" by hardware. [0DBH] IENH Interrupt Enable Register (Higher byte) IRQH [0DDH] BIT INT0 INT1 INT2 Timer 1 BITIF INT0F INT1IF INT2IF T1IF Release STOP Priority Control To CPU I Flag Interrupt Master Enable Flag Interrupt Vector Address Generator IRQL [0DCH] WDT WT KS WDTIF WTIF KSIF [0DAH] IENL Interrupt Enable Register (Lower byte) Internal bus line Figure 13-1 Block Diagram of Interrupt 46 MAR. 1999 Ver 1.01 GMS81C3004 Interrupt enable registers are shown in Figure 13-3 . These registers are composed of interrupt enable flags of each interrupt source and these flags determines whether an interrupt will be accepted or not. When enable flag is "0", a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once. R/W R/W T1IF - R/W R/W R/W LSB IRQH MSB - - INT2IF INT1IF INT0IF BITIF ADDRESS: 0DDH INITIAL VALUE: --00 -000 Basic Interval Timer interrupt request flag External interrupt 0 request flag External interrupt 1 request flag Timer/Counter 1 interrupt request flag External interrupt 2 request flag R/W R/W WTIF - R/W WDTIF IRQL MSB - - KSIF ADDRESS: 0DCH INITIAL VALUE: --00 ---0 Watchdog timer interrupt request flag Watch Timer interrupt request flag Key scan interrupt request flag LSB Figure 13-2 Interrupt Request Flag R/W R/W - R/W R/W R/W LSB IENH MSB - - INT2EN T1EN IN T1EN INT0EN BITEN ADDRESS: 0DBH INITIAL VALUE: --00 -000 Basic Interval Timer interrupt enable flag External interrupt 0 enable flag External interrupt 1 enable flag Timer/Counter 2 Interrupt enable flag External interrupt 2 enable flag VALUE 0: Disable 1: Enable R/W R/W - R/W W D TEN IENL MSB - - KSEN WTEN ADDRESS: 0DAH INITIAL VALUE: --00 ---0 Watchdog Timer interrupt enable flag Watch Timer Interrupt enable flag Key Scan Interrupt enable flag LSB Figure 13-3 Interrupt Enable Flag MAR. 1999 Ver 1.01 47 GMS81C3004 13.1 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an instruction. Interrupt acceptance sequence requires 8 fOSC (2 s at fMAIN=4.19MHz) after the completion of the current instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruction [RETI]. Interrupt acceptance 1. The interrupt master enable flag (I-flag) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. Interrupt request flag for the interrupt source accepted is cleared to "0". 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the interrupt service program is executed. System clock Instruction Fetch Address Bus PC SP SP-1 SP-2 V.L. V.H. New PC Data Bus Internal Read Internal Write Not used PCH PCL PSW V.L. ADL ADH OP code Interrupt Processing Step V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents. Interrupt Service Task Figure 13-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction Basic Interval Timer Vector Table Address Entry Address When nested interrupt service is required, the I-flag should be set to "1" by "EI" instruction in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. 0FFE6 H 0FFE7H 012 H 0E3H 0E312 H 0E313H 0EH 2EH Saving/Restoring General-purpose Register Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program. A interrupt request is not accepted until the I-flag is set to "1" even if a requested interrupt has higher priority than that of the current interrupt being serviced. During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. These registers are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory 48 MAR. 1999 Ver 1.01 GMS81C3004 area for saving registers. The following method is used to save/restore the generalpurpose registers. Example: Register save using push and pop instructions INTxx: PUSH PUSH LDA PUSH A X RPR A ;SAVE ACC. ;SAVE X REG. ;SAVE RPR 13.2 BRK Interrupt Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 13-5 . interrupt processing POP STA POP POP RETI A PRP X A ;RESTORE RPR ;RESTORE X REG. ;RESTORE ACC. ;RETURN BRK or TCALL0 B-FLAG =1 BRK INTERRUPT ROUTINE RETI =0 General-purpose register save/restore using push and pop instructions; TCALL0 ROUTINE RET main task acceptance of interrupt interrupt service task saving registers Figure 13-5 Execution of BRK/TCALL0 restoring registers interrupt return MAR. 1999 Ver 1.01 49 GMS81C3004 13.3 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time simultaneously, an internal polling sequence determines by hardware which request is serviced. However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But as user sets I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. Main Program service Example: Even though Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend. TIMER 1 service INT0 service enable INT0 disable other EI Occur TIMER1 interrupt Occur INT0 TIMER1: PUSH PUSH PUSH LDM LDM EI : : : : : : LDM LDM POP POP POP RETI A X Y IENH,#2 IENL,#0 ;Enable INT0 only ;Disable other ;Enable Interrupt enable INT0 enable other IENH,#37H IENL,#31H Y X A ;Enable all interrupts In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable "EI" in the TIMER1 routine. Figure 13-6 Execution of Multi Interrupt 50 MAR. 1999 Ver 1.01 GMS81C3004 13.4 External Interrupt The external interrupt on INT0, INT1 and INT2 pins are edge triggered depending on the edge selection register IESR (address 0D8H) as shown in Figure 13-7 . The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. INT0, INT1 and INT2 are multiplexed with general I/O ports (R10~R12). To use external interrupt pin, the bit of R0 port mode register PMR0 should be set to "1" correspondingly. Port Mode Register 0 PMR0 INT0 pin INT0IF INT0 INTERRUPT 0: R00 1: INT0 0: R01 1: INT1 0: R02 1: INT2 INT1 INTERRUPT 0: R03 1: EC1 ADDRESS : 0D9H RESET VALUE : ----0000 INT1 pin edge selection INT1IF INT2 pin INT2IF INT2 INTERRUPT Figure 13-9 PMR0: R0 Port Mode Register IESR [0DCH] Example: To use as an INT0 and INT2 : : ;**** Set port as an input port R00,R02 LDM R0DD,#1111_1010B ; ;**** Set port as an interrupt port LDM PMR0,#05H ; ;**** Set Falling-edge Detection LDM IESR,#0001_0001B : : : Figure 13-7 External Interrupt Block Diagram Ext. Interrupt Edge Selection Register W W IESR ADDRESS : 0D8H RESET VALUE : --000000 W W W W INT0 edge select 00: Int. disable 01: falling 10: rising 11: both INT1 edge select 00: Int. disable 01: falling 10: rising 11: both INT2 edge select 00: Int. disable 01: falling 10: rising 11: both Response Time The INT0, INT1 and INT2 edge are latched into INT1IF, INT1IF and INT2IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The DIV itself takes twelve cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. Figure 13-8 External Interrupt Edge Selection Register MAR. 1999 Ver 1.01 51 GMS81C3004 shows interrupt response timings. max. 12 fOSC 8 fOSC Interrupt Interrupt goes latched active Interrupt processing Interrupt routine Figure 13-10 Interrupt Response Timing Diagram 52 MAR. 1999 Ver 1.01 GMS81C3004 14. KEY SCAN The key-scan block consists of Port selection Multiplexer, Interrupt controller, 4-bit binary counter and Key scan control register, and Key data register. When the key scan interrupt is used, key scan register KSCR (address 0F4H) should be set properly as shown in Figure 14-2 . Key Scan matrix is configured by 8 inputs (KS0~KS7) and 16 pins strobe signal output SEG30 SEG28 SEG16 SEG17 SEG29 SEG31 16 outputs (SEG16~SEG31). Number of key inputs are defined by the key scan control register (KSCR[6:5]). Output signal that are strobe are fixed as SEG16 to SEG31. If key scan is detected at any one or more of these pins, the KSIF request flag is set to "1". This generates an interrupt request. It also can be used in the way of release from STOP mode. KSCR[3:0] KSCR[4] 4 count value overflow 00 WTMR[2:1] strobe out controller f SUB fMAIN/27 4 bit Counter 01 Key Input Latch Port Selection R10/KS0 R11/KS1 8 pins data input R16/KS6 R17/KS7 overflow MUX "1" "0" Key Scan Interrupt KSIF select interrupt key input detect Selection 2 Port KSCR[6:5] 8 key input data KDTR[7:0] KSCR[7] Figure 14-1 Key Scan Interrupt Block Diagram Strobe output signals are generated according to 4-bit count value. The relation between Key scan register value and strobe signal is shown as below table. Counter value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Strobe Pin SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 Once key scan interrupt occurs, key scan interrupt is disabled. To accept next interrupt, the KDTR has to be read by software. Otherwise, key-scan is not enabled. At every 8th clock, one strobe output is generated. There are 16 pins in all, therefore total key scan time is 3900s (244s x 16) Refer to Figure 14-3 . Example: The registers should be defined properly to use key scan input function. : : LDM LDM LDM EI : : PUR1,#0 ;For disabling pull-ups KSCR,#0E0H ;For using 8 inputs IENL,#20H ;Enable Keyscan Note: When R1 is used as key scan port, there should be no pull-up. PUR1 should be written to '0' in order not to operate pull-up. Otherwise, VCLn voltage is changed and may occur flicker in LCD panel display. MAR. 1999 Ver 1.01 53 GMS81C3004 Usage of Key Scan 1. Clear bit 7 of the KSCR, interrupt activate on Key Scan. 2. Specify bit 5 and bit 6 of the KSCR properly by selecting what port you want as key scan input. 3. Enable key scan interrupt. 4. When interrupt occurs, store the 4-bit counter value (lower 4-bit of KSCR) and key input data (KDTR) into user RAM area. 5. When the next interrupt occurs, compare the 4-bit counter values of KSCR and KDTR with RAM value stored before MSB R/W 6. In case that these 2 values are not equal If KDTR value is different, it means 2 keys are pressed successively. And if KSCR value is different, it means more than 2 keys are pressed simultaneously. In case that these 2 values are equal; If the number of bit `0' in KSCR values is over 2, more than 2keys are pressed. And if the number of bit "0" is one, it indicates the key input pin of bit "0"and seg pin number of strobe point as Counter Value. Therefore, it is possible to distinguish which key is pressed. R/W R/W R KOV R R R LSB R KSCR INSL KPS KSCNT ADDRESS: 0F4H INITIAL VALUE: 0000 0000 4-bit binary counter value Counter Overflow Flag Port Selection 00: R10~R17 (Key Scan Disable, No strobe output) 01: R14~R17, KS0~KS3 10: R10~R13, KS4~KS7 11: KS0~KS7 Interrupt source selection 0: Interrupt occurs by Key-scan input only. 1: Interrupt occurs by either Keyscan input or Counter overflow. MSB R LSB R R R R KDTR R R R KDTR ADDRESS: 0F5H INITIAL VALUE: 0000 0000 Figure 14-2 Key Scan Registers 30.5s CLOCK SOURCE 244.0s KEY SCAN CLOCK 228.75s 15.25s STROBE OUTPUT 15.27s KEY SCAN (INPUT LATCH) 20ns Figure 14-3 Key Scan Timing 54 MAR. 1999 Ver 1.01 GMS81C3004 15. LCD DRIVER The GMS81C3004 has the circuit that directly drives the liquid crystal display (LCD) and its control circuit. The GMS81C3004 has the following pins connected with LCD. Segment output port 40 pins (SEG0-SEG39) Common output port 8 pins (COM0-COM7) In addition, VCLn pin is provided as the drive power pin. The devices that can be directly driven are shown below. 1/8 duty (1/4 Bias) LCD............Max. 320 Segment By short between pin VCL2 and VCL3, 1/4 bias is used in GMS81C3004. 15.1 Configuration of LCD driver Figure 15-1 shows the configuration of the LCD driver. R4 or Segment Select SEG or Normal port by LPMR [0F3H] SEG0/R40 SEG7/R47 LPMR[1:0] Display Data Select Control Display Data Buffer register Display Memory (40 bytes) SEG8/R50 "Same with above" Segment Driver LPMR[3:2] "Same with above" SEG15/R57 SEG16/R60 WTMR[2:1] INTERNAL BUS LINE 00 01 LPMR[5:4] fSUB fMAIN/2 "Same with above" 7 SEG23/R67 SEG24/R70 MUX LCD Timing Control /8 Prescaler / 16 / 32 / 64 Select clock MUX clock LPMR[7:6] SEG31/R77 LCDCK SEG32 LCDEN 1 0 R06 Power & Bias control SEG39 Select port R06/LCDCK LCR [0F1H] 3 Enable LCD Bias control Common Driver VCL1 VCL5 COM0 Figure 15-1 LCD Driver Block Diagram MAR. 1999 Ver 1.01 COM7 55 GMS81C3004 15.2 Control of LCD Driver Circuit The LCD driver is controlled by the LCD control register, LCR. Further, when the LCD is accessed, the most significant bit of the LCR must be cleared to "0" (Blanking). R/W 7 6 - R/W 5 R/W 4 3 - R/W 2 R/W 1 R/W 0 ADDRESS: 0F1H INITIAL VALUE:0-00 -000 LCR LCDEN Reserved Note Clock source selection 00: f SUB / 64 01: f SUB / 32 10: f SUB / 16 11: f SUB / 8 LCD clock output 0: R06 port 1: LCD clock output Bias resistor control 0: Use internal resistor 1: Use external resistor Bias transistor control 0: off 1: on LCD display control 0: Disable (LCD blanking) 1: Enable LCD display (Blanking is released) NOTE: Bit 6 is fixed to `0' in GMS81C3004. In the Emulator if it is written to "1", then it operates as 16-common operation mode with COM0~COM15 Figure 15-2 LCD Control Register Selecting Frame Frequency Frame frequency is set to the base frequency as shown in the following Table 15-1. LCR[1:0] 00 01 10 11 LCD clock fSUB / 64 fSUB / 32 fSUB / 16 fSUB / 8 Frame Frequency (Hz) (When fSUB = 32.768 kHz) 64 128 256 512 The LCR[1:0] determines the frequency of COM signal scanning of each segment output. This is also referred to as the LCD clock signal pin, LCDCK. Since LCDCK is generated by dividing the watch timer clock(fW), the watch timer must be enabled when the LCD display is turned on. RESET clears the LCD control register LCR values to logic zero. When Bit 2 of LCR is `1', this clock outputs to R06 pin The LCD display can continue to operate during SLEEP and STOP modes if a sub-frequency clock is used as system clock source. Table 15-1 Setting of LCD Frame Frequency one frame 56 MAR. 1999 Ver 1.01 GMS81C3004 Display On/Off Blanking is applied by setting LCDEN (bit 7 of LCR) to "0" and turns off the LCD by outputting the non light op- eration level to the COM pin. When setting Frame frequency or changing operating mode, LCD display should be off before operation, to prevent display flickering. 15.3 Bias Resistor To operate LCD, built-in Bias resistor dividing VDD to VSS section into several stages generates necessary voltage. Bit 5 of LCR switches Transistor supplying voltage to serially connected Bias resistor. If it is '1', it turns on, and if it is `0', it turns off. When the system needs adjusting the contrast of LCD, the bit 5 of LCR should be clear to "0" always. Then power is supplied through the external resistor as shown in Figure 15-3 . Note: Since the GMS81C3004 using 1/8 duty, so recommend to use 1/4 Bias. To use 1/4 Bias, VCL 2 pin and VCL 3 pin should be shorted externally as shown in Figure 15-3 (a). Furthermore, in case that user wants to use the specific voltage instead of voltage of internal Bias resistor, external Bias resistor can be used as shown in Figure 15-3 (b). To use external Bias resistor, Bit 4 and Bit 5 of LCR should be set. MCU Internal LCDEN LCR.4 VDD MCU Internal LCDEN LCR.4 VDD VDD VCL1 VCL1 LCR.5 = "0" LCR.5 = "0" VCL2 VCL2 VCL3 Two pins are connected each other VCL3 VCL4 VCL4 VCL5 LCDEN LCR.5 VSS When LCD turns on, output "Low" When LCD turns off, output "High" R Port When LCD turns on, output "Low" When LCD turns off, output "High" Adjust Contrast LCDEN LCR.5 VSS VCL5 Adjust Contrast R Port (a) Internal Bias Resistors (b) External Bias Resistors Figure 15-3 Application Example of Adjusting the Contrast MAR. 1999 Ver 1.01 External Bias resistors LCR.4 = "0" Internal Bias resistors LCR.4 = "1" 57 GMS81C3004 MCU Internal LCDEN LCR.4 VDD MCU Internal LCDEN LCR.4 VDD VDD VCL1 VCL1 LCR.5 = "1" LCR.5 = "1" VCL2 VCL2 VCL3 Two pins are connected each other VCL3 VCL4 VCL4 VCL5 LCDEN LCR.5 VSS When LCD turns on, "LCR.5=1" When LCD turns off, "LCR.5=0" When LCD turns on, "LCR.5=1" When LCD turns off, "LCR.5=0" LCDEN LCR.5 VSS VCL5 (a) Internal Bias Resistors (b) External Bias Resistors Figure 15-4 Application Example for No Adjusting of Contrast 58 MAR. 1999 Ver 1.01 External Bias resistors LCR.4 = "0" Internal Bias resistors LCR.4 = "1" GMS81C3004 15.4 LCD Display Memory Display data are stored to the display data area (page 12) in the data memory. The display data stored to the display data area (address 0C00H-0C47H) are read automatically and sent to the LCD driver by the hardware. The LCD driver generates the segment signals and common signals in accordance with the display data and drive method. SEG39 SEG38 SEG37 0C40 0C41 0C42 0C43 0C44 0C45 0C46 0C36 0C26 0C16 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 0C30 0C31 0C32 0C33 0C34 0C35 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 0C20 0C21 0C22 0C23 0C24 0C25 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 0C10 0C11 0C12 0C13 0C14 0C15 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 0C00 0C01 0C02 0C03 0C04 0C05 0C06 SEG4 SEG3 SEG2 SEG1 SEG0 0C07 COM7 7 COM0 COM1 COM2 COM3 COM4 COM5 0C17 Bit 0 1 2 3 4 5 6 0C27 0C37 0C47 Figure 15-5 LCD Display Memory MAR. 1999 Ver 1.01 COM6 59 GMS81C3004 Therefore, display patterns can be changed by only overwriting the contents of the display data area with a program. The table look up instruction is mainly used for this overwriting. Figure 15-5 shows the correspondence between the display data area and the SEG/COM pins. The LCD lights when the display data is "1" and turn off when "0". LCD display memory in this location that are not used for LCD display can be allocated for general purpose use. 15.5 LCD Port Selection Segment pins are also used for normal I/O pins. The LCD port selection register LPMR is used to set Rn pin for ordiR/W R/W 7 6 R7LPMR R/W R/W 5 4 R6LPMR R/W R/W 3 2 R5LPMR nary digital input. LPMR R/W R/W 1 0 R4LPMR ADDRESS: 0F3H INITIAL VALUE:0000 0000 R4 port selection 00:SEG0~SEG7 01:SEG4~SEG7,R40~R43 10:SEG0~SEG3,R44~R47 11:R40~R47 R5 port selection 00:SEG8~SEG15 01:SEG12~SEG15,R50~R53 10:SEG8~SEG11,R54~R57 11:R50~R57 R6 port selection 00:SEG16~SEG23 01:SEG20~SEG23,R60~R63 10:SEG16~SEG19,R64~R67 11:R60~R67 R7 port selection 00:SEG24~SEG31 01:SEG28~SEG31,R70~R73 10:SEG24~SEG27,R74~R77 11:R70~R77 Figure 15-6 LCD Port Selection Register 15.6 Control Method of LCD Driver Initial Setting Flow chart of initial setting is shown in Figure 15-7 . Example: Driving of LCD Select Frame Frequency LDM : SETG LDM LCR,#23H RPR,#12 #0 #0 {X}+ #048H C_LCD1 RPR,#00 LCR.7 ;fF=512Hz (f SUB= 32.768kHz) ;Select LCD Memory ;area (Bank C) ;RAM Clear ;(0C00H->0C47H) Clear LCD Display Memory LDX C_LCD1: LDA STA CMPX BNE CLRG LDM : SET1B : : ;Bank=0 ;Enable display Turn on LCD 60 MAR. 1999 Ver 1.01 GMS81C3004 . SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG5 Setting of LCD drive method Data 0FH 11H 11H 0FH 05H 09H 11H 00H Address 0C0H 0C1H 0C2H 0C3H 0C4H 0C5H 0C6H 0C7H COM0 COM1 COM2 1 1 1 1 1 1 1 0 bit 0 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 7 00 00 1 0 0 0 0 1 1 0 0 0 Initialize of display memory COM3 COM4 COM5 Enable display (Release of blanking) COM6 COM7 Figure 15-7 Initial Setting of LCD Driver Figure 15-8 Example of Connection COM & SEG Display Data Normally, display data are kept permanently in the program memory and then stored at the display data area by the table look-up instruction. This can be explained using 5x7 dot matrix character display with 1/8 duty LCD as an : : SETG LDM LDX LDY LDA STA INC CMPY BNE CLRG : : example as well as any LCD panel. The COM and SEG connections to the LCD and display data are the same as those shown is Figure 15-8 . Programming example for displaying character is shown below. Write into the LCD Memory LP: RPR,#12 #0 #0 !DTBL+Y {X}+ Y #8 LP ;Set G-flag ;Select Bank C to access LCD ;Load font data ;Clear G-flag Font data DTBL: DB DB 0FH,11H,11H,0FH 05H,09H,11H,00H MAR. 1999 Ver 1.01 61 GMS81C3004 15.7 LCD Waveform 0 FRAME 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 One Frame VDD VCL1 VCL2=VCL3 VCL4 VCL5 VDD VCL1 VCL2=VCL3 VCL4 VCL5 VDD VCL1 VCL2=VCL3 VCL4 VCL5 VDD VCL1 VCL2=VCL3 VCL4 VCL5 1/8 Duty, 1/4 Bias Drive In this case, VCL2 and VCL3 pins are shorted each other (VCL2=VCL3) to use as 1/4 bias. COM0 COM1 COM2 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG1 SEG2 SEG3 SEG4 COM3 SEG0 VDD VCL1 VCL2=VCL3 VCL4 VCL5 VDD VCL1 VCL2=VCL3 VCL4 VCL5 VDD VCL1 VCL2=VCL3 VCL4 VCL5 SEG1 SEG2 SEG0 - COM0 VDD VCL1 VCL2=VCL3 VCL4 0 -VCL4 -VCL2=VCL3 -VCL1 -VDD Figure 15-9 Example of LCD drive output 62 MAR. 1999 Ver 1.01 GMS81C3004 0 FRAME 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 One Frame VDD VCL1 VCL2=VCL3 VCL4 VCL5 VDD VCL1 VCL2=VCL3 VCL4 VCL5 VDD VCL1 VCL2=VCL3 VCL4 VCL5 VDD VCL1 VCL2=VCL3 VCL4 VCL5 1/8 Duty, 1/4 Bias Drive In this case, VCL2 and VCL3 pins are shorted each other (VCL2=VCL3) to use as 1/4 bias. COM0 COM1 COM2 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG1 SEG2 SEG3 SEG4 COM3 SEG0 VDD VCL1 VCL2=VCL3 VCL4 VCL5 VDD VCL1 VCL2=VCL3 VCL4 VCL5 VDD VCL1 VCL2=VCL3 VCL4 VCL5 SEG1 SEG2 SEG0 - COM0 VDD VCL1 VCL2=VCL3 VCL4 0 -VCL4 -VCL2=VCL3 -VCL1 -VDD Figure 15-10 Example of LCD drive output MAR. 1999 Ver 1.01 63 GMS81C3004 16. WATCHDOG TIMER The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset CPU or a interrupt request. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. 6-bit up-counter Clock source (BIT overflow) WDT clear clear comparator WDTIF Watchdog Timer interrupt 6-bit compare data clear to reset CPU enable 5 WDTCL WDTR[5:0] WDTON WDTR [0DFH] Watchdog Timer Register Figure 16-1 Block Diagram of Watchdog Timer Watchdog Timer Control Figure 16-2 shows the watchdog timer control register. The watchdog timer is automatically disabled after reset. The CPU malfunction is detected during setting of the detection time, selecting of output, and clearing of the binary counter. Clearing the binary counter is repeated within the detection time. If the malfunction occurs for any cause, the watchdog timW W 7 6 WDTON WDTCL W 5 W 4 W 3 W 2 er output will become active at the rising overflow from the binary counters unless the binary counter is cleared. At this time, when WDTON=1, a reset is generated, which drives the RESET pin to low to reset the internal hardware. When WDTON=0, a watchdog timer interrupt (WDTIF) is generated. The watchdog timer temporarily stops counting in the STOP mode, and when the STOP mode is released, it automatically restarts (continues counting). W 1 W 0 WDTR ADDRESS: 0DFH INITIAL VALUE:0011 1111 6-bit compare data Clear count flag 0: Free-run count 1: When the WDTCL is set to ""1", binary counter is cleared to "0". And the WDTCL becomes "0" automatically after one machine cycle. Counter count up again. WDT enable flag 0: 6-bit Timer 1: Watchdog timer on Figure 16-2 WDTR: Watchdog Timer Data Register 64 MAR. 1999 Ver 1.01 GMS81C3004 Example: Sets the watchdog timer detection time to 0.5 sec at 4.19MHz LDM LDM LDM : : : : LDM : : : : LDM CKCTLR,#0EH WDTR,#0CFH WDTR,#0CFH ;Select 1/512 clock source ;WDTON 1, Clear Counter ;Clear counter Within WDT detection time WDTR,#0CFH ;Clear counter Within WDT detection time WDTR,#0CFH ;Clear counter Enable and Disable Watchdog Watchdog timer is enabled by setting WDTON (bit 7 in WDTR) to "1". WDTON is initialized to "0" during reset and it should be set to "1" to operate after reset is released. Example: Enables watchdog timer reset : LDM : : WDTR,#0FFH ;WDTON 1 Watchdog Timer Interrupt The watchdog timer can be also used as a simple 6-bit timer by clearing bit 7 of WDTR to "0". The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is shown as below. T = WDTR x Interval of BIT The watchdog timer is disabled by clearing bit 7 (WDTON) of WDTR. The watchdog timer is halted in STOP mode and restarts automatically after STOP mode is released. The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source. Example: 6-bit timer interrupt set up. LDX TXSP LDM : : #03FH WDTR,#3FH ;SP 3F ;WDTON 0 ;WDTCL 0 Source clock BIT overflow Binary-counter 1 2 3 0 1 2 3 0 Counter Clear WDTR WDTIF interrupt n 3 Match Detect WDTR "1100_0011" WDT reset reset Figure 16-3 Watchdog timer Timing If the watchdog timer output becomes active, a reset is generated, which drives the RESET pin low to reset the internal hardware. The main clock oscillator also turns on when a watchdog timer reset is generated in sub clock mode. MAR. 1999 Ver 1.01 65 GMS81C3004 17. BUZZER DRIVER The buzzer driver block consists of 6-bit binary counter, buzzer register, and clock source selector. It generates square-wave which has very wide range frequency (500Hz ~ 125kHz at fMAIN = 4MHz) by user software. A 50% duty pulse can be output to R13/BUZ pin to use for piezo-electric buzzer drive. The port mode register PMR1 (address 0F6H) should be set to "1", the R13 will be configured as BUZ pin regardless of port direction register R1DD. The frequency of output signal is controlled by the buzzer control register BUR. R13 port data SCMR[1:0] Multiplexer MPX XIN PIN SXIN PIN 0X 1X main or sub clock Prescaler /8 /16 /32 /64 6-bit binary Counter /2 F/F Comparator Compare data 2 6 BUR [0F7 H] Internal bus line PMR1 [0F6 H] 0 R13/BUZ PIN 1 Figure 17-1 Block Diagram of Buzzer Driver The bit 0 to bit 5 of BUR determine output frequency for buzzer driving. The 6-bit counter is cleared and starts the counting by writing signal at BUR register. It is incremental from 00H until it matches 6-bit BUR value. BUR is undefined after reset, so it must be initialized to between 1H and 3FH by software. fBUZ: BUZ pin frequency Prescaler ratio: Prescaler divide ratio by BUR[7:6] BUR value: 6-bit compare data, BUR[5:0] Note that BUR is a write-only register. Equation of frequency calculation is shown below. Oscillator frequency fBUZ ( Hz ) = ----------------------------------------------------------------------------------------------2 x Prescaler ratio x ( BUR value + 1 ) Port 1 Mode Register ADDRESS : 0F6H RESET VALUE : ---- ---0H R/W - Buzzer Register W W W W W ADDRESS : 0F7H RESET VALUE : 0FFH W W W PMR1 - - BUR Port select "0": R13 port "1": BUZ port Buzzer counter compare data Source clock select 00: /8 01: /16 10: /32 11: /64 Figure 17-2 PMR1 and Buzzer Register 66 MAR. 1999 Ver 1.01 GMS81C3004 When main-frequency is 4.194304MHz, buzzer frequency is shown as below and if sub-frequency is selected as clock BUR [5:0] 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Output frequency (kHz) /8 131.072 87.381 65.536 52.429 43.691 37.338 32.768 29.127 26.214 23.831 21.845 20.165 18.725 17.476 16.384 15.420 14.564 13.797 13.107 12.483 11.916 11.398 10.923 10.486 10.082 9.709 9.362 9.039 8.738 8.456 8.192 /16 65.536 43.691 32.768 26.214 21.845 18.725 16.384 14.564 13.107 11.916 10.923 10.082 9.362 8.738 8.192 7.710 7.282 6.899 6.554 6.242 5.958 5.699 5.461 5.243 5.041 4.855 4.681 4.520 4.369 4.228 4.096 /32 32.768 21.846 16.384 13.107 10.923 9.362 8.192 7.282 6.554 5.958 5.462 5.041 4.681 4.369 4.096 3.855 3.641 3.450 3.277 3.121 2.979 2.850 2.731 2.622 2.251 2.428 2.341 2.260 2.185 2.114 2.048 /64 16.384 10.923 8.192 6.554 5.462 4.682 4.096 3.641 3.277 2.979 2.731 2.521 2.341 2.185 2.048 1.928 1.821 1.725 1.639 1.561 1.490 1.425 1.366 1.311 1.261 1.214 1.171 1.130 1.093 1.057 1.024 source, buzzer frequency is used after dividing by 128. BUR [5:0] 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Output frequency (kHz) /8 7.944 7.710 7.490 7.282 7.085 6.899 6.722 6.554 6.394 6.242 6.096 5.958 5.825 5.699 5.578 5.461 5.350 5.243 5.140 5.041 4.946 4.855 4.766 4.681 4.599 4.520 4.443 4.369 4.297 4.228 4.161 4.069 /16 3.972 3.855 3.745 3.641 3.542 3.449 3.361 3.277 3.197 3.121 3.048 2.979 2.913 2.849 2.789 2.731 2.675 2.621 2.570 2.521 2.473 2.427 2.383 2.341 2.300 2.260 2.222 2.185 2.149 2.114 2.081 2.048 /32 1.986 1.928 1.873 1.821 1.771 1.725 1.681 1.639 1.599 1.561 1.524 1.490 1.457 1.425 1.395 1.366 1.338 1.311 1.285 1.261 1.237 1.214 1.192 1.171 1.150 1.130 1.111 1.093 1.075 1.057 1.041 1.024 /64 0.993 0.964 0.936 0.910 0.885 0.862 0.840 0.819 0.799 0.780 0.762 0.745 0.728 0.712 0.697 0.683 0.669 0.655 0.642 0.630 0.618 0.607 0.596 0.585 0.575 0.565 0.555 0.546 0.537 0.528 0.520 0.512 MAR. 1999 Ver 1.01 67 GMS81C3004 18. POWER DOWN OPERATION GMS81C3004 has 2 power-down mode. In power-down mode, power consumption is reduced considerably that in Battery operation Battery life can be extended a lot. Sleep mode is entered by setting bit 0 of Sleep Mode Register, and STOP Mode is entered by STOP instruction. 18.1 SLEEP Mode In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operate normally but CPU stops. Movement of all Peripherals is shown in Table 18-1. Sleep mode is entered by setting bit 0 of SMR (address 0DEH). It is released by RESET or interrupt. To be release by interrupt, interrupt should be enabled before Sleep mode. Sleep Mode Register SMR 0: Release Sleep Mode 1: Enter Sleep Mode ADDRESS : 0DEH RESET VALUE : -------0 Figure 18-1 SLEEP Mode Register Oscillator (XIN or SXIN pin) Internal CPU Clock ~ ~ ~ ~ Interrupt Set bit 0 of SMR Release Normal Operation Stand-by Mode Normal Operation Figure 18-2 Sleep Mode Release Timing by External Interrupt . Oscillator (XIN or SXIN pin) ~ ~ ~ ~ Internal CPU Clock ~ ~ ~~ ~~ RESET Set bit 0 of SMR Release ~~ ~~ ~~ ~~ BIT Counter 0 1 2 FE FF 0 1 2 Clear & Start Normal Operation Stand-by Mode t ST = 62.5ms Normal Operation at 4.19MHz by hardware tST = 1 fMAIN /1024 x 256 Figure 18-3 SLEEP Mode Release Timing by RESET pin 68 MAR. 1999 Ver 1.01 GMS81C3004 18.2 STOP Mode For applications where power consumption is a critical factor, device provides reduced power of STOP. Start The Stop Operation An instruction that STOP causes to be the last instruction is executed before going into the STOP mode. In the Stop Peripheral CPU RAM LCD driver Basic Interval Timer Timer/Event counter 1 Watch Timer Key Scan XIN PIN XOUT PIN Main-oscillation Sub-oscillation I/O ports Control Registers Release method STOP Mode All CPU operations are disabled Retain LCDdriver operates continuously Halted Halted (Only when the Event counter mode is enabled, Timer 1 operates normally) Watch Timer operates continuously Active LOW LOW Stop Oscillation Retain Retain by RESET, by Key Scan interrupt, Watch Timer interrupt, Timer interrupt (EC1), by External interrupt mode, the on-chip main-frequency oscillator is stopped. With the clock frozen, all functions are stopped, but the onchip RAM and Control registers are held. The port pins output the values held by their respective port data register, the port direction registers. The status of peripherals during Stop mode is shown below. Sleep Mode All CPU operations are disabled Retain LCD driver operates continuously BIT operates continuously Timer/Event counter 1 operates continuously Watch Timer operates continuously Active Oscillation Oscillation Oscillation Oscillation Retain Retain by RESET, All interrupts Table 18-1 Peripheral Operation during Power Down Mode : LDM STOP NOP NOP : Note: Since the XIN pin is connected internally to GND to avoid current leakage due to the crystal oscillator in STOP mode, do not use STOP instruction when an external clock is used as the main system clock. CKCTLR,#0000_1110B In the Stop mode of operation, VDD can be reduced to minimize power consumption. Be careful, however, that VDD is not reduced before the Stop mode is invoked, and that VDD is restored to its normal operating level before the Stop mode is terminated. The reset should not be activated before VDD is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. And after STOP instruction, at least two or more NOP instruction should be written as shown in example below. Example) The Interval Timer Register CKCTLR should be initialized (0FH or 0EH) by software in order that oscillation stabilization time should be longer than 20ms before STOP mode. Release the STOP mode The exit from STOP mode is using hardware reset or external interrupt, watch timer, key scan or timer/counter. To release STOP mode, corresponding interrupt should be enabled before STOP mode. Specially as a clock source of Timer/Event counter, EC1 pin can release it by Timer/Event counter Interrupt re- MAR. 1999 Ver 1.01 69 GMS81C3004 quest Reset redefines all the control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. Start-up is performed to acquire the time for stabilizing oscillation. During the start-up, the internal operations are all stopped. Oscillator (XIN pin) ~~ ~~ ~ ~ ~ ~ Internal Clock ~ ~ ~ ~ External Interrupt STOP Instruction Executed ~ ~ ~~ ~~ ~~ ~~ BIT Counter n n+1 n+2 n+3 0 Clear 1 FE FF 0 1 2 Normal Operation Stop Operation tST > 20ms by software Normal Operation Before executing Stop instruction, Basic Interval Timer must be set properly by software to get stabilization time which is longer than 20ms. Figure 18-4 STOP Mode Release Timing by External Interrupt Oscillator (XIN pin) ~~ ~~ ~ ~ Internal Clock ~ ~ ~ ~ ~ ~ RESET BIT Counter ~ ~ STOP Instruction Executed n n+1 n+2 n+2 n+3 ~~ ~~ Normal Operation Stop Operation tST > 62.5ms at 4.19MHz by hardware 1 fMAIN /1024 Figure 18-5 STOP Mode Release Timing by RESET ~~ ~~ 0 Clear 1 FE FF 0 1 2 Normal Operation tST = x 256 70 MAR. 1999 Ver 1.01 GMS81C3004 Minimizing Current Consumption The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. Note: In the STOP operation, the power dissipation associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD /VSS); however, when the input level becomes higher than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the highimpedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means. It should be set properly that current flow through port doesn't exist. First consider the setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn't flow. But input voltage level should be VSS or VDD. Be careful that if unspecified voltage, i.e. if unfirmed voltage level (not V SSor VDD) is applied to input pin, there can be little current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low. VDD INPUT PIN INPUT PIN internal pull-up OPEN VDD VDD i=0 VDD O O i GND VDD i Very weak current flows X Weak pull-up current flows X OPEN i=0 GND O O When port is configured as an input, input level should be closed to 0V or 5V to avoid power consumption. Figure 18-6 Application Example of Unused Input Port MAR. 1999 Ver 1.01 71 GMS81C3004 OUTPUT PIN ON OPEN ON OFF i GND ON OFF VDD OFF OUTPUT PIN VDD L ON OFF i GND ON i=0 GND L VDD O OFF X X O O In the left case, Tr. base current flows from port to GND. To avoid power consumption, there should be low output to the port . In the left case, much current flows from port to GND. Figure 18-7 Application Example of Unused Output Port 72 MAR. 1999 Ver 1.01 GMS81C3004 19. OSCILLATOR CIRCUIT The GMS81C3004 has two oscillation circuits internally. XIN and X OUT are input and output for main frequency and SXIN and SX OUT are input and output for sub frequency, C1 XOUT respectively, inverting amplifier which can be configured for being used as an on-chip oscillator, as shown in Figure 19-1 . C1 SXOUT C2 4.19MHz XIN VSS C2 32.768KHz SXIN VSS Recommend Crystal Oscillator Ceramic Resonator C1,C2 = 20pF C1,C2 = 30pF Recommend C1,C2 = 100~120pF Crystal or Ceramic Oscillator Open XOUT REXT XOUT External Clock XIN XIN For selection R value, Refer to AC Characteristics External Oscillator RC Oscillator (mask option) Figure 19-1 Oscillation Circuit Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. In addition, see Figure 19-2 for the layout of the crystal. Note: Minimize the wiring length. Do not allow the wiring to intersect with other signal conductors. Do not allow the wiring to come near changing high current. Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do not ground it to any ground pattern where high current is present. Do not fetch signals from the oscillator. XOUT XIN Figure 19-2 Layout of Oscillator PCB circuit MAR. 1999 Ver 1.01 73 GMS81C3004 20. RESET The GMS81C3004 have two types of reset generation procedures; one is an external reset input, the other is a watchOn-chip Hardware Program counter RAM page register G-flag Operation mode (PC) (RPR) (G) Initial Value (FFFFH) - (FFFEH) 0 0 Main-frequency clock dog timer reset. Table 20-1 shows on-chip hardware initialization by reset action. On-chip Hardware Peripheral clock Watchdog timer Control registers Power fail detector Initial Value Off Disable Refer to Table 8-1 on page 22 Disable Table 20-1 Initializing Internal Status by Reset Action 20.1 External Reset Input The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, it is applied, and the internal state is initialized. After reset, 64ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 20-2 . Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before read or tested it. When the RESET pin input goes to high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH - FFFFH. A connection for simple power-on-reset is shown in Figure 20-1 . VDD VDD Typical 60k at VDD=3V RESET + - GND MCU Figure 20-1 Simple Power-on-Reset Circuit 1 2 3 4 5 6 7 ~ ~ System Clock ~ ~ RESET ~ ~ ADDRESS BUS DATA BUS ? ? ? ? FFFE FFFF Start ~~ ~~ ? ? ? ? FE ADL ADH OP Stabilization Time tST = 62.5mS at 4.19MHz Figure 20-2 Timing Diagram after RESET ~ ~ RESET Process Step 1 fMAIN /1024 MAIN PROGRAM tST = x 256 20.2 Watchdog Timer Reset Refer to "16. WATCHDOG TIMER" on page 64. 74 MAR. 1999 Ver 1.01 GMS81C3004 21. POWER FAIL PROCESSOR The GMS81C3004 has an on-chip low voltage detection circuitry to detect the VDD voltage. A configuration register, LVDR, can enable or disable the low voltage detect circuitry. Whenever VDD falls close to or below 3.4V, the LVD flag1, LVDF0 is just set to "1", and if it recovering 3.4V, LVDF0 is holded to "1". If VDD falls below around 2.2V range, the low voltage situation may reset MCU according to setting of LVDR. Refer to "7.3 DC Electrical Characteristics" on page 10. In the in-circuit emulator, power fail function is not implemented and user can not experiment with it. Therefore, after final development of user program, this function may be experimented or evaluated. Note: Power fail processor function is not available on 3V operation, because this function will detect power fail at all the time. 7 6 5 LVDR R/W R/W R/W R/W R/W 4 3 2 1 0 LVDM LVDF1 LVDE LVDRST LVDF0 ADDRESS: 0FEH INITIAL VALUE: ---1 0000 LVD flag 0 (typ. 2.2V) 0: Not detect low voltage (Normal) 1: Detect low voltage Reset by LVD 0: Disable 1: Enable Operation Mode 0 : Normal operation regardless of power fail 1 : MCU will be reset by power fail detection LVD flag 1 (typ. 3.4V) 0: VDD is above 3.4V 1: VDD is below 3.4V Freeze by LVD 0: Disable 1: Enable Figure 21-1 Low Voltage Detector Register RESET VECTOR YES LVDF =1 NO RAM CLEAR INITIALIZE RAM DATA Skip the initial routine INITIALIZE ALL PORTS INITIALIZE REGISTERS FUNTION EXECUTION Figure 21-2 Example S/W of RESET by Power fail MAR. 1999 Ver 1.01 75 GMS81C3004 VDD 64mS LVDVDD MAX LVDVDDMIN Internal RESET VDD When LVDM = 1 Internal RESET VDD t <64mS LVDVDD MAX LVDVDDMIN 64mS Internal RESET 64mS LVDVDD MAX LVDVDDMIN Figure 21-3 Power Fail Processor Situations 76 MAR. 1999 Ver 1.01 APPENDIX GMS81C3004 A. CONTROL REGISTER LIST Address 00C0 00C1 00C2 00C4 00C5 00C6 00C7 00C8 00C9 00CA 00CC 00CD 00CE 00CF 00D4 00D5 00D6 00D8 00D9 00DA 00DB 00DC 00DD 00DE 00DF 00E4 00E5 00EC 00ED 00F0 00F1 00F3 00F4 00F6 00F7 00F8 00F9 00FA 00FB 00FE Register Name R0 port data register R1 port data register R2 port data register R4 port data register R5 port data register R6 port data register R7 port data register R0 port I/O direction register R1 port I/O direction register R2 port I/O direction register R4 port I/O direction register R5 port I/O direction register R6 port I/O direction register R7 port I/O direction register R0 port pull-up resistor selection register R1 port pull-up resistor selection register R2 port pull-up resistor selection register External Interrupt Edge selection register R0 port mode register Interrupt enable low register Interrupt enable high register Interrupt request flag low register Interrupt request flag high register Sleep mode register Watchdog Timer Register Timer 1 mode register Timer 1 count register Timer 1 data register Comparator mode register Comparator channel selection register Watch timer mode register LCD control register LCD port selection register Key Scan control register R1 port mode register Buzzer register RAM paging register Basic interval timer mode register Clock control register System clock mode register Peripheral clock control register LVD mode register Symbol R0 R1 R2 R4 R5 R6 R7 R0DD R1DD R2DD R4DD R5DD R6DD R7DD PUR0 PUR1 PUR2 IESR PMR0 IENL IENH IRQL IRQH SMR WDTR TM1 T1 TDR1 CMR CSR WTMR LCR LPMR KSCR PMR1 BUR RPR BITR CKCTLR SCMR PCOR LVDR R/W R/W R/W R/W R/W R/W R/W R/W W W W W W W W W W W W W R/W R/W R/W R/W W W R/W R W W W W R/W R/W R/W R/W W R/W R W R/W W R/W Initial Value 76543210 Page 30 30 31 31 31 32 32 30 30 31 31 31 32 32 30 30 31 51 51 47 47 47 47 68 64 40 40 40 45 45 43 56 60 54 66 66 25 39 39 34 34 75 Undefined Undefined Undefined Undefined Undefined Undefined Undefined 00000000 00000000 - - - - -000 00000000 00000000 00000000 00000000 00000000 00000000 - - - - -000 - -000000 - - - -0000 ---0---0 - -00-000 ---0---0 - -00-000 -------0 00111111 - - -00000 00000000 Undefined 00-00000 0 - - - - -00 - - - -0000 0 -00-000 00000000 00000000 -------0 00000000 00000000 Undefined - - - -0111 - - - -0000 -------0 - - -10000 MAR. 1999 Ver 1.01 i GMS81C3004 B. PAD COORDINATION Device Chip size Pad Size GMS81C3004 2670m x 2980m 95m x 95m B.1 Pad Layout Y 2 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 3 4 5 6 7 8 9 10 11 62 61 60 59 58 57 56 55 54 53 12 13 14 15 16 17 18 (0, 0) 52 X 51 50 49 48 47 46 19 20 21 22 45 44 43 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 ii MAR. 1999 Ver 1.01 GMS81C3004 B.2 Bonding Pad Coordination Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name R76 / SEG30 R77 / SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 VSS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 VCL1 VCL2 VCL3 VCL4 VCL5 R10 / KS0 R11 / KS1 R12 / KS2 R13 / KS3 R14/ CMP0 / KS4 R15 / CMP1 / KS5 R16 / CMP2 / KS6 R17 / CMP3 / KS7 R00 / INT0 R01 / INT1 R02 /INT2 R03 / EC1 R04 R05 R06 / LCDCK R07 Pad Coordination (X,Y) (-1077.5, 1412.5) (-1257.5, 1412.5) (-1257.5, 1232.5) (-1257.5, 1082.5) (-1257.5, 935.0) (-1257.5, (-1257.5, (-1257.5, (-1257.5, (-1257.5, 815.0) 695.0) 575.0) 455.0) 335.0) Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Name R20 R21 R22 RESET TEST VDD XOUT XIN SXOUT SXIN SEG0 / R40 SEG1 / R41 SEG2 / R42 SEG3 / R43 SEG4 / R44 SEG5 / R45 SEG6 / R46 SEG7 / R47 SEG8 / R50 SEG9 / R51 SEG10 / R52 SEG11 / R53 SEG12 / R54 SEG13 / R55 SEG14 / R56 SEG15 / R57 SEG16 / R60 SEG17 / R61 SEG18 / R62 SEG19 / R63 SEG20 / R64 SEG21 / R65 SEG22 / R66 SEG23 / R67 SEG24 / R70 SEG25 / R71 SEG26 / R72 SEG27 / R73 SEG28 / R74 SEG29 / R75 Pad Coordination (X,Y) (1077.5, -1412.5) (1257.5, -1412.5) (1257.5, -1232.5) (1257.5, -1082.5) (1257.5, -935.0) (1257.5, -780.0) (1257.5, -625.0) (1257.5, -505.0) (1257.5, -385.0) (1257.5, -265.0) (1257.5, -145.0) (1257.5, -25.0) (1257.5, 95.0) (1257.5, 215.0) (1257.5, 335.0) (1257.5, 455.0) (1257.5, 575.0) (1257.5, 695.0) (1257.5, 815.0) (1257.5, 935.0) (1257.5, 1082.0) (1257.5, 1232.5) (1257.5, 1412.5) (1077.5, 1412.5) (922.5, 1412.5) (780.0, 1412.5) (660.0, 1412.5) (540.0, 1412.5) (420.0, 1412.5) (300.0, 1412.5) (180.0, 1412.5) (60.0, 1412.5) (-60.0, 1412.5) (-180.0, 1412.5) (-300.0, 1412.5) (-420.0, 1412.5) (-540.0, 1412.5) (-660.0, 1412.5) (-780.0, 1412.5) (-922.5, 1412.5) (-1257.5, 180.0) (-1257.5, 25.0) (-1257.5, -95.0) (-1257.5, -215.0) (-1257.5, -335.0) (-1257.5, (-1257.5, (-1257.5, (-1257.5, (-1257.5, -455.0) -575.0) -695.0) -815.0) -935.0) (-1257.5, -1082.5) (-1257.5, -1232.5) (-1257.5, -1412.5) (-1077.5, -1412.5) (-922.5, -1412.5) (-780.0, -1412.5) (-660.0, -1412.5) (-540.0, -1412.5) (-420.0, -1412.5) (-300.0, -1412.5) (-180.0, -1412.5) (-60.0, -1412.5) (60.0, -1412.5) (180.0, -1412.5) (300.0, -1412.5) (420.0, -1412.5) (540.0, -1412.5) (660.0, -1412.5) (780.0, -1412.5) (922.5, -1412.5) MAR. 1999 Ver 1.01 iii GMS81C3004 C. INSTRUCTION C.1 Terminology List Terminology A X Y PSW #imm dp !abs [] {} { }+ .bit A.bit dp.bit M.bit rel upage n + x Accumulator X - register Y - register Program Status Word 8-bit Immediate data Direct Page Offset Address Absolute Address Indirect expression Register Indirect expression Register Indirect expression, after that, Register auto-increment Bit Position Bit Position of Accumulator Bit Position of Direct Page Memory Bit Position of Memory Data (000 H~0FFF H) Relative Addressing Data U-page (0FF00H~0FFFFH) Offset Address Table CALL Number (0~15) Addition 0 Bit Position Description Upper Nibble Expression in Opcode y - x / () 1 Bit Position Upper Nibble Expression in Opcode Subtraction Multiplication Division Contents Expression AND OR Exclusive OR NOT Assignment / Transfer / Shift Left Shift Right Exchange Equal Not Equal ~ = iv MAR. 1999 Ver 1.01 GMS81C3004 C.2 Instruction Map LOW 00000 HIGH 00 - 00001 01 SET1 dp.bit 00010 02 00011 03 00100 04 ADC #imm SBC #imm CMP #imm OR #imm AND #imm EOR #imm LDA #imm LDM dp,#imm 00101 05 ADC dp SBC dp CMP dp OR dp AND dp EOR dp LDA dp STA dp 00110 06 ADC dp+X SBC dp+X CMP dp+X OR dp+X AND dp+X EOR dp+X LDA dp+X STA dp+X 00111 07 ADC !abs SBC !abs CMP !abs OR !abs AND !abs EOR !abs LDA !abs STA !abs 01000 08 ASL A ROL A LSR A ROR A INC A DEC A TXA 01001 09 ASL dp ROL dp LSR dp ROR dp INC dp DEC dp LDY dp STY dp 01010 0A TCALL 0 01011 0B SETA1 .bit 01100 0C BIT dp COM dp TST dp CMPX dp CMPY dp DBNE dp LDX dp STX dp 01101 0D POP A POP X POP Y POP PSW CBNE dp+X XMA dp+X LDX dp+Y STX dp+Y 01110 0E PUSH A PUSH X PUSH Y PUSH PSW TXSP 01111 0F BRK BRA rel PCALL Upage RET INC X DEC X DAS 000 BBS BBS A.bit,rel dp.bit,rel 001 CLRC TCALL CLRA1 2 .bit TCALL 4 TCALL 6 NOT1 M.bit OR1 OR1B 010 CLRG 011 DI 100 CLRV TCALL AND1 8 AND1B TCALL EOR1 10 EOR1B TCALL 12 TCALL 14 LDC LDCB STC M.bit 101 SETC TSPX 110 SETG XCN 111 EI TAX XAX STOP LOW 10000 HIGH 10 BPL rel BVC rel BCC rel BNE rel BMI rel BVS rel BCS rel BEQ rel 10001 11 CLR1 dp.bit 10010 12 BBC A.bit,rel 10011 13 BBC dp.bit,rel 10100 14 ADC {X} SBC {X} CMP {X} OR {X} AND {X} EOR {X} LDA {X} STA {X} 10101 15 ADC !abs+Y SBC !abs+Y CMP !abs+Y OR !abs+Y AND !abs+Y EOR !abs+Y LDA !abs+Y STA !abs+Y 10110 16 ADC [dp+X] SBC [dp+X] CMP [dp+X] OR [dp+X] AND [dp+X] EOR [dp+X] LDA [dp+X] STA [dp+X] 10111 17 ADC [dp]+Y SBC [dp]+Y CMP [dp]+Y OR [dp]+Y AND [dp]+Y EOR [dp]+Y LDA [dp]+Y STA [dp]+Y 11000 18 ASL !abs ROL !abs LSR !abs ROR !abs INC !abs DEC !abs LDY !abs STY !abs 11001 19 ASL dp+X ROL dp+X LSR dp+X ROR dp+X INC dp+X DEC dp+X LDY dp+X STY dp+X 11010 1A TCALL 1 TCALL 3 TCALL 5 TCALL 7 TCALL 9 TCALL 11 TCALL 13 TCALL 15 11011 1B JMP !abs CALL !abs MUL DBNE Y DIV XMA {X} LDA {X}+ STA {X}+ 11100 1C BIT !abs TEST !abs 11101 1D ADDW dp SUBW dp 11110 1E LDX #imm LDY #imm CMPX #imm CMPY #imm INC Y DEC Y XAY 11111 1F JMP [!abs] JMP [dp] CALL [dp] RETI 000 001 010 TCLR1 CMPW !abs dp CMPX !abs CMPY !abs XMA dp LDX !abs STX !abs LDYA dp INCW dp DECW dp STYA dp CBNE dp 011 100 TAY 101 TYA 110 DAA 111 XYX NOP MAR. 1999 Ver 1.01 v GMS81C3004 C.3 Instruction Set Arithmetic / Logic Operation No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Mnemonic ADC #imm ADC dp ADC dp + X ADC !abs ADC !abs + Y ADC [ dp + X ] ADC [ dp ] + Y ADC { X } AND #imm AND dp AND dp + X AND !abs AND !abs + Y AND [ dp + X ] AND [ dp ] + Y AND { X } ASL A ASL dp ASL dp + X ASL !abs CMP #imm CMP dp CMP dp + X CMP !abs CMP !abs + Y CMP [ dp + X ] CMP [ dp ] + Y CMP { X } CMPX #imm CMPX dp CMPX !abs CMPY #imm CMPY dp CMPY !abs COM dp DAA DAS DEC A DEC dp DEC dp + X DEC !abs DEC X DEC Y Op Code 04 05 06 07 15 16 17 14 84 85 86 87 95 96 97 94 08 09 19 18 44 45 46 47 55 56 57 54 5E 6C 7C 7E 8C 9C 2C DF CF A8 A9 B9 B8 AF BE Byte No 2 2 2 3 3 2 2 1 2 2 2 3 3 2 2 1 1 2 2 3 2 2 2 3 3 2 2 1 2 2 3 2 2 3 2 1 1 1 2 2 3 1 1 Cycle No 2 3 4 4 5 6 6 3 2 3 4 4 5 6 6 3 2 4 5 5 2 3 4 4 5 6 6 3 2 3 4 2 3 4 4 3 3 2 4 5 5 2 2 Arithmetic shift left C Operation Add with carry. A(A)+(M)+C Flag NVGBHIZC NV--H-ZC Logical AND A (A)(M) N-----Z- 76543210 N-----ZC "0" Compare accumulator contents with memory contents (A) -(M) N-----ZC Compare X contents with memory contents (X)-(M) Compare Y contents with memory contents (Y)-(M) 1'S Complement : ( dp ) ~( dp ) Decimal adjust for addition Decimal adjust for subtraction Decrement M (M)-1 N-----ZC N-----ZN-----ZC N-----ZC N-----ZN-----ZN-----ZN-----ZN-----ZN-----ZN-----ZC vi MAR. 1999 Ver 1.01 GMS81C3004 No. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 DIV Mnemonic Op Code 9B A4 A5 A6 A7 B5 B6 B7 B4 88 89 99 98 8F 9E 48 49 59 58 5B 64 65 66 67 75 76 77 74 28 29 39 38 68 69 79 78 24 25 26 27 35 36 37 34 4C CE Byte No 1 2 2 2 3 3 2 2 1 1 2 2 3 1 1 1 2 2 3 1 2 2 2 3 3 2 2 1 1 2 2 3 1 2 2 3 2 2 2 3 3 2 2 1 2 1 Cycle No 12 2 3 4 4 5 6 6 3 2 4 5 5 2 2 2 4 5 5 9 2 3 4 4 5 6 6 3 2 4 5 5 2 4 5 5 2 3 4 4 5 6 6 3 3 5 Subtract with Carry Logical shift right Increment M (M)+1 Exclusive OR A (A)(M) Operation Divide : YA / X Q: A, R: Y Flag NVGBHIZC NV--H-Z- EOR #imm EOR dp EOR dp + X EOR !abs EOR !abs + Y EOR [ dp + X ] EOR [ dp ] + Y EOR { X } INC A INC dp INC dp + X INC !abs INC X INC Y LSR A LSR dp LSR dp + X LSR !abs MUL OR #imm OR dp OR dp + X OR !abs OR !abs + Y OR [ dp + X ] OR [ dp ] + Y OR { X } ROL A ROL dp ROL dp + X ROL !abs ROR A ROR dp ROR dp + X ROR !abs SBC #imm SBC dp SBC dp + X SBC !abs SBC !abs + Y SBC [ dp + X ] SBC [ dp ] + Y SBC { X } TST dp XCN N-----Z- N-----ZC N-----ZN-----ZN-----ZN-----ZN-----ZN-----ZC 76543210 C "0" Multiply : YA Y x A Logical OR A (A)(M) N-----Z- N-----Z- Rotate left through Carry C 76543210 N-----ZC Rotate right through Carry 76543210 C N-----ZC A ( A ) - ( M ) - ~( C ) NV--HZC Test memory contents for negative or zero, ( dp ) - 00H Exchange nibbles within the accumulator A 7~A 4 A3~A 0 N-----ZN-----Z- MAR. 1999 Ver 1.01 vii GMS81C3004 Register / Memory Operation No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Mnemonic LDA #imm LDA dp LDA dp + X LDA !abs LDA !abs + Y LDA [ dp + X ] LDA [ dp ] + Y LDA { X } LDA { X }+ LDM dp,#imm LDX #imm LDX dp LDX dp + Y LDX !abs LDY #imm LDY dp LDY dp + X LDY !abs STA dp STA dp + X STA !abs STA !abs + Y STA [ dp + X ] STA [ dp ] + Y STA { X } STA { X }+ STX dp STX dp + Y STX !abs STY dp STY dp + X STY !abs TAX TAY TSPX TXA TXSP TYA XAX XAY XMA dp XMA dp+X XMA {X} XYX Op Code C4 C5 C6 C7 D5 D6 D7 D4 DB E4 1E CC CD DC 3E C9 D9 D8 E5 E6 E7 F5 F6 F7 F4 FB EC ED FC E9 F9 F8 E8 9F AE C8 8E BF EE DE BC AD BB FE Byte No 2 2 2 3 3 2 2 1 1 3 2 2 2 3 2 2 2 3 2 2 3 3 2 2 1 1 2 2 3 2 2 3 1 1 1 1 1 1 1 1 2 2 1 1 Cycle No 2 3 4 4 5 6 6 3 4 5 2 3 4 4 2 3 4 4 4 5 5 6 7 7 4 4 4 5 5 4 5 5 2 2 2 2 2 2 4 4 5 6 5 4 Load Y-register Y(M) Load accumulator A(M) Operation Flag NVGBHIZC N-----Z- X- register auto-increment : A ( M ) , X X + 1 Load memory with immediate data : ( M ) imm Load X-register X (M) N-----Z-------- N-----Z- Store accumulator contents in memory (M)A -------- X- register auto-increment : ( M ) A, X X + 1 Store X-register contents in memory (M) X Store Y-register contents in memory (M) Y Transfer accumulator contents to X-register : X A Transfer accumulator contents to Y-register : Y A Transfer stack-pointer contents to X-register : X sp Transfer X-register contents to accumulator: A X Transfer X-register contents to stack-pointer: sp X Transfer Y-register contents to accumulator: A Y Exchange X-register contents with accumulator :X A Exchange Y-register contents with accumulator :Y A Exchange memory contents with accumulator (M)A Exchange X-register contents with Y-register : X Y N-----Z--------------- N-----ZN-----ZN-----ZN-----ZN-----ZN-----Z--------------- -------- viii MAR. 1999 Ver 1.01 GMS81C3004 16-BIT operation No. 1 2 3 4 5 6 7 Mnemonic ADDW dp CMPW dp DECW dp INCW dp LDYA dp STYA dp SUBW dp Op Code 1D 5D BD 9D 7D DD 3D Byte No 2 2 2 2 2 2 2 Cycle No 5 4 6 6 5 5 5 Operation 16-Bits add without Carry YA ( YA ) ( dp +1 ) ( dp ) Compare YA contents with memory pair contents : (YA) - (dp+1)(dp) Decrement memory pair ( dp+1)( dp) ( dp+1) ( dp) - 1 Increment memory pair ( dp+1) ( dp) ( dp+1) ( dp ) + 1 Load YA YA ( dp +1 ) ( dp ) Store YA ( dp +1 ) ( dp ) YA 16-Bits subtract without carry YA ( YA ) - ( dp +1) ( dp) Flag NVGBHIZC NV--H-ZC N-----ZC N-----ZN-----ZN-----Z-------NV--H-ZC Bit Manipulation No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mnemonic AND1 M.bit AND1B M.bit BIT dp BIT !abs CLR1 dp.bit CLRA1 A.bit CLRC CLRG CLRV EOR1 M.bit EOR1B M.bit LDC M.bit LDCB M.bit NOT1 M.bit OR1 M.bit OR1B M.bit SET1 dp.bit SETA1 A.bit SETC SETG STC M.bit TCLR1 !abs TSET1 !abs Op Code 8B 8B 0C 1C y1 2B 20 40 80 AB AB CB CB 4B 6B 6B x1 0B A0 C0 EB 5C 3C Byte No 3 3 2 3 2 2 1 1 1 3 3 3 3 3 3 3 2 2 1 1 3 3 3 Cycle No 4 4 4 5 4 2 2 2 2 5 5 4 4 5 5 5 4 2 2 2 6 6 6 Operation Bit AND C-flag : C ( C ) ( M .bit ) Bit AND C-flag and NOT : C ( C ) ~( M .bit ) Bit test A with memory : Z ( A ) ( M ) , N ( M7 ) , V ( M6 ) Clear bit : ( M.bit ) "0" Clear A bit : ( A.bit ) "0" Clear C-flag : C "0" Clear G-flag : G "0" Clear V-flag : V "0" Bit exclusive-OR C-flag : C ( C ) ( M .bit ) Bit exclusive-OR C-flag and NOT : C ( C ) ~(M .bit) Load C-flag : C ( M .bit ) Load C-flag with NOT : C ~( M .bit ) Bit complement : ( M .bit ) ~( M .bit ) Bit OR C-flag : C ( C ) ( M .bit ) Bit OR C-flag and NOT : C ( C ) ~( M .bit ) Set bit : ( M.bit ) "1" Set A bit : ( A.bit ) "1" Set C-flag : C "1" Set G-flag : G "1" Store C-flag : ( M .bit ) C Test and clear bits with A : A - ( M ) , ( M ) ( M ) ~( A ) Test and set bits with A : A-(M), (M) (M)(A) Flag NVGBHIZC -------C -------C MM----Z- ---------------------0 --0-----0--0---------C -------C -------C -------C --------------C -------C ---------------------1 --1-----------N-----ZN-----Z- MAR. 1999 Ver 1.01 ix GMS81C3004 Branch / Jump Operation No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mnemonic BBC A.bit,rel BBC dp.bit,rel BBS A.bit,rel BBS dp.bit,rel BCC rel BCS rel BEQ rel BMI rel BNE rel BPL rel BRA rel BVC rel BVS rel CALL !abs CALL [dp] CBNE dp,rel CBNE dp+X,rel DBNE dp,rel DBNE Y,rel JMP !abs JMP [!abs] JMP [dp] PCALL upage Op Code y2 y3 x2 x3 50 D0 D0 90 70 10 2F 30 B0 3B 5F FD 8D AC 7B 1B 1F 3F 4F Byte No 2 3 2 3 2 2 2 2 2 2 2 2 2 3 2 3 3 3 2 3 3 2 2 Cycle No 4/6 5/7 4/6 5/7 2/4 2/4 2/4 2/4 2/4 2/4 4 2/4 2/4 8 8 5/7 6/8 5/7 4/6 3 5 4 6 Branch if bit clear : Operation Flag NVGBHIZC -------- if ( bit ) = 0 , then pc ( pc ) + rel Branch if bit set : if ( bit ) = 1 , then pc ( pc ) + rel Branch if carry bit clear if ( C ) = 0 , then pc ( pc ) + rel Branch if carry bit set if ( C ) = 1 , then pc ( pc ) + rel Branch if equal if ( Z ) = 1 , then pc ( pc ) + rel Branch if minus if ( N ) = 1 , then pc ( pc ) + rel Branch if not equal if ( Z ) = 0 , then pc ( pc ) + rel Branch if minus if ( N ) = 0 , then pc ( pc ) + rel Branch always pc ( pc ) + rel Branch if overflow bit clear if (V) = 0 , then pc ( pc) + rel Branch if overflow bit set if (V) = 1 , then pc ( pc ) + rel Subroutine call M( sp)( pcH ), spsp - 1, M(sp) (pcL), sp sp - 1, if !abs, pc abs ; if [dp], pc L ( dp ), pcH ( dp+1 ) . Compare and branch if not equal : if ( A ) ( M ) , then pc ( pc ) + rel. Decrement and branch if not equal : if ( M ) 0 , then pc ( pc ) + rel. Unconditional jump pc jump address U-page call M(sp) ( pcH ), sp sp - 1, M(sp) ( pcL ), sp sp - 1, pcL ( upage ), pcH "0FFH" . Table call : (sp) ( pcH ), sp sp - 1, M(sp) ( pcL ),sp sp - 1, pc L (Table vector L), pcH (Table vector H) --------------------------------------------------------------------------------------------------- -------- 24 TCALL n nA 1 8 -------- x MAR. 1999 Ver 1.01 GMS81C3004 Control Operation & Etc. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 BRK DI EI NOP POP A POP X POP Y POP PSW PUSH A PUSH X PUSH Y PUSH PSW RET Mnemonic Op Code 0F 60 E0 FF 0D 2D 4D 6D 0E 2E 4E 6E 6F Byte No 1 1 1 1 1 1 1 1 1 1 1 1 1 Cycle No 8 3 3 2 4 4 4 4 4 4 4 4 5 Operation Software interrupt : B "1", M(sp) (pcH), sp sp-1, M(s) (pcL), sp sp - 1, M(sp) (PSW), sp sp -1, pc L ( 0FFDEH ) , pc H ( 0FFDFH ) . Disable all interrupts : I "0" Enable all interrupt : I "1" No operation sp sp + 1, A M( sp ) sp sp + 1, X M( sp ) sp sp + 1, Y M( sp ) sp sp + 1, PSW M( sp ) M( sp ) A , sp sp - 1 M( sp ) X , sp sp - 1 M( sp ) Y , sp sp - 1 M( sp ) PSW , sp sp - 1 Return from subroutine sp sp +1, pcL M( sp ), sp sp +1, pcH M( sp ) Return from interrupt sp sp +1, PSW M( sp ), sp sp + 1, pc L M( sp ), sp sp + 1, pcH M( sp ) Stop mode ( halt CPU, stop oscillator ) Flag NVGBHIZC ---1-0------0------1---------------restored -------- -------- 14 15 RETI STOP 7F EF 1 1 6 3 restored -------- MAR. 1999 Ver 1.01 xi D. MASK ORDER SHEET MASK ORDER & VERIFICATION SHEET GMS81C3004-LA Customer should write inside thick line box. 1. Customer Information Company Name Application YYYY MM DD 2. Device Information Package OSC Opt. 80QFP Crystal DIE RC .OTP) ) Set "FF" in this area 6FFFH 7000H .OTP file data Order Date Tel: Name & Signature: Fax: Mask Data File Name: ( Hitel Check Sum: ( 0000H Chollian Internet 3. Marking Specification (if 80QFP sale) LGS 7FFFH (Please check mark into ) G M S81C 3004-LAxxx Y YW W KO REA #1 index mark 4. Delivery Schedule Date YYYY MM DD Quantity pcs LG Confirmation Customer Sample YYYY MM DD Risk Order pcs 5. ROM Code Verification YYYY MM DD This box is written after "5.Verification". Approval Date: YYYY MM DD Verification D ate: Please confirm our verification data. I agree w ith your verification data and confirm you to m ake m ask set. Check Sum: Tel: Name & Signature: Fax: Tel: Name & Signature: Fax: LG Semicon |
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