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| August 2004 rev 2.0 3.3 V `SpreadTrak' Zero Delay Buffer Features Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations - Refer "ASM5P23S04A Configurations Table". Input frequency range: 10MHz to 133MHz Multiple low-skew outputs. Output-output skew less than 200 ps. Device-device skew less than 500 ps. Two banks of four outputs. Less than 200 ps cycle-to-cycle jitter Available in space saving, 8-pin 150-mil SOIC packages. 3.3V operation. Advanced 0.35 CMOS technology. Industrial temperature available. `SpreadTrak' Functional Description ASM5P23S04A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications. It is available in a 8-pin package. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven to ASMP5P23S04A FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 250ps, and the output-to-output skew is guaranteed to be less than 200ps. The ASM5P23S04A has two banks of two outputs each. Multiple ASM5P23S04A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 500ps. The ASM5P23S04A (Refer is available in two different configurations "ASM5P23S04A Configurations Table). The ASM5P23S04A-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The ASM5P23S04A-1H is the high-drive version of the -1 and the rise and fall times on this device are much faster. The ASM5P23S04A-2 allows the user to obtain Ref, 1/2 X and 2X frequencies on each output bank. The exact configuration and output frequencies depend on which output drives the feedback pin. The ASM5P23S04A-5H is a high-drive version with REF/2 on both banks Block Diagram FBK CLKA1 REF PLL CLKA2 /2 Extra Divider (-2) CLKB1 CLKB2 Alliance Semiconductor 2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com Notice: The information in this document is subject to change without notice. August 2004 rev 2.0 ASM5P23S04A Configurations Device ASM5P23S04A-1 ASM5P23S04A-1H ASM5P23S04A-2 ASM5P23S04A-2 ASM5P23S04A-5H `SpreadTrak' Many systems being designed now utilize a technology called Spread Frequency Timing Generation. ASM3P23S04A is designed so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero Zero Delay and Skew Control For applications requiring zero input-output delay, all outputs must be equally loaded. 1500 ASM5P23S04A Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A or Bank B Bank A Frequency Reference Reference Reference 2 X Reference Reference /2 Bank B Frequency Reference Reference Reference /2 Reference Reference /2 delay buffer is not designed to pass the Spread Spectrum feature through, the result is a significant amount of tracking skew which may cause problems in the systems requiring synchronization. 1000 REF-Input to CLKA/CLKB Delay (ps) 500 0 -30 -500 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -1000 -1500 Output Load Difference: FBK Load - CLKA/CLKB Load (pF) REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins 3.3 `SpreadTrak' Zero Delay Buffer Notice: 2 of 13 The information in this document is subject to change without notice. August 2004 rev 2.0 To close the feedback loop of the ASM5P23S04A, the FBK pin can be driven from any of the four available output pins. The output driving the FBK pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input output delay. This is shown in the above graph. Pin Configuration REF CLKA1 CLKA2 GND 1 2 3 4 8 FBK VDD CLKB2 ASM5P23S04A For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. ASM5P23S04A 7 6 5 CLKB1 Pin Description for ASM5P23S04A Pin # 1 2 3 4 5 6 7 8 Pin Name REF1 CLKA12 CLKA22 GND CLKB12 CLKB2 2 VDD FBK Description Input reference frequency, 5V tolerant input Buffered clock output, bank A Buffered clock output, bank A Ground Buffered clock output, bank B Buffered clock output, bank B 3.3V supply PLL feedback input Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3.3 `SpreadTrak' Zero Delay Buffer Notice: 3 of 13 The information in this document is subject to change without notice. August 2004 rev 2.0 Absolute Maximum Ratings Parameter Supply Voltage to Ground Potential DC Input Voltage (Except REF) DC Input Voltage (REF) Storage Temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (per MIL-STD-883, Method 3015) Min -0.5 -0.5 -0.5 -65 Max +7.0 VDD + 0.5 7 +150 260 150 >2000 ASM5P23S04A Unit V V V C C C V Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can affect device reliability. Operating Conditions for ASM5P23S04A Commercial Temperature Devices Parameter VDD TA CL CL CIN Supply Voltage Description Min 3.0 0 Max 3.6 70 30 15 7 Unit V C Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance3 pF pF pF Note: 3. Applies to both Ref Clock and FBK. 3.3 `SpreadTrak' Zero Delay Buffer Notice: 4 of 13 The information in this document is subject to change without notice. August 2004 rev 2.0 Electrical Characteristics for ASM5P23S04A Commercial Temperature Devices ASM5P23S04A Parameter VIL VIH IIL IIH VOL Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage 4 Test Conditions Min Max 0.8 Unit V V 2.0 VIN = 0V VIN = VDD IOL = 8mA (-1, -2) IOH = 12mA (-1H, -5H) IOL = -8mA (-1, -2) IOH = -12mA (-1H, -5H) Unloaded outputs 100MHz REF, Select inputs at VDD or GND 2.4 50.0 100.0 A A 0.4 V VOH Output HIGH Voltage 4 V TBD TBD mA IDD Supply Current Unloaded outputs, 66MHz REF (-1, -2) Unloaded outputs, 33MHz REF (-1, -2) TBD TBD Note: 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. 5. REF Input Vth = ~ VDD/2 3.3 `SpreadTrak' Zero Delay Buffer Notice: 5 of 13 The information in this document is subject to change without notice. August 2004 rev 2.0 Switching Characteristics for ASM5P23S04A Commercial Temperature Devices Parameter t1 t1 t1 Description Output Frequency Output Frequency Output Frequency Duty Cycle = (t2 / t1) * 100 (-1, -2, -1H, -5H) Duty Cycle = (t2 / t1) * 100 (-1, -2,-1H, -5H) t3 Output Rise Time (-1, -2) Output Rise Time (-1, -2) Output Rise Time (-1H, -5H) Output Fall Time (-1, -2) Output Fall Time (-1, -2) Output Fall Time (-1H, -5H) 4 4 4 4 ASM5P23S04A Test Conditions 30-pF load, All devices 20-pF load, -1H, -5H devices 15-pF load, -1, -2 devices Measured at 1.4V, FOUT = 66.66 MHz 30-pF load Measured at 1.4V, FOUT = <50 MHz 15-pF load Measured between 0.8V and 2.0V 30-pF load Measured between 0.8V and 2.0V 15-pF load Measured between 0.8V and 2.0V 30-pF load Measured between 2.0V and 0.8V 30-pF load Measured between 2.0V and 0.8V 15-pF load Measured between 2.0V and 0.8V 30-pF load All outputs equally loaded Min 10 10 10 40.0 Typ Max 100 133.3 133.3 Unit MHz MHz MHz % 50.0 60.0 45.0 50.0 55.0 % 2.20 ns 4 t3 1.50 ns 4 t3 1.50 ns 4 t4 2.20 ns 4 t4 1.50 ns 4 t4 1.25 ns Output-to-output skew on same bank (-1, -2) 200 t5 Output-to-output skew (-1H, -5H) Output bank A -to- output bank B skew (-1, 5H) Output bank A to output bank b skew (-2) All outputs equally loaded 200 ps All outputs equally loaded All outputs equally loaded Measured at VDD /2 Measured at VDD/2 on the FBK pins of the device Measured between 0.8V and 2.0V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs, 15 pF load 1 0 0 200 400 250 500 ps ps V/ns t6 t7 t8 Delay, REF Rising Edge to FBK Rising Edge 3 Device-to-Device Skew Output Slew Rate 4 4 175 ps tJ Cycle-to-cycle jitter (-1, -1H, -5H) 4 Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 133.3 MHz, loaded outputs, 15 pF load Measured at 66.67 MHz, loaded outputs, 30pF load Measured at 66.67 MHz, loaded outputs, 15 pF load 200 100 tJ Cycle-to-cycle jitter (-2,) 4 400 ps 375 tLOCK PLL Lock Time 4 Stable power supply, valid clock presented on REF and FBK pins 1.0 ms 3.3 `SpreadTrak' Zero Delay Buffer Notice: 6 of 13 The information in this document is subject to change without notice. August 2004 rev 2.0 Operating Conditions for ASM5I23S04A Industrial Temperature Devices Parameter VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance3 Description Min 3.0 -40 ASM5P23S04A Max 3.6 85 30 15 7 Unit V C pF pF pF Electrical Characteristics for ASM5I23S04A Industrial Temperature Devices Parameter VIL VIH IIL IIH VOL Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage 4 Test Conditions Min Max 0.8 Unit V V 2.0 VIN = 0V VIN = VDD IOL = 8mA (-1, -2) IOH = 12mA (-1H, -5H) IOL = -8mA (-1, -2) IOH = -12mA (-1H, -5H) Unloaded outputs 100MHz REF, Select inputs at VDD or GND 2.4 TBD TBD TBD 50.0 100.0 0.4 A A V VOH Output HIGH Voltage 4 V IDD Supply Current Unloaded outputs, 66MHz REF (-1, -2) Unloaded outputs, 33MHz REF (-1, -2) mA TBD 3.3 `SpreadTrak' Zero Delay Buffer Notice: 7 of 13 The information in this document is subject to change without notice. August 2004 rev 2.0 Switching Characteristics for ASM5I23S04A Industrial Temperature Devices All parameters are specified with loaded outputs Parameter t1 t1 t1 Description Output Frequency Output Frequency Output Frequency Duty Cycle = (t2 / t1) * 100 (-1, -2, -1H, -5H) Duty Cycle = (t2 / t1) * 100 (-1, -2, -1H, -5H) t3 Output Rise Time (-1, -2) Output Rise Time (-1, -2) Output Rise Time (-1H, -5H) Output Fall Time (-1, -2) Output Fall Time (-1, -2) Output Fall Time (-1H, -5H) 4 4 4 ASM5P23S04A Test Conditions 30-pF load, All devices 20-pF load, -1H, -5H devices 15-pF load, -1 and -2 devices Measured at 1.4V, FOUT = <66.66 MHz 30-pF load Measured at 1.4V, FOUT = <50 MHz 15-pF load Measured between 0.8V and 2.0V 30-pF load Measured between 0.8V and 2.0V 15-pF load Measured between 0.8V and 2.0V 30-pF load Measured between 2.0V and 0.8V 30-pF load Measured between 2.0V and 0.8V 15-pF load Measured between 2.0V and 0.8V 30-pF load 4 Min 10 10 10 40.0 Typ Max 100 133.3 133.3 Unit MHz MHz MHz % 50.0 60.0 45.0 50.0 55.0 % 2.50 ns 4 t3 1.50 ns 4 t3 1.50 ns 4 t4 2.50 ns 4 t4 1.50 ns 4 t4 1.25 200 200 200 400 0 0 1 250 500 ns Output-to-output skew on same bank (-1, -2) Output-to-output skew (-1H, -5H) All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded t5 ps Output bank A -to- output bank B skew (-1, -5H) Output bank A -to- output bank B skew (-2) t6 t7 t8 Delay, REF Rising Edge to FBK Rising Edge Device-to-Device Skew Output Slew Rate 4 4 4 Measured at VDD /2 Measured at VDD/2 on the FBK pins of the device Measured between 0.8V and 2.0V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs, 15 pF load ps ps V/ns 180 ps tJ Cycle-to-cycle jitter (-1, -1H, -5H) 4 Measured at 66.67 MHz, loaded outputs, 30 pF load Measured at 133.3 MHz, loaded outputs, 15 pF load 4 200 100 400 ps 380 tJ Cycle-to-cycle jitter (-2) Measured at 66.67 MHz, loaded outputs, 30pF load Measured at 66.67 MHz, loaded outputs, 15 pF load Stable power supply, valid clock presented on REF and FBK pins tLOCK PLL Lock Time 4 1.0 ms 3.3 `SpreadTrak' Zero Delay Buffer Notice: 8 of 13 The information in this document is subject to change without notice. August 2004 rev 2.0 Switching Waveforms Duty Cycle Timing t1 t2 ASM5P23S04A 1.4 V 1.4 V 1.4 V All Outputs Rise/Fall Time 2.0 V OUTPUT 0.8 V t3 t4 2.0 V 0.8 V 3.3 V 0V Output - Output Skew 1.4 V OUTPUT 1.4 V OUTPUT t5 Input - Output Propagation Delay V INPUT DD /2 V OUTPUT DD /2 t6 Device - Device Skew V FBK, Device 1 DD /2 V FBK, Device 2 DD /2 t7 3.3 `SpreadTrak' Zero Delay Buffer Notice: 9 of 13 The information in this document is subject to change without notice. August 2004 rev 2.0 Test Circuits Test Circuit #1 Test Circuit #2 ASM5P23S04A V 0.1 yF DD V OUTPUTS C 0.1 yF DD 1k OUTPUTS 1k LOAD 10 pF V 0.1 yF DD V GND 0.1 yF DD GND GND GND For parameter 8 (output slew rate) on -1H devices t 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 10 of 13 August 2004 rev 2.0 Package Information: 8-lead (150 Mil) Molded SOIC ASM5P23S04A E H D A D e B A1 L C Dimensions in inches Symbol Min A A1 B C D E H e L 0.053 0.004 0.013 0.007 0.188 0.150 0.228 Max 0.069 0.010 0.022 0.012 0.197 0.158 0.244 Dimensions in millimeters Min 1.35 0.10 0.33 0.18 4.78 3.80 5.80 Max 1.75 0.25 0.53 0.27 5.00 4.01 6.20 0.050 BSC 0.016 0 0.035 8 1.27 BSC 0.40 0 0.89 8 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 11 of 13 August 2004 rev 2.0 Ordering Information Ordering Code ASM5P23S04A-1-08-SR ASM5P23S04A-1-08-ST ASM5I23S04A-1-08-SR ASM5I23S04A-1-08-ST ASM5P23S04A-1H-08-SR ASM5P23S04A-1H-08-ST ASM5I23S04A-1H-08-SR ASM5I23S04A-1H-08-ST ASM5P23S04A-2-08-SR ASM5P23S04A-2-08-ST ASM5I23S04A-2-08-SR ASM5I23S04A-2-08-ST ASM5P23S04A-5H-08-SR ASM5P23S04A-5H-08-ST ASM5I23S04A-5H-08-SR ASM5I23S04A-5H-08-ST Package Type 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE 8-pin 150-mil SOIC-TAPE & REEL 8-pin 150-mil SOIC-TUBE ASM5P23S04A Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 12 of 13 August 2004 rev 2.0 ASM5P23S04A Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright (c) Alliance Semiconductor All Rights Reserved Part Number: ASM5P23S04A Document Version: 2.0 8_30_2004 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 (c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 3.3 `SpreadTrak' Zero Delay Buffer Notice: The information in this document is subject to change without notice. 13 of 13 |
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