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| Preliminary Technical Data FEATURES 150 ps propagation delay 25 ps overdrive and slew rate dispersion 8 GHz equivalent input rise time bandwidth 100 ps minimum pulse width 35 ps typical output rise/fall 10 ps deterministic jitter(DJ) 200 fs random jitter (RJ) -2 V to +3 V input range with +5 V/-5.2 V supplies On-chip terminations at both input pinsl Resistor-programmable hysteresis Differential latch control Power supply rejection > 70 dB Ultrafast SiGe Voltage Comparator ADCMP580/ADCMP581/ADCMP582 FUNCTIONAL BLOCK DIAGRAM VTP TERMINATION VP NONINVERTING INPUT VN INVERTING INPUT VTN TERMINATION ADCMP580/ ADCMP581/ ADCMP582 Q OUTPUT CML/ECL/ PECL Q OUTPUT LE INPUT HYS LE INPUT Figure 1. APPLICATIONS Automatic test equipment (ATE) High speed instrumentation Pulse spectroscopy Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Clock and data signal restoration The 5 V power supplies enable a wide -2 V to +3 V input range with logic levels referenced to the CML/NECL/PECL outputs. The three inputs have 50 on-chip termination resistors with the optional capability to be left open (on an individual pin basis) for applications requiring high impedance input. The CML output stage is designed to directly drive 400 mV into 50 transmission lines terminated to ground. The NECL output stages are designed to directly drive 400 mV into 50 terminated to -2 V. The PECL output stages are designed to directly drive 400 mV into 50 terminated to VCCO - 2 V. High speed latch and programmable hysteresis are also provided. The differential latch input controls are also 50 terminated to an independent VTT pin to interface to either CML or ECL or to PECL logic. The ADCMP580/ADCMP581/ADCMP582 are available in a 16-lead LFCSP package. GENERAL DESCRIPTION The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage comparators fabricated on Analog Devices, Inc.'s proprietary XFCB3 Silicon Germanium (SiGe) bipolar process. The ADCMP580 features CML output drivers; the ADCMP581 features reduced swing ECL (negative ECL) output drivers; and the ADCMP582 features reduced-swing PECL (positive ECL) output drivers. The three comparators offer 150 ps propagation delay and 100 ps minimum pulse width for 10 Gbps operation with 200 fs random jitter (RJ). Overdrive and slew rate dispersion is typically less than 25 ps. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 (c) 2004 Analog Devices, Inc. All rights reserved. 04672-0-001 Preliminary Technical Data TABLE OF CONTENTS Electrical Characteristics ................................................................. 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Thermal Considerations.............................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Application Information.................................................................. 9 Power/Ground Layout and Bypassing ....................................... 9 ADCMP58x Family of Output Stages ....................................... 9 ADCMP580/ADCMP581/ADCMP582 Using/Disabling the Latch Feature..............................................9 Optimizing High Speed Performance ..................................... 10 Comparator Propagation Delay Dispersion ........................... 10 Comparator Hysteresis .............................................................. 11 Minimum Input Slew Rate Requirement ................................ 11 Typical Application Circuits.......................................................... 12 Timing Information ....................................................................... 13 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14 REVISION HISTORY 6/04--Revision PrA Rev. PrA | Page 2 of 16 Preliminary Technical Data ELECTRICAL CHARACTERISTICS VCCI = +5.0 V, VEE = -5.0 V, VCCO = +3.3 V, TA = 25C, unless otherwise noted. Table 1. Parameter DC INPUT CHARACTERISTICS Input Voltage Range Input Differential Range Input Offset Voltage Offset Voltage Tempco Input Bias Current Input Bias Current Tempco Input Offset Current Input Capacitance Input Resistance Input Resistance, Differential Mode Input Resistance, Common Mode Active Gain Common-Mode Rejection Hysteresis LATCH ENABLE CHARACTERISTICS ADCMP580 (CML) Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time ADCMP581 (NECL) Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time ADCMP582 (PECL) Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time Latch Enable Input Impedance Latch to Output Delay Latch Minimum Pulse Width DC OUTPUT CHARACTERISTICS ADCMP580 (CML) Output Impedance Output Voltage High Level Output Voltage Low Level Output Voltage Differential Temperature Coefficient, VOH Temperature Coefficient, VOL ADCMP581 (NECL) Output Voltage High Level Output Voltage Low Level Output Voltage Differential Symbol VP, VN VOS VOS/dT IP, IN Condition ADCMP580/ADCMP581/ADCMP582 Min -2.0 -2.0 -5.0 Typ Max +3.0 +2.0 +5.0 30.0 5.0 52.5 Unit V V mV V/C A nA/C A pF k k dB dB mV Open termination CP, CN 47.5 Open termination Open termination AV CMRR VCM = -2.0 V to +3.0 V RHYS = 2.0 10.0 15.0 50.0 2.0 TBD 50 50 500 48 50 1 -0.8 0.2 tS tH VOD = 100 mV VOD = 100 mV -1.8 0.2 tS tH VOD = 100 mV VOD = 100 mV VCCO - 1.8 0.2 tS tH tPLOH, tPLOL tPL VOD = 100 mV VOD = 100 mV 47.5 VOD = 100 mV VOD = 100 mV 0.4 60 0 0 0.5 V V ps ps V V ps ps V V ps ps ps ps ps 0.4 25 0 +0.8 0.5 0.4 5 0 50.0 150 100 VCCO - 0.8 0.5 52.5 ZOUT VOH VOL VOH/dT VOL/dT VOH VOL 50 to GND 50 to GND 50 to GND 50 to GND 50 GND 50 to -2.0 V 50 to -2.0 V 50 to -2.0 V 47.5 -0.10 VOH - 0.45 350 50 -0.05 VOH - 0.40 400 TBD TBD -0.80 VOH - 0.40 400 52.5 0.00 VOH - 0.35 450 V V mV mV/C mV/C V V mV -0.90 VOH - 0.45 350 -0.70 VOH - 0.35 450 Rev. PrA | Page 3 of 16 Preliminary Technical Data Parameter ADCMP582 (PECL) Output Voltage High Level Output Voltage Low Level Output Voltage Differential AC PERFORMANCE Propagation Delay Propagation Delay Propagation Delay Tempco Prop Delay Skew--Rising Transition to Falling Transition Overdrive Dispersion Slew Rate Dispersion Pulse Width Dispersion Duty Cycle Dispersion Common-Mode Dispersion Equivalent Input Bandwidth1 Toggle Rate Deterministic Jitter Deterministic Jitter RMS Random Jitter Minimum Pulse Width Minimum Pulse Width Rise Time Fall Time POWER SUPPLY Positive Supply Voltage Negative Supply Voltage Logic Supply Voltage ADCMP580 (CML) Positive Supply Current Negative Supply Current Power Dissipation ADCMP581 (NECL) Positive Supply Current Negative Supply Current Power Dissipation ADCMP582 (PECL) Positive Supply Current Negative Supply Current Power Dissipation Power Supply Rejection (VCCI) Power Supply Rejection (VEE) Power Supply Rejection (VCCO) Symbol VOH VOL Condition 50 to VCCO - 2.0 V 50 to VCCO - 2.0 V 50 to VCCO - 2.0 V VOD = 200 mV VOD = 20 mV VOD = 200 mV, 5 V/ns ADCMP580/ADCMP581/ADCMP582 Min VCCO - 0.9 VOH - 0.45 350 Typ VCCO - 0.80 VOH - 0.40 400 150 165 0.5 10 10 15 25 5 10 5 5 8.0 12.5 10 TBD 0.2 100 80 35 35 +4.5 -5.5 +4.5/+2.0 VCCI = +5.0 V, 50 to Ground VEE = -5.0 V, 50 to Ground 50 to Ground VCCI = +5.0 V, 50 to -2 V VEE = -5.0 V, 50 to -2 V 50 to -2 V VCCI = +5.0 V, VCCO = +5.0 V 50 to VCCO - 2 V VEE = -5.0 V, 50 to VCCO - 2 V 50 to VCCO - 2 V VCCI=5.0 V + 5% VEE=-5.0 V + 5% VCCO=3.3 V + 5% +5.0 -5.0 +5.0/+2.5 6 43 244 6 28 218 47 28 253 70 75 70 +5.5 -4.5 +5.5/+3.0 8 50 260 8 35 240 55 35 275 Max VCCO- 0.70 VOH - 0.35 450 Unit V V mV ps ps ps/C ps ps ps ps ps ps ps ps/V GHz Gbps ps ps ps ps ps ps ps V V V mA mA mW mA mA mW mA mA mW dB dB dB tPD tPD/dT BWEQ DJ DJ RJ PWMIN PWMIN tR tF VCCI VEE VCCO IVCCI IVEE PD IVCCI IVEE PD IVCCI + IVCCO IVEE PD PSRVCCI PSRVEE PSRVCCO 50 mV < VOD < 1.0 V 5 mV < VOD < 1.0 V 2 V/ns to 10 V/ns 100 ps to 5 ns 1.0 V/ns, VCM = 0.0 V 1.0 V/ns, VCM = 2.0 V VOD = 0.4V , -2 V < VCM < 3 V 0.0 V to 400 mV input tR = tF = 25 ps, 20/80 >50% Output Swing VOD = 200 mV, 5 V/ns PRBS31 - 1 NRZ, 4 Gbps VOD = 200 mV, 5 V/ns PRBS31 - 1 NRZ, 10 Gbps VOD = 200 mV, 5 V/ns, 1.25 GHz tPD/PW < 5 ps tPD/PW < 10 ps 20/80 20/80 1 Equivalent Input Bandwidth assumes a simple first-order input response and is calculated with the following formula: BWEQ = 0.22/(trCOMP2 - trIN2), where trIN is the 20/80 transition time of a quasi-Gaussian input edge applied to the comparator input and trCOMP is the effective transition time digitized by the comparator. Rev. PrA | Page 4 of 16 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 2. Parameter SUPPLY VOLTAGES Positive Supply Voltage (VCCI to GND) Negative Supply Voltage (VEE to GND) Logic Supply Voltage (VCCO to GND) INPUT VOLTAGES Input Voltage Differential Input Voltage Input Voltage, Latch Enable HYSTERESIS CONTROL PIN Applied Voltage (HYS to VEE) Maximum Input/Output Current OUTPUT CURRENT ADCMP580 (CML) ADCMP581 (NECL) ADCMP582 (PECL) TEMPERATURE Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range Rating -0.5 V to +6.0 V -6.0 V to +0.5 V -0.5 V to +6.0 V ADCMP580/ADCMP581/ADCMP582 THERMAL CONSIDERATIONS The ADCMP580/ADCMP581/ADCMP582 LFCSP 16-lead package option has a JA (junction to ambient thermal resistance) of 70C/W in still air. Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. -3.0 V to +4.0 V -2.5 V to +2.5 V -2.5 V to +5.5 V -5.5 V to +0.5 V 1 mA -25 mA -40 mA -40 mA -40C to +85C 125C -65C to +150C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrA | Page 5 of 16 Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 15 GND 16 VCCI 15 GND 16 VCCI ADCMP580/ADCMP581/ADCMP582 16 VCCI 15 GND 14 HYS 14 HYS 14 HYS 13 VEE 13 VEE VTP 1 VP 2 VN 3 VTN 4 PIN 1 INDICATOR 12 GND 11 Q 10 Q 9 GND 04672-0-002 VTP 1 VP 2 VN 3 VTN 4 PIN 1 INDICATOR 12 GND 11 Q 10 Q 9 GND 04672-0-028 VTP 1 VP 2 VN 3 VTN 4 PIN 1 INDICATOR 13 VEE 12 VCCO 11 Q 10 Q 9 VCCO 04672-0-029 ADCMP580 TOP VIEW (Not to Scale) ADCMP581 TOP VIEW (Not to Scale) ADCMP582 TOP VIEW (Not to Scale) VTT 8 VTT 8 VCCI 5 VCCI 5 VCCI 5 Figure 2. ADCMP580 Pin Configuration Figure 3. ADCMP581 Pin Configuration Figure 4. ADCMP582 Pin Configuration Table 3. Pin Descriptions Pin No. 1 2 3 4 5, 16 6 Mnemonic VTP VP VN VTN VCCI LE Description Termination Resistor Return Pin for VP Input. Noninverting Analog Input. Inverting Analog Input. Termination Resistor Return Pin for VN Input. Positive Supply Voltage. Latch Enable Input Pin, Inverting Side. In compare mode (LE = low), the output tracks changes at the input of the comparator. In latch mode (LE = high), the output reflects the input state just prior to the comparator's being placed into latch mode. LE must be driven in compliment with LE. Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes at the input of the comparator. In latch mode (LE = low), the output reflects the input state just prior to the comparator's being placed into latch mode. LE must be driven in compliment with LE. Termination Return Pin for the LE/LE Input Pins. For the ADCMP580 (CML output stage), this pin should be connected to the GND ground. For the ADCMP581 (ECL output stage), this pin should be connected to the -2 V termination potential. For the ADCMP582 (PECL output stage), this pin should be connected to the VCCO - 2 V termination potential. Digital Ground Pin/Positive Logic Power Supply Terminal. For the ADCMP580/ADCMP581, this pin should be connected to the GND pin. For the ADCMP582, this pin should be connected to the positive logic power VCCO supply. Inverting Output. Q is logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE descriptions (Pins 6 to 7) for more information. Noninverting Output. Q is logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE descriptions (Pins 6 to 7) for more information. Negative Power Supply. Hysteresis Control. Leave this pin disconnected for zero hysteresis. Connect this pin to the VEE supply with a suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 9 for proper sizing of the HYS hysteresis control resistor. Analog Ground. The metallic back surface of the package is not electrically connected to any part of the circuit. It can be left floating for optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. 7 LE 8 VTT 9, 12 GND/VCCO 10 Q 11 Q 13 14 VEE HYS 15 Heatsink GND N/C Rev. PrA | Page 6 of 16 VTT 8 LE 7 LE 7 LE 7 LE 6 LE 6 LE 6 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS VCCI = +5.0 V, VEE = -5.0 V, VCCO = +3.3 V, TA = 25C, unless otherwise noted. ADCMP580/ADCMP581/ADCMP582 Figure 5. Propagation Delay vs. Input Overdrive Figure 8. Rise/Fall Time vs. Temperature Figure 6. Propagation Delay vs. Input Common Mode Figure 9. Hysteresis vs. RHYS Control Resistor Figure 7. Propagation Delay vs. Temperature Figure 10. Input Bias Current vs. Input Differential Rev. PrA | Page 7 of 16 Preliminary Technical Data ADCMP580/ADCMP581/ADCMP582 Figure 11. Input Bias Current vs. Temperature Figure 13. Output Levels vs. Temperature Figure 12. Input Offset Voltages vs. Temperature Rev. PrA | Page 8 of 16 Preliminary Technical Data APPLICATION INFORMATION POWER/GROUND LAYOUT AND BYPASSING The ADCMP58x family of comparators is designed for very high speed applications. Consequently, high speed design techniques must be used to achieve the specified performance. It is critically important to use low impedance supply planes, particularly for the negative supply (VEE), the output supply plane (VCCO) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for the switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. A 1 F electrolytic bypass capacitor should be placed within several inches of each power supply pin to ground. In addition, multiple high quality 0.1F bypass capacitors should be placed as close as possible to each of the VEE, VCCI, and VCCO supply pins and should be connected to the GND plane with redundant vias. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should be strictly avoided to maximize the effectiveness of the bypass at high frequencies. ADCMP580/ADCMP581/ADCMP582 GND 50 Q Q 16mA 04672-0-014 VEE Figure 14. Simplified Schematic Diagram of ADCMP580 CML Output Stage GND Q ADCMP58x FAMILY OF OUTPUT STAGES Specified propagation delay dispersion performance can be achieved by using proper transmission line terminations. The outputs of the ADCMP580 comparators are designed to directly drive 400 mV into 50 cable or microstrip/stripline transmission lines terminated with 50 referenced to the GND return. The CML output stage is shown in the simplified schematic diagram in Figure 14. The outputs are each backterminated with 50 for best transmission line matching. The outputs of the ADCMP581/ADCMP582 are illustrated in Figure 15 and should be terminated to -2 V for ECL outputs of ADCMP581 and VCCO - 2 V for PECL outputs of ADCMP582. As an alternative, Thevenin equivalent termination networks may also be used. If high speed CML signals must be routed more than a centimeter, then either microstrip or stripline techniques is required to ensure proper transition times and to prevent excessive output ringing and pulse-width-dependant propagation delay dispersion. Q VEE Figure 15. Simplified Schematic Diagram of the ADCMP581/ADCMP582 ECL Output Stage USING/DISABLING THE LATCH FEATURE The latch inputs (LE/LE) are active low for latch mode, and are internally terminated with 50 resistors to the VTT pin. When using the ADCMP580, VTT should be connected to ground. When using the ADCMP581, VTT should be connected to -2 V. When using the ADCMP582, VTT should be connected externally to VCCO - 2 V, preferably to its own low inductance plane. When using the ADCMP580/ADCMP582, the latch function can be disabled by connecting the LE pin to VEE with an external pull-down resistor and leaving the LE pin unconnected. To prevent excessive power dissipation, the resistor should be 1.5 k. When using the ADCMP581 comparators, the latch can be disabled by connecting the LE pin to GND with an external 450 resistor, and leaving the LE pin disconnected. Rev. PrA | Page 9 of 16 04672-0-015 Preliminary Technical Data OPTIMIZING HIGH SPEED PERFORMANCE As with any high speed comparator, proper design and layout techniques are essential to obtaining the specified performance. Stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and can cause oscillation. Discontinuities along input and output transmission lines can also severely limit the specified pulse width dispersion performance. For applications working in a 50 environment, input and output matching have a significant impact on data-dependant (or deterministic) jitter (DJ) and pulse width dispersion performance. The ADCMP58x family of comparators provides internal 50 termination resistors for both VP and VN inputs. The return side for each termination is pinned out separately with the VTP and VTN pins, respectively. If the a 50 termination is desired at one or both of the VP/VN inputs, the VTP and VTN pins can be connected (or disconnected) to (from) the desired termination potential as appropriate. The termination potential should be carefully bypassed using ceramic capacitors as discussed previously to prevent undesired aberrations on the input signal due to parasitic inductance in the termination return path. If a 50 termination is not desired, either one or both of the VTP/VTN termination pins can be left disconnected. In this case, the open pins should be left floating with no external pull downs or bypassing capacitors. For applications that require high speed operation, but do not have on-chip 50 termination resistors, some reflections should be expected because the comparator inputs can no longer provide matched impedance to the input trace leading up to the device. It then becomes important to back-match the drive source impedance to the input transmission path leading to the input to minimize multiple reflections. For applications in which the comparator is very close to the driving signal source, the source impedance should be minimized. High source impedance in combination with parasitic input capacitance of the comparator could cause undesirable degradation in bandwidth at the input, thus degrading the overall response. Although the ADCMP58x family of comparators has been designed to minimize input capacitance, some parasitic capacitance is inevitable. It is therefore recommended that the drive source impedance should be no more than 50 for best high speed performance. ADCMP580/ADCMP581/ADCMP582 COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP58x family of comparators has been specifically designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mV to 500 mV. Propagation delay dispersion is a change in propagation delays, which results from a change in the degree of overdrive or slew rate (how far or fast the input signal exceeds the switching threshold). The overall result is a higher degree of timing accuracy. Propagation delay dispersion is a specification which becomes important in critical timing applications such as data communication, automatic test and measurement, instrumentation, and event driven applications such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in the overall propagation delay as the input overdrive conditions are changed (Figure 16 and Figure 17). For the ADCMP58x family of comparators, dispersion is typically < 25 ps since the overdrive varies from 5 mV to 500 mV, and the input slew rate varies from 1 V/ns to 10 V/ns. This specification applies for both positive and negative signals since the ADCMP58x family of comparators has almost equal delays for positive- and negative-going inputs. 500mV OVERDRIVE INPUT VOLTAGE 5mV OVERDRIVE VN VOS DISPERSION Q/Q OUTPUT Figure 16. Propagation Delay--Overdrive Dispersion INPUT VOLTAGE 1V/ns VN VOS 10V/ns DISPERSION Q/Q OUTPUT Figure 17. Propagation Delay--Slew Rate Dispersion Rev. PrA | Page 10 of 16 04672-0-017 04672-0-016 Preliminary Technical Data COMPARATOR HYSTERESIS Adding hysteresis to a comparator is often desirable in a noisy environment or when the differential inputs are very small or slow moving. The transfer function for a comparator with hysteresis is shown in Figure 18. If the input voltage approaches the threshold from the negative direction, the comparator switches from a low to a high when the input crosses +VH/2. The new switching threshold becomes -VH/2. The comparator remains in the high state until the threshold -VH/2 is crossed coming from the positive direction. In this manner, noise centered on 0 V input does not cause the comparator to switch states unless it exceeds the region bounded by VH/2. The customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. A limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. The external feedback network can also introduce significant parasitics that will reduce high speed performance, and can even reduce overall stability in some cases. The ADCMP58x family of comparators offers a programmable hysteresis feature that can significantly improve the accuracy and stability of the desired hysteresis. By connecting an external pull-down resistor from the HYS pin to VEE, a variable amount of hysteresis can be applied. Leaving the HYS pin disconnected disables the feature and hysteresis is then less than 1 mV as specified. The maximum range of hysteresis that can be applied by using this method is approximately 25 mV. Figure 19 illustrates the amount of applied hysteresis as a function of external resistor value. The advantage of applying hysteresis in this manner is improved accuracy, stability, and reduced component count. An external bypass capacitor is not required on the HYS pin because it would likely degrade the jitter performance of the device. ADCMP580/ADCMP581/ADCMP582 -VH 2 0V +VH 2 INPUT 1 0 04672-0-018 OUTPUT Figure 18. Comparator Hysteresis Transfer Function of the ADCMP580/ADCMP581 Figure 19. Comparator Hysteresis vs. RHYS Control Resistor MINIMUM INPUT SLEW RATE REQUIREMENT As with all high speed comparators, a minimum slew rate must be met to ensure that the device does not oscillate when the input signal crosses the threshold. This oscillation is due in part to the high input bandwidth of the comparator and the feedback parasitics inherent in the package. Analog Devices recommends a minimum slew rate of 50 V/s to ensure a clean output transition from the ADCMP58x family of comparators unless hysteresis is programmed as discussed previously. Rev. PrA | Page 11 of 16 Preliminary Technical Data TYPICAL APPLICATION CIRCUITS GND VTP VIN VP VN VTN ADCMP580/ADCMP581/ADCMP582 GND 50 50 75 75 100 100 50 04672-0-021 Q ADCMP580 Q ADCMP580 LATCH INPUTS LATCH INPUTS Figure 20. Zero-Crossing Detector with CML Outputs Figure 21. Interfacing CML to a 50 Ground-Terminated Instrument GND VTP VP VN VP VN VTN 50 50 Q ADCMP580 Q VP VN ADCMP580 LATCH INPUTS 04672-0-022 VEE Figure 22. LVDS to a 50 Back-Terminated (RS)ECL Receiver Figure 23. Disabling the Latch Feature GND 50 VIN VTH + 50 Q Q ADCMP580 - ADCMP580 HYS 04672-0-023 LATCH INPUTS VEE Figure 24. Comparator with -2 V to +3 V Input Range Figure 25. Adding Hysteresis Using the HYS Control Rev. PrA | Page 12 of 16 04672-0-026 0 TO 5k 50 50 04672-0-025 1.5k 50 50 04672-0-024 50 Preliminary Technical Data TIMING INFORMATION ADCMP580/ADCMP581/ADCMP582 Figure 26 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 4 provides a definition of the terms shown in the figure. LATCH ENABLE 50% LATCH ENABLE tS tH tPL DIFFERENTIAL INPUT VOLTAGE VN VOD VN VOS tPDL Q OUTPUT tPLOH 50% tPDH tF 50% Q OUTPUT tR Figure 26. Comparator Timing Diagram Table 4. Timing Descriptions Symbol tPDH tPDL tPLOH tPLOL tH tPL tS tR tF VOD Timing Input to output high delay Input to output low delay Latch enable to output high delay Latch enable to output low delay Minimum hold time Minimum latch enable pulse width Minimum setup time Output rise time Output fall time Voltage overdrive Description Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output high-to-low transition. Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to the 50% point of an output low-to-high transition. Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to the 50% point of an output high-to-low transition. Minimum time after the negative transition of the Latch Enable signal that the input signal must remain unchanged to be acquired and held at the outputs. Minimum time that the Latch Enable signal must be high to acquire an input signal change. Minimum time before the negative transition of the Latch Enable signal that an input signal change must be present to be acquired and held at the outputs. Amount of time required to transition from a low to a high output as measured at the 20% and 80% points. Amount of time required to transition from a high to a low output as measured at the 20% and 80% points. Difference between the input voltages VP and VN. Rev. PrA | Page 13 of 16 04672-0-027 tPLOL Preliminary Technical Data OUTLINE DIMENSIONS ADCMP580/ADCMP581/ADCMP582 3.00 BSC SQ 0.45 PIN 1 INDICATOR TOP VIEW 2.75 BSC SQ 0.50 BSC 12 MAX 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.20 REF 0.60 MAX 0.50 0.40 0.30 PIN 1 INDICATOR 16 1 13 12 BOTTOM VIEW 1.65 1.50 SQ* 1.35 9 8 5 4 0.25 MIN 1.50 REF * COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION Figure 27. 16-Lead Lead Frame Chip Scale Package [LFCSP] (CP-16) Dimensions shown in millimeters ORDERING GUIDE Model ADCMP580BCP ADCMP581BCP ADCMP582BCP Temperature Range -40C to +85C -40C to +85C -40C to +85C Package Description LFCSP-16 LFCSP-16 LFCSP-16 Package Option CP-16 CP-16 CP-16 Rev. PrA | Page 14 of 16 Preliminary Technical Data NOTES ADCMP580/ADCMP581/ADCMP582 Rev. PrA | Page 15 of 16 Preliminary Technical Data NOTES ADCMP580/ADCMP581/ADCMP582 (c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04672-0-6/04(PrA) Rev. PrA | Page 16 of 16 |
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