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8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Parallel Interface AD5424/AD5433/AD5445*
FEATURES 2.5 V to 5.5 V Supply Operation Fast Parallel Interface (17 ns Write Cycle) 10 MHz Multiplying Bandwidth 10 V Reference Input Extended Temperature Range -40 C to +125 C 20-Lead TSSOP and Chip Scale (4 mm 4 mm) Packages 8-, 10-, and 12-Bit Current Output DACs Upgrades to AD7524/AD7533/AD7545 Pin Compatible 8-, 10-, and 12-Bit DACs in Chip Scale Guaranteed Monotonic 4-Quadrant Multiplication Power-On Reset with Brownout Detection Readback Function 0.4 A Typical Power Consumption APPLICATIONS Portable Battery-Powered Applications Waveform Generators Analog Processing Instrumentation Applications Programmable Amplifiers and Attenuators Digitally-Controlled Calibration Programmable Filters and Oscillators Composite Video Ultrasound Gain, Offset, and Voltage Trimming GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
VDD VREF R 8-/10-/12-BIT R-2R DAC RFB IOUT1 IOUT 2
AD5424/ AD5433/ AD5445
POWER-ON RESET
DAC REGISTER
CS R/W
INPUT LATCH
GND
DB0 DATA INPUTS
DB7/DB9/DB11
The AD5424/AD5433/AD5445 are CMOS 8-, 10-, and 12-bit current output digital-to-analog converters (DACs), respectively. These devices operate from a 2.5 V to 5.5 V power supply, making them suited to battery-powered applications and many other applications. These DACs utilize data readback allowing the user to read the contents of the DAC register via the DB pins. On power-up, the internal register and latches are filled with 0s and the DAC outputs are at zero scale. As a result of manufacture on a CMOS submicron process, they offer excellent 4-quadrant multiplication characteristics, with large signal multiplying bandwidths of up to 10 MHz.
The applied external reference input voltage (VREF) determines the full-scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full-scale voltage output when combined with an external I-to-V precision amplifier. While these devices are upgrades of AD7524/AD7533/AD7545 in multiplying bandwidth performance, they have a latched interface and cannot be used in transparent mode. The AD5424 is available in small 20-lead LFCSP and 16-lead TSSOP packages, while the AD5433/AD5445 DACs are available in small 20-lead LFCSP and TSSOP packages.
*U.S. Patent No. 5,689,257
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD5424/AD5433/AD5445-SPECIFICATIONS1
(VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = O V. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured with OP1177, AC performance with AD8038, unless otherwise noted.)
Parameter STATIC PERFORMANCE AD5424 Resolution Relative Accuracy Differential Nonlinearity AD5433 Resolution Relative Accuracy Differential Nonlinearity AD5445 Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temperature Coefficient2 Output Leakage Current2 REFERENCE INPUT2 Reference Input Range VREF Input Resistance RFB Resistance Input Capacitance Code 0 Code 4095 DIGITAL INPUTS/OUTPUT2 Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIL Input Capacitance VDD = 4.5 V to 5.5 V Output Low Voltage, VOL Output High Voltage, VOH VDD = 2.5 V to 3.6 V Output Low Voltage, VOL Output High Voltage, VOH DYNAMIC PERFORMANCE2 Reference Multiplying Bandwidth Output Voltage Settling Time AD5424 AD5433 AD5445 Digital Delay 10% to 90% Settling Time Digital to Analog Glitch Impulse Multiplying Feedthrough Error Min Typ Max Unit Conditions
8 0.25 0.5 10 0.5 1 12 1 -1/+2 10 10 20
Bits LSB LSB Bits LSB LSB
Guaranteed monotonic
Guaranteed monotonic
5
Bits LSB LSB Guaranteed monotonic mV ppm FSR/ C nA Data = 0x0000, TA = 25 C, IOUT1 nA Data = 0x0000, IOUT1 V k k pF pF V V A pF V V V V MHz ISINK = 200 A ISOURCE = 200 A ISINK = 200 A ISOURCE = 200 A VREF = 3.5 V; DAC loaded all 1s VREF = 10 V, RLOAD = 100 , CLOAD = 15 pF Measured to 16 mV of full scale Measured to 4 mV of full scale Measured to 1 mV of full scale Interface delay time Rise and Fall time, VREF = 10 V, RLOAD = 100 1 LSB change around major carry, VREF = 0 V DAC latch loaded with all 0s. VREF = 3.5 V Reference = 1 MHz Reference = 10 MHz
8 8
10 10 10 3 5
12 12 6 8
Input resistance TC = -50 ppm/ C Input resistance TC = -50 ppm/ C
1.7 0.6 1 10 0.4 VDD - 1 0.4 VDD - 0.5 10 30 35 80 20 15 2 70 48 60 70 120 40 30
4
ns ns ns ns ns nV-s dB dB
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AD5424/AD5433/AD5445
Parameter Output Capacitance IOUT2 IOUT1 Digital Feedthrough Total Harmonic Distortion Digital THD Clock = 10 MHz 50 kHz fOUT Output Noise Spectral Density SFDR Performance (Wide Band) Clock = 10 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Clock = 25 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT SFDR Performance (Narrow Band) Clock = 10 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Clock = 25 MHz 500 kHz fOUT 100 kHz fOUT 50 kHz fOUT Intermodulation Distortion Clock = 10 MHz f1 = 400 kHz, f2 = 500 kHz f1 = 40 kHz, f2 = 50 kHz Clock = 25 MHz f1 = 400 kHz, f2 = 500 kHz f1 = 40 kHz, f2 = 50 kHz POWER REQUIREMENTS Power Supply Range IDD 2.5 0.4
NOTES 1 Temperature range is as follows: Y version: -40 C to +125 C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
Min
Typ 22 10 12 25 1 -81
Max 25 12 17 30
Unit pF pF pF pF nV-s dB
Conditions All 0s loaded All 1s loaded All 0s loaded All 1s loaded Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s VREF = 3.5 V pk-pk; all 1s loaded, f = 100 kHz
65 25
dB nVHz
@ 1 kHz AD5445, 65k codes, VREF = 3.5 V
55 63 65 50 60 62
dB dB dB dB dB dB AD5445, 65k codes, VREF = 3.5 V
73 80 87 70 75 80
dB dB dB dB dB dB AD5445, 65k codes, VREF = 3.5 V
65 72 51 65 5.5 0.6 5
dB dB dB dB V A A
TA = 25 C, logic inputs = 0 V or VDD Logic inputs = 0 V or VDD
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AD5424/AD5433/AD5445 TIMING CHARACTERISTICS1, 2 (V
Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 VDD = 2.5 V to 5.5 V 0 0 10 6 0 5 9 20 40 5 10
REF
= 5 V, IOUT2 = O V. All specifications TMIN to TMAX, unless otherwise noted.)
Unit ns min ns min ns min ns min ns min ns min ns min ns typ ns max ns typ ns max Conditions/Comments R/W to CS setup time R/W to CS hold time CS low time (write cycle) Data setup time Data hold time R/W high to CS low CS min high time Data access time Bus relinquish time
VDD = 4.5 V to 5.5 V 0 0 10 6 0 5 7 10 20 5 10
NOTES 1 See Figure 1. Temperature range is as follows: Y version: -40 C to +125 C. Guaranteed by design and characterization, not subject to production test. 2 All input signals are specified with tr = tf = 1 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2. Digital output timing measured with load circuit in Figure 2. Specifications subject to change without notice.
R/W
t1
t2
t6
t2
t7
CS
t3 t4 t5 t8
DATA VALID
t9
DATA
DATA VALID
Figure 1. Timing Diagram
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AD5424/AD5433/AD5445
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25 C, unless otherwise noted.)
200 A TO OUTPUT PIN IOL VOH (MIN) + VOL (MAX) CL 50pF 200 A IOH 2
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VREF, RFB to GND . . . . . . . . . . . . . . . . . . . . . . -12 V to +12 V IOUT1, IOUT2 to GND . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Logic Inputs and Output2 . . . . . . . . . . . -0.3 V to VDD +0.3 V Operating Temperature Range Extended Industrial (Y Version) . . . . . . . . -40 C to +125 C Storage Temperature Range . . . . . . . . . . . . . -65 C to +150 C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C 16-Lead TSSOP JA Thermal Impedance . . . . . . . . . 150 C/W 20-Lead TSSOP JA Thermal Impedance . . . . . . . . . 143 C/W 20-Lead LFCSP JA Thermal Impedance . . . . . . . . . 135 C/W Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300 C IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235 C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at DBx, CS, and R/W, will be clamped by internal diodes.
Figure 2. Load Circuit for Data Output Timing Specifications
ORDERING GUIDE
Model AD5424YRU AD5424YRU-REEL AD5424YRU-REEL7 AD5424YCP AD5424YCP-REEL AD5424YCP-REEL7 AD5433YRU AD5433YRU-REEL AD5433YRU-REEL7 AD5433YCP AD5433YCP-REEL AD5433YCP-REEL7 AD5445YRU AD5445YRU-REEL AD5445YRU-REEL7 AD5445YCP AD5445YCP-REEL AD5445YCP-REEL7 EVAL-AD5424EB EVAL-AD5433EB EVAL-AD5445EB
Resolution INL (Bits) (LSB) 8 8 8 8 8 8 10 10 10 10 10 10 12 12 12 12 12 12 0.25 0.25 0.25 0.25 0.25 0.25 0.5 0.5 0.5 0.5 0.5 0.5 1 1 1 1 1 1
Temperature Range -40 -40 -40 -40 -40 -40 -40 -40 -40 -40 -40 -40 -40 -40 -40 -40 -40 -40 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C to +125 C C C C C C C C C C C C C C C C C C
Package Description TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) LFCSP (Chip Scale Package) LFCSP (Chip Scale Package) LFCSP (Chip Scale Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) LFCSP (Chip Scale Package) LFCSP (Chip Scale Package) LFCSP (Chip Scale Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) LFCSP (Chip Scale Package) LFCSP (Chip Scale Package) LFCSP (Chip Scale Package) Evaluation Kit Evaluation Kit Evaluation Kit
Package Option RU-16 RU-20 RU-20 CP-20 CP-20 CP-20 RU-20 RU-20 RU-20 CP-20 CP-20 CP-20 RU-20 RU-20 RU-20 CP-20 CP-20 CP-20
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5424/AD5433/AD5445 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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AD5424/AD5433/AD5445
PIN CONFIGURATIONS TSSOP
IOUT1 1 IOUT2 2 GND 3 DB7 4 DB6 5 DB5 6 DB4 7 DB3 8
16 R FB
LFCSP
20 IOUT2 19 IOUT1 18 RFB 17 V REF 16 V DD
GND DB7 DB6 DB5 DB4 1 2 3 4 5
AD5424
(Not to Scale)
15 VREF 14 V DD 13 R/W 12 CS 11 DB0 (LSB) 10 DB1 9 DB2
PIN 1 INDICATOR
AD5424
TOP VIEW
15 R/W 14 CS 13 NC 12 NC 11 NC
NC = NO CONNECT
AD5424 PIN FUNCTION DESCRIPTIONS
Pin No. TSSOP LFCSP 1 2 3 4-11 12 13 14 15 16 19 20 1 2-9 10-13 14 15 16 17 18
Mnemonic IOUT1 IOUT2 GND DB7-DB0 NC CS R/W VDD VREF RFB
Function DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Ground Parallel Data Bits 7 to 0. No Internal Connection. Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Rising edge of CS loads data. Read/Write. When low, used in conjunction with CS to load parallel data. When high, use with CS to readback contents of DAC register. Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. DAC Reference Voltage Input Terminal. DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.
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DB3 6 DB2 7 DB1 8 DB0 9 NC 10
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AD5424/AD5433/AD5445
PIN CONFIGURATIONS TSSOP
IOUT1 1 IOUT2 2 GND 3 DB9 4 DB8 5 DB7 6 DB6 7 DB5 8 DB4 9 DB3 10 NC = NO CONNECT
20 R FB
LFCSP
20 IOUT2 19 IOUT1 18 RFB 17 V REF 16 V DD GND DB9 DB8 DB7 DB6 1 2 3 4 5
AD5433
(Not to Scale)
19 VREF 18 VDD 17 R/W 16 CS 15 NC 14 NC 13 DB0 (LSB) 12 DB1 11 DB2
PIN 1 INDICATOR
AD5433
TOP VIEW
15 R/W 14 CS 13 NC 12 NC 11 DB0
NC = NO CONNECT
AD5433 PIN FUNCTION DESCRIPTIONS
Pin No. TSSOP LFCSP 1 2 3 4-13 14, 15 16 17 18 19 20 19 20 1 2-11 12, 13 14 15 16 17 18
Mnemonic Function IOUT1 IOUT2 GND DB9-DB0 NC CS R/W VDD VREF RFB DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Ground Parallel Data Bits 9 to 0. Not Internally Connected. Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Rising edge of CS loads data. Read/Write. When low, used in conjunction with CS to load parallel data. When high, use with CS to readback contents of DAC register. Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. DAC Reference Voltage Input Terminal. DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.
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DB5 6 DB4 7 DB3 8 DB2 9 DB1 10
AD5424/AD5433/AD5445
PIN CONFIGURATIONS TSSOP
IOUT1 1 IOUT2 2 GND 3 DB11 4 DB10 5 DB9 6 DB8 7 DB7 8 DB6 9 DB5 10
20
LFCSP
RFB VREF VDD R/W CS DB0 (LSB) DB1 DB2 DB3 DB4
GND DB11 DB10 DB9 DB8 1 2 3 4 5
AD5445
(Not to Scale)
19 18 17 16 15 14 13 12 11
20 IOUT2 19 IOUT1 18 RFB 17 V REF 16 VDD
PIN 1 INDICATOR
AD5445
TOP VIEW
15 R/W 14 CS 13 DB0 12 DB1 11 DB2
AD5445 PIN FUNCTION DESCRIPTIONS
Pin No. TSSOP LFCSP Mnemonic 1 2 3 4-15 16 17 18 19 20 19 20 1 2-13 14 15 16 17 18 IOUT1 IOUT2 GND DB11-DB0 CS R/W VDD VREF RFB
Function DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Ground Pin. Parallel Data Bits 11 to 0. Chip Select Input. Active low. Rising edge of CS loads data. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. Read/Write. When low, used in conjunction with CS to load parallel data. When high, use with CS to readback contents of DAC register. Positive Power Supply Input. These parts can be operated from a supply of +2.5 V to +5.5 V. DAC Reference Voltage Input Terminal. DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.
-8-
DB7 6 DB6 7 DB5 8 DB4 9 DB3 10
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Typical Performance Characteristics-AD5424/AD5433/AD5445
0.20 0.15 0.10 TA = 25 C VREF = 10V VDD = 5V
0.5 0.4 0.3 0.2 TA = 25 C VREF = 10V VDD = 5V
1.0 0.8 0.6 0.4 TA = 25 C VREF = 10V VDD = 5V
INL (LSB)
INL (LSB)
INL (LSB)
0.05 0
0.1 0 -0.1 -0.2
0.2 0 -0.2 -0.4 -0.6 -0.8
-0.05 -0.10
-0.3
-0.15 -0.20
-0.4
0 50 100 150 CODE 200 250
-0.5
0
200
400 600 CODE
800
1000
-1.0
0
500 1000 1500 2000 2500 3000 3500 4000 CODE
TPC 1. INL vs. Code (8-Bit DAC)
TPC 2. INL vs. Code (10-Bit DAC)
TPC 3. INL vs. Code (12-Bit DAC)
0.20 0.15 0.10 DNL (LSB)
DNL (LSB)
0.5 TA = 25 C VREF = 10V VDD = 5V 0.4 0.3 0.2
DNL (LSB)
1.0 TA = 25 C VREF = 10V VDD = 5V 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0 200 400 600 CODE 800 1000 -1.0 0 500 1000 1500 2000 2500 3000 3500 4000 CODE TA = 25 C VREF = 10V VDD = 5V
0.05 0 -0.05 -0.10 -0.15 -0.20 250
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
0
50
100
150 CODE
200
TPC 4. DNL vs. Code (8-Bit DAC)
TPC 5. DNL vs. Code (10-Bit DAC)
TPC 6. DNL vs. Code (12-Bit DAC)
0.6 0.5
-0.40 TA = 25 C VREF = 10V VDD = 5V
5 4 3 2 VDD = 5V
-0.45 0.4 MAX INL 0.3 0.2 0.1 0 MIN INL -0.1 -0.65 -0.2 -0.3 2 3 4 5 6 7 8 REFERENCE VOLTAGE 9 10 -0.70 2 TA = 25 C VREF = 10V VDD = 5V -0.50
ERROR (mV)
DNL (LSB)
INL (LSB)
1 0 -1 -2 VDD = 2.5V
-0.55
-0.60 MIN DNL
-3 -4
VREF = 10V
3
4 5 6 7 8 REFERENCE VOLTAGE
9
10
-5 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE ( C)
TPC 7. INL vs. Reference Voltage, AD5445
TPC 8. DNL vs. Reference Voltage, AD5445
TPC 9. Gain Error vs. Temperature
REV. 0
-9-
AD5424/AD5433/AD5445
2.0 1.5 1.0 0.5
LSB
4 3 TA = 25 C VREF = 2.5V VDD = 3V MAX INL MAX DNL
0.5 0.4 0.3 0.2
VOLTAGE (mV)
MAX INL MAX DNL
TA = 25 C VREF = 0V VDD = 3V LSB
2 1 0 -1
TA = 25 C VREF = 0V VDD = 3V AND 5V GAIN ERROR
0.1 0 -0.1 -0.2 -0.3 OFFSET ERROR
0 -0.5 -1.0 -1.5 -2.0 MIN INL MIN DNL
MIN DNL
-2 -3 -4 MIN INL
-0.4 -0.5 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VBIAS (V)
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VBIAS (V)
-5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VBIAS (V)
TPC 10. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445
TPC 11. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445
TPC 12. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2
0.5 0.4
3
2
TA = 25 C VREF = 0V VDD = 5V
MAX INL
4 3 2 TA = 25 C VREF = 2.5V VDD = 5V MAX DNL
0.3 0.2
VOLTAGE (mV)
GAIN ERROR
1
LSB
1 MAX DNL
LSB
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 TA = 25 C VREF = 2.5V VDD = 3V AND 5V 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VBIAS (V)
-2 0
0 -1 MAX INL MIN DNL
OFFSET ERROR
-1 MIN INL
-2 -3
MIN DNL -3 0.5 1.0 1.5 VBIAS (V) 2.0 2.5
-4 -5 0.5 MIN INL 1.0 VBIAS (V) 1.5 2.0
TPC 13. Gain and Offset Errors vs. VBIAS Voltage Applied to IOUT2
TPC 14. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445
TPC 15. Linearity vs. VBIAS Voltage Applied to IOUT2, AD5445
8 TA = 25 C 7
1.6 1.4
0.50 0.45 0.40 VDD = 5V ALL 0s ALL 1s TA = 25 C
IOUT LEAKAGE (nA)
6 CURRENT (mA) 5 VDD = 5V 4 3 2 1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) VDD = 3V VDD = 2.5V
1.2 1.0 0.8 0.6 0.4 0.2 0 -40 -20 IOUT1 VDD 3V
CURRENT ( A)
IOUT1 VDD 5V
0.35 0.30 0.25 0.20 VDD = 2.5V 0.15 ALL 1s 0.10 0.05 ALL 0s
0 20 40 60 80 TEMPERATURE ( C)
100 120
0 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE ( C)
TPC 16. Supply Current vs. Logic Input Voltage (Driving DB0-DB11, All Other Digital Inputs @ Supplies)
TPC 17. IOUT1 Leakage Current vs. Temperature
TPC 18. Supply Current vs. Temperature
-10-
REV. 0
AD5424/AD5433/AD5445
14 12 10
IDD (mA)
TA = 25 C LOADING ZS TO FS VDD = 5V
8 6 VDD = 3V 4 VDD = 2.5V 2 0 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz)
6 0 -6 -12 -18 -24 -30 -36 -42 -48 -54 -60 -66 -72 -78 -84 -90 -96 -102 1
TA = 25 C LOADING ZS TO FS
ALL ON DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0.2
0
GAIN (dB)
GAIN (dB)
-0.2
-0.4 TA = 25 C VDD = 5V VREF = 3.5V CCOMP = 1.8pF AD8038 AMPLIFIER AD5445 DAC 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz)
ALL OFF
TA = 25 C VDD = 5V VREF = 3.5V INPUT CCOMP = 1.8pF AD8038 AMPLIFIER AD5445 DAC
-0.6
10
100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz)
-0.8
TPC 19. Supply Current vs. Update Rate
TPC 20. Reference Multiplying Bandwidth vs. Frequency and Code
TPC 21. Reference Multiplying Bandwidth--All Ones Loaded
3
TA = 25 C VDD = 5V AD5445
OUTPUT VOLTAGE (V)
0.045 0.040 0.035 0.030 0.025 0.020 0.015 0.010 0.005 0 -0.005 -0.010 7FF TO 800H VDD = 5V
OUTPUT VOLTAGE (V)
0 GAIN (dB)
TA = 25 C VREF = 0V AD8038 AMPLIFIER CCOMP = 1.8pF
-1.68 -1.69 -1.70 -1.71 -1.72 -1.73 -1.74 -1.75 -1.76 7FF TO 800H VDD = 5V
TA = 25 C VREF = 3.5V AD8038 AMPLIFIER CCOMP = 1.8pF
VDD = 3V 800 TO 7FFH VDD = 3V
VDD = 3V 800 TO 7FFH VDD = 5V VDD = 3V
-3
-6
-9
VREF = VREF = VREF = VREF = VREF =
2V, AD8038 CC 1.47pF 2V, AD8038 CC 1pF 0.15V, AD8038 CC 1pF 0.15V, AD8038 CC 1.47pF 3.51V, AD8038 CC 1.8pF
VDD = 5V 0 20 40 60 80 100 120 140 160 180 200 TIME (ns)
10k
100k 1M 10M FREQUENCY (Hz)
100M
-1.77
0
20 40 60 80 100 120 140 160 180 200 TIME (ns)
TPC 22. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor
TPC 23. Midscale Transition, VREF = 0 V
TPC 24. Midscale Transition, VREF = 3.5 V
20
TA = 25 C VDD = 3V 0 AMP = AD8038
-60
TA = 25 C VDD = 3V -65 VREF = 3.5 V p-p
100 MCLK = 1MHz 80
TA = 25 C VREF = 3.5V AD8038 AMPLIFIER AD5445
-20
-70
THD + N (dB)
PSRR (dB)
SFDR (dB)
-40 -60 -80 -100 -120
60
MCLK = 200kHz
MCLK = 0.5MHz
-75
FULL SCALE ZERO SCALE
40
-80
20
-85
1
10
100 1k 10k 100k FREQUENCY (Hz)
1M
10M
-90 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M
0 0 20 40 60 80 100 120 140 160 180 200 fOUT (kHz)
TPC 25. Power Supply Rejection vs. Frequency
TPC 26. THD and Noise vs. Frequency
TPC 27. Wideband SFDR vs. fOUT Frequency
REV. 0
-11-
AD5424/AD5433/AD5445
90 MCLK = 5MHz 80 70 MCLK = 10MHz
0 -10 -20 -30
SFDR (dB)
TA = 25 C VDD = 5V AMP = AD8038 AD5445 65k CODES
SFDR (dB)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 TA = 25 C VDD = 5V AMP = AD8038 AD5445 65k CODES
SFDR (dB)
60 50 40 30 20 10 0 TA = 25 C VREF = 3.5V AD8038 AMPLIFIER AD5445 0 100 200 300 400 500 600 700 800 900 1000 fOUT (kHz) MCLK = 25MHz
-40 -50 -60 -70 -80 -90 0 2 4 6 8 FREQUENCY (MHz) 10 12
-100
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz)
TPC 28. Wideband SFDR vs. fOUT Frequency
TPC 29. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz
TPC 30. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz
0 -10 -20 -30 TA = 25 C VDD = 5V AMP = AD8038 AD5445 65k CODES
0 -10 -20 -30
SFDR (dB)
TA = 25 C VDD = 3V AMP = AD8038 AD5445 65k CODES SFDR (dB)
20 0 -20 -40 -60 -80 -100 -120 50 60 70 80 90 100 110 120 130 140 150 FREQUENCY (MHz) TA = 25 C VDD = 3V AMP = AD8038 AD5445 65k CODES
SFDR (dB)
-40 -50 -60 -70 -80 -90
-40 -50 -60 -70 -80 -90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz)
-100 250 300 350 400 450 500 550 600 650 700 750 FREQUENCY (kHz)
TPC 31. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz
TPC 32. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz
TPC 33. Narrow-Band SFDR, fOUT = 100 kHz, MCLK = 25 MHz
0 -10 -20 -30 -40
(dB) (dB)
0 TA = 25 C VDD = 3V AMP = AD8038 AD5445 65k CODES -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 70 75 80 85 90 95 100 105 110 115 120 FREQUENCY (MHz) (dB) TA = 25 C VDD = 3V AMP = AD8038 AD5445 65k CODES
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 25 30 35 40 45 50 55 60 65 70 FREQUENCY (MHz) MCLK 10MHz VDD 5V TA = 25 C VDD = 5V AMP = AD8038 AD5445 65k CODES
-50 -60 -70 -80 -90
-100 200 250 300 350 400 450 500 550 600 650 700 FREQUENCY (MHz)
TPC 34. Narrow-Band IMD, fOUT = 400 kHz, 500 kHz, Clock = 10 MHz
TPC 35. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
TPC 36. Narrow-Band IMD, fOUT = 40 kHz, 50 kHz, Clock = 10 MHz
-12-
REV. 0
AD5424/AD5433/AD5445
0 -10 -20 -30 -40
(dB) (dB)
0 TA = 25 C VDD = 5V AMP = AD8038 AD5445 65k CODES -10 -20 -30 -40 -50 -60 -70 -80 -90 0 50 100 150 200 250 300 350 400 FREQUENCY (kHz) -100 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz) TA = 25 C VDD = 5V AMP = AD8038 AD5445 65k CODES
-50 -60 -70 -80 -90
-100
TPC 37. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz
TPC 38. Wideband IMD, fOUT = 60 kHz, 50 kHz, Clock = 10 MHz
REV. 0
-13-
AD5424/AD5433/AD5445
TERMINOLOGY Relative Accuracy Digital Feedthrough
Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for 0 and full scale and is normally expressed in LSBs or as a percentage of full-scale reading.
Differential Nonlinearity
When the device is not selected, high frequency logic activity on the device digital inputs may be capacitively coupled through the device to show up as noise on the IOUT pins and subsequently into the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of -1 LSB max over the operating temperature range ensures monotonicity.
Gain Error
This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal, when all 0s are loaded to the DAC.
Total Harmonic Distortion (THD)
Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is VREF - 1 LSB. Gain error of the DACs is adjustable to 0 with external resistance.
Output Leakage Current
The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonics are included, such as second to fifth. THD = 20 log
(V
2
2
+ V3 + V4 + V5 V1
2
2
2
)
Output leakage current is current that flows in the DAC ladder switches when these are turned off. For the IOUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current will flow in the IOUT2 line when the DAC is loaded with all 1s.
Output Capacitance
Digital Intermodulation Distortion
Second-order intermodulation distortion (IMD) measurements are the relative magnitude of the fa and fb tones generated digitally by the DAC and the second-order products at 2fa - fb and 2fb - fa.
Spurious-Free Dynamic Range (SFDR)
Capacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling Time
This is the amount of time it takes for the output to settle to a specified level for a full scale input change. For these devices, it is specified with a 100 resistor to ground. The settling time specification includes the digital delay from CS rising edge to the full-scale output change.
Digital to Analog Glitch lmpulse
It is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. SFDR is the measure of difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full Nyquist bandwidth (half the DAC sampling rate, or fS/2). Narrow band SFDR is a measure of SFDR over an arbitrary window size, in this case 50% of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is digitally generated sine wave.
The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage signal.
-14-
REV. 0
AD5424/AD5433/AD5445
DAC SECTION
The AD5424, AD5433, and AD5445 are 8-, 10- and 12-bit current output DACs consisting of a standard inverting R-2R ladder configuration. A simplified diagram for the 8-bit AD5424 is shown in Figure 3. The matching feedback resistor RFB has a value of R. The value of R is typically 10 k (minimum 8 k and maximum 12 k). If IOUT1 and IOUT2 are kept at the same potential, a constant current flows in each ladder leg, regardless of digital input code. Therefore, the input resistance presented at VREF is always constant and nominally of resistance value R. The DAC output (IOUT) is code-dependent, producing various resistances and capacitances. External amplifier choice should take into account the variation in impedance generated by the DAC on the amplifiers inverting input node.
R VREF 2R S1 2R S2 2R S3 2R S8 2R R RFB A IOUT1 IOUT 2 DAC DATA LATCHES AND DRIVERS R R
CIRCUIT OPERATION Unipolar Mode
Using a single op amp, these devices can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing as shown in Figure 4.
VDD R2 C1 RFB IOUT1 A1 VOUT = 0 TO -VREF
VDD VREF R1 VREF
AD5424/ AD5433/AD5445 IOUT2
R/W CS GND
AGND DATA INPUTS NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. C1 PHASE COMPENSATION (1pF - 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 4. Unipolar Operation
When an output amplifier is connected in unipolar mode, the output voltage is given by
Figure 3. Simplified Ladder
Access is provided to the VREF, RFB, IOUT1 and IOUT2 terminals of the DAC, making the device extremely versatile and allowing it to be configured in several different operating modes, for example, to provide a unipolar output, 4-quadrant multiplication in bipolar mode or in single-supply modes of operation. Note that a matching switch is used in series with the internal RFB feedback resistor. If users attempt to measure RFB, power must be applied to VDD to achieve continuity.
PARALLEL INTERFACE
VOUT = -VREF x
D 2n
where D is the fractional representation of the digital word loaded to the DAC and n is the resolution of the DAC. D = 0 to 255 (8-Bit AD5424) = 0 to 1023 (10-Bit AD5433) = 0 to 4095 (12-Bit AD5445) Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. These DACs are designed to operate with either negative or positive reference voltages. The VDD power pin is only used by the internal digital logic to drive the DAC switches' on and off states. These DACs are also designed to accommodate ac reference input signals in the range of -10 V to +10 V. With a fixed 10 V reference, the circuit shown in Figure 4 will give a unipolar 0 V to -10 V output voltage swing. When VIN is an ac signal, the circuit performs 2-quadrant multiplication. Table I shows the relationship between digital code and expected output voltage for unipolar operation. (AD5424, 8-bit device).
Table I. Unipolar Code Table
Data is loaded to the AD5424/33/45 in the format of an 8-, 10-, or 12-bit parallel word. Control lines CS and R/W allow data to be written to or read from the DAC register. A write event takes place when CS and R/W are brought low, data available on the data lines fills the shift register, and the rising edge of CS latches the data and transfers the latched data-word to the DAC register. The DAC latches are not transparent, thus a write sequence must consist of a falling and rising edge on CS to ensure data is loaded to the DAC register and its analog equivalent reflected on the DAC output. A read event takes place when R/W is held high and CS is brought low. Now data is loaded from the DAC register back to the input register and out onto the data line where it can be read back to the controller for verification or diagnostic purposes.
Digital Input 1111 1111 1000 0000 0000 0001 0000 0000
Analog Output (V) -VREF (255/256) -VREF (128/256) = -VREF/2 -VREF (1/256) -VREF (0/256) = 0
REV. 0
-15-
AD5424/AD5433/AD5445
R3 10k VDD VDD R1 VREF 10V VREF RFB IOUT1 R2 C1 A1 R5 20k R4 10k A2 VOUT = -VREF TO +VREF
AD5424/ AD5433/AD5445 IOUT 2
R/W CS GND
AGND DATA INPUTS NOTES 1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0 V WITH CODE 10000000 LOADED TO DAC. 2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3. C1 PHASE COMPENSATION (1pF-2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH SPEED AMPLIFIER.
Figure 5. Bipolar Operation (4-Quadrant Multiplication)
Bipolar Operation
Stability
In some applications, it may be necessary to generate full 4-quadrant multiplying operation or a bipolar output swing. This can be easily accomplished by using another external amplifier and some external resistors as shown in Figure 5. In this circuit, the second amplifier A2 provides a gain of 2. Biasing the external amplifier with an offset from the reference voltage results in full 4-quadrant multiplying operation. The transfer function of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from code zero (VOUT = -VREF) to midscale (VOUT = 0 V ) to full scale (VOUT = +VREF).
In the I-to-V configuration, the IOUT of the DAC and the inverting node of the op amp must be connected as close as possible, and proper PCB layout techniques must be employed. Since every code change corresponds to a step function, gain peaking may occur if the op amp has limited GBP and there is excessive parasitic capacitance at the inverting node. This parasitic capacitance introduces a pole into the open-loop response, which can cause ringing or instability in closed-loop applications. An optional compensation capacitor, C1, can be added in parallel with RFB for stability as shown in Figures 4 and 5. Too small a value of C1 can produce ringing at the output, while too large a value can adversely affect the settling time. C1 should be found empirically but 1 pF to 2 pF is generally adequate for compensation.
VOUT = VREF x D 2n-1 - VREF
where D is the fractional representation of the digital word loaded to the DAC and n is the resolution of the DAC. D = 0 to 255 (8-Bit AD5424) = 0 to 1023 (10-Bit AD5433) = 0 to 4095 (12-Bit AD5445) When VIN is an ac signal, the circuit performs 4-quadrant multiplication. Table II shows the relationship between digital code and the expected output voltage for bipolar operation (AD5426, 8-bit device).
Table II. Bipolar Code Table
(
)
Digital Input 1111 1111 1000 0000 0000 0001 0000 0000
Analog Output (V) +VREF (127/128) 0 -VREF (127/128) -VREF (128/128)
-16-
REV. 0
AD5424/AD5433/AD5445
SINGLE-SUPPLY APPLICATIONS Current Mode Operation
VDD R1 R2
Figure 6 shows a typical circuit for operation with a single 2.5 V to 5 V supply. In the current mode circuit of Figure 6, IOUT2 and hence IOUT1 is biased positive by the amount applied to VBIAS. In this configuration, the output voltage is given by
VOUT = D x ( RFB RDAC ) x (VBIAS - VIN ) + VBIAS
RFB VIN IOUT1 IOUT2
VDD DAC GND VREF A1 VOUT
{
}
As D varies from 0 to 255 (AD5424), 1023 (AD5433), or 4095 (AD5445), the output voltage varies from VOUT = VBIAS to VOUT = 2 VBIAS - VIN. VBIAS should be a low impedance source capable of sinking and sourcing all possible variations in current at the IOUT2 terminal.
VDD C1 VDD VREF VIN GND DAC RFB IOUT1 IOUT2 A1 VOUT
NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY 2. C1 PHASE COMPENSATION (1pF- 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 7. Single-Supply Voltage Switching Mode Operation
POSITIVE OUTPUT VOLTAGE
Note that the output voltage polarity is opposite to the VREF polarity for dc reference voltages. In order to achieve a positive voltage output, an applied negative reference to the input of the DAC is preferred over the output inversion through an inverting amplifier because of the resistor tolerance errors. To generate a negative reference, the reference can be level shifted by an op amp such that the VOUT and GND pins of the reference become the virtual ground and -2.5 V respectively, as shown in Figure 8.
VDD = 5V
VBIAS NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY 2. C1 PHASE COMPENSATION (1pF-2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
ADR03
VOUT VIN GND +5V VDD -2.5V VREF GND -5V RFB C1
Figure 6. Single-Supply Current Mode Operation
1/2 AD8552
8-/10-/12-BIT DAC IOUT1
IOUT2 VOUT = 0 TO +2.5V
Voltage Switching Mode of Operation
Figure 7 shows these DACs operating in the voltage-switching mode. The reference voltage, VIN, is applied to the IOUT1 pin; IOUT2 is connected to AGND; and the output voltage is available at the VREF terminal. In this configuration, a positive reference voltage results in a positive output voltage making single-supply operation possible. The output from the DAC is voltage at a constant impedance (the DAC ladder resistance), thus an op amp is necessary to buffer the output voltage. The reference input no longer sees a constant input impedance, but one that varies with code. So, the voltage input should be driven from a low impedance source. It is important to note that VIN is limited to low voltages because the switches in the DAC ladder no longer have the same source-drain drive voltage. As a result, their on resistance differs, which degrades the linearity of the DAC. See TPCs 10-15. Also, VIN must not go negative by more than 0.3 V or an internal diode will turn on, exceeding the max ratings of the device. In this type of application, the full range of multiplying capability of the DAC is lost.
1/2 AD8552
NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY 2. C1 PHASE COMPENSATION (1pF-2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 8. Positive Voltage Output with Minimum of Components
REV. 0
-17-
AD5424/AD5433/AD5445
ADDING GAIN
In applications where the output voltage is required to be greater than VIN, gain can be added with an additional external amplifier or it can also be achieved in a single stage. It is important to consider the effect of temperature coefficients of the thin film resistors of the DAC. Simply placing a resistor in series with the RFB resistor will cause mismatches in the temperature coefficients resulting in larger gain temperature coefficient errors. Instead, the circuit of Figure 9 is a recommended method of increasing the gain of the circuit. R1, R2, and R3 should all have similar temperature coefficients, but they need not match the temperature coefficients of the DAC. This approach is recommended in circuits where gains of great than 1 are required.
VDD
resistor as shown in Figure 10, then the output voltage is inversely proportional to the digital input fraction D. For D = 1 - 2n the output voltage is
VOUT = -VIN D = -VIN 1 - 2- n
(
)
VDD R1 VIN
RFB
C1
As D is reduced, the output voltage increases. For small values of the digital fraction D, it is important to ensure that the amplifier does not saturate and also that the required accuracy is met. For example, an 8-bit DAC driven with the binary code 10H (00010000), i.e., 16 decimal, in the circuit of Figure 10 should cause the output voltage to be 16 VIN. However, if the DAC has a linearity specification of 0.5 LSB then D can in fact have the weight anywhere in the range 15.5/256 to 16.5/256 so that the possible output voltage will be in the range 15.5 VIN to 16.5 VIN--an error of +3% even though the DAC itself has a maximum error of 0.2%.
VIN RFB VDD
8-/10-/12-BIT DAC IOUT1
VREF GND IOUT2 R3 R2
VOUT
VDD VREF GND
GAIN = R2 + R3 R2 R1 = R2R3 R2 + R3
IOUT1 IOUT2
NOTES 1. ADDITIONAL PINS OMITTED FOR CLARITY 2. C1 PHASE COMPENSATION (1pF- 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 9. Increasing Gain of Current Output DAC
USING DACS AS A DIVIDER OR A PROGRAMMABLE GAIN ELEMENT
VOUT NOTE ADDITIONAL PINS OMITTED FOR CLARITY
Current steering DACs are very flexible and lend themselves to many different applications. If this type of DAC is connected as the feedback element of an op amp and RFB is used as the input
Figure 10. Current Steering DAC Used as a Divider or Programmable Gain Element
Table III. Suitable ADI Precision References Recommended for Use with AD5424/AD5433/AD5445 DACs
Part No. ADR01 ADR02 ADR03 ADR425
Output Voltage 10 V 5V 2.5 V 5V
Initial Tolerance 0.1% 0.1% 0.2% 0.04%
Temperature Drift 3 ppm/C 3 ppm/C 3 ppm/C 3 ppm/C
0.1 Hz to 10 Hz Noise 20 10 10 3.4 V p-p V p-p V p-p V p-p
Package SC70, TSOT, SOIC SC70, TSOT, SOIC SC70, TSOT, SOIC MSOP, SOIC
Table IV. Some Precision ADI Op Amps Suitable for Use with AD5424/AD5433/AD5445 DACs
Part No. OP97 OP1177 AD8551
Max Supply Voltage (V) 20 18 6
VOS (max) ( V) 25 60 5
IB (max) (nA) 0.1 2 0.05
GBP (MHz) 0.9 1.3 1.5
Slew Rate (V/ s) 0.2 0.7 0.4
Table V. Some High Speed ADI Op Amps Suitable for Use with AD5424/AD5433/AD5445 DACs
Part No. AD8065 AD8021 AD8038 AD9631
Max Supply Voltage (V) 12 12 5 5
BW @ ACL (MHz) 145 200 350 320
Slew Rate (V/ s) 180 100 425 1300
VOS (max) ( V) 1500 1000 3000 10000
IB (max) (nA) 0.01 1000 0.75 7000
-18-
REV. 0
AD5424/AD5433/AD5445
DAC leakage current is also a potential error source in divider circuits. The leakage current must be counterbalanced by an opposite current supplied from the op amp through the DAC. Since only a fraction D of the current into the VREF terminal is routed to the IOUT1 terminal, the output voltage has to change as follows: Output Error Voltage Due to DAC Leakage = (Leakage R)/D where R is the DAC resistance at the VREF terminal. For a DAC leakage current of 10 nA, R = 10 k and a gain (i.e., 1/D) of 16 the error voltage is 1.6 mV.
REFERENCE SELECTION
rail-to-rail signals; there is a large range of single-supply amplifiers available from Analog Devices.
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5424/AD5433/AD5445 is mounted should be designed so that the analog and digital sections are separated, and confined to certain areas of the board. If the DAC is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. These DACs should have ample supply bypassing of 10 F in parallel with 0.1 F on the supply located as close to the package as possible, ideally right up against the device. The 0.1 F capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side. It is good practice to employ compact, minimum lead length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance. The PCB metal traces between VREF and RFB should also be matched to minimize gain error. To maximize on high frequency performance, the I-to-V amplifier should be located as close to the device as possible.
EVALUATION BOARD FOR THE AD5424/AD5433/AD5445
When selecting a reference for use with the AD5424 series of current output DACs, pay attention to the references output voltage temperature coefficient specification. This parameter not only affects the full-scale error, but can also affect the linearity (INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy specifications. For example, an 8-bit system required to hold its overall specification to within 1 LSB over the temperature range 0 C to 50 C dictates that the maximum system drift with temperature should be less than 78 ppm/ C. A 12-bit system with the same temperature range to overall specification within 2 LSBs requires a maximum drift of 10 ppm/ C. By choosing a precision reference with low output temperature coefficient this error source can be minimized. Table III suggests some references available from Analog Devices that are suitable for use with this range of current output DACs.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. The input offset voltage of an op amp is multiplied by the variable gain (due to the code dependent output resistance of the DAC) of the circuit. A change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifier's input offset voltage. This output voltage change is superimposed on the desired change in output between the two codes and gives rise to a differential linearity error, which if large enough, could cause the DAC to be nonmonotonic. In general, the input offset voltage should be <1/4 LSB to ensure monotonic behavior when stepping through codes. The input bias current of an op amp also generates an offset at the voltage output as a result of the bias current flowing in the feedback resistor RFB. Most op amps have input bias currents low enough to prevent any significant errors in 12-bit applications. Common-mode rejection of the op amp is important in voltage switching circuits since it produces a code dependent error at the voltage output of the circuit. Most op amps have adequate common mode rejection for use at 8-, 10-, and 12-bit resolution. Provided the DAC switches are driven from true wideband low impedance sources (VIN and AGND), they settle quickly. Consequently, the slew rate and settling time of a voltage switching DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, it is important to minimize capacitance at the VREF node (voltage output node in this application) of the DAC. This is done by using low inputs capacitance buffer amplifiers and careful board design. Most single-supply circuits include ground as part of the analog signal range, which in turns requires an amplifier that can handle REV. 0
The board consists of a 12-bit AD5445 and a current to voltage amplifier AD8065. Included on the evaluation board is a 10 V reference ADR01. An external reference may also be applied via an SMB input. The evaluation kit consists of a CD-ROM with self-installing PC software to control the DAC. The software simply allows the user to write a code to the device.
OPERATING THE EVALUATION BOARD Power Supplies
The board requires 12 V, and +5 V supplies. The +12 V VDD and VSS are used to power the output amplifier, while the +5 V is used to power the DAC (VDD1) and transceivers (VCC). Both supplies are decoupled to their respective ground plane with 10 F tantalum and 0.1 F ceramic capacitors. Link1 (LK1) is provided to allow selection between the on-board reference (ADR01) or an external reference applied through J2.
-19-
VCC VCC C1 0.1 F VDD1
R2 10k
B-A (LSB) C6 + C5 10 F R1 18 0.1 F
U4 VCC 23 LEBA
P1-36 P1-7 P1-6 P1-5 P1-4 P1-3 P1-2 C7 20 4.7pF VSS 2 4
V- V+
C9
VCC 1 6 2 3 7 C11 10 F + VDD C12 0.1 F
10 F + C10 0.1 F TP1 J1 OUTPUT
R3 10k
1 2 3 4 5 6 7 8 9 10 11 12 OEBA A0 A1 A2 A3 A4 A5 A6 A7 CEAB GND CEBA B7 B6 B5 B4 B3 B2 B1 B0 LEAB OEAB 23 15 16 17 18 19 20 21 22 14 13
AD5424/AD5433/AD5445
P1-9
A-B (LSB)
74ABT543 U3
TP2
VCC VCC C2 0.1 F
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 15 14 13 12 11 10 9 8 7 6 5 4 DB0 U1 V DD DB1 DB2 DB3 DB4 DB5 RFB DB6 DB7 IOUT1 DB8 DB9 IOUT2 DB10 DB11
R4 10k
CS RW
3 GND VREF 19
16 CS 17 R/W
P1-31
B-A (MSB)
U5 VCC 24 AD5424/AD5433/ AD5445 V
DD
2 +V IN
VOUT 6
J2
Figure 11. Evaluation Board Schematic
23 15 16 17 18 19 20 21 22 J3 10 F J4 C3 C4 0.1 F
-20-
14 13
U2 ADR01AR 5 TRIM
GND
BA LK1 C8 0.1 F
EXTERNAL REFERENCE
VCC
R5 10k
1 2 3 4 5 6 7 8 9 10 11 12 LEBA OEBA A0 A1 A2 A3 A4 A5 A6 A7 CEAB GND CEBA B7 B6 B5 B4 B3 B2 B1 B0 LEAB OEAB
4
P1-8
A-B (MSB)
74ABT543
P1-1
P1-14 VDD
P2-3 C13 + C14 10 F + C16 AGND 10 F VSS VDD1 0.1 F C15 0.1 F
P2-2
P2-1
P2-4 C17 + C18 10 F VCC 0.1 F
P1-19 P1-20 P1-21 P1-22 P1-23 P1-24 P1-25 P1-26 P1-27 P1-28 P1-29 P1-30
P2-6 C19 + C20 10 F 0.1 F
REV. 0
P2-5
AD5424/AD5433/AD5445
P1
R2 R4
C1 C12
C10
U5 R5 C2
TP2
DB10 DB8 DB6 DB4 DB2 DB0 CS J3
DB11 DB9 U1 DB7 DB5 R1 DB3 DB1 C6 C5 RW J2 C18
U3 TP1 C7 C8 U2 LK1 EXT VREF C14 C16 J1 OUTPUT C4
C3
U4 J4 R3 CS
R/W C19 C20
C17
C13
C15 P2
DGND
VDD1
AGND
VCC
VDD
EVAL-AD5424/ AD5433/AD5445EB
Figure 12. Silkscreen--Component Side View
REV. 0
-21-
VSS
AD5424/AD5433/AD5445
Table VI. Bill of Materials for AD5424/AD5433/AD5445 Evaluation Board
Name C1, C2, C4, C6, C8 C10, C12, C13, C15 C3, C5, C9, C11, C14 C17, C19 C16, C18, C20 C7 CS DB0-DB11 J1-J4 LK1 P1 P2 R1 R2, R3, R4, R5 RW, TP1, TP2 U1 U2* U3* U4 U5 Each Corner
Part Description X7R Ceramic Capacitor X7R Ceramic Capacitor Tantalum Capacitor - Taj Series X7R Ceramic Capacitor Tantalum Capacitor - Taj Series X7R Ceramic Capacitor TESTPOINT Red Testpoint SMB Socket 3-Pin Header (3 1) 36-Pin Centronics Connector 6-Pin Terminal Block 0.063 W Resistor 0.063 W Resistor Red Testpoint AD5445 ADR425/ADR01/ADR02/ADR03 AD8065 74ABT543 74ABT543 Rubber Stick-on Feet
Value 0.1 F 0.1 F 10 F 20 V 0.1 F 10 F 10 V 4.7 pF
Tolerance 10% 10% 10% 10% 10% 10%
PCB Decal 0603 0603 CAP\TAJ_B 0603 CAP\TAJ_A 0603 TESTPOINT TESTPOINT SMB LINK-3P36WAY CON\POWER6 0603 0603 TESTPOINT TSSOP20 SO8NB SO8NB TSSOP24 TSSOP24
Stock Code FEC 499-675 FEC 499-675 FEC 197-427 FEC 499-675 FEC 197-130 FEC 240-345 (Pack) FEC 240-345 (Pack) FEC 310-682 FEC 511-717 and 150-411 FEC 147-753 FEC 151-792 Not Inserted FEC 911-355 FEC 240-345 (Pack) AD5445BRU ADR01AR AD8065AR Fairchild 74ABT543CMTC Fairchild 74ABT543CMTC FEC 148-922
10 k
1%
*See section on Amplifier and Reference Selection FEC - Farnell Electronic Components, Units 4 and 5 Gofton Court, Jamestown Road, Finglas, Dublin 11, Ireland. Tel. Int +353 (0)1 8309277 www.farnell.com
-22-
REV. 0
AD5424/AD5433/AD5445
Overview of AD54xx Devices
Part No. AD5403*
Resolution 8
No. DACs 2
INL 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.25 1 1 1 1 1 1 1 0.5 2
tS max 60 ns
Interface Package Parallel CP-40
Features
AD5410* AD5413* AD5424 AD5425 AD5426 AD5428 AD5429 AD5450 AD5404*
8 8 8 8 8 8 8 8 10
1 2 1 1 1 2 2 1 2
100 ns 100 ns 60 ns 100 ns 100 ns 60 ns 100 ns 100 ns 70 ns
Serial Serial Parallel Serial Serial Parallel Serial Serial Parallel
AD5411* AD5414* AD5432 AD5433 AD5439 AD5440 AD5451 AD5405
10 10 10 10 10 10 10 12
1 2 1 1 2 2 1 2
110 ns 110 ns 110 ns 70 ns 110 ns 70 ns 110 ns 120 ns
Serial Serial Serial Parallel Serial Parallel Serial Parallel
AD5412* AD5415 AD5443 AD5445 AD5447 AD5449 AD5452 AD5453
12 12 12 12 12 12 12 14
1 2 1 1 2 2 1 1
160 ns 160 ns 160 ns 120 ns 120 ns 160 ns 160 ns 180 ns
Serial Serial Serial Parallel Parallel Serial Serial Serial
10 MHz Bandwidth, 10 ns CS Pulse Width, 4-Quadrant Multiplying Resistors RU-16 10 MHz Bandwidth, 50 MHz Serial, 4-Quadrant Multiplying Resistors RU-24 10 MHz Bandwidth, 50 MHz Serial, 4-Quadrant Multiplying Resistors RU-16, CP-20 10 MHz Bandwidth, 17 ns CS Pulse Width RM-10 Byte Load, 10 MHz Bandwidth, 50 MHz Serial RM-10 10 MHz Bandwidth, 50 MHz Serial RU-20 10 MHz Bandwidth, 17 ns CS Pulse Width RU-10 10 MHz Bandwidth, 50 MHz Serial RJ-8 10 MHz Bandwidth, 50 MHz Serial CP-40 10 MHz Bandwidth, 17 ns CS Pulse Width, 4-Quadrant Multiplying Resistors RU-16 10 MHz Bandwidth, 50 MHz Serial, 4-Quadrant Multiplying Resistors RU-24 10 MHz Bandwidth, 50 MHz Serial, 4-Quadrant Multiplying Resistors RM-10 10 MHz Bandwidth, 50 MHz Serial RU-20, CP-20 10 MHz Bandwidth, 17 ns CS Pulse Width RU-16 10 MHz Bandwidth, 50 MHz Serial RU-24 10 MHz Bandwidth, 17 ns CS Pulse Width RJ-8 10 MHz Bandwidth, 50 MHz Serial CP-40 10 MHz Bandwidth, 17 ns CS Pulse Width, 4-Quadrant Multiplying Resistors RU-16 10 MHz Bandwidth, 50 MHz Serial, 4-Quadrant Multiplying Resistors RU-24 10 MHz Bandwidth, 50 MHz Serial, 4-Quadrant Multiplying Resistors RM-10 10 MHz Bandwidth, 50 MHz Serial RU-20, CP-20 10 MHz Bandwidth, 17 ns CS Pulse Width RU-24 10 MHz Bandwidth, 17 ns CS Pulse Width RU-16 10 MHz Bandwidth, 17 ns CS Pulse Width RJ-8, RM-8 10 MHz Bandwidth, 50 MHz Serial RJ-8, RM-8 10 MHz Bandwidth, 50 MHz Serial
*Future parts, contact factory for availability
REV. 0
-23-
AD5424/AD5433/AD5445
OUTLINE DIMENSIONS 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16)
Dimensions shown in millimeters
5.10 5.00 4.90
20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20)
Dimensions shown in millimeters
6.60 6.50 6.40
9
16
4.50 4.40 4.30
1 8
20
11
6.40 BSC
4.50 4.40 4.30
1 10
6.40 BSC
PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45
PIN 1 0.65 BSC 0.15 0.05 0.30 COPLANARITY 0.19 0.10 1.20 MAX 0.20 0.09 SEATING PLANE 8 0 0.75 0.60 0.45
0.15 0.05
COMPLIANT TO JEDEC STANDARDS MO-153AB
COMPLIANT TO JEDEC STANDARDS MO-153AC
20-Lead Lead Frame Chip Scale Package [LFCSP] (CP-20)
Dimensions shown in millimeters
4.0 BSC SQ 0.60 MAX PIN 1 INDICATOR
TOP VIEW
0.60 MAX
16 15
20 1
3.75 BSC SQ 0.75 0.55 0.35
11 10
BOTTOM VIEW
6 5
2.25 2.10 SQ 1.95 0.25 MIN
12 MAX 1.00 0.90 0.80 SEATING PLANE 0.50 BSC
0.80 MAX 0.65 NOM
0.20 REF
0.05 0.02 0.00 COPLANARITY 0.08
0.30 0.23 0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
-24-
REV. 0
C03160-0-10/03(0)

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