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ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS MICROCONTROLLER
s Complete Universal Serial Bus Specification 1.0 Compatibility -- Supports Isochronous and Non-isochronous Data -- Bidirectional Half-duplex Link s On-chip USB Transceiver s Serial Bus Interface Engine (SIE) -- Packet Decoding/Generation -- CRC Generation and Checking -- NRZI Encoding/Decoding and Bit-stuffing s USB Reset Interrupt s Four Transmit FIFOs -- Three 16-byte FIFOs -- One Configurable FIFO (up to 1 Kbyte) s Four Receive FIFOs -- Three 16-byte FIFOs -- One Configurable FIFO (up to 1 Kbyte) s Automatic Transmit/Receive FIFO Management s Suspend/Resume Operation s Three New USB Interrupt Vectors -- USB Function Interrupt -- Start of Frame -- Suspend/Resume s Phase-locked Loop -- 12 Mbps or 1.5 Mbps Data Rate s Low Clock Mode s User-selectable Configurations -- External Wait State -- Address Range -- Page Mode s Real-time Wait Function s 256-Kbyte External Code/Data Memory Space s On-chip ROM Options -- 0, 8, or 16 Kbytes s 1 Kbyte On-chip Data RAM s Four Input/Output Ports -- 1 Open-drain port -- 3 Quasi-bidirectional Ports s Programmable Counter Array (PCA) -- 5 Capture/Compare Modules s Serial I/O Port (UART) s Hardware Watchdog Timer s Three Flexible 16-bit Timer/Counters s Power-saving Idle and Powerdown Modes s Register-based MCS(R) 251 Architecture -- 40-byte Register File -- Registers Accessible as Bytes, Words, or Doublewords s Code Compatible with MCS 51 and MCS 251 Microcontrollers s 6 or 12 MHz Crystal Operation
The 8x930Ax USB microcontroller is based on an 8xC251Sx microcontroller core. It consists of standard 8xC251Sx peripherals plus an added USB function. The 8x930Ax uses the standard instruction set of the MCS 251 architecture, which is binary code compatible with the MCS 51 architecture. The USB function integrates the USB transceiver, serial bus interface engine (SIE), function interface unit (FIU) and transmit/receive FIFOs. The USB function also supports full-speed/low-speed data rates, suspend/resume modes, isochronous/non-isochronous transfers, and is fully compliant with the USB rev 1.0 specification.
COPYRIGHT (c) INTEL CORPORATION, 1997
February 1997
Order Number: 272917-003
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. The product may contain design defects or errors known as errata. Current characterized errata are available on request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation Literature Sales P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-548-4725
COPYRIGHT (c) INTEL CORPORATION, 1997
CONTENTS
1.0 Nomenclature Overview ...................................................................................................... 3 2.0 Pinout .................................................................................................................................. 4 3.0 Signals ................................................................................................................................ 7 4.0 Address Map ..................................................................................................................... 10 5.0 Electrical Characteristics ................................................................................................... 11 5.1 Operating Frequencies ................................................................................................. 12 5.2 DC Characteristics........................................................................................................ 13 5.3 Definition of AC Symbols.............................................................................................. 15 5.4 AC Characteristics........................................................................................................ 16 5.4.1 System Bus AC Characteristics ............................................................................16 5.4.2 System Bus Timing Diagrams, Nonpage Mode ....................................................18 5.4.3 System Bus Timing Diagrams, Page Mode ...........................................................20 5.4.4 Definition of Real-time Wait Symbols ....................................................................22 5.4.5 Real-time Wait Function AC Characteristics .........................................................22 5.4.6 Real-Time Wait Function Timing Diagrams ...........................................................23 5.5 AC Characteristics -- Serial Port, Synchronous Mode 0 ............................................. 27 5.6 External Clock Drive ..................................................................................................... 28 5.7 Testing Waveforms ...................................................................................................... 29 6.0 Thermal Characteristics .................................................................................................... 30 7.0 Product Reference ............................................................................................................ 30 7.1 External Bus Timing and Peripheral Timing Affected by PLLSEL2:0 Selection ........... 30 7.2 Low Clock Mode Frequency ......................................................................................... 30 7.3 Setting FFRC Bit Clears Only the Oldest Packet in the FIFO ...................................... 30 7.4 Series Resistor Requirement for Impedance Matching ................................................ 30 7.5 Pullup Requirement for Full Speed Device and Low Speed Device............................. 30 7.6 Powerdown Mode Cannot Be Invoked Before USB Suspend ...................................... 30 8.0 Specification Supplement for 8x930Ax3 and 8x930Ax4.................................................... 31 8.1 Six Endpoint Pairs Functionality ................................................................................... 31 8.2 DC Characteristics........................................................................................................ 31 8.3 Extended Data Float (EDF) AC Timing Feature ........................................................... 31 9.0 Device Errata .................................................................................................................... 34 10.0 Datasheet Revision History ............................................................................................... 34
iii
8x930Ax UNIVERSAL SERIAL BUS MICROCONTROLLER
Figures
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19.
8x930Ax Internal Block Diagram ..........................................................................................1 USB Module Block Diagram.................................................................................................2 Product Nomenclature .........................................................................................................3 8x930Ax 68-pin PLCC Package...........................................................................................4 Clock Circuit .......................................................................................................................12 8x930Ax Code Fetch, Nonpage Mode ...............................................................................18 8x930Ax Data Read, Nonpage Mode ................................................................................19 8x930Ax Data Write, Nonpage Mode.................................................................................19 8x930Ax Code Fetch, Page Mode .....................................................................................20 8x930Ax Data Read, Page Mode.......................................................................................21 8x930Ax Data write, Page Mode........................................................................................21 External Code Fetch/Data Read (Nonpage Mode, Real-time Wait State) .........................23 External Data Write (Nonpage Mode, Real-time Wait State) .............................................24 External Data Read (Page Mode, Real-time Wait State) ...................................................25 External Data Write (Page Mode, Real-time Wait State) ...................................................26 Serial Port Waveform -- Synchronous Mode 0..................................................................27 External Clock Drive Waveforms........................................................................................28 AC Testing Input, Output Waveforms.................................................................................29 Float Waveforms ................................................................................................................29
Tables
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21.
Description of Product Nomenclature...................................................................................3 Proliferation Options.............................................................................................................3 68-pin PLCC Pin Assignment...............................................................................................5 68-pin PLCC Signal Assignments Arranged by Functional Category ..................................6 Signal Descriptions ..............................................................................................................7 Memory Signal Selections (RD1:0) ....................................................................................10 8x930Ax Address Map .......................................................................................................10 Frequency Selection and Operating Frequency.................................................................12 DC Characteristics at Operating Conditions.......................................................................13 AC Timing Symbol Definitions............................................................................................15 AC Characteristics at Operating Conditions.......................................................................16 Real-time Wait Timing Symbol Definitions .........................................................................22 Real-time Wait AC Timing Specifications...........................................................................22 Serial Port Timing -- Synchronous Mode 0 .......................................................................27 External Clock Drive...........................................................................................................28 Thermal Characteristics .....................................................................................................30 SIx Endpoint Pair Feature ..................................................................................................31 Effect of "EDF#" on Wait States .........................................................................................31 AC Characteristics for 8x930Ax3 and 8x930Ax4 in Compatibility Mode ............................32 8x930Ax3 and 8x930Ax4 Default and Extended Data Float Timings.................................32 8x930Ax3 and 8x930Ax4 Real-time Wait State AC Timing Specifications ........................33
iv
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
System Bus and I/O Ports P0.7:0 P2.7:0
I/O Ports and Peripheral Signals P1.7:0 P3.7:0
Port 0 Drivers
Port 2 Drivers
ROM
RAM
Port 1 Drivers
Port 3 Drivers
Memory Data (16)
Memory Address (16)
Watchdog Timer
Bus Interface
Peripheral Interface Timer/ Counters Interrupt Handler Data Address (24) PCA IB Bus (8)
Code Bus (16)
Code Address (24)
Instruction Sequencer
SRC2 (8)
Data Bus (8)
SRC1 (8)
Serial I/O Clock & Reset
ALU
Register File
Data Memory Interface
USB
DST (16) Microcontroller Core
For details, see the USB module block diagram.
USB Ports
A4340-01
Figure 1. 8x930Ax Internal Block Diagram
ADVANCE INFORMATION
1
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
USB Upstream Port
Transceiver
Serial Bus Interface Engine (SIE)
Control Transmit/Receive Bus
A4231-03
Function Interface Unit (FIU) To CPU Data Bus
Control
Control
FIFOs
Figure 2. USB Module Block Diagram
2
ADVANCE INFORMATION
DM0
DP0
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
1.0
NOMENCLATURE OVERVIEW
X
Te
XX
Pa ck
8
X
X
XXXXX
XX
ed pe eS vic De ily am tF uc od on Pr ati ns rm tio nfo Op sI ry es mo oc Pr Me m ra og Pr
Table 1. Description of Product Nomenclature Parameter Temperature and Burn-in Packaging Options Program Memory Options Options no mark N 0 3 Process and Voltage Information Product Family Device Speed no mark 930 no mark Description Commercial operating temperature range (0oC to 70oC) with Intel standard burn-in. Plastic Leaded Chip Carrier (PLCC) Without ROM With ROM CHMOS Advanced 8-bit microcontroller architecture with on-chip Universal Serial Bus (USB) function peripherals 6 or 12 MHz crystal
Product Name 80930AD 83930AD 83930AE 0 8 Kbytes
ADVANCE INFORMATION
mp er
ag ing Op n tio
atu re an
Figure 3. Product Nomenclature
ur dB
s
Table 2. Proliferation Options ROM Size 1 Kbyte 1 Kbyte 1 Kbyte RAM Size
16 Kbytes
nin Op
tio ns
A2815-01
3
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
2.0
PINOUT
and Table 4 lists the pin assignments by functional categories. Table 5 describes the signals.
Figure 4 illustrates the 8x930Ax PLCC package. Table 3 lists the pin assignments by pin number,
AD7 / P0.7 AD6 / P0.6 AD5 / P0.5 AD4 / P0.4 AD3 / P0.3 AD2 / P0.2 AD1 / P0.1 AD0 / P0.0 VSSP VCCP P3.0 / RXD P3.1 / TXD P3.2 / INT0# P3.3 / INT1# P3.4 / T0 P3.5 / T1 P3.6 / WR#
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
A8 / P2.0 A9 / P2.1 A10 / P2.2 A11 / P2.3 A12 / P2.4 A13 / P2.5 A14 / P2.6 A15 / P2.7 VSS VCC EA# ALE PSEN# Reserved Reserved Reserved Reserved
View of component as mounted on PC board
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
Reserved Reserved Reserved Reserved Reserved DP0 DM0 ECAP VSSP VCCP SOF# Reserved Reserved Reserved Reserved Reserved PLLSEL0
Note: Reserved pins must be left unconnected.
A4392-02
Figure 4. 8x930Ax 68-pin PLCC Package
4
P3.7 / RD# / A16 P1.0 / T2 P1.1 / T2EX P1.2 / ECI P1.3 / CEX0 P1.4 / CEX1 P1.5 / CEX2 P1.6 / CEX3 / WAIT# P1.7 / CEX4 / A17 / WCLK VCC VSS XTAL1 XTAL2 AVCC RST PLLSEL1 PLLSEL2
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 3. 68-pin PLCC Pin Assignment Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Name VSS A15/P2.7 A14/P2.6 A13/P2.5 A12/P2.4 A11/P2.3 A10/P2.2 A9/P2.1 A8/P2.0 AD7/P0.7 AD6/P0.6 AD5/P0.5 AD4/P0.4 AD3/P0.3 AD2/P0.2 AD1/P0.1 AD0/P0.0 VSSP VCCP P3.0/RXD P3.1/TXD P3.2/INT0# P3.3/INT1# Pin 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 P3.4/T0 P3.5/T1 P3.6/WR# P3.7/RD#/A16 P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3/WAIT# P1.7/CEX4/A17/WCLK VCC VSS XTAL1 XTAL2 AVCC RST PLLSEL1 PLLSEL2 PLLSEL0 Reserved Reserved Name Pin 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Name Reserved Reserved Reserved SOF# VCCP VSSP ECAP DM0 DP0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PSEN# ALE EA# VCC
ADVANCE INFORMATION
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 4. 68-pin PLCC Signal Assignments Arranged by Functional Category Address & Data Name AD0/P0.0 AD1/P0.1 AD2/P0.2 AD3/P0.3 AD4/P0.4 AD5/P0.5 AD6/P0.6 AD7/P0.7 A8/P2.0 A9/P2.1 A10/P2.2 A11/P2.3 A12/P2.4 A13/P2.5 A14/P2.6 A15/P2.7 P3.7/RD#/A16 P1.7/CEX4/A17/WCLK Pin 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 27 35 Bus Control & Status Name P3.6/WR# P3.7/RD#/A16 ALE PSEN# Pin 26 27 66 65 P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3/WAIT# P1.7/CEX4/A17/WCLK P3.0/RXD P3.1/TXD P3.4/T0 P3.5/T1 Input/Output Name Pin 28 29 30 31 32 33 34 35 20 21 24 25 Processor Control Name P3.2/INT0# P3.3/INT1# EA# RST XTAL1 XTAL2 Pin 22 23 67 41 38 39 USB Name PLLSEL0 PLLSEL1 PLLSEL2 SOF# ECAP DM0 DP0 Pin 44 42 43 50 53 54 55
Power & Ground Name VCC VCCP AVCC EA# VSS VSSP Pin 36, 68 19, 51 40 67 1, 37 18, 52
6
ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
3.0
SIGNALS
Table 5. Signal Descriptions Signal Name Type O Description Alternate Function
A17
18th Address Bit (A17). Output to memory as 18th exterP1.7/CEX4/WCLK nal address bit (A17) in extended bus applications, depending on the values of bits RD0 and RD1 in configuration byte UCONFIG0. See also RD#, PSEN#. Address Line 16. See RD#. Address Lines. Upper address lines for the external bus. Address/Data Lines. Multiplexed lower address lines and data lines for external memory. Address Latch Enable (ALE). ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A15:8 and AD7:0. An external latch can use ALE to demultiplex the address from the address/data bus. Analog VCC. A separate VCC input for the phase-locked loop circuitry. Programmable Counter Array (PCA) Input/Output Pins. These are input signals for the PCA capture mode and output signals for the PCA compare mode and PCA PWM mode. Data Minus. USB minus data line interface. Data Plus. USB plus data line interface. External Access. Directs program memory accesses to on-chip or off-chip code memory. For EA# strapped to ground, all program memory accesses are off-chip. For EA# strapped to VCC, program accesses on-chip ROM if the address is within the range of the on-chip ROM; otherwise, the access is off-chip. The value of EA# is latched at reset. For devices without on-chip ROM, EA# must be strapped to ground. External Capacitor. Must be connected to a 1 F capacitor (or larger) to ensure proper operation of the differential line driver. The other lead of the capacitor must be connected to VSS. PCA External Clock Input. External clock input to the 16bit PCA timer. External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are set by a low level on INT1:0#. Port 0. This is an 8-bit, open-drain, bidirectional I/O port. P1.2 P3.3:2 P1.5:3 P1.6/WAIT# P1.7/A17/WCLK -- -- RD# P2.7:0 P0.7:0 PROG#
A16 A15:8 AD7:0 ALE
O O I/O O
AVCC CEX2:0 CEX3 CEX4 DM0 DP0 EA#
PWR I/O
I/O I/O I
ECAP
I
ECI INT1:0#
I I
P0.7:0
I/O
AD7:0
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration. If the chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).
ADVANCE INFORMATION
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 5. Signal Descriptions (Continued) Signal Name P1.0 P1.1 P1.2 P1.5:3 P1.6 P1.7 P2.7:0 P3.0 P3.1 P3.3:2 P3.5:4 P3.6 P3.7 PLLSEL2:0 PSEN# Type I/O Description Port 1. This is an 8-bit, bidirectional I/O port with internal pullups. Alternate Function T2 T2EX ECI CEX2:0 CEX3/WAIT# CEX4/A17/WCLK A15:8 RXD TXD INT1:0# T1:0 WR# RD#/A16 -- --
I/O I/O
Port 2. This is an 8-bit, bidirectional I/O port with internal pullups. Port 3. This is an 8-bit, bidirectional I/O port with internal pullups.
I O
Phase-locked Loop Select. Three-bit code selects USB data rate (see Table 8 on page 12). Program Store Enable. Read signal output. This output is asserted for a memory address range that depends on bits RD0 and RD1 in configuration byte UCONFIG0 (see RD#). Read or 17th Address Bit (A16). Read signal output to external data memory or 17th external address bit (A16), depending on the values of bits RD0 and RD1 in configuration byte UCONFIG0 (See PSEN#). Reset. Reset input to the chip. Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The port pins are driven to their reset conditions when a voltage greater than VIH1 is applied, whether or not the oscillator is running. This pin has an internal pulldown resistor which allows the device to be reset by connecting a capacitor between this pin and VCC. Asserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation. Receive Serial Data. RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2, and 3. Start of Frame. Start of Frame pulse. Active low, asserted for 8 states (see Table 8 on page 12 for state versus XTAL clock) when Frame Timer is locked to USB frame timing and SOF token or artificial SOF is detected. Timer 1:0 External Clock Inputs. When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count. Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal is the external clock input. For the clock-out mode, it is the timer 2 clock output.
RD#
O
P3.7/A16
RST
I
--
RXD
I/O
P3.0
SOF#
O
--
T1:0
I
P3.5:4
T2
I/O
P1.0
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration. If the chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).
8
ADVANCE INFORMATION
8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 5. Signal Descriptions (Continued) Signal Name T2EX Type I Description Timer 2 External Input. In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In autoreload mode, a falling edge causes the timer 2 registers to be reloaded. In the up-down counter mode, this signal determines the count direction: 1 = up, 0 = down. Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0 and transmits serial data in serial I/O modes 1, 2, and 3. Supply Voltage. Connect this pin to the +5V supply voltage. Supply Voltage for I/O buffers. Connect this pin to the +5V supply voltage. Circuit Ground. Connect this pin to ground. Circuit Ground for I/O buffers. Connect this pin to ground. Real-time Wait State Input. The real-time WAIT# input is enabled by writing a logical `1' to the WCON.0 (RTWE) bit at S:A7H. During bus cycles, the external memory system can signal `system ready' to the microcontroller in real time by controlling the WAIT# input signal on the port 1.6 input. Wait Clock Output. The real-time WCLK output is driven at port 1.7 (WCLK) by writing a logical `1' to the WCON.1 (RTWCE) bit at S:A7H. When enabled, the WCLK output produces a square wave signal with a period of TCLK. Write. Write signal output to external memory. Input to the On-chip, Inverting, Oscillator Amplifier. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal timing. Output of the On-chip, Inverting, Oscillator Amplifier. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected. Alternate Function P1.1
TXD
O
P3.1
VCC VCCP VSS VSSP WAIT#
PWR PWR GND GND I
-- -- -- -- P1.6/CEX3
WCLK
O
P1.7/CEX4/A17
WR# XTAL1
O I
P3.6 --
XTAL2
O
--
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration. If the chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0).
ADVANCE INFORMATION
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 6. Memory Signal Selections (RD1:0) RD1:0
A17/P1.7 /CEX4/WCLK A17 P1.7/CEX4/WCLK P1.7/CEX4/WCLK
A16/P3.7/RD# A16 A16 P3.7 only
PSEN# Asserted for all addresses Asserted for all addresses Asserted for all addresses
WR# Asserted for writes to all memory locations Asserted for writes to all memory locations Asserted for writes to all memory locations
Features 256-Kbyte external memory 128-Kbyte external memory 64-Kbyte external memory One additional port pin Compatible with MCS 51 microcontrollers
00 01 10
11
P1.7/CEX4/WCLK
RD# Asserted for addresses 7F:FFFFH
Asserted for addresses 80:0000H
Asserted for all compatible MCS 51 memory locations
RD1:0 are bits 3:2 of configuration byte UCONFIG0. Refer to figure 4-3 on page 4-5 in the 8x930Ax Universal Serial Bus Microcontroller User's Manual.
4.0
ADDRESS MAP
Table 7. 8x930Ax Address Map
Internal Address FF:FFFFH FF:0000H FE:FFFFH FE:0000H FD:FFFFH 02:0000H 01:FFFFH 01:0000H 00:FFFFH 00:0420H 00:041FH 00:0080H 00:007FH 00:0020H 00:001FH 00:0000H
Description External Memory: The last eight bytes of the external address range FF:XFF8H- FF:XFFFH contain configuration byte information. External Memory Reserved Addresses External Memory External Memory On-chip RAM On-chip RAM Storage for R0-R7 of Register File
Notes 1, 2, 3 2 4 2 5 5 6 7, 8
NOTES: 1. Eighteen address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration). 2. Data in this area is accessible by indirect addressing only. 3. Eight addresses at the top of all external memory maps are reserved for current and future device configuration byte information. 4. This reserved area returns unspecified values and writes no data. 5. Data is accessible by direct and indirect addressing. 6. Data is accessible by direct, indirect, and bit addressing. 7. The special function registers (SFRs) and the register file have separate internal address spaces. 8. Data is accessible by direct, indirect, and register addressing.
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.0
ELECTRICAL CHARACTERISTICS
NOTICE: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias.................... -40C to +85C Storage Temperature ................................... -65C to +150C Voltage on Any Pins to VSS ............................. -0.5 V to +6.5 V IOL per I/O Pin ................................................................. 15 mA Power Dissipation .......................................................... 1.5 W
AVCC (Analog Supply Voltage) ...................... 4.00 V to 5.25 V FOSC .............................................................. 6 MHz or 12 MHz
WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. OperTA (Ambient Temperature Under Bias): Commercial ........................................................ -0C to +70C ation beyond the "Operating Conditions" is not recommended and extended exposure beyond the VCC/VCCP (Digital Supply Voltage) .................. 4.00 V to 5.25 V "Operating Conditions" may affect device VSS / VSSP ............................................................................ 0 V reliability.
OPERATING CONDITIONS
NOTE:
Maximum power dissipation is based on package heat-transfer limitations, not device power consumption.
ADVANCE INFORMATION
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.1
Operating Frequencies
Table 8. Frequency Selection and Operating Frequency 8x930Ax Internal Frequency for CPU and Peripherals (FCLK) (5) 3 MHz 6 MHz (3) 12 MHz (3) Number of XTAL1 Clocks (TOSC) in One StateTime (4) 2 TOSC/state 2 TOSC/state 1 TOSC/state
PLLSEL2 Pin 43
PLLSEL1 Pin 42
PLLSEL0 Pin 44
USB Rate (Low Speed or Full Speed)
XTAL1 External Frequency (FOSC)
Comments
0 1 1
0 0 1
1 0 0
1.5 Mbps (LS) 1.5 Mbps (LS) 12 Mbps (FS)
6 MHz 12 MHz 12 MHz
PLL Off PLL Off PLL On
NOTES: 1. Other PLLSELx combinations are not valid. 2. The sampling rate is 4X the USB rate. 3. The 8x930Ax CPU and peripherals frequency is 3 MHz (low clock mode) until firmware disables the low clock mode. 4. The number of XTAL clocks in one state depends on the PLLSELx selections. When the CPU is operating at low clock mode (3 MHz), there are four TOSC per state for the PLLSEL2:1:0 = 100 and 110. 5. The AC timing specification (Table 11) defines the following symbol: CPU frequency = FCLK = 1/TCLK.
(6 or 12 MHz) XTAL1 Clock Generator
FOSC
Internal Clock /2 0 1 1 3 MHz CPU
FCLK
0
On-chip Peripherals
XTAL2
PD PCON.1 (Powerdown) 210 PLLSEL
LC PCON.5 (Low-clock Mode)
IDL PCON.0 (Idle Mode)
A5135-01
Figure 5. Clock Circuit
12
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.2
DC Characteristics
Table 9. DC Characteristics at Operating Conditions
Symbol
Parameter
Min
Typical (1)
Max
Units
Test Conditions
VIL VIL1 VIH VIH1 VOL
Input Low Voltage (Except EA#) Input Low Voltage (EA#) Input High Voltage (Except XTAL1, RST) Input High Voltage (XTAL1, RST) Output Low Voltage (Port 1, 2, 3)
-0.5 0 0.2 VCC + 0.9 0.7 VCC
0.2 VCC - 0.1 0.2 VCC - 0.3 VCC + 0.5 VCC + 0.5 0.3 0.45 1.0 0.3 0.45 1.0
V V V V IOL = 100 A (2, 3) IOL = 1.6 mA IOL = 3.5 mA IOL = 200 A (2, 3) IOL = 3.2 mA IOL = 7.0 mA IOH = -10 A (4) IOH = -30 A IOH = -60 A IOH = -200 A (4) IOH = -3.2 mA IOH = -7.0 mA VIN = 0.45 V 0.45 < VIN < VCC
V
VOL1
Output Low Voltage (Port 0, ALE, PSEN#, SOF#) Output High Voltage (Port 1, 2, 3,ALE, PSEN#, SOF#) Output High Voltage (Port 0 in External Address) Logical 0 Input Current (Port 1,2,3) Input Leakage Current (Port 0) VCC - 0.3 VCC - 0.7 VCC - 1.5 VCC - 0.3 VCC - 0.7 VCC - 1.5
V
VOH
V
VOH1
V -150 10
IIL ILI
A A
NOTE: 1. Typical values are obtained using VCC = 5.0V, TA = 25C and are not guaranteed. 2. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOH per port pin:10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1-3: 15 mA Maximum Total IOL for all output pins: 71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading exceeds 100pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic. 4. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the VCC specification when the address lines are stabilizing. 5. The abbreviations "LS" and "FS" indicate "Low Speed" and "Full Speed," respectively.
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 9. DC Characteristics at Operating Conditions (Continued)
Symbol Parameter Min Typical (1) Max Units Test Conditions
ITL
Logical 1-to-0 Transition Current (Port 1, 2,3) RST Pulldown Resistor 40 10 Powerdown Current -- Normal powerdown -- USB suspend Idle Mode ICC
-650 A 225 K pF
VIN = 2.0 V
RRST CIO IPD
FOSC = 12 MHz TA = 25C
25 145
50 175 40
A PLLSEL = 110 3MHz - FS (in low clock mode) PLLSEL = 110 12MHz - FS (not in low clock mode) PLLSEL = 001 3MHz - LS PLLSEL = 100 6 MHz - LS
IDL (5)
100 mA 30 55
NOTE: 1. Typical values are obtained using VCC = 5.0V, TA = 25C and are not guaranteed. 2. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOH per port pin:10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1-3: 15 mA Maximum Total IOL for all output pins: 71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading exceeds 100pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic. 4. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the VCC specification when the address lines are stabilizing. 5. The abbreviations "LS" and "FS" indicate "Low Speed" and "Full Speed," respectively.
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Table 9. DC Characteristics at Operating Conditions (Continued)
Symbol Parameter Min Typical (1) Max Units Test Conditions
ICC (5)
Active ICC
60
PLLSEL = 110 3 MHz - FS (in low clock mode) PLLSEL = 110 12 MHz - FS (not in low clock mode) PLLSEL = 001 3 MHz - LS PLLSEL = 100 6 MHz - LS
150 mA 45 75
NOTE: 1. Typical values are obtained using VCC = 5.0V, TA = 25C and are not guaranteed. 2. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOH per port pin:10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1-3: 15 mA Maximum Total IOL for all output pins: 71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading exceeds 100pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger or CMOS-level input logic. 4. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the VCC specification when the address lines are stabilizing. 5. The abbreviations "LS" and "FS" indicate "Low Speed" and "Full Speed," respectively.
5.3
Definition of AC Symbols
Table 10. AC Timing Symbol Definitions
Signals
A D L Q R W Address Data In ALE Data Out RD#/PSEN# WR# H L V X Z
Conditions
High Low Valid Hold Floating
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.4
AC Characteristics
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall times = 10 ns, FOSC = 6 MHz or 12 MHz 5.4.1 SYSTEM BUS AC CHARACTERISTICS Table 11. AC Characteristics at Operating Conditions Symbol TCLK TLHLL TAVLL TLLAX TRLRH (5) TWLWH TLLRL (5) TLHAX TRLDV (5) TRHDX (5) TRLAZ (5) TRHDZ1 (5) TRHDZ2 (5) TRHLH1 (5) TRHLH2 (5) TWHLH TAVDV1 Parameter 1/(CPU Frequency) ALE Pulse Width Address Valid to ALE Low Address Hold after ALE Low RD# or PSEN# Pulse Width WR# Pulse Width ALE Low to RD# or PSEN# Low ALE High to Address Hold RD# or PSEN# Low to Valid Data/Instruction In Data/Instruct. Hold After RD# or PSEN# High RD# or PSEN# Low to Address Float Instruct. Float After PSEN# High Data Float After RD# or PSEN# High PSEN# High to ALE High (Instruction) RD# or PSEN# High to ALE High (Data) WR# High to ALE High Address (P0) Valid to Valid Data/Instruction In CPU Frequency @ 12 MHz (M, N = 0) 83.33 (Typical) 34.66 26.66 4 73.33 71.33 8 40.33 50.33 0 0 10 83.33 10 83.33 88.33 106.66 10 TCLK TCLK + 5 (2+M+N)TCLK - 63 0 0 10 TCLK (0.5+M)TCLK - 7 (0.5+M)TCLK - 17 4 (1+N)TCLK - 10 (1+N)TCLK - 12 8 (1+M)TCLK - 43 (1+N)TCLK - 33 CPU Frequency (FCLK) Variable Min Max Units ns (1, 2) ns (3) ns (3) ns (4) ns (6) ns (6) ns ns (3) ns (6) ns ns ns ns ns ns ns ns (3, 6)
NOTES: 1. Refer to Table 8 on page 12 for CPU frequencies vs. XTAL1 frequencies. 2. XTAL1 frequency is 0.25% for full speed and 1.5% for low speed. 3. M= 0,1 is the extended ALE state. 4. At 50 C, TLLAX = 8 ns 5. Specifications for PSEN# are identical to those for RD#. 6. N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.
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Table 11. AC Characteristics at Operating Conditions (Continued) Symbol TAVDV2 TAVDV3 TAVRL (5) TAVWL1 TAVWL2 TWHQX TQVWH TWHAX Parameter Address (P2) Valid to Valid Data/Instruction In Address (P2) Valid to Valid Instruction In Address Valid to RD# or PSEN# Low Address (P0) Valid to WR# Low Address (P2) Valid to WR# Low Data Hold after WR# High Data Valid to WR# High WR# High to Address Hold CPU Frequency @ 12 MHz (M, N = 0) 118.66 23.33 40.33 40.33 66.33 28.66 68.33 70.33 (1+M)TCLK - 46 (1+M)TCLK - 46 (1+M)TCLK - 17 0.5 TCLK - 13 (1+N)TCLK -15 TCLK - 13 CPU Frequency (FCLK) Variable Min Max (2+M+N)TCLK - 48 (1+N)TCLK - 60 Units ns
(3, 6)
ns (6) ns (3) ns (3) ns (3) ns ns (6) ns
NOTES: 1. Refer to Table 8 on page 12 for CPU frequencies vs. XTAL1 frequencies. 2. XTAL1 frequency is 0.25% for full speed and 1.5% for low speed. 3. M= 0,1 is the extended ALE state. 4. At 50 C, TLLAX = 8 ns 5. Specifications for PSEN# are identical to those for RD#. 6. N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.4.2
SYSTEM BUS TIMING DIAGRAMS, NONPAGE MODE
State 1
State 2
State 1 (next cycle)
ALE
TLHLL
RD#/PSEN#
TLLRL
TRLRH TRLDV
TRHLH1
TAVLL TRLAZ TAVRL TLLAX TLHAX
TRHDX TRHDZ1
Instruction In
P0
A7:0
TAVDV1
A17/A16/P2 A17/A16/A15:8
TAVDV2
A5011-01
Figure 6. 8x930Ax Code Fetch, Nonpage Mode
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
State 1 ALE
State 2
State 3
TLHLL
RD#/PSEN#
TLLRL TAVLL TAVRL TRLAZ TLLAX TLHAX
TRLRH
TRHLH2
TRLDV
TRHDX TRHDZ2
D7:0
P0
A7:0
TAVDV1
A17/A16/P2 A17/A16/A15:8
TAVDV2
A5025-02
Figure 7. 8x930Ax Data Read, Nonpage Mode
State 1 ALE
State 2
State 3
TLHLL TWLWH
WR#
TWHLH
TAVLL
TAVWL1 TAVWL2 TLLAX TLHAX TQVWH
D7:0
TWHQX
P0
A7:0
TWHAX
A17/A16/P2 A17/A16/A15:8
A5026-02
Figure 8. 8x930Ax Data Write, Nonpage Mode
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.4.3
SYSTEM BUS TIMING DIAGRAMS, PAGE MODE
State 1 ALE
Cycle 1, Page Miss State 2
Cycle 2, Page Hit State 1
TLHLL
RD#/PSEN#
TLLRL
TRLRH TRLDV
TRHLH1
TAVLL TRLAZ TAVRL TLLAX TLHAX
TRHDX TRHDZ1
Instruction 1 In Instruction 2 In
P2
A15:8
TAVDV1
A17/A16/P0 A17/A16/A7:0
TAVDV3
TAVDV2
During a sequence of page hits, PSEN# remains low until the end of the last page hit cycle.
A5028-02
Figure 9. 8x930Ax Code Fetch, Page Mode
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State 1 ALE
State 2
State 3
TLHLL
RD#/PSEN#
TLLRL TAVLL TAVRL TRLAZ TLLAX TLHAX
TRLRH
TRHLH2
TRLDV
TRHDX TRHDZ2
D7:0
P2
A15:8
TAVDV1
A17/A16/P0 A17/A16/A7:0
TAVDV2
A5029-02
Figure 10. 8x930Ax Data Read, Page Mode
State 1 ALE
State 2
State 3
TLHLL TWLWH
WR#
TWHLH
TAVLL
TAVWL1 TAVWL2 TLLAX TLHAX TQVWH
D7:0
TWHQX
P2
A15:8
TWHAX
A17/A16/P0 A17/A16/A7:0
A5030-02
Figure 11. 8x930Ax Data write, Page Mode
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
5.4.4
DEFINITION OF REAL-TIME WAIT SYMBOLS Table 12. Real-time Wait Timing Symbol Definitions
Signals
A D C Y W R Address Data WCLK WAIT# WR# RD#/PSEN# L X V
Conditions
Low Hold Setup
5.4.5
REAL-TIME WAIT FUNCTION AC CHARACTERISTICS Table 13. Real-time Wait AC Timing Specifications
Symbol TCLYV TCLYX TRLYV TRLYX TWLYV TWLYX
Parameter Wait Clock Low to Wait Setup Wait Hold after Wait Clock Low PSEN# or RD# Low to Wait Setup Wait Hold after PSEN# or RD# Low WR# Low to Wait Setup Wait Hold after WR# Low
FCLK Variable (1) (2) Min 0 (W)TCLK + 5 0 (W)TCLK + 5 0 (W)TCLK + 5 Typ Max 0.5 TCLK - 13 (0.5+W)TCLK - 13 0.5 TCLK - 13 (0.5+W)TCLK - 13 0.5 TCLK - 13 (0.5+W)TCLK - 13
Units ns ns ns ns ns ns
NOTES: 1. W = 0, 1, 2, ... is the number of real-time wait states. 2. Real-time Wait function has a critical timing for instruction read. It is not advisable to use this feature for instruction read during page mode.
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5.4.6
REAL-TIME WAIT FUNCTION TIMING DIAGRAMS
State 1 WCLK
State 2
State 3
State 1 (next cycle)
ALE TCLYV RD#/PSEN# TRLYX max TRLYX min TRLYV WAIT# P0 P2
TCLYX min TCLYX max RD#/PSEN# stretched
A7:0 A15:8
D7:0
stretched stretched
A7:0 A15:8
A5000-02
Figure 12. External Code Fetch/Data Read (Nonpage Mode, Real-time Wait State)
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
State 1 WCLK
State 2
State 3
State 4
TCLYX min ALE TCLYV WR# TWLYX max TWLYX min TWLYV WAIT# P0 P2 WR# stretched TCLYX max
A7:0 A15:8
D7:0
stretched stretched
A5002-02
Figure 13. External Data Write (Nonpage Mode, Real-time Wait State)
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State 1 WCLK
State 2
State 3
State 1 (next cycle)
ALE TCLYV RD#/PSEN# TRLYX max TRLYX min TRLYV WAIT# P2 P0
TCLYX min TCLYX max RD#/PSEN# stretched
A15:8 A7:0
D7:0
stretched stretched
A15:8 A7:0
A5001-02
Figure 14. External Data Read (Page Mode, Real-time Wait State)
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
State 1 WCLK
State 2
State 3
State 4
TCLYX min ALE TCLYV WR# TWLYX max TWLYX min TWLYV WAIT# P2 P0 WR# stretched TCLYX max
A15:8 A7:0
D7:0
stretched stretched
A5003-02
Figure 15. External Data Write (Page Mode, Real-time Wait State)
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5.5
AC Characteristics -- Serial Port, Synchronous Mode 0
Table 14. Serial Port Timing -- Synchronous Mode 0
Symbol TXLXL TQVSH TSHQX TXHDX TXHDV
Parameter Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data hold after Clock Rising Edge Input Data Hold after Clock Rising Edge Clock Rising Edge to Input Data Valid
Min 6 TOSC 5 TOSC - 133 TOSC - 50 0
Max
Units ns ns ns ns
5 TOSC - 133
ns
TXLXL
TXD
TXHQX TQVXH
Set TI
2 3 4 5 6 7
RXD (Out)
0
1
TXHDV
TXHDX Valid Valid Valid Valid Valid Valid
Set RI
Valid
RXD (In)
Valid
TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit.
A2592-02
Figure 16. Serial Port Waveform -- Synchronous Mode 0
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5.6
External Clock Drive
Table 15. External Clock Drive Symbol 1/TOSC TCHCX TCLCX TCLCH TCHCL Parameter Oscillator Frequency (FOSC) High Time Low Time Rise Time Fall Time Min 6 0.35 TOSC 0.35 TOSC Max 12 0.65 TOSC 0.65 TOSC 10 10 Units MHz ns ns ns ns
TCLCH
VCC - 0.5 0.7 VCC
TCHCX
TCLCX 0.45 V
0.2 VCC - 0.1
TCHCL
TCLCL
A4119-01
Figure 17. External Clock Drive Waveforms
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5.7
Testing Waveforms
Inputs VCC - 0.5
0.45 V
Outputs 0.2 VCC + 0.9 0.2 VCC - 0.1 VIH MIN VOL MAX
AC inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45 V for a logic 0. Timing measurements are made at a min of VIH for a logic 1 and VOL for a logic 0.
A4118-01
Figure 18. AC Testing Input, Output Waveforms
VLOAD + 0.1 V VLOAD VLOAD - 0.1 V Timing Reference Points
VOH - 0.1 V
VOL + 0.1 V
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with IOL/IOH = 20 mA.
A4117-01
Figure 19. Float Waveforms
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6.0
THERMAL CHARACTERISTICS
7.3
This microcontroller operates over the commercial temperature range from 0oC to 70oC. All thermal impedance data (Table 16) is approximate for static air conditions at 1 watt of power dissipation. Values change depending on operating conditions and application requirements. The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology. The Components Quality and Reliability Handbook (order number 210997) provides quality and reliability information. Table 16. Thermal Characteristics Package Type 68-pin PLCC JA N/A JC N/A
Setting FFRC Bit Clears Only the Oldest Packet in the FIFO
If the receive FIFO is set as a dual packet mode, it can receive two packets. Setting FFRC to indicate FIFO Read Complete will not flush the entire FIFO, only the oldest packet will be flushed. The read marker will be advanced to the location of the read pointer.
7.4
Series Resistor Requirement for Impedance Matching
7.0
PRODUCT REFERENCE
This section lists design considerations for the 8x930Ax Universal Serial Bus microcontroller.
Per the USB 1.0 specification (page 111, section 7.1.1.1), the impedance of the differential driver must be between 29 and 44 Ohms. To match the cable impedance, a series resistor of 27 to 33 Ohms should be connected to each USB line; i.e., on DP0 (pin 55) and on DM0 (pin 54). If the USB line is improperly terminated or not matched, signal fidelity will suffer. This can be seen on the scope as excessive overshoot and undershoot. This will potentially introduce bit errors.
7.1
External Bus Timing and Peripheral Timing Affected by PLLSEL2:0 Selection
7.5
Pullup Requirement for Full Speed Device and Low Speed Device
PLLSEL2 (pin43), PLLSEL1 (pin 42), and PLLSEL0 (pin 44) determine the 8x930Ax internal CPU operating frequency. The selected CPU operating frequency also influences all the peripherals. If the PLLSEL2:0 pins of the 8x930Ax are set to 110, then the internal clock frequency is 12MHz, and one state time equals one clock time (please refer to Table 8 on page 12). Therefore, all internal and external instruction times for the timer, serial port, PCA, are two times faster than with other PLLSEL2:0 selections. Refer to the 8x930Ax, 8x930Hx Universal Serial Bus Microcontroller User's Manual for the new peripheral timing formulas.
The pullup is a USB requirement to allow the host to identify which devices are low speed and which are full speed in order to communicate at the appropriate data rate. For Full Speed devices (12 Mbps) use a 1.5K pullup resistor (to 3.0 V - 3.6 V) on the DP0 line. For Low Speed devices (1.5Mbps), use a 1.5K pullup resistor (to 3.0 V - 3.6 V) on the DM0 line.
7.6
Powerdown Mode Cannot Be Invoked Before USB Suspend
7.2
Low Clock Mode Frequency
If the 8x930Ax is put into powerdown mode prior to receiving a USB Suspend signal from the host, a USB Resume will not properly wake up the 8x930Ax from powerdown mode.
In low clock mode, the CPU and peripherals run at 3 MHz. All external bus accesses are affected, including instruction fetch, data read/write, and peripheral timing. Please refer to Table 8 on page 12 for the relationship of 3 MHz CPU and peripheral timing (TCLK) to state times. One peripheral cycle is 6 state times.
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8.0
SPECIFICATION SUPPLEMENT FOR 8X930AX3 AND 8X930AX4
8.2
DC Characteristics
All descriptions above apply to the 8x930Ax and 8x930Ax2 microcontrollers. The following specifications apply to recent steppings of the 8x930Ax (8x930Ax3 and 8x930Ax4). This information is in addition to (or in place of) the specifications described above.
The VOH specification given in the DC Characteristics section of this datasheet is changed to VOH = {min} VCC - 1.7 V when IOH = -60 A for the A3 stepping onward.
8.3
Extended Data Float (EDF) AC Timing Feature
8.1
Six Endpoint Pairs Functionality
In the default state, the SIXEPPEN bit of 8x930Ax3's and 8x930Ax4's EPCONFIG SFR is cleared and the 6 endpoint pair feature is disabled. In this state, the endpoint pairs of the 8x930Ax3 and 8x930Ax4 are similar to those of the 8x930Ax and 8x930Ax2 devices. To enable the 6 endpoint pair feature, set EPCONFIG's SIXEPPEN bit. The 8x930Ax3 and 8x930Ax4 will then have the endpoint pairs shown in Table 17.
To provide a direct interface capability to slower memory without the use of tristate drivers, an extended data float (EDF) option has been added to the 8x930Ax3 and 8x930Ax4. This option is controlled by the EDF# bit (bit 3 in the UCONFIG1 configuration byte). If the EDF# bit is configured to 1, the 8x930Ax3 and 8x930Ax4 behave per the current specification (some AC timings are different). This is known as "Compatibility Mode". Table 19 on page 32 lists the AC characteristics in this "Compatibility Mode" that are different compared to the 8x930Ax and 8x930Ax2. Parameters not listed in the table remain the same as for 8x930Ax and 8x930Ax2. If the 8x930Ax3 and 8x930Ax4 are configured with EDF# = 0, the device will have extended data float timings. This mode is known as the "Increased TRHDZ1 Mode." Table 20 on page 32 and Table 21 on page 33 show the parameters that are affected when EDF#= 0. Configuring the device with EDF# = 0 does not affect wait state A (all regions except 01:). Wait state A can have 0, 1, 2, or 3 wait states. EDF#=0 affects external wait state B (region 01:). The summary of the effect EDF# has on wait states is listed in Table 18.
Table 17. SIx Endpoint Pair Feature EPINDEX 0xxx x000 0xxx x001 0xxx x010 0xxx x011 0xxx x100 0xxx x101 FFSZ1:0 xx 00 xx xx xx xx Transmit FIFO (bytes) 16 256 32 32 32 16 Receive FIFO (bytes) 16 256 32 32 32 16
When the 6 endpoint pair feature is enabled, two additional SFRs -- the Function Interrupt Enable Register 1 (FIE1) and the Function Interrupt Flag Register 1 (FIFLG1) -- are enabled to manage interrupts for the additional endpoint pairs. See the 8x930Ax, 8x930Hx Universal Serial Bus Microcontroller User's Manual for additional information.
Table 18. Effect of "EDF#" on Wait States EDF# 1 1 1 1 0 0 0 0 WSB#[1:0] 11 10 01 00 11 10 01 00 Wait-state (for page 01) 0 1 2 3 1 1 3 3
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Table 19. AC Characteristics for 8x930Ax3 and 8x930Ax4 in Compatibility Mode Symbol TAVLL TLLAX TWLWH TLLRL TLHAX TRLDV TRLAZ TRHDZ2 TRHLH2 TWHLH TAVDV2 TAVRL TAVWL1 Parameter Address Valid to ALE Low Address Hold after ALE Low WR# Pulse Width ALE Low to RD# or PSEN# low ALE High to Address Hold RD# or PSEN# Low to Valid Data/Inst. In RD# or PSEN# Low to Address Float Data Float After PSEN# or RD# High RD# or PSEN# High to ALE High (data) WR# High to ALE High Address (demux'ed) Valid to Valid Data/Instr. In Address Valid to RD# or PSEN# Low Address (mux'ed) Valid to WR# Low 8x930Ax3/8x930Ax4 Compatibility Mode (ns) (EDF# =1) (1) (0.5+M)TCLK - 13 [min] 10 [min] (1+N)TCLK - 10 [min] 10 [min] (1+M)TCLK - 27 [min] (1+N)TCLK - 30 [max] 3 max (2) TCLK + 10 [max] TCLK + 10 [min] TCLK+10 [min] (2+M+N)TCLK - 38 [max] (1+M)TCLK - 40 [min] (1+M)TCLK - 40 [min]
NOTES: 1. Device configured with default data float timing for fast memory interface. 2. Typical value is 0 ns.
Table 20. 8x930Ax3 and 8x930Ax4 Default and Extended Data Float Timings Symbol TLLAX TRLRH TWLWH TLLRL TLHAX TRLDV TRHDZ1 Parameter Address Hold after ALE Low RD# or PSEN# Pulse Width WR# Pulse Width ALE Low to RD# or PSEN# low ALE High to Address Hold RD# or PSEN# Low to Valid Data/Inst. In Instruct. Float After PSEN# or RD# High Default Data Float Timing (ns) Compatibility Mode (EDF# =1) (1,2,4,5) 10 [min] (1+N)TCLK - 10 [min] (1+N)TCLK - 10 [min] 10 [min] (1+M)TCLK - 27 [min] (1+N)TCLK - 30 [max] 10 [max] Extended Data Float Timing (ns) Increased TRHDZ1 mode (EDF#=0) (1,3,4,5) 20 [min] (1+N)TCLK - 32 [min] (1+N)TCLK - 32 [min] 20 [min] (0.5+M)TCLK + 15 [min] (1+N)TCLK - 50 [max] (0.5)TCLK - 5 [max]
NOTES: 1. Worst-case numbers based on silicon data collected to date. 2. Device configured with default data float timing for fast memory interface. 3. Device configured with extended data float timing for slow memory interface. 4. The values listed are for 12 MHz. For 6 MHz, the value of TCLK will double and will equal 166.6 ns. 5. M=0,1 is the extended ALE state; N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
Table 20. 8x930Ax3 and 8x930Ax4 Default and Extended Data Float Timings (Continued) Symbol TRHDZ2 TRHLH2 TRHLH1 TWHLH TAVDV1 TAVRL TAVWL1 TAVWL2 Parameter Data Float After PSEN# or RD# High RD# or PSEN# High to ALE High (data) PSEN# High to ALE High (inst.) WR# High to ALE High Address (mux'ed) Valid to Valid Data/Inst. In Address Valid to RD# or PSEN# Low Address (mux'ed) Valid to WR# Low Address (demux'ed) Valid to WR# Low Default Data Float Timing (ns) Compatibility Mode (EDF# =1) (1,2,4,5) TCLK + 10 [max] TCLK + 10 [min] 10 [min] TCLK + 10 [min] (2+M+N)TCLK - 60 [max] (1+M)TCLK- 40 [min] (1+M)TCLK- 40 [min] (1+M)TCLK- 17 [min] Extended Data Float Timing (ns) Increased TRHDZ1 mode (EDF#=0) (1,3,4,5) 1.5 TCLK - 5 [max] (1.5)TCLK - 7 [min] (0.5)TCLK - 7 [min] (1.5)TCLK - 7 [min] (1.5+M+N)TCLK - 28 [max] (0.5+M)TCLK + 10 [min] (0.5+M)TCLK + 10 [min] (1+M)TCLK + 10 [min]
NOTES: 1. Worst-case numbers based on silicon data collected to date. 2. Device configured with default data float timing for fast memory interface. 3. Device configured with extended data float timing for slow memory interface. 4. The values listed are for 12 MHz. For 6 MHz, the value of TCLK will double and will equal 166.6 ns. 5. M=0,1 is the extended ALE state; N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.
Table 21. 8x930Ax3 and 8x930Ax4 Real-time Wait State AC Timing Specifications FCLK Variable Default Data Float Timing (ns) (EDF#=1) Min TRLYV (PSEN# or RD# Low to Wait Setup) TWLYV (WR# Low to Wait Setup) 0 0 Typ Max 0.5 TCLK - 13 0.5 TCLK - 13 FCLK Variable Extended Data Float Timing (ns) (EDF#=0) Min 0 Typ Max 0.5 TCLK - 35 0.5 TCLK - 35
Symbol (Parameter)
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8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER
9.0
DEVICE ERRATA
The 8x930Ax may contain design defects or errors known as errata. Characterized errata that may cause the 8x930Ax's behavior to deviate from published specifications are documented in a specification update. Refer to the 8x930Ax (8x930AD, 8x930AE) Specification Update (Order Number 272940, Revision 007 or later). Specification updates can be obtained from your local Intel sales office or from the World Wide Web (www.intel.com).
10.0 DATASHEET REVISION HISTORY
This datasheet is valid for A-2 through A-4 step devices. Datasheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices. This (-003) revision of the 8x930Ax datasheet replaces earlier product information. The following changes were made in this version: 1. 2. 3. Added "Specification Supplement for 8x930Ax3 and 8x930Ax4" on page 31. The following AC Characteristics were changed: TAVLL, TAVDV1, TAVRL, TAVWL1. ICC characteristics updated.
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