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| PRODUCT SPECIFICATION PE3293 Product Description The PE3293 is a dual fractional-N phase-lock loop (PLL) IC designed for frequency synthesis and fabricated on Peregrine's patented UTSi(R) CMOS process. Each PLL includes a prescaler, phase detector, charge pump and on-board fractional spur compensation. The patented spur compensation circuitry designed into the device ensures superior spur performance over the full temperature and VCO tuning range. The PE3293 provides fractional-N division with power-oftwo denominator values up to 32. This allows comparison frequencies up to 32 times the channel spacing, providing a lower phase noise floor than integer PLLs. The 32/33 RF prescaler (PLL1) operates up to 1.8 GHz and the 16/17 IF prescaler (PLL2) operates up to 550 MHz. Applications * Triple mode,dual-band PCS / Cellular handset * PCS/CDMA/Cellular handsets * PCS/CDMA/Cellular base stations Figure 1. Block Diagram 1.8 GHz / 550 MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis Features * Industry leading fractional spur compensation: no adjusting required, stable over temp. * Ultra-Low Power consumption: 4.0 mA typical, both loops operating * Modulo-32 fractional-N main counters * Supply voltage range 2.7 to 3.3 VDC fin1 32/33 Prescaler 19-bit Fractional-N Main Divider Fractional Spur Compensation fr Ref. Amp. 9-bit Reference Divider Phase Detector Charge Pump CP1 Clock Data LE 21-bit Serial Control Interface Multiplexer foLD 9-bit Reference Divider Phase Detector Charge Pump CP2 fin2 16/17 Prescaler 18-bit Fractional-N Main Divider Fractional Spur Compensation PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 1 of 18 PE3293 Product Specification Figure 2. Pin Configuration: TSSOP (JEDEC MO-153-AC) N/C VDD CP1 GND fin1 Dec1 VDD1 fr GND 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VDD VDD CP2 GND fin2 DEC2 VDD2 LE Data Clock foLD 10 Table 1. Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name N/C VDD CP1 GND fin1 Dec1 VDD1 fr GND foLD Clock Data LE VDD2 Dec2 fin2 GND CP2 VDD VDD Type No connect. (Note 1) Output Description Power supply voltage input. Input may range from 2.7 V to 3.3 V. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Internal charge-pump output from PLL1 for connection to a loop filter for driving the input of an external VCO. Ground. Input Prescaler input from the PLL1 (RF) VCO. Maximum frequency is 1.8 GHz. Power supply decoupling pin for PLL1. A capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. PLL1 prescaler power supply. 3.3 kohm resistor to VDD. Input Reference frequency input. Ground. Output Input Input Input Output Output Input Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect signals, and data out of the shift register. CMOS output (see Table 11, foLD Programming Truth Table). CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the 21-bit shift register. Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits. Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is loaded into one of the four appropriate latches (as assigned by the control bits). PLL2 prescaler power supply. 3.3 kohm resistor to VDD. Power supply decoupling pin for PLL2. A capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Prescaler input from the PLL2 (IF) VCO. Maximum frequency is 550 MHz. Ground. Output (Note 1) (Note 1) Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of an external VCO. Same as pin 2. Same as pin 2. Note 1: VDD pins 2, 19, and 20 are connected by diodes and must be supplied with the same voltage level. Copyright Peregrine Semiconductor Corp. 2003 File No. 70/0015~02C | UTSi CMOS RFIC SOLUTIONS Page 2 of 18 PE3293 Product Specification Figure 3. Pin Configuration: 24-Pin BCC (Top View) GND N/C CP2 VDD VDD N/C VDD N/C 19 20 21 22 23 24 1 2 3 4 5 6 18 fin2 17 Dec2 16 VDD2 15 LE 14 13 12 11 10 9 8 7 N/C Data Clock foLD GND fr N/C CP1 GND fin1 VDD1 DEC1 Table 2. Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Pin Name N/C CP1 GND fin1 Dec1 VDD1 N/C fr GND foLD Clock Data N/C LE VDD2 Dec2 fin2 GND N/C CP2 VDD Type No connect. Output Description Internal charge-pump output from PLL1 for connection to a loop filter for driving the input of an external VCO. Ground Input Prescaler input from the PLL1 (RF) VCO. Maximum frequency is 1.8 GHz. Power supply decoupling pin for PLL1. A capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. PLL1 prescaler power supply (FlexiPower 1). No connect. Input Reference frequency input. Ground. Output Input Input Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect signals, and data out of the shift register. CMOS output (see Table 11, foLD Programming Truth Table). CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the 21-bit shift register. Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits. No connect. Input Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is loaded into one of the four appropriate latches (as assigned by the control bits). PLL2 prescaler power supply. 3.3 kohm resistor to VDD. Power supply decoupling pin for PLL2. A capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Input Prescaler input from the PLL2 (IF) VCO. Maximum frequency is 550MHz. Ground. No connect. Output (Note 1) Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of an external VCO. Power supply voltage input. Input may range from 2.7 V to 3.3 V. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 PEREGRINE SEMICONDUCTOR CORP. | Page 3 of 18 PE3293 Product Specification Pin No. 22 23 24 Pin Name VDD N/C VDD Type (Note 1) Same as pin 21. No connect. (Note 1) Same as pin 21. Description Note 1: VDD pins 21, 22, and 24 are connected by diodes and must be supplied with the same voltage level. PE3293 Description The PE3293 is intended for such applications as the local oscillator for the RF and first IF of dualconversion transceivers. The RF PLL (PLL1) includes a 32/33 prescaler with a 1.8 GHz maximum frequency of operation, where the IF PLL (PLL2) incorporates a 16/17 prescaler with a 550 MHz maximum frequency of operation. Using an advanced fractional-N phase-locked loop technique, the PE3293 can generate a stable, very low phase- noise signal. The dual fractional architecture allows fine resolution in both PLLs, with no degradation in phase noise performance. Data is transferred into the PE3293 via a threewire interface (Data, Clock, LE). Supply voltage can range from 2.7 to 3.3 volts for VDD. PE3293 features very low power consumption and is available in a JEDEC MO-153-AC (TSSOP), 20pin package and 24-lead BCC package. Spurious Response A critical parameter for synthesizer designs is spurious output. Spurs occur at the integer multiples of the step size away from center tone. An important feature of fractional synthesizers is their ability to reduce these spurious sidebands. The PE3293 has a built-in method for reducing these spurs, with no external components or tuning required. In addition, this circuitry works over the full commercial temperature and VCO tuning range. Copyright Peregrine Semiconductor Corp. 2003 File No. 70/0015~02C | UTSi CMOS RFIC SOLUTIONS Page 4 of 18 PE3293 Product Specification Table 3. Absolute Maximum Ratings Symbol VDD VDDI, VDD2 VI Electrostatic Discharge (ESD) Precautions Max 4.0 VDD VDD + 0.3 +10 150 Parameter/Conditions Supply voltage Prescaler supply voltage Voltage on any input Min -0.3 -0.3 -0.3 Units V V V When handling this UTSi device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 5. Latch-Up Avoidance Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up. II Tstg DC into any input Storage temperature range -10 -65 mA C Table 4. Operating Ratings Symbol VDD VDD1, VDD2 TA Parameter/Conditions Supply voltage Prescaler supply voltage Operating ambient temperature range Min 2.7 0.8 -40 Max 3.3 VDD 85 Units V C C Table 5. ESD Ratings Symbol VESD Parameter/Conditions ESD voltage human body model (Note 1) Level 2000 Units V Note 1: Periodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2 PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 5 of 18 PE3293 Product Specification Table 6. DC Characteristics VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol IDD Istby VIH VIL IIH IIL IIHR IILR VOLD VOHD ICP - Source ICP - Sink ICPL ICP - Source vs. ICP - Sink ICP vs TA ICP vs. VCP Parameter 3 V supply current Total standby current High level input voltage Low level input voltage High level input current Low level input current Input current Input current Output voltage LOW Output voltage HIGH Conditions C10, C20 = 00 (both PLLs on) Min Typ 4.0 5.0 Max 50 Units mA A V Digital inputs: Clock, Data, LE VDD = 2.7 to 3.3 volts VDD = 2.7 to 3.3 volts VIH = VDD = 3.3 volts VIL = 0, VDD = 3.3 volts VIH = VDD = 3.3 volts VIL = 0, VDD = 3.3 volts Iout = 1 mA Iout = -1 mA VDD - 0.4 -70 -70 -5 10 10 10 5 % % % -25 0.4 -1 -1 0.7 x VDD 0.3 x VDD +1 +1 +25 V A A A A V V A A nA Reference Divider input: fr Digital output: foLD Charge Pump outputs: CP1, CP2 Drive current Leakage current Sink vs. source mismatch Output current vs. temperature Output current magnitude variation vs. voltage VCP = VDD / 2 0.5 V < VCP < VDD - 0.5 volt VCP = VDD / 2, TA = 25 C VCP = VDD / 2 0.5 V < VCP < VDD - 0.5 volt, TA = 25 C Copyright Peregrine Semiconductor Corp. 2003 File No. 70/0015~02C | UTSi CMOS RFIC SOLUTIONS Page 6 of 18 PE3293 Product Specification Table 7. AC Characteristics VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol fClock tClockH tClockL tDSU tDHLD tLEW tCLE tLEC tData Out fin1 fin2 Pfin1 Pfin2 fc Reference Divider fr Vfr Note 1: Operating frequency Input sensitivity CMOS logic levels may be used if DC coupled. External AC coupling (note 1) 0.5 50 MHz VP-P Parameter Serial data clock frequency Serial clock HIGH time Serial clock LOW time Data set-up time to Clock rising edge Data hold time after Clock rising edge LE pulse width Clock falling edge to LE rising edge LE falling edge to Clock rising edge Data Out delay after Clock falling edge (foLD pin) Operating frequency Operating frequency Input level range Input level range Comparison frequency CL = 50 pf Conditions Min Max 10 Units MHz ns ns ns ns ns ns ns Control Interface and Latches (see figure 6) 50 50 50 10 50 50 50 90 300 45 External AC coupling External AC coupling -7 -10 1800 550 5 5 10 ns MHz MHz dBm dBm MHz Main Divider (Including Prescaler) PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 7 of 18 PE3293 Product Specification Functional Description The Functional Block Diagram in Figure 5 shows a 21-bit serial control register, a multiplexed output, and PLL sections PLL1 and PLL2. Each PLL contains a fractional-N main counter chain, a reference counter, a phase detector, and an internal charge pump with on-chip fractional spur compensation. Each fractional-N main counter chain includes an internal dual modulus prescaler, supporting counters, and a fractional accumulator. Serial input data is clocked on the rising edge of Clock, MSB first. The last two bits are the address bits that determine the register address. Data is transferred into the counters as shown in Table 8, PE3293 Register Set. If the foLD pin is configured as data out, then the contents of shift register bit S20 are clocked on the falling edge of Clock onto the foLD pin. This feature allows the PE3293 and compatible devices to be connected in a daisychain configuration. The PLL1 (RF) VCO frequency fin1 is related to the reference frequency fr by the following equation: fin1 = [(32 x M1) + A1 + (F1/32)] x (fr/R1) (1) Note that A1 must be less than or equal to M1. Also, fin1 must be greater than or equal to 1024 x (fr/R1) to obtain contiguous channels. The PLL2 (IF) VCO frequency fin2 is related to the reference frequency fr by the following equation: fin2 = [(16 x M2) + A2 + (F2/32)] x (fr/R2) (2) Note that A2 must be less than or equal to M2. Also, fin2 must be greater than or equal to 256 x (fr / R2) to obtain contiguous channels. F1 sets PLL1 fractionality. If F1 is an even number, the PE3293 automatically reduces the fraction. For example, if F1 = 12, then the fraction 12/32 is automatically reduced to 3/8. In this way, fractional denominators of 2, 4, 8, 16 and 32 are available. F2 sets the fractionality for PLL2 in the same manner. Figure 4. Functional Block Diagram A1 5 A1 Counter 0 Prescaler Control Logic F1 5 fin1 32/33 Prescaler M1 Counter 3 fr Ref. Amp. 9-bit Reference Divider R1 9 Phase Detector C11 Charge Pump C12 C22 C22 C22 C22 CP1 Clock Data LE 21-bit Serial Control Interface R2 9 Multiplexer C21 C22 foLD 9-bit Reference Divider Phase Detector Charge Pump CP2 fin2 16/17 Prescaler M2 Counter 3 F2 Counter 0 Fractional Spur Compensation P1 P2 A2 Counter 0 Prescaler Control Logic Copyright Peregrine Semiconductor Corp. 2003 File No. 70/0015~02C | UTSi CMOS RFIC SOLUTIONS Page 8 of 18 PE3293 Product Specification Table 8. Register Set S20 S19 S18 S17 S16 Test 0 C24 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Reserved PLL2 Synthesizer control C23 C22 C21 C20 R28 R 27 PLL2 Reference counter R2 divide ratio R 26 R 25 R 24 R 23 R 22 R 21 R 20 Address 0 0 Res. M28 M27 PLL2 Main counter M2 divide ratio M26 M25 M24 M23 M22 M21 M20 PLL2 Swallow counter A2 divide ratio A23 A22 A21 A20 PLL2 Fractional counter F2 numerator value F24 F23 F22 F21 F20 Address 0 1 Res. FlexiPower voltage regulation P2 PLL1 Synthesizer control C14 C13 C12 C11 C10 R18 R17 PLL1 Reference counter R1 divide ratio R16 R15 R14 R13 R12 R11 R10 Address 1 0 Res. P1 PLL1 Main counter M1 divide ratio M18 M17 M16 M15 M14 M13 M12 M11 M10 A14 PLL1 Swallow counter A1 divide ratio A13 A12 A11 A10 PLL1 Fractional counter F1 numerator value F14 F13 F12 F11 F10 Address 1 1 MSB (first in) (last in) LSB Figure 5. Serial Interface Mode Timing Diagram Data tDSU tDHLD tClockL tClockH Clock tCLE tLEW tLEC LE tData Out Data Out (foLD pin) PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 9 of 18 PE3293 Product Specification Programmable Divide Values (R1, R2, F1, F2, A1, A2, M1, M2) Data is clocked into the 21-bit shift register, MSB first. When LE is asserted HIGH, data is latched into the registers addressed by the last two bits shifted into the 21-bit register, according to Table 8. For example, to program the PLL1 (RF) swallow counter, A1, the last two bits shifted into the register (S0, S1) would be (1,1). The 5-bit A1 counter would then be programmed according to Table 9. For normal operation, S16 of address (0,0) (the Test bit) must be programmed to 0 even if PLL2 (IF) is not used. Program Modes Table 9. PE3293 Counter Programming Example Divide Value MSB S11 A14 0 1 2 31 0 0 0 1 S10 A13 0 0 0 1 S9 A12 0 0 0 1 S8 A11 0 0 1 1 LSB S7 A10 0 1 0 1 Address S1 1 1 1 1 1 1 S0 1 1 1 1 1 1 Several modes of operation can be programmed with bits C10 - C14 and C20 - C24, including the phase detector polarity, charge pump high impedance, output of the foLD pin and power-down modes. The PE3293 modes of operation are shown on Table 10. The truth table for the foLD output is shown in Table 11. Table 10. PE3293 Program Modes S15 C24 See Table 11 C23 See Table 11 S14 C22 S13 C21 (Note 2) S12 S11 C20 (Note 1) 0 = PLL2 on 1 = PLL2 off C10 (Note 1) 0 = PLL1 on 1 = PLL1 off S1 0 S0 0 0 = PLL1 CP normal 1 = PLL1 CP High Z 0 = PLL2 Phase Detector inverted 1 = PLL2 Phase Detector normal C11 (Note 2) 0 = PLL1 Phase Detector inverted 1 = PLL1 Phase Detector normal C14 See Table 11 C13 See Table 11 C12 0 = PLL1 CP normal 1 = PLL1 CP High Z 1 0 Note 1: The PLL1 power-down mode disables all of PLL1's components except the R1 counter and the reference frequency input buffer, with CP1 (pin 3) and fin1 (pin 5) becoming high impedance. The power down of PLL2 has similar results with CP2 (pin 18) and fin2 (pin 16) becoming high impedance. Power down of both PLL1 and PLL2 further disables counters R1 and R2, the reference frequency input, and the foLD output, causing fr (pin 8) and foLD (pin 10) to become high impedance. The Serial Control Interface remains active at all times. Note 2: The C11 and C21 bits should be set according to the voltage versus frequency slope of the VCO as shown in Figure 7. This relationship presumes the use of a passive loop filter. If an inverting active loop filter is used the relationship is also inverted. Figure 6. VCO Characteristics VCO Output Frequency (1) Positive slope VCO * When VCO1 (RF) slope is positive like (1), C11 should be set HIGH. * When VCO1 (RF) slope is negative like (2), C11 should be set LOW. * When VCO2 (IF) slope is positive like (1), C21 should be set HIGH. * When VCO2 (IF) slope is negative like (2), C21 should be set LOW. (2) Negative slope VCO VCO Input voltage Copyright Peregrine Semiconductor Corp. 2003 File No. 70/0015~02C | UTSi CMOS RFIC SOLUTIONS Page 10 of 18 PE3293 Product Specification Table 11. foLD Programming Truth Table X = don't care condition foLD Output State Disabled (Note 1) PLL 1 Lock detect (Note 2) (LD1) PLL2 Lock detect (Note 2) (LD2) PLL1 / PLL2 Lock detect (Note 2) PLL1 Reference divider output (fc1) PLL2 Reference divider output (fc2) PLL1 Programmable divider output (fp1) PLL2 Programmable divider output (fp2) Serial data out Reserved Reserved Counter reset (Note 3) C14 (PLL1F0) 0 0 0 0 1 0 1 0 1 1 1 1 C13 (PLL1LD) 0 1 0 1 X X X X 0 0 1 1 C24 (PLL2F0) 0 0 0 0 0 1 0 1 1 1 1 1 C23 (PLL2LD) 0 0 1 1 0 0 1 1 0 1 0 1 Note 1: When the foLD is disabled the output is a CMOS LOW. Note 2: Lock detect indicates when the VCO frequency is in "lock". When PLL1 is in lock and PLL1 lock detect is selected, the foLD pin will be HIGH with narrow pulses LOW. When PLL2 is in lock and PLL2 lock detect is selected, the foLD pin will be HIGH with narrow pulses LOW. When PLL1 / PLL2 lock detect is selected the foLD pin will be HIGH with narrow pulses LOW only when both PLL1 and PLL2 are in lock. Note 3: The counter reset state when activated resets all counters. Upon removal of the reset, counters M, A, and F resume counting in close alignment with the R counter (the maximum error is one prescaler cycle). The reset bits can be activated to allow smooth acquisition upon powering up. Programming the Pre-scaler P2 and P1 are used for internal testing of the prescaler and must be programmed with 0,0 for normal PLL operation. PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 11 of 18 PE3293 Product Specification Phase Comparator Characteristics PLL1 has the timing relationships shown below for fc1, fp1, LD1, UP1, and DOWN1. When C11 = HIGH, UP1 directs the internal PLL1 charge pump to source current and DOWN1 directs the PLL1 internal charge pump to sink current. If C11 = LOW, UP1 and DOWN1 are interchanged. PLL2 has the timing relationships shown below for fc2, fp2, LD2, UP2, and DOWN2. When C21 = HIGH, UP2 directs the internal PLL2 charge pump to source current and DOWN2 directs the PLL2 internal charge pump to sink current. If C21 = LOW, UP2 and DOWN2 are interchanged. Figure 7. Phase Comparator Timing Diagram fc1 (2) (Note 1) fp1 (2) (Note 1) LD1 (2) (Note 1) UP1 (2) DOWN1 (2) fc leads fp fc = fp fc lags fp fc lags fp fc lags fp Note 1: fc1(2), fp1(2), and LD1(2) are accessible via the foLD pin per programming in Table 11. Copyright Peregrine Semiconductor Corp. 2003 File No. 70/0015~02C | UTSi CMOS RFIC SOLUTIONS Page 12 of 18 PE3293 Product Specification Loop Filter Second/Third Order Loops Choosing the optimum loop filter for a design encompasses many trade offs. The rule of thumb for choosing the loop filter bandwidth is 10 percent of the step size. A second order loop (C1 C2 R2 and C4 C5 R5 in Figure 9 omitting C3 R3 C6 and R6) will provide the least amount of components and the fastest lock times. If lock time is an issue, one might try opening up the loop filter, although if it is too wide, instability will dominate and worsen lock time. If lock time is not an issue, a narrower second order filter will minimize residual FM without requiring additional components. Third Order loop filters (C1 C2 R2 C3 R3 and C4 C5 R5 C6 R6 in Figure 9) provide a good compromise between lock time and residual FM. We have found using a third order loop with 20 dB of rejection at the step size will halve the Residual FM as measured with a similar second order loop, with minimum effect on lock time. Loop Filter Bandwidth Design Considerations As part of the spur compensation circuitry, the PE329x series PLLs contain capacitors to ground internal to the charge pump. PLL1 contains a 50 pF capacitor and PLL2 contains a 100 pF capacitor. To ensure accurate loop filter calculations, it is critical that the calculated value of the first shunt capacitor (C1 & C4 in Figure 11) be at least 100 pF for PLL1 and 200 pF for PLL2. With this requirement satisfied, the remaining loop components can be calculated. For a stable loop, it is also important that the loop bandwidth be less than or equal to one tenth of the step size. Digital Control Lines Control Line Noise We have noticed frequency jitter during programming when a low impedance, such as a capacitor to ground, is placed next to any control line pin (clock, data, and load enable). The use of a 51 k ohm resistor in series with the control line will eliminate the problem with no effect to programming time. Enable Line Voltage The PE329x series PLLs use a level sensitive load enable. Therefore the digital controller must provide an active low to the part at all times except when the data is to be loaded into the shift register. If the PLL controller does not hold the voltage low, a high impedance resistor to ground should be added to the enable line to ensure stable operation. 5 Volt Operation: The PE329x series PLLs are not capable of accepting control voltages greater than 3.3 volts. Interface to 5 volt controllers requires the addition of resistor dividers to comply with the 3.3 volt maximum operation voltage. PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 13 of 18 PE3293 Product Specification Figure 8. Application Example Note 1: For optimum fractional spur and lock-time performance C2 and C5 should be polyester (or poly propylene). In addition, the loop filter components must be free from contamination. Contamination will result in poor spur performance. For accurate loop bandwidth, C1 must be greater than or equal to 100 pF, and C4 must be greater than or equal to 200 pF. Copyright Peregrine Semiconductor Corp. 2003 File No. 70/0015~02C | UTSi CMOS RFIC SOLUTIONS Page 14 of 18 PE3293 Product Specification Figure 9. Package Drawing 20-lead TSSOP (JEDEC MO-153-AC) S Y M B O L COMMON DIMENSION(MILLIMETERS) 0.65mm LEAD PITCH MIN --0.05 0.85 0.50 0.09 0.09 0.19 0.19 0.09 0.09 0 NOM ----0.90 0.60 ------0.22 ------1.0 REF 0.10 0.10 0.05 0.20 0.65 BSC 12 REF 12 REF MAX 1.10 0.15 0.95 0.75 ----0.30 0.25 0.20 0.16 8 A A1 A2 L R R1 b b1 c c1 01 L1 aaa bbb ccc ddd e 02 03 S Y M B O L AC MIN 6.40 4.30 NOM 6.50 4.40 6.4 BSC 0.65 BSC 20 1,2 A MAX 6.60 4.50 N O T E D E1 E e 3,8 4,8 N NOTE ISSUE 6 PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 15 of 18 PE3293 Product Specification Figure 10. Package Drawing 24-lead BCC Copyright Peregrine Semiconductor Corp. 2003 File No. 70/0015~02C | UTSi CMOS RFIC SOLUTIONS Page 16 of 18 PE3293 Product Specification Table 12. Ordering Information Order Code 3293-11 3293-12 3293-14 3293-15 3293-00 3293-04 Part Marking PE3293 PE3293 3293 3293 PE3293EK PE3293EK Description Screened to datasheet specs., fully qualified Screened to datasheet specs., fully qualified Screened to datasheet specs., fully qualified Screened to datasheet specs., fully qualified Evaluation Board Evaluation Board Package 20-lead TSSOP 20-lead TSSOP 24-lead BCC 24-lead BCC 20-lead TSSOP 24-lead BCC Shipping Method 74 units / Tube 2000 unit / T&R 640 Unit Trays 2000 Unit T&R 1 / Box 1 / Box PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 17 of 18 PE3293 Product Specification Sales Offices United States Peregrine Semiconductor Corp. 6175 Nancy Ridge Drive San Diego, CA 92121 Tel 1-858-455-0660 Fax 1-858-455-0770 Japan Peregrine Semiconductor K.K. 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: 03-3507-5755 Fax: 03-3507-5601 Europe Peregrine Semiconductor Europe Batiment Maine 13-15 rue des Quatre Vents F- 92380 Garches Tel 33-1-47-41-91-73 Fax 33-1-47-41-91-73 Australia Peregrine Semiconductor Australia 8 Herb Elliot Ave. Homebush, NSW 2140 Australia Tel: 011-61-2-9763-4111 Fax: 011-61-2-9746-1501 For a list of representatives in your area, please refer to our Web site at: http://www.peregrine-semi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Peregrine products are protected under one or more of the following U.S. patents: 6,090,648; 6,057,555; 5,973,382; 5,973,363; 5,930,638; 5,920,233; 5,895,957; 5,883,396; 5,864,162; 5,863,823; 5,861,336; 5,663,570; 5,610,790; 5,600,169; 5,596,205; 5,572,040; 5,492,857; 5,416,043. Other patents are pending. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a PCN (Product Change Notice). Peregrine, the Peregrine logotype, Peregrine Semiconductor Corp., and UTSi are registered trademarks of Peregrine Semiconductor Corporation. Copyright (c) 2003 Peregrine Semiconductor Corp. All rights reserved. Copyright Peregrine Semiconductor Corp. 2003 File No. 70/0015~02C | UTSi CMOS RFIC SOLUTIONS Page 18 of 18 |
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