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| OKI Semiconductor MSM7732-01 Audio CODEC FEDL7732-01-10 Issue Date: Nov. 2, 2005 GENERAL DESCRIPTION The MSM7732 is a single-channel full duplex CODEC CMOS IC which performs mutual transcoding between the analog voice band signals and 64 kbps PCM serial data. This device performs such functions as DTMF tone and several types of tone generation, transmit/receive data mute and gain control, and side tone path. FEATURES * Single 3 V power supply operation VDD: 2.4 V to 3.3 V * PCM interface data format : -law/A-law/linear (2's complement) selectable * PCM interface timing : long frame synchronous timing/short frame synchronous timing * Full-duplex single channel operation * Serial PCM transmission data rate: 64 kbps to 2048 kbps * Low power consumption Operating mode: 15 mW typ. (VDD = 3.0 V) Power-down mode: 3 W typ. (VDD = 3.0 V) * Master clock frequency: 2.048 MHz * Analog output stage 35 mW drive for receiver speaker (differential drive of 32 )--Gain adjustable 66 mW drive for receiver speaker (differential drive of 30 )--Gain adjustable 6.6 mW drive for earphone speaker (single drive of 32 ) --Gain adjustable * Transmit/receive mute, transmit/receive programmable gain control * Side tone path with programmable attenuation (8-step adjustment level) * Built-in DTMF tone generator * Built-in various ringing/function tone generator * Built-in various ring back tone generator * Serial MCU interface control: 3 bit * Built-in transmit voice signal detector * Built-in op amps and analog switches for various analog interface * Package options : 30-pin plastic SSOP (SSOP30-P-56-0.65-K) (MSM7732-01 MB) 48-pin plastic TQFP (TQFP48-P-0707-0.50-K) (MSM7732-01 TB) 48-pin plastic LGA (P-TFLGA48-0707-0.8) (MSM7732-01 LB) 48-pin plastic BGA (P-LFBGA48-0707-0.8) (MSM7732-01 LA) 1/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 BLOCK DIAGRAM AMPAI AMPAO AIN- AIN+ GSX AOUT+ 35 mW for receiver AMPA 20 k Voice Detect A/D 20 k 32 -1 CR3-B7, 6, 5 off,-15 to -3 dB 2 dB step to MCUI/F Microphone amp input Slope Filter CR0-B2 CR4-B6 BPF CR2-B7 TX ON/OFF PCM Compand PCMOUT CR0-B0 CR2-B6, 5, 4 -6 to +8 dB 2 dB step AOUT- PWI VFRO 8.8 mW SAO for earphone TONE GEN. CR3-B3, 2, 1, 0 -36 to -6 dB 2 dB step CR2-B3 RX ON/OFF CR2-B2, 1, 0 CR1-B0 -12 to +9 dB Through (0 dB loss) 3 dB step or -12 loss CR0-B0 32 20 k D/A 32 CR4-B5 LPF PCM Expand PCMIN SWA SWB SWC SWD SWE CR1-B1 SG VREF MCU I/F BCLK SYNC MCK PDN AG1 AG2 VDD DG VA EXCK DEN DIO 2/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 PIN CONFIGURATION (TOP VIEW) VDD SWA SWB SWC AMPAI AMPAO AIN+ AIN- GSX SWD SWE SG VFRO AG1 SAO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DG MCK DEN DIO EXCK PCMOUT PCMIN SYNC BCLK PDN AG2 AOUT+ AOUT- PWI VA 30-Pin Plastic SSOP 47 SWC 46 SWB 45 SWA 40 MCK 39 DEN 38 DIO 44 VDD 41 DG 48 NC 43 NC 42 NC NC 1 AMPAI 2 AMPAO 3 AIN+ 4 AIN- 5 GSX 6 NC 7 NC 8 SWD 9 SWE 10 SG 11 NC 12 NC 13 NC 14 VFRO 15 AG1 16 NC 17 SAO 18 VA 19 PWI 20 NC 21 AOUT- 22 AOUT+ 23 NC 24 37 NC 36 NC 35 EXCK 34 PCMOUT 33 PCMIN 32 SYNC 31 NC 30 BCLK 29 PDN 28 NC 27 AG2 26 NC 25 NC NC: No Connection 48-Pin Plastic TQFP 3/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 8 AG2 7 6 5 PWI 4 VA 3 SAO 2 AG1 1 VFRO H AOUT+ AOUT- G PDN NC NC NC NC NC SG SWE F BCLK NC NC SWD E SYNC NC NC GSX D PCMIN NC NC AIN- C PCMOUT NC NC AIN+ B EXCK DIO NC NC NC NC NC AMPAO A DEN MCK DG VDD SWA SWB SWC AMPAI Index (A1) NC: No Connection 48-Pin Plastic LGA 48-Pin Plastic BGA 4/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol VDD SWA SWB SWC AMPAI AMPAO AIN+ AIN- GSX SWD SWE SG VFRO AG1 SAO VA PWI AOUT- AOUT+ AG2 PDN BCLK SYNC PCMIN PCMOUT EXCK DIO DEN MCK DG Type -- IO IO IO I O I I O IO IO O O -- O -- I O O -- I I I I O I IO I I -- Power supply (3.0 V) Analog switch A Analog switch B Analog switch C Amplifier A inverting input Amplifier A output Transmit side amplifier non-inverting input Transmit side amplifier inverting input Transmit side amplifier output Analog switch D Analog switch E Analog signal ground (1.4 V) Receive side voice output Analog ground 1 (0 V) Receive side sounder amplifier output Analog power supply (3.0 V) Receive side voice amplifier input Receive side voice amplifier output - Receive side voice amplifier output + Analog ground 2 (0 V) Power down control input PCM data shift clock input PCM data shift sync signal input Receive side PCM signal input Transmit side PCM signal output Clock signal input for control register Address and data input or output for control register Enable signal input for control register Master clock input (2.048 MHz) Digital ground (0 V) Description 5/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 PIN FUNCTIONAL DESCRIPTION AIN+, AIN-, GSX Transmit analog inputs and the output for transmit gain adjustment. AIN- connects to inverting input of the internal transmit amplifier. AIN+ connects to non-inverting input of the internal transmit amplifier. GSX connects to the internal transmit amplifier output. Refer to Figure 1 for gain adjustment. VFRO, SAO, AOUT+, AOUT-, PWI Receive analog outputs and the outputs for receive gain adjustment. VFRO is the receive filter output for the voice signal. SAO is the receive filter output for an acoustic component of the sound tone. SAO can directly drive 32 load. AOUT+ and AOUT- are differential analog signal outputs which can directly drive a 32 load. Refer to Figure 1. GSX R2 Vi C1 R1 AIN- AIN+ - + Transmit Gain: VGSX/Vi to ENCODER 10 F 0.1 F + - SG AOUT+ VREF -1 Vo = VVFRO (R3/R4) x2 R3 R4 AOUT- PWI VFRO SAO D/A Conv. Sounder output signal Figure 1 Analog Input/Output Interface 6/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 SG Analog signal ground. The output voltage of this pin is approximately 1.4 V. Put the bypass capacitors (10 F in parallel with 0.1 F ceramic type) between this pin and AG to get the specified noise characteristics. During power-down, this output voltage is 0 V. AMPAI, AMPAO Used for amplifier A. The pin AMPAI is connected to the amplifier A inverting input, and the pin AMPAO is connected to the amplifier A output. SWA, SWB, SWC Used for the internal analog switch. The pin SWB connects to the pin SWA or the pin SWC. This is controlled by CR1-B1. SWD, SWE Used for the internal analog switch. The pin SWD connects to the pin SWE or not. This is controlled by CR1-B2. VDD, VA +3 V power supply for analog. VDD is the digital power supply. VA is the analog power supply. Since these pins are separated in the device, connect them as close as possible on the PCB. DG, AG1, AG2 Ground. DG is the digital system ground. AG1 and AG2 are connected to the analog system ground. The DG pin must be kept as close as possible to AG1 and AG2 on the PCB. PDN Power down and reset control input. When set to digital "0", the system changes to the power down state and control registers are reset. Since the power down mode is controlled by a logical OR with CR0-B5 of the control register, set CR0-B5 to logic "0" when using this pin. Be sure to reset the control registers by executing this power down to keep this pin to digital "0" level for 200 ns or longer after the power is turned on and VDD exceeds 2.4 V. MCK Master clock input. The frequency must be 2.048 MHz. MCK can be asynchronous with SYNC and BCLK. BCLK Shift clock input for the PCM data. The frequency is set in the range of 64 kHz to 2048 kHz. 7/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 SYNC 8 kHz synchronous signal input for transmit and receive PCM data. Synchronize this signal with BCLK signal. Refer to Figure 2. PCMOUT Transmit PCM data output. This PCM output signal is output from MSB synchronously with the rising edge of BCLK and SYNC. Refer to Figure 2. This is a logic output pin so that external pull-up is not required. This pin outputs logic "L" except during effective PCM data bits, and outputs logic "H" during power-down. PCMIN Receive PCM data input. This PCM input signal is shifted in on the falling edge of BCLK and is input from MSB. Refer to Figure 2. SYNC BCLK PCMIN or PCMOUT MSB 8 kHz (125 s) LSB 14 bit in the case of linear mode (a) Long frame synchronous interface 8 kHz (125 s) SYNC BCLK PCMIN or PCMOUT MSB LSB 14 bit in the case of linear mode (b) Short frame synchronous interface Figure 2 PCM Interface Basic Timing Diagram 8/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 DEN, EXCK, DIO Serial control ports for MCU interface. Reading and writing data is performed by an external MCU through these pins. Eight registers with eight bits are provided on the devices. DEN is the "Enable" control signal input, EXCK is the data shift clock input, and DIO is the address and data input or output. Figure 3 shows the input or output timing diagram. DEN EXCK DIO W A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 (a) Write Data Timing Diagram DEN EXCK DIO R A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 input output (b) Read Data Timing Diagram Figure 3 MCU Interface Input/Output Timing Table 1 shows the register map. Table 1 Name CR0 CR1 CR2 CR3 Address A2 0 0 0 0 A1 0 0 1 1 A0 0 1 0 1 B7 A/ SEL -- TX ON/OFF GAIN2 DTMF/ CR4 CR5 CR6 CR7 1 1 1 1 0 0 1 1 0 1 0 1 OTHERS SEL -- VOX ON/OFF VOX OUT B6 PON AOUT -- B5 Control and Detect Data B4 B3 PDN RX SHORT FRAME RX ON/OFF TONE GAIN3 TONE3 -- -- -- B2 SLP SW D/E B1 SLP SEL SW C/A B0 LNR RX PAD R/W R/W R/W R/W R/W PDN ALL PDN TX -- -- TX GAIN2 TX GAIN1 TX GAIN0 TONE ON/OFF TONE4 -- -- -- RX GAIN2 RX GAIN1 RX GAIN0 TONE GAIN2 TONE2 -- -- -- TONE GAIN1 TONE1 -- -- -- TONE GAIN0 TONE0 -- -- -- Side Tone Side Tone Side Tone GAIN1 TONE SEND -- GAIN0 SAO/ VFRO -- R/W R/W R/W R ON LVL1 ON LVL0 TX NOISE TX NOISE LVL1 LVL0 R/W : Read/Write enable R : Read only register 9/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition -- -- -- -- Rating -0.3 to +5.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -55 to +150 Unit V V V C RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Operating Temperature Input High Voltage Input Low Voltage Digital Input Rise Time Digital Input Fall Time Digital Output Load Bypass Capacitor for SG Master Clock Frequency Bit Clock Frequency Synchronous Signal Frequency Clock Duty Ratio Sync Pulse Setting Time Synchronous Signal Width Symbol VDD Ta VIH VIL tir tif CDL CSG FMCK FBCK1 FBCK2 FSYNC DCLK TSB TBS tWS Condition Voltage must be fixed -- To all digital input pins To all digital input pins To all digital input pins To all digital input pins To all digital output pins Between SG and AG MCK BCLK (A/-law) BCLK (Linear) SYNC MCK, BCLK, EXCK SYNC BCLK BCLK SYNC SYNC Min. +2.4 -40 0.7 x VDD 0 -- -- -- 10+0.1 -0.01% 64 128 -- 40 -100 100 1BCLK Typ. +3.0 -- -- -- -- -- -- -- 2.048 -- -- 8.0 50 -- -- -- Max. +3.3 +85 VDD 0.16 x VDD 50 50 100 -- 0.01% 2048 2048 -- 60 100 -- 100 Unit V C V V ns ns pF F MHz kHz kHz kHz % ns ns s 10/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 2.4 V to 3.3 V, Ta = -40C to +85C) Parameter Symbol IDD1 Condition Operation Mode No Signal (VDD = 3.0 V) Operation Mode Power Supply Current IDD2 No Signal (VDD = 3.0 V) AOUT+, AOUT- or SAO is active IDD3 Input Leakage Voltage Output High Voltage Output Low Voltage Input Capacitance IIH IIL VOH VOL CIN Power Down Mode (VDD = 3.0 V, Ta = 25C) VI = VDD VI = 0 V IOH = 0.4 mA IOL = -1.2 mA -- 0 -- -- 0.5 x VDD 0 -- 1.0 -- -- -- 0.2 5 10 2.0 0.5 VDD 0.4 -- A A A V V pF 0 9.0 20.0 mA Min. 0 Typ. 5.0 Max. 11.0 Unit mA Analog Interface Characteristics (VDD = 2.4 V to 3.3 V, Ta = -40C to +85C) Parameter Input Resistance Output Load Resistance Output Load Capacitance Symbol RINX RLGX1 RLGX2 CLGX VO1 Condition AMPAI, AIN+, AIN-, PWI AMPAO, GSX, VFRO SAO, AOUT+, AOUT- Analog output pins AMPAO, GSX, VFRO RL = 20 k SAO RL = 32 AOUT+, AOUT- Differential output VDD = 2.7 to 3.3 V RL = 32 AOUT+, AOUT- 2 * VO3 Min. 10 20 32 -- -- Typ. -- -- -- -- -- Max. -- -- -- 100 *11.3 Unit M k pF VPP Output Amplitude VO2 -- -- 3.0 VPP Differential output VDD = 3.0 V RL = 30 -- -- -- -20 -100 -- -- -- -- -- 1.0 -- -- 1.4 40 -- 3.98 1.0 -- 20 100 -- 80 300 VPP % % mV mV V k Total Harmonic Distortion Input Offset Voltage SG Output Voltage SG Output Impedance THD1 * THD2 VOFGX1 VOFGX2 VSG RSG 2 SAO, AOUT+, AOUT-(VO1, VO2) AOUT+, AOUT- (VO3) AMPAO, GSX VFRO, SAO, AOUT+, AOUT- SG SG Internal Switch ON Impedance Rsw All internal switches *1 -7.7 dBm (600) = 0 dBm0 , +3.17 dBm0 = 1.3 VPP *2 Expected value 11/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 AC Characteristics (VDD = 2.4 V to 3.3 V, Ta = -40C) Parameter Symbol LOSS T1 LOSS T3 LOSS T4 LOSS T5 LOSS R6 LOSS R1 LOSS R2 Receive Frequency Response LOSS R3 LOSS R4 LOSS R5 SD T1 Transmit Signal to Distortion Ratio SD T2 SD T3 SD T4 SD T5 SD R1 Receive Signal to Distortion Ratio SD R2 SD R3 SD R4 SD R5 GT T1 GT T2 Transmit Gain Tracking GT T3 GT T4 GT T5 GT R1 GT R2 Receive Gain Tracking GT R3 GT R4 GT R5 1020 1020 1020 1020 Freq. (Hz) 0 to 60 1020 3300 3400 3968.75 0 to 3000 1020 3300 3400 3968.75 3 0 -30 -40 -45 3 0 -30 -40 -45 3 -10 -40 -50 -55 3 -10 -40 -50 -55 -- -0.2 -0.6 -1.2 -- -0.2 -0.6 -1.2 -0.2 (*1) (*1) 0 -- -0.15 0 13 35 35 35 28 23 35 35 35 28 23 -0.2 Condition Level (dBm0) Others Min. 25 -0.15 0 -- -0.15 0 13 -0.15 Typ. -- -- Reference -- -- -- -- Reference -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reference -- -- -- -- Reference -- -- -- 0.2 0.6 1.2 0.2 0.6 1.2 0.2 0.80 0.80 -- -- -- -- -- -- -- -- -- -- -- 0.2 0.80 0.80 -- 0.20 Max. -- 0.20 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB LOSS T2 300 to 3000 Transmit Frequency Response 12/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 AC Characteristics (Continued) (VDD = 2.4 V to 3.3 V, Ta = -40C to +85C) Symbol Parameter NIDLT NIDLR AVT Absolute Signal Amplitude AVR Power Supply Noise Rejection Ratio PSRRT PSRRR tSDX tSDR tXD1 Digital Input/Output Timing PCM Interface tRD1 tXD2 tRD2 tXD3 tRD3 tM1 tM2 tM3 tM4 Serial Port Digital Input/Output Setting Time tM5 tM6 tM7 tM8 tM9 tM10 tM11 Shift Clock Frequency *1 *2 *3 fEXCK -- -- EXCK -- CL = 50 pF See Fig. 6 -- 1 LSTTL + 100 pF See Fig. 5 Noise Freq: 0 to 50 kHz Noise Level: 50 mVpp -- 1020 0 VFRO 0.285 30 30 0 0 0 0 50 50 50 50 100 50 50 0 50 50 0 -- Freq. (Hz) Idle Channel Noise -- -- Condition Level (dBm0) AIN = SG -- (*1) (*1,*2) GSX -- -- 0.285 -- -- 0.320 (*3) 0.320 (*3) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -68 -72 0.359 0.359 -- -- 200 200 200 200 -- -- -- -- -- -- -- 100 -- -- 50 10 dBm0p Vrms Vrms dB dB ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz Others Min. Typ. Max. Unit Use the P-message weighted filter. PCMIN input code "11010101"(A-law) "11111111"(-law) 0.320 Vrms = 0 dBm0 = -7.7 dBm 13/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 AC Characteristics (DTMF and Other Tones) (VDD = 2.4 V to 3.3 V, Ta = -40C to +85C) Parameter Frequency Difference Symbol DFT VTL VTH VRL VRH Relative Level of DTMF Tones RDTMF Transmit Tones 0 dB) Receive Tones -6 dB) Condition DTMF Tones, Other Tones DTMF (Low) Min. -1.5 -18 -16 -10 -8 +1 Typ. -- -16 -14 -8 -6 +2 Max. +1.5 -14 -12 -6 -4 +3 Unit % dBm0 dBm0 dBm0 dBm0 dB (Gain setting DTMF (High) and Other Tones DTMF (Low) Original (Reference) Tones Signal Level *4 (Gain setting DTMF (High) and Other Tones VTH/VTL, VRH/VRL *4 Does not include the setting value for the programmable gain. AC Characteristics (Programmable Gain Stages) (VDD = 2.4 V to 3.3 V, Ta = -40C to +85C) Parameter Gain Accuracy Symbol DG Condition All gain stages, to programmed value Min. -1 Typ. 0 Max. +1 Unit dB AC Characteristics (Voice Detect Function) (VDD = 2.4 V to 3.3 V, Ta = -40C to +85C) Parameter Voice Detection Time Voice Detection Accuracy Symbol TVON TVOF DVX Condition Silence>Voice (Voice/Silence differential: 10 dB) For detection level set values by CR6-B6, B5 Min. -- 140 -2.5 Typ. 5 160 0 Max. -- 180 2.5 Unit ms ms dB 14/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 TIMING DIAGRAM Transmit Side PCM Timing (Normal Synchronous Interface) BCLK 0 1 2 3 4 5 6 7 8 9 10 tSB tWS tXD1 tXD2 tXD3 MSB LSB SYNC PCMOUT tSDX When tSB >= 0, the Delay of the MSB is defined as tXD1. When tSB < 0, the Delay of the MSB is defined as tSDX. Transmit Side PCM Timing (Short Frame Synchronous Interface) BCLK 0 1 2 3 4 5 6 7 8 9 10 tSB tWS tBS SYNC tXD1 tXD2 MSB tXD3 LSB PCMOUT Receive Side PCM Timing (Normal Synchronous Interface) BCLK 0 1 2 3 4 5 6 7 8 9 10 tSB tRD1 MSB tSDR tWS tRD2 SYNC tRD3 LSB PCMIN Receive Side PCM Timing (Short Frame Synchronous Interface) BCLK 0 1 2 3 4 5 6 7 8 9 10 tSB tWS tBS tRD1 tRD2 MSB SYNC tRD3 LSB PCMIN Figure 4 PCM Interface Timing 15/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 Serial Port Timing for Microcontroller Interface DEN EXCK tM1 tM4 tM2 1 tM3 tM6 2 3 tM5 4 tM7 5 6 11 12 tM9 tM10 DIO (WRITE) DIO (READ) W/R W/R A1 A2 A1 A1 A0 A0 B7 tM8 B7 B1 B1 B0 tM11 B0 Figure 5 Serial Control Port Interface 16/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 FUNCTIONAL DESCRIPTION Control Registers CR0 (Basic operating mode 1) Note: Initial Value: Reset state by PDN B7 CR0 Initial Value A/ SEL 0 B6 PON AOUT 0 B5 B4 B3 B2 SLP 0 B1 SLP SEL 0 B0 LNR 0 PDN ALL PDN TX PDN RX 0 0 0 B7............ PCM companding law select; 0/-law, 1/A-law B6............ Power on control for output amps (AOUT+, AOUT-); 0/Power down, 1/Power on B5............ Power down (entire system); 0/Power on, 1/Power down B4............ Power down (transmit and amplifier A); 0/Power on, 1/Power down B3............ Power down (receive only); 0/Power on, 1/Power down B2............ Slope filter enable; 0/Slope filter disable, 1/ Slope filter enable When using this data for power down control, set pin PDN at "1" level. The control registers are not reset by this signal. B1............ The type of slope filter select; 0/CASE1, 1/CASE2, refer to Figure 6. B0............ PCM interface linear code select; 0/Companding law selected by CR0-B7 1/14-bit linear code (2's complement) in spite of CR0-B7 6 4 2 0 Gain [dB] -2 -4 -6 -8 -10 -12 -14 0 500 1000 1500 2000 2500 Frequency [Hz] 3000 3500 4000 CASE1 CASE2 Figure 6 Frequency Response of Slope Filter 17/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 CR1 (Basic operating mode 2) B7 CR1 Initial Value -- 0 B6 -- 0 B5 -- 0 B4 -- 0 B3 SHORT FRAME 0 B2 SW D/E 0 B1 B0 SW C/A RX PAD 0 0 B7, B6, B5, B4......Not used B3.....................Short frame synchronous interface select; 0/Long frame synchronous interface, 1/Short frame synchronous interface .....................Analog switch control B2 : 0/SWD to SWE open, 1/ SWD to SWE closed B1.....................Analog switch control B0.....................Receive side PAD : 0/SWB to SWA closed. The SWC pin is high impedance. 1/SWB to SWC closed. The SWA pin is high impedance. : 1/inserted, 12 dB loss 0/no PAD 18/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 CR2 (PCM CODEC operating mode setting and transmit/receive gain adjustment) B7 CR2 Initial Value TX ON/OFF 0 B6 TX GAIN2 0 B5 TX GAIN1 1 B4 TX GAIN0 1 B3 RX ON/OFF 0 B2 RX GAIN2 0 B1 RX GAIN1 1 B0 RX GAIN0 1 B7..................... PCM coder disable; 0/Enable, 1/Disable (transmit PCM idle pattern) B6, B5, B4............ Transmit gain adjustment, refer to Table 2. B3..................... PCM decoder disable; 0/Enable, 1/Disable (receive PCM idle pattern) B2, B1, B0............ Receive gain adjustment, refer to Table 2. Table 2 B6 0 0 0 0 1 1 1 1 B5 0 0 1 1 0 0 1 1 B4 0 1 0 1 0 1 0 1 Transmit Gain -6 d B -4 d B -2 d B 0 dB +2 dB +4 dB +6 dB +8 dB B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Receive Gain -1 2 d B -9 d B -6 d B -3 d B 0 dB +3 dB +6 dB +9 dB The above gain settings table shows the transmit/receive voice signal gain settings and the transmit side gain settings for DTMF tones and other tones. Tone signal transmission is enabled by CR4-B6, and the gain setting is set to the levels shown below. DTMF tones (low group): -16 dBm0 DTMF tones (high group) and other tones: -14 dBm0 For example, if the transmit gain set value is set to +8 dB (B6, B5, B4) = (1, 1, 1), then the following tones appear at the PCMOUT pin. DTMF tones (low group): -8 dBm0 DTMF tones (high group) and other tones: -6 dBm0 Gain setting for the side tone (path to the receive side from the transmit side) and the receive side tone is provided by register CR3. 19/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 CR3 (Side tone and other tone generator gain setting) B7 CR3 Initial Value GAIN2 0 B6 GAIN1 0 B5 GAIN0 0 B4 TONE ON/OFF 0 B3 TONE GAIN3 0 B2 TONE GAIN2 0 B1 TONE GAIN1 0 B0 TONE GAIN0 0 Side Tone Side Tone Side Tone B7, B6, B5............Side tone path gain setting, refer to Table 3. B4..................... Tone generator enable; 0/Disable, 1/Enable B3, B2, B1, B0...... Tone generator gain adjustment for receive side, refer to Table 4. Table 3 B7 0 0 0 0 1 1 1 1 B6 0 0 1 1 0 0 1 1 B5 0 1 0 1 0 1 0 1 Side Tone Path Gain OFF -15 dB -13 dB -11 dB -9 dB -7 dB -5 dB -3 dB Table 4 B3 0 0 0 0 0 0 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Tone Generator Gain OFF -34 dB -32 dB -30 dB -28 dB -26 dB -24 dB -22 dB B3 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Tone Generator Gain -20 dB -18 dB -16 dB -14 dB -12 dB -10 dB -8 dB -6 dB The tone generator gain setting table for the receive side, as shown in Table 4, depends upon the following reference levels. DTMF tones (low group): -2 dBm0 DTMF tones (high group) and other tones: 0 dBm0 For example, when selecting -6 dB (B3, B2, B1, B0) = (1, 1, 1, 1) as a tone generator gain, the signal amplitude of each DTMF tone on SAO or VFRO is as follows: DTMF tones (low group): -8 dBm0 DTMF tones (high group) and other tones: -6 dBm0 20/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 CR4 (Tone generator operating mode and frequency select) B7 CR4 Initial Value DTMF/ Others SEL 0 B6 TONE SEND 0 B5 SAO/ VFRO 0 B4 TONE4 0 B3 TONE3 0 B2 TONE2 0 B1 TONE1 0 B0 TONE0 0 B7 ........................ B6 ........................ B5 ........................ B4, B3, B2, B1, B0 ... DTMF or other tones select; 0/Others, 1/DTMF Tone transmit enable (transmit side); 0/Voice signal (transmit), 1/Tone transmit Tone output pin select (receive side); 0/VFRO, 1/SAO Tone frequency setting, refer to Tables 5-1 and 5-2. Table 5-1 (a) B7 = 1 (DTMF tones) B4 * * * * * * * * B3 0 0 0 0 0 0 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Frequency 697 Hz + 1209 Hz 697 Hz + 1336 Hz 697 Hz + 1477 Hz 697 Hz + 1633 Hz 770 Hz + 1209 Hz 770 Hz + 1336 Hz 770 Hz + 1477 Hz 770 Hz + 1633 Hz B4 * * * * * * * * B3 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Frequency 852 Hz + 1209 Hz 852 Hz + 1336 Hz 852 Hz + 1477 Hz 852 Hz + 1633 Hz 941 Hz + 1209 Hz 941 Hz + 1336 Hz 941 Hz + 1477 Hz 941 Hz + 1633 Hz *Undefined (b) B7 = 0 (Other tones) Table 5-2 B4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Frequency 2730 Hz/2500 Hz 8 Hz wamble 2000 Hz/2667 Hz 8 Hz wamble 1000 Hz/1333 Hz 8 Hz wamble B4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Frequency 1200 Hz 1300 Hz -- 1477 Hz 1633 Hz 2000 Hz 2100 Hz -- 2400 Hz -- 2500 Hz -- -- 2700 Hz -- 3000 Hz -- -- -- -- -- -- 400 Hz 440 Hz 480 Hz -- 667 Hz 800 Hz 1000 Hz 21/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 CR5 (Not used) B7 CR5 Initial Value -- B6 -- B5 -- B4 -- B3 -- B2 -- B1 -- B0 -- 0 0 0 0 0 0 0 0 B7-B0......... Not used CR6 (VOX function control) B7 CR6 Initial Value VOX ON/OFF 0 B6 B5 B4 -- B3 -- B2 -- B1 -- B0 -- ON LVL1 ON LVL0 0 0 0 0 0 0 0 B7 ........................... VOX function enable; 0/Disable, 1/Enable If B7 is set to a logic "1", B3 should be set to a logic "1". B6, B5........................ Voice detector level setting; (0,0): -20 dBm0 (0,1): -26 dBm0 (1,0): -32 dBm0 (1,1): -38 dBm0 B4, B2, B1, B0 ......... Not used CR7 (Detect register, read only) B7 CR7 Initial Value *For IC testing VOX OUT 0 B6 LVL1 0 B5 LVL0 0 B4 -- * B3 -- * B2 -- * B1 -- * B0 -- * TX NOISE TX NOISE B7.............................. Voice detection; 0/Silence, 1/Voice detect B6, B5........................ Voice detect level (indicator); (0,0): Below -50 dBm0 (0,1): -40 to -50 dBm0 (1,0): -30 to -40 dBm0 (1,1): Above -30 dBm0 Note: These outputs are enabled when the VOX function is turned on by CR6-B7. B4, B3, B2, B1, B0......... Not used 22/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 APPLICATION CIRCUIT VDD Mic GND C9 10 F DEN 39 DIO 38 NC 37 NC R1 C1 C4 NC 1 AMPAI 2 R2 AMPAO 3 AIN+ 4 AIN - C2 R3 5 GSX 6 NC R4 7 NC 8 SWD 9 SWE C3 10 SG 11 NC C5 12 NC 48 SWC 47 SWB 46 SWA 45 VDD 44 NC 43 NC 42 DG 41 MCK 40 MCU I/F 20 k Voice Detect PCM Compand 20 k A/D Slope Filter BPF TONE / DTMF Gen 36 EXCK 35 PCMOUT 34 PCMIN 33 SYNC 32 NC 31 BCLK 30 PDN 29 NC 28 AG2 27 NC GND 26 NC 25 D/A LPF PCM Expand VREF 20 k 32 32 32 0.1 F NC 13 NC 14 VFRO 15 AG1 16 NC 17 SAO 18 VA 19 PWI 20 NC 21 AOUT22 AOUT+ 23 NC 24 C6 VDD R5 R6 Earphone IN OUT Speaker C7 Hands Free Kit 23/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 PACKAGE DIMENSIONS (Unit: mm) SSOP30-P-56-0.65-K Mirror finish 5 Notes for Mounting the Surface Mount Type Package Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (5m) 0.19 TYP. 5/Dec. 5, 1996 The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 24/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 (Unit: mm) TQFP48-P-0707-0.50-K Mirror finish 5 Notes for Mounting the Surface Mount Type Package Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised Epoxy resin 42 alloy Solder plating (5m) 0.13 TYP. 4/Oct. 28, 1996 The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 25/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 (Unit: mm) P-LFBGA48-0707-0.80 5 Notes for Mounting the Surface Mount Type Package Package material Package weight (g) Rev. No./Last Revised Epoxy resin 0.12 TYP. 1/Jun. 20, 2001 The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 26/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 (Unit: mm) P-TFLGA48-0707-0.80 5 Notes for Mounting the Surface Mount Type Package Package material Package weight (g) Rev. No./Last Revised Epoxy resin 0.10 TYP. 2/Jun. 20, 2001 The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 27/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 REVISION HISTORY Document No. FEDL7732-01-04 FEDL7732-01-05 FEDL7732-01-06 FEDL7732-01-07 FEDL7732-01-08 FEDL7732-01-09 FEDL7732-01-10 Date Nov. 2001 Jan. 15, 2002 Page Previous Current Edition Edition 26 27 26 27 2 8 23 2 10 15 Edition 4 Description Changed the package outline diagram. Changed the package outline diagram. Addition of RX PAD in the Block Diagram. More clarification of PCMOUT output state Correction of false connection of C2 and R3 in APPLICATION CIRCUIT Addition of TXON/OFF and RXON/OFF in the Block Diagram Addition of tSB Addition of tSB Addition of description about tXD1and tSDX Jun. 3, 2004 Jun. 15, 2004 Jul. 29, 2004 May 18, 2005 Nov 2, 2005 2 8 23 2 10 15 28/29 FEDL7732-01-10 OKI Semiconductor MSM7732-01 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2005 Oki Electric Industry Co., Ltd. 29/29 |
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