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CPC7582
Line Card Access Switch
Features * Small 16 pin surface mount SOIC package * Monolithic IC reliability * Low matched RDSON * Eliminates the need for zero cross switching * Flexible switch timing to transition from ringing mode to idle/talk mode. * Clean, bounce free switching * Tertiary protection consisting of integrated current limiting, thermal shutdown and SLIC protection * 5V operation with power consumption <10mW * Intelligent battery monitor * Latched logic level inputs, no drive circuitry * Pin to pin compatible to the Lucent 7582 family
Description The CPC7582 is a monolithic solid state switch in a 16 pin surface mount SOIC package. It provides the necessary functions to replace two 2-Form-C electromechanical relays on analog line cards found in Central Office, Access and PBX equipment. The device contains solid state switches for tip and ring line break, ring injection/ring return and line test access. The CPC7582 requires only a +5V supply and offers "break-before-make" or "make-before-break" switch operation using simple logic level input control. There are two versions of the CPC7582, the CPC7582BA and the CPC7582BB. The "BA" version has a protection SCR which provides protection to the SLIC device and subsequent circuitry during fault conditions.
Applications * Central office (CO) * Digital Loop Carrier (DLC) * PBX Systems * Digitally Added Main Line (DAML) * Hybrid Fiber Coax (HFC) * Fiber in the Loop (FITL) * Pair Gain System * Channel Banks
Ordering Information Part # CPC7582BA CPC7582BB CPC7582BA-TR CPC7582BB-TR Description 6 Pole with protection SCR 6 Pole without protection SCR Tape & Reel Version Tape & Reel Version
Block Diagram
TACCESS(5) TRING(4) VBAT Reference (16)
TIP
R1
TLINE (3)
SW5 Line Test Access
SW3 Ringing Return SW1 Break SCR and Trip Circuit
TBAT (2)
Secondary Protection
SLIC
Ring
R2 RLINE (14) SW6 Line Test Access SW4 Ringing Access SW2 Break
CPC7582BA
RBAT(15)
Ring Generator
RACCESS (12) RRING (13) + Battery
DS-CPC7582-R1.0
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CPC7582
Absolute Maximum Ratings (@ 25 C)
Parameter Min Operating Temperature Range -40 Storage Temperature Range -40 Relative Humidity Range 5 Pin Soldering Temperature (t=10 s max) +5V Power Supply Battery Supply Logic Input Voltage Logic Input to Switch Output Isolation Switch Isolation (SW1, SW2, SW3, SW5, SW6) Switch Isolation (SW4) Max Units +110 C +150 C 95 % +260 C 7 -85 7 330 330 480 V V V V V V Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and effect its reliability.
Power Supply Specifications
Supply VDD VBAT1 Min +4.5 -19 Typ +5.0 Max +5.5 -72 Unit V V
Electrical Characteristics TA = -40oC to +85oC (unless otherwise specified) Minimum and maximum values are production testing requirements. Typical values are characteristic of the device and are the result of engineering evaluations. Typical values are provided for information purposes only and are not part of the testing requirements.
1V BAT is used only as a reference for internal protection circuitry. If VBAT rises above -10V, the device will enter an all off state and will remain in the all off state until the battery voltage drops below -15V.
ESD Rating (HBM) 1000V
Table 1. Break Switch, SW1 and SW2
Parameters Conditions Symbol Isw Isw Isw Min Typ 0.1 0.3 0.1 Max 1 1 1 Units A A A Off-state Leakage Current: +25C Vsw (differential)= -320V to Gnd Vsw (differential)= -60V to +260V +85C Vsw (differential)= -330V to Gnd Vsw (differential)= -60V to +270V -40C Vsw (differential)= -310V to Gnd Vsw (differential)= -60V to +250V RDSON (SW1,SW2): +25C TLINE= +/-10 mA, +/-40mA, TBAT= -2V +85C TLINE= +/-10 mA, +/-40mA, TBAT= -2V -40C TLINE= +/-10 mA, +/-40mA, TBAT= -2V RDSON Match Per ON-resistance Test Condition of SW1, SW2RON SW1-RONSW2 dc Current Limit: +25C Vsw (on) = +/- 10V +85C Vsw (on) = +/- 10V -40C Vsw (on) = +/- 10V Dynamic Current Limit: Break switches in ON state, Ringing (t=<0.5s) access switches OFF, Apply +/- 1000V at 10/1000ms pulse, Appropriate secondary protection in place.
V V V Magnitude
-
14.5 20.5 10.5 0.15
28 0.8

lsw lsw lsw Isw
80 -
300 160 400 2.5
425 -
mA mA mA A
2
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CPC7582
Table 1. Break Switch, SW1 and SW2 (Continued)
Parameters Conditions Symbol Isw Isw Isw Min Typ 0.1 0.3 0.1 200 Max 1 1 1 Units A A A V/s Logic Input to Switch Output Isolation: +25C Vsw (TLINE, RLINE) = +/-320V Logic Inputs = Gnd +85C Vsw (TLINE, RLINE) = +/-330V Logic Inputs = Gnd -40C Vsw (TLINE, RLINE) = +/-310V Logic Inputs = Gnd dv/dt Sensitivity1 1
Applied voltage is 100 Vp-p square wave at 100Hz.
Table 2. Ring Return Switch, SW3
Parameters Off-state Leakage Current +25C +85C -40C dc Current Limit: +25C +85C -40C Dynamic Current Limit: (t=<0.5ms) Conditions Vsw (differential)= -320V to Gnd Vsw (differential)= -60V to +260V Vsw (differential)= -330V to Gnd Vsw (differential)= -60V to +270V Vsw (differential)= -310V to Gnd Vsw (differential)= -60V to +250V Vsw (on) = +/- 10V Vsw (on) = +/- 10V Vsw (on) = +/- 10V Break switches in ON state, Ringing access switches OFF, Apply +/- 1000V at 10/1000ms pulse, Appropriate secondary protection in place. Symbol Isw Isw Isw Min Typ 0.1 0.3 0.1 Max 1 1 1 Units A A A
Isw Isw Isw Isw
-
135 85 210 2.5
-
mA mA mA A
RDSON +25C Isw (on) = +/-0mA, +/-10mA +85C Isw (on) = +/-0mA, +/-10mA -40C Isw (on) = +/-0mA, +/-10mA Logic Input to Switch Output Isolation +25C Vsw (TRING, TLINE) = +/-320V Logic Inputs = Gnd +85C Vsw (TRING, TLINE) = +/-330V Logic Inputs = Gnd -40C Vsw (TRING, TLINE) = +/-310V Logic Inputs = Gnd
V V V Isw Isw Isw
-
60 85 45 0.1 0.3 0.1
100 1 1 1
A A A
Rev. 1.0
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CPC7582
Table 3. Ringing Access Switch, SW4
Parameters Off-state Leakage Current +25C +85C -40C Conditions Vsw (differential)= -255V to +210V Vsw (differential)= +255V to -210V Vsw (differential)= -270V to +210V Vsw (differential)= +270V to -210V Vsw (differential)= -245V to +210V Vsw (differential)= +245V to -210V Isw (on) = +/- 1mA Vcc = 5V, INaccess = 0 Symbol Isw Isw Isw IR V Isw Isw Isw Min Typ 0.05 0.1 .05 1.5 0.1 300 8.5 .05 0.1 .05 Max 1 1 1 3 0.25 2 12 1 1 1 Units A A A V mA A A A A A
ON Voltage Ring Generator Current During Ring Surge Current Release Current RDSON Isw (on) = +/-70mA, +/-80mA Logic Input to Switch Output Isolation: +25C Vsw (RRING, RLINE) = +/-320V Logic Inputs = Gnd +85C Vsw (RRING, RLINE) = +/-330V Logic Inputs = Gnd -40C Vsw (RRING, RLINE) = +/-310V Logic Inputs = Gnd
Table 4. Loop Access Switches, SW5 and SW6
Parameters Off-state Leakage Current +25C +85C -40C DC Current Limit: +25C +85C -40C Dynamic Current Limit: (t=<0.5s) Conditions Vsw (differential)= -320V to Gnd Vsw (differential)= -60V to +260V Vsw (differential)= -330V to Gnd Vsw (differential)= -60V to +270V Vsw (differential)= -310 to Gnd Vsw (differential)= -60V to +250V Vsw (on) = +/- 10V Vsw (on) = +/- 10V Vsw (on) = +/- 10V Break switches in ON state, Ringing access switches OFF, Apply +/- 1000V at 10/1000ms pulse, Appropriate secondary protection in place. Symbol Isw Isw Isw Min Typ 0.1 0.3 0.1 Max 1 1 1 Units A A A
Isw Isw Isw Isw
80 -
175 110 210 2.5
250 -
mA mA mA A
RDSON: +25C Isw (on) = +/-10 mA, +/-40mA +85C Isw (on) = +/-10 mA, +/-40mA -40C Isw (on) = +/-10 mA, +/-40mA Logic Input to Switch Output Isolation: +25C Vsw (TACCESS, TLINE) = +/-320V Logic Inputs = Gnd +85C Vsw (TACCESS, TLINE) = +/-330V Logic Inputs = Gnd -40C Vsw (TACCESS, TLINE) = +/-310V Logic Inputs = Gnd
V V V Isw Isw Isw
-
38 46 28 0.1 0.3 0.1
70 1 1 1
A A A
4
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Rev. 1.0
CPC7582
Table 5. Additional Electrical Characteristics
Parameters Digital Input Characteristics Input Low Voltage Input High Voltage Input Leakage Current (High) Input Leakage Current (Low) Power Requirements Power Dissipation Conditions VDD = 5.5V, VBAT = -75V, Vlog = 5V VDD = 5.5V, VBAT = -75V, Vlog = 0V Symbol Ilog Ilog Min 3.5 Typ 0.1 0.1 Max 1.5 1 1 Units V V A A
VDD = 5V, VBAT = -48V, Idle/Talk State or All Off State Ringing State or Access State VDD Current VDD = 5V, Idle/Talk State or All Off State Ringing State or Access State VBAT Current VBAT = -48V, Idle/Talk State or All Off State Ringing State or Access State Temperature Shutdown Requirements1 Shutdown Activation Temperature Shutdown Circuit Hysteresis 1
IDD, IBAT IDD IDD IDD IBAT IBAT -
110 10
5.5 6.5 1.1 1.3 0.1 0.1 125 -
7.5 10 1.5 1.9 10 10 150 25
mW mW mA mA A A C C
Temperature shutdown flag (TSD) will be high during normal operation and low during temperature shutdown state.
Table 6. Make-Before-Break Operation (Ringing to Idle/Talk Transition)
Break Switches Timing 1&2 Open SW4 waiting for next zero current Closed crossing to turn off. Maximum time is one half of ringing. In this transition state, current that is limited to the dc break switch current limit value will be sourced from the ring node of the SLIC Zero cross current has occurred Closed Ring Return Switch 3 Closed Open Ring Access Switch 4 Closed Closed Line Access Switches 5&6 Open Open
Access Input 0V 5V 0V 0V
TSD Float Float
State Ringing Make-before-break
0V
0V
Float
Idle / Talk
Open
Open
Open
Rev. 1.0
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CPC7582
Table 7. Break-Before-Make Operation (Ringing to Idle/Talk Transition)
Break Switches 1&2 Open Open Return Switch 3 Closed Open Ring Ring Access Line Access Switch Switches 4 5&6 Closed Open Closed Open
Access Input 0V 5V 5V 5V
TSD Float Float
State Ringing All Off
5V 0V
5V 0V
Float Float
All Off SW4 has opened. Idle/Talk
Timing Hold this state for <= 25ms. SW4 waiting for zero current to turn off. Zero current has occurred. Release Break Switches
Open Closed
Open Open
Open Open
Open Open
Alternate "Break-Before-Make" Operation Note that the "break-before-make" operation can also be achieved using TSD as an input. In lines 2 & 3 of Table 7, instead of using the logic input pins to force the "all off" state, force TSD to ground. This will override the logic inputs and also force the all off state. Hold this state for 25 ms. During this 25 ms all off state, toggle the inputs from the ringing state (Input=5V, Access=0V) to the idle/talk state (Input=0V, Access=0V). After 25 ms, release TSD to return switch control to the input pins which will set the idle talk state. When using the CPC7582 in this mode, forcing TSD to ground will override the INPUT pins and force an all off state. Setting TSD to +5V will allow switch control via the logic INPUT pins. However, setting TSD to +5V will also disable the thermal shutdown mechanism. This is not recommended. Therefore, to allow switch control via the logic INPUT pins, allow TSD to float. Thus when using TSD as an input, the two recommended states are 0 (overrides logic input pins and forces all off state) and float (allows switch control via logic input pins and thermal shutdown mechanism is active). This may require use of an open collector buffer.
Table 8. Electrical Specifications, Protection Circuitry
Parameters Conditions Parameters Related to Diodes (in Diode Bridge) Voltage Drop @ Continuous Apply +/-dc current limit of break Current (50/60 Hz) switches Voltage Drop @ Surge Apply +/-dynamic current limit of Current break switches Parameters Related to Protection SCR1 Surge Current Trigger Current (+25C) Hold Current (+25C) Trigger Current (+85C) Hold Current (+85C) Gate Trigger Voltage Trigger Current Reverse Leakage Current VBAT ON State Voltage1 0.5A t = 0.5 ms 2.0A t = 0.5 ms
1 Only for the CPC7581BA. * Passes GR1089 & ITU-T K.20 with appropriate secondary protection in place.
Symbol
Min
Typ
Max
Units
Forward Voltage Forward Voltage
-
2.1 5
3 -
V V
ITRIG IHOLD ITRIG IHOLD Von -
60 VBAT - 4 -
60 100 35 70 -3 -5
* VBAT - 2 1.0 -
A mA mA mA mA V A V V
6
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Rev. 1.0
CPC7582
Table 9. Truth Table
Input Access TSD Tip Break Switch On Off Off Off Off Ring Break Switch On Off Off Off Off Ringing Return Switch Off On Off Off Off Ring Switch Off On Off Off Off Tip Access Switch Off Off On Off Off Ring Access Switch Off1 Off2 On3 Off4 Off4
0V 5V 0V 5V Don't Care
1 2 3 4 5
0V 0V 5V 5V Don't Care
5V/Float5 5V/Float5 5V/Float5 5V/Float5 0V6
Idle/Talk State Power Ringing State Test out message waiting state. All OFF State If TSD = 5V, the thermal shutdown mechanism is disabled. If TSD if floating, the thermal shutdown mechanism is active. Forcing TSD to ground overrides the logic input pins and forces an all off state.
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Package Pinout
CPC7582
FGND TBAT 1 2
SW1
SCR and Trip Circuit
Pin
16 15
SW2
Name FGND TBAT TLINE TRING TACCESS VDD TSD
Function Fault ground Connect to TIP on SLIC side Connect to TIP on line side Connect to return ground for ringing generator Test access +5V supply Temperature shutdown pin. Can be used as a logic level input or output. See Tables 6, 7 and 9 for more details. As an output, will read +5V when device is in its operational mode and 0V in the thermal shutdown mode. To disable the thermal shutdown mechanism, tie this pin to +5V (NOT Recommended). Digital ground Logic level switch control Logic level input switch control Data latch control, active high, transparent low Test access Connect to ringing generator Connect to RING on line side Connect to RING on SLIC side Battery voltage. Used as a reference for protection circuit
VBAT RBAT RLINE
1 2 3 4 5 6 7
TLINE 3 TRING TACCESS VDD TSD DGND 4 5 6 7 8
14
13 R RING
SW3 SW5
Control Logic
SW4 SW6
12 11 10 9
RACCESS LATCH INRING INACCESS
* Only the CPC7582BA contains the protection SCR.
8 9 10 11 12 13 14 15 16
DGND INACCESS INRING LATCH RACCESS RRING RLINE RBAT VBAT
Rev. 1.0
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CPC7582
Functional Description Introduction The CPC7582 has four states: * Idle/talk state (line break switches SW1, and SW2 closed, ringing switches SW3, SW4 open and loop access switches SW5, SW6 open), * Ringing state (line break switches SW1, and SW2 open, ringing switches SW3, SW4 closed and loop access switches SW5, SW6 open) * Loop access (line break switches SW1, and SW2 open, ringing switches SW3, SW4 open and loop access switches SW5, SW6 closed) * All Off state (line break switches SW1, and SW2 open, ringing switches SW3, SW4 open and loop access switches SW5, SW6 open) The CPC7582 offers break-before-make and makebefore-break switching with simple logic level input control. Solid state switch construction means no impulse noise is generated when switching during ring cadence or ring trip, thus eliminating the need for external "zero cross" switching circuitry. State control is via logic level input so no additional driver circuitry is required. The line break switches SW1 and SW2 are linear switches that have exceptionally low RDSON and excellent matching characteristics. The ringing access switch SW4 has a breakdown voltage rating of >480V which is sufficiently high, with proper protection, to prevent breakdown in the presence of a transient fault condition (i.e., passing the transient on to the ring generator). Integrated into the CPC7582 is a diode bridge/SCR clamping circuit, current limiting and thermal shutdown mechanism to provide protection to the SLIC device during a fault condition. Positive and negative surges are reduced by the current limiting circuitry and steered to ground via diodes and the integrated SCR. Power cross transients are also reduced by the current limiting and thermal shutdown circuits. Please note that only the CPC7582BA has the integrated protection SCR. To protect the CPC7582 from an overvoltage fault condition, use of a secondary protector is required. The secondary protector must limit the voltage seen at the tip and ring terminals to a level below the max breakdown voltage of the switches. To minimize the stress on the solid-state contacts, use of a foldback or crowbar type secondary protector is recommended. With proper selection of the secondary protector, a line card using the CPC7582 will meet all relevant ITU, LSSGR, FCC or UL protection requirements. The CPC7582 operates from a +5V supply only. This gives the device extremely low idle and active power 8
dissipation and allows use with virtually any range of battery voltage. A battery voltage is also used by the CPC7582 as a reference for the integrated protection circuit. In the event of a loss of battery voltage, the CPC7582 will enter an "all off" state. Switch Timing The CPC7582 provides, when switching from the ringing state to the idle/talk state, the ability to control the timing when the ringing access switches SW3 and SW4 are released relative to the state of the line break switches SW1 and SW2 using simple logic level input. This is referred to a "make before break" or "break before make" operation. When the line break switch contacts (SW1, SW2) are closed (or made) before the ringing access switch contact (SW3, SW4) is opened (or broken), this is referred to a `make-before-break' operation. Break-before-make operation occurs when the ringing access contact (SW3, SW4) is opened (broken) before the line break switch contacts (SW1, SW2) are closed (made). With the CPC7582 the "make before break" and "break before make" operations can easily be selected by applying logic level inputs to pins 9 and 10 (INring and INaccess) of the device. The logic sequences for either mode of operation are given in Tables 6 and 7. Logic states and explanations are given in Table 9. Break-before make operation can also be achieved using pin 7 (TSD) as an input. In table 7 lines 2 and 3 it is possible to induce the switches to "all off" by grounding pin 7 (TSD) instead of apply logic input to the pins. This has the effect of overriding the logic inputs and forcing the device to the "all off" state. Hold this input state for 25ms. During this hold period, toggle the inputs from the ringing state (10) to the idle/talk state (00). After the 25ms release pin 7 (TSD) to return the switch control to the input pins 9 and 10 and reset the device to the idle/talk state. Setting TSD to +5V will allow switch control using the logic pins 9 and 10. This setting, however, will also disable the thermal shutdown circuit and is therefore not recommended. When using logic controls via the input pins 9 and 10, pin 7 (TSD) should be allowed to float. As a result the two recommended states when using pin 7 (TSD) as a control are 0 which forces the device to the "all of state" or float which allows logic inputs to pins 9 and 10 to remain active. This may require use of an open collector buffer.
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CPC7582
Ring Access Switch Zero Cross Current Turn Off After the application of a logic input to turn SW4 off, the ring access switch is designed to delay the change in state until the next zero crossing. Once on, the switch requires a zero current cross to turn off and therefore should not be used to switch a pure DC signal. The switch will remain in the on state no matter what logic input until the next zero crossing. For proper operation, pin 13 (RRing) should be connected using proper impedance to a ring generator or other ac source. These switching characteristics will reduce and possibly eliminate overall system impulse noise normally associated with ringing access switches. The attributes of ringing access switch SW4 may make it possible to eliminate the need for a zero cross switching scheme. A minimum impedence of 300 in series with the ring generator is recommended. Power Supplies Both a +5V supply and battery voltage are connected to the CPC7582. CPC7582 switch state control is powered exclusively by the +5V supply. As a result, the CPC7582 exhibits extremely low power dissipation during both active and idle states. The battery voltage is not used for switch control but rather as a reference by the integrated secondary protection circuitry. The integrated SCR is designed to trigger when pin 2 (TBAT) or pin 15 (RBAT) drops 2 to 4V below the battery. This trigger prevents a fault induced overvoltage event at the TBAT or RBAT nodes. Battery Voltage Monitor The CPC7582 also uses the voltage reference to monitor battery voltage. If battery voltage is lost, the CPC7582 will immediately enter the "all off" state and remain in this state until the battery voltage is restored. The device will also enter the "all off" state if the battery voltage rises above -10V and will remain there until the battery voltage drops below -15V. This battery monitor feature draws a small current from the battery (<1A typ.) and will add slightly to the device's overall power dissipation. Protection Diode Bridge/SCR The CPC7582 uses a combination of current limited break switches, a diode bridge/SCR clamping circuit and a thermal shutdown mechanism to protect the SLIC device or other associated circuitry from damage during line transient events such as lightning. During a
Rev. 1.0
positive transient condition, the fault current is conducted through the diode bridge to ground. Voltage is clamped to the diode drop above ground. During a negative transient of 2 - 4 volts more negative than the battery, the SCR conducts and faults are shunted to ground via the SCR and diode bridge. Also, in order for the SCR to crowbar or foldback, the on voltage (see Table 8) of the SCR must be less negative than the battery reference voltage. If the battery voltage is less negative the SCR on voltage, the SCR will not crowbar, however it will conduct fault currents to ground. For power induction or power cross fault conditions, the positive cycle of the transient is clamped to the diode drop above ground and the fault current directed to ground. The negative cycle of the transient will cause the SCR to conduct when the voltage exceeds the battery reference voltage by two to four volts, steering the current to ground. Current Limiting function If a lightning strike transient occurs when the device in the talk/idle state, the current is passed along the line to the integrated protection circuitry and limited by the dynamic current limit response of break switches SW1 and SW2. When a 1000V 10x1000 pulse (LSSGR lightning) is applied to the line though a properly clamped external protector, the current seen at pins 2 (TBAT) and pin 15 (RBAT) will be a pulse with a typical magnitude and duration of 2.5A and < 0.5ms. If a power cross fault occurs with device in the talk/idle state, the current is passed though the break switches SW1 and SW2 on to the integrated protection circuit and is limited by the dynamic DC current limit response of the two break switches. The DC current limit, specified over temperature, is between 80mA and 425mA and the circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to power cross fault, the measured current at pin 2 (TBAT) and pin 15 (RBAT) will decrease as the device temperature increases. If the device temperature rises sufficiently, the temperature shutdown mechanism will activate and the device will default to the "all off" state. Temperature Shutdown The thermal shutdown mechanism will activate when the device temperature reaches a minimum of 110C placing the device in the "all off" state regardless of logic input. During this thermal shutdown mode, pin 7 (TSD) will read 0V. Normal output of TSD is +VDD 9
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CPC7582
If presented with a short duration transient such as a lightning event, the thermal shutdown feature will not typically activate. But in an extended power cross transient, the device temperature will rise and the thermal shutdown will activate forcing the switches to an "all off" state. At this point the current measured at pin 2 (TBAT) and pin 15 (RBAT) will drop to zero. Once the device enters thermal shutdown it will remain in the "all off" state until the temperature of the device drops below the activation level of the thermal shutdown circuit. This will return the device to the state prior to thermal shutdown. If the transient has not passed, current will flow at the value allowed by the dynamic DC current limiting of the switches and heating will begin again, reactivating the thermal shutdown mechanism. This cycle of entering and exiting the thermal shutdown mode will continue as long as the fault condition persists. If the magnitude of the fault condition is great enough, the external secondary protector could activate and shunt all current to ground. The thermal shutdown mechanism of the CPC7582 can be disable by applying +VDD to pin 7 (TSD) External Protection Elements The CPC7582 requires only one overvoltage secondary protector on the loop side of the device. The integrated protection feature described above negates the need for protection on the line side. The purpose of the secondary protector is to limit voltage transients to levels that do not exceed the breakdown voltage or input-output isolation barrier of the CPC7582. A foldback or crowbar type protector is recommended to minimize stresses on the device. Consult Clare's application note, AN-100, "Designing Surge and Power Fault Protection Circuits for Solid State Subscriber Line Interfaces" for equations related to the specifications of external secondary protectors, fused resistors and PTCs. Data Latch The CPC7582 has an integrated data latch. The latch operation is controlled by logic level input pin 11 (LATCH). The data input of the latch is pin 10 (INRING) and pin 9 (INACCESS) of the device while the output of the data latch is an internal node used for state control. When LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly through to state control. A change in input will be reflected in a change is switch state. When LATCH control pin is at logic 1, the data latch is now active and a change in input control will not affect switch 10
state. The switches will remain in the position they were in when the LATCH changed from logic 0 to logic 1 and will not respond to changes in input as long as the latch is at logic 1. In addition, TSD input is not tied to the data latch. Therefore, TSD is not affected by the LATCH input and TSD input will override state control via pin 10 (INRING) and pin 9 (INACCESS) and the LATCH.
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Rev. 1.0
CPC7582
MECHANICAL DIMENSIONS
16 Pin SOIC (JEDEC Package)
10.11 MIN / 10.31 MAX (.398 MIN / .406 MAX) 1.27 (.050)
2.44 MIN / 2.64 MAX (.096 MIN / .104 MAX) 0.51 MIN / 1.01 MAX (.020 MIN / .040 MAX)
0.23 MIN / 0.32 MAX (.0091 MIN / .0125 MAX) 7.40 MIN / (.291 MIN /
32 MAX 125 MAX) 7.40 MIN / 7.60 MAX (.291 MIN / .299 MAX) 10.11 MIN / 10.51 MAX (.398 MIN / .414 MAX)
0.36 MIN / 0.46 MAX (.014 MIN / .018 MAX)
PC Board Pattern (Top View)
1.270 (.050)
9.728 .051 (.383 .002) 1.193 (.047) .787 (.031)
Dimensions mm (Inches)
Rev. 1.0
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Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in Clare's Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare's product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC7582BA-R1.0 (c)Copyright 2001, Clare, Inc. All rights reserved. Printed in USA. 9/20/01

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